2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
5 * Copyright (c) 2003 Fabrice Bellard
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #if !defined(CONFIG_USER_ONLY)
28 #include "exec/softmmu_exec.h"
29 #endif /* !defined(CONFIG_USER_ONLY) */
32 # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
33 # define LOG_PCALL_STATE(cpu) \
34 log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP)
36 # define LOG_PCALL(...) do { } while (0)
37 # define LOG_PCALL_STATE(cpu) do { } while (0)
40 /* return non zero if error */
41 static inline int load_segment(CPUX86State
*env
, uint32_t *e1_ptr
,
42 uint32_t *e2_ptr
, int selector
)
53 index
= selector
& ~7;
54 if ((index
+ 7) > dt
->limit
) {
57 ptr
= dt
->base
+ index
;
58 *e1_ptr
= cpu_ldl_kernel(env
, ptr
);
59 *e2_ptr
= cpu_ldl_kernel(env
, ptr
+ 4);
63 static inline unsigned int get_seg_limit(uint32_t e1
, uint32_t e2
)
67 limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
68 if (e2
& DESC_G_MASK
) {
69 limit
= (limit
<< 12) | 0xfff;
74 static inline uint32_t get_seg_base(uint32_t e1
, uint32_t e2
)
76 return (e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000);
79 static inline void load_seg_cache_raw_dt(SegmentCache
*sc
, uint32_t e1
,
82 sc
->base
= get_seg_base(e1
, e2
);
83 sc
->limit
= get_seg_limit(e1
, e2
);
87 /* init the segment cache in vm86 mode. */
88 static inline void load_seg_vm(CPUX86State
*env
, int seg
, int selector
)
91 cpu_x86_load_seg_cache(env
, seg
, selector
,
92 (selector
<< 4), 0xffff, 0);
95 static inline void get_ss_esp_from_tss(CPUX86State
*env
, uint32_t *ss_ptr
,
96 uint32_t *esp_ptr
, int dpl
)
98 int type
, index
, shift
;
103 printf("TR: base=%p limit=%x\n", env
->tr
.base
, env
->tr
.limit
);
104 for (i
= 0; i
< env
->tr
.limit
; i
++) {
105 printf("%02x ", env
->tr
.base
[i
]);
114 if (!(env
->tr
.flags
& DESC_P_MASK
)) {
115 cpu_abort(env
, "invalid tss");
117 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
118 if ((type
& 7) != 1) {
119 cpu_abort(env
, "invalid tss type");
122 index
= (dpl
* 4 + 2) << shift
;
123 if (index
+ (4 << shift
) - 1 > env
->tr
.limit
) {
124 raise_exception_err(env
, EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
127 *esp_ptr
= cpu_lduw_kernel(env
, env
->tr
.base
+ index
);
128 *ss_ptr
= cpu_lduw_kernel(env
, env
->tr
.base
+ index
+ 2);
130 *esp_ptr
= cpu_ldl_kernel(env
, env
->tr
.base
+ index
);
131 *ss_ptr
= cpu_lduw_kernel(env
, env
->tr
.base
+ index
+ 4);
135 /* XXX: merge with load_seg() */
136 static void tss_load_seg(CPUX86State
*env
, int seg_reg
, int selector
)
141 if ((selector
& 0xfffc) != 0) {
142 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
143 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
145 if (!(e2
& DESC_S_MASK
)) {
146 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
149 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
150 cpl
= env
->hflags
& HF_CPL_MASK
;
151 if (seg_reg
== R_CS
) {
152 if (!(e2
& DESC_CS_MASK
)) {
153 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
155 /* XXX: is it correct? */
157 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
159 if ((e2
& DESC_C_MASK
) && dpl
> rpl
) {
160 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
162 } else if (seg_reg
== R_SS
) {
163 /* SS must be writable data */
164 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
)) {
165 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
167 if (dpl
!= cpl
|| dpl
!= rpl
) {
168 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
171 /* not readable code */
172 if ((e2
& DESC_CS_MASK
) && !(e2
& DESC_R_MASK
)) {
173 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
175 /* if data or non conforming code, checks the rights */
176 if (((e2
>> DESC_TYPE_SHIFT
) & 0xf) < 12) {
177 if (dpl
< cpl
|| dpl
< rpl
) {
178 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
182 if (!(e2
& DESC_P_MASK
)) {
183 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
185 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
186 get_seg_base(e1
, e2
),
187 get_seg_limit(e1
, e2
),
190 if (seg_reg
== R_SS
|| seg_reg
== R_CS
) {
191 raise_exception_err(env
, EXCP0A_TSS
, selector
& 0xfffc);
196 #define SWITCH_TSS_JMP 0
197 #define SWITCH_TSS_IRET 1
198 #define SWITCH_TSS_CALL 2
200 /* XXX: restore CPU state in registers (PowerPC case) */
201 static void switch_tss(CPUX86State
*env
, int tss_selector
,
202 uint32_t e1
, uint32_t e2
, int source
,
205 int tss_limit
, tss_limit_max
, type
, old_tss_limit_max
, old_type
, v1
, v2
, i
;
206 target_ulong tss_base
;
207 uint32_t new_regs
[8], new_segs
[6];
208 uint32_t new_eflags
, new_eip
, new_cr3
, new_ldt
, new_trap
;
209 uint32_t old_eflags
, eflags_mask
;
214 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
215 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector
, type
,
218 /* if task gate, we read the TSS segment and we load it */
220 if (!(e2
& DESC_P_MASK
)) {
221 raise_exception_err(env
, EXCP0B_NOSEG
, tss_selector
& 0xfffc);
223 tss_selector
= e1
>> 16;
224 if (tss_selector
& 4) {
225 raise_exception_err(env
, EXCP0A_TSS
, tss_selector
& 0xfffc);
227 if (load_segment(env
, &e1
, &e2
, tss_selector
) != 0) {
228 raise_exception_err(env
, EXCP0D_GPF
, tss_selector
& 0xfffc);
230 if (e2
& DESC_S_MASK
) {
231 raise_exception_err(env
, EXCP0D_GPF
, tss_selector
& 0xfffc);
233 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
234 if ((type
& 7) != 1) {
235 raise_exception_err(env
, EXCP0D_GPF
, tss_selector
& 0xfffc);
239 if (!(e2
& DESC_P_MASK
)) {
240 raise_exception_err(env
, EXCP0B_NOSEG
, tss_selector
& 0xfffc);
248 tss_limit
= get_seg_limit(e1
, e2
);
249 tss_base
= get_seg_base(e1
, e2
);
250 if ((tss_selector
& 4) != 0 ||
251 tss_limit
< tss_limit_max
) {
252 raise_exception_err(env
, EXCP0A_TSS
, tss_selector
& 0xfffc);
254 old_type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
256 old_tss_limit_max
= 103;
258 old_tss_limit_max
= 43;
261 /* read all the registers from the new TSS */
264 new_cr3
= cpu_ldl_kernel(env
, tss_base
+ 0x1c);
265 new_eip
= cpu_ldl_kernel(env
, tss_base
+ 0x20);
266 new_eflags
= cpu_ldl_kernel(env
, tss_base
+ 0x24);
267 for (i
= 0; i
< 8; i
++) {
268 new_regs
[i
] = cpu_ldl_kernel(env
, tss_base
+ (0x28 + i
* 4));
270 for (i
= 0; i
< 6; i
++) {
271 new_segs
[i
] = cpu_lduw_kernel(env
, tss_base
+ (0x48 + i
* 4));
273 new_ldt
= cpu_lduw_kernel(env
, tss_base
+ 0x60);
274 new_trap
= cpu_ldl_kernel(env
, tss_base
+ 0x64);
278 new_eip
= cpu_lduw_kernel(env
, tss_base
+ 0x0e);
279 new_eflags
= cpu_lduw_kernel(env
, tss_base
+ 0x10);
280 for (i
= 0; i
< 8; i
++) {
281 new_regs
[i
] = cpu_lduw_kernel(env
, tss_base
+ (0x12 + i
* 2)) |
284 for (i
= 0; i
< 4; i
++) {
285 new_segs
[i
] = cpu_lduw_kernel(env
, tss_base
+ (0x22 + i
* 4));
287 new_ldt
= cpu_lduw_kernel(env
, tss_base
+ 0x2a);
292 /* XXX: avoid a compiler warning, see
293 http://support.amd.com/us/Processor_TechDocs/24593.pdf
294 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
297 /* NOTE: we must avoid memory exceptions during the task switch,
298 so we make dummy accesses before */
299 /* XXX: it can still fail in some cases, so a bigger hack is
300 necessary to valid the TLB after having done the accesses */
302 v1
= cpu_ldub_kernel(env
, env
->tr
.base
);
303 v2
= cpu_ldub_kernel(env
, env
->tr
.base
+ old_tss_limit_max
);
304 cpu_stb_kernel(env
, env
->tr
.base
, v1
);
305 cpu_stb_kernel(env
, env
->tr
.base
+ old_tss_limit_max
, v2
);
307 /* clear busy bit (it is restartable) */
308 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_IRET
) {
312 ptr
= env
->gdt
.base
+ (env
->tr
.selector
& ~7);
313 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
314 e2
&= ~DESC_TSS_BUSY_MASK
;
315 cpu_stl_kernel(env
, ptr
+ 4, e2
);
317 old_eflags
= cpu_compute_eflags(env
);
318 if (source
== SWITCH_TSS_IRET
) {
319 old_eflags
&= ~NT_MASK
;
322 /* save the current state in the old TSS */
325 cpu_stl_kernel(env
, env
->tr
.base
+ 0x20, next_eip
);
326 cpu_stl_kernel(env
, env
->tr
.base
+ 0x24, old_eflags
);
327 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 0 * 4), env
->regs
[R_EAX
]);
328 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 1 * 4), env
->regs
[R_ECX
]);
329 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 2 * 4), env
->regs
[R_EDX
]);
330 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 3 * 4), env
->regs
[R_EBX
]);
331 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 4 * 4), env
->regs
[R_ESP
]);
332 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 5 * 4), env
->regs
[R_EBP
]);
333 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 6 * 4), env
->regs
[R_ESI
]);
334 cpu_stl_kernel(env
, env
->tr
.base
+ (0x28 + 7 * 4), env
->regs
[R_EDI
]);
335 for (i
= 0; i
< 6; i
++) {
336 cpu_stw_kernel(env
, env
->tr
.base
+ (0x48 + i
* 4),
337 env
->segs
[i
].selector
);
341 cpu_stw_kernel(env
, env
->tr
.base
+ 0x0e, next_eip
);
342 cpu_stw_kernel(env
, env
->tr
.base
+ 0x10, old_eflags
);
343 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 0 * 2), env
->regs
[R_EAX
]);
344 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 1 * 2), env
->regs
[R_ECX
]);
345 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 2 * 2), env
->regs
[R_EDX
]);
346 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 3 * 2), env
->regs
[R_EBX
]);
347 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 4 * 2), env
->regs
[R_ESP
]);
348 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 5 * 2), env
->regs
[R_EBP
]);
349 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 6 * 2), env
->regs
[R_ESI
]);
350 cpu_stw_kernel(env
, env
->tr
.base
+ (0x12 + 7 * 2), env
->regs
[R_EDI
]);
351 for (i
= 0; i
< 4; i
++) {
352 cpu_stw_kernel(env
, env
->tr
.base
+ (0x22 + i
* 4),
353 env
->segs
[i
].selector
);
357 /* now if an exception occurs, it will occurs in the next task
360 if (source
== SWITCH_TSS_CALL
) {
361 cpu_stw_kernel(env
, tss_base
, env
->tr
.selector
);
362 new_eflags
|= NT_MASK
;
366 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_CALL
) {
370 ptr
= env
->gdt
.base
+ (tss_selector
& ~7);
371 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
372 e2
|= DESC_TSS_BUSY_MASK
;
373 cpu_stl_kernel(env
, ptr
+ 4, e2
);
376 /* set the new CPU state */
377 /* from this point, any exception which occurs can give problems */
378 env
->cr
[0] |= CR0_TS_MASK
;
379 env
->hflags
|= HF_TS_MASK
;
380 env
->tr
.selector
= tss_selector
;
381 env
->tr
.base
= tss_base
;
382 env
->tr
.limit
= tss_limit
;
383 env
->tr
.flags
= e2
& ~DESC_TSS_BUSY_MASK
;
385 if ((type
& 8) && (env
->cr
[0] & CR0_PG_MASK
)) {
386 cpu_x86_update_cr3(env
, new_cr3
);
389 /* load all registers without an exception, then reload them with
390 possible exception */
392 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
|
393 IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
| NT_MASK
;
395 eflags_mask
&= 0xffff;
397 cpu_load_eflags(env
, new_eflags
, eflags_mask
);
398 /* XXX: what to do in 16 bit case? */
399 env
->regs
[R_EAX
] = new_regs
[0];
400 env
->regs
[R_ECX
] = new_regs
[1];
401 env
->regs
[R_EDX
] = new_regs
[2];
402 env
->regs
[R_EBX
] = new_regs
[3];
403 env
->regs
[R_ESP
] = new_regs
[4];
404 env
->regs
[R_EBP
] = new_regs
[5];
405 env
->regs
[R_ESI
] = new_regs
[6];
406 env
->regs
[R_EDI
] = new_regs
[7];
407 if (new_eflags
& VM_MASK
) {
408 for (i
= 0; i
< 6; i
++) {
409 load_seg_vm(env
, i
, new_segs
[i
]);
411 /* in vm86, CPL is always 3 */
412 cpu_x86_set_cpl(env
, 3);
414 /* CPL is set the RPL of CS */
415 cpu_x86_set_cpl(env
, new_segs
[R_CS
] & 3);
416 /* first just selectors as the rest may trigger exceptions */
417 for (i
= 0; i
< 6; i
++) {
418 cpu_x86_load_seg_cache(env
, i
, new_segs
[i
], 0, 0, 0);
422 env
->ldt
.selector
= new_ldt
& ~4;
429 raise_exception_err(env
, EXCP0A_TSS
, new_ldt
& 0xfffc);
432 if ((new_ldt
& 0xfffc) != 0) {
434 index
= new_ldt
& ~7;
435 if ((index
+ 7) > dt
->limit
) {
436 raise_exception_err(env
, EXCP0A_TSS
, new_ldt
& 0xfffc);
438 ptr
= dt
->base
+ index
;
439 e1
= cpu_ldl_kernel(env
, ptr
);
440 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
441 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2) {
442 raise_exception_err(env
, EXCP0A_TSS
, new_ldt
& 0xfffc);
444 if (!(e2
& DESC_P_MASK
)) {
445 raise_exception_err(env
, EXCP0A_TSS
, new_ldt
& 0xfffc);
447 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
450 /* load the segments */
451 if (!(new_eflags
& VM_MASK
)) {
452 tss_load_seg(env
, R_CS
, new_segs
[R_CS
]);
453 tss_load_seg(env
, R_SS
, new_segs
[R_SS
]);
454 tss_load_seg(env
, R_ES
, new_segs
[R_ES
]);
455 tss_load_seg(env
, R_DS
, new_segs
[R_DS
]);
456 tss_load_seg(env
, R_FS
, new_segs
[R_FS
]);
457 tss_load_seg(env
, R_GS
, new_segs
[R_GS
]);
460 /* check that env->eip is in the CS segment limits */
461 if (new_eip
> env
->segs
[R_CS
].limit
) {
462 /* XXX: different exception if CALL? */
463 raise_exception_err(env
, EXCP0D_GPF
, 0);
466 #ifndef CONFIG_USER_ONLY
467 /* reset local breakpoints */
468 if (env
->dr
[7] & DR7_LOCAL_BP_MASK
) {
469 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
470 if (hw_local_breakpoint_enabled(env
->dr
[7], i
) &&
471 !hw_global_breakpoint_enabled(env
->dr
[7], i
)) {
472 hw_breakpoint_remove(env
, i
);
475 env
->dr
[7] &= ~DR7_LOCAL_BP_MASK
;
480 static inline unsigned int get_sp_mask(unsigned int e2
)
482 if (e2
& DESC_B_MASK
) {
489 static int exception_has_error_code(int intno
)
505 #define SET_ESP(val, sp_mask) \
507 if ((sp_mask) == 0xffff) { \
508 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
510 } else if ((sp_mask) == 0xffffffffLL) { \
511 env->regs[R_ESP] = (uint32_t)(val); \
513 env->regs[R_ESP] = (val); \
517 #define SET_ESP(val, sp_mask) \
519 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
520 ((val) & (sp_mask)); \
524 /* in 64-bit machines, this can overflow. So this segment addition macro
525 * can be used to trim the value to 32-bit whenever needed */
526 #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
528 /* XXX: add a is_user flag to have proper security support */
529 #define PUSHW(ssp, sp, sp_mask, val) \
532 cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \
535 #define PUSHL(ssp, sp, sp_mask, val) \
538 cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \
541 #define POPW(ssp, sp, sp_mask, val) \
543 val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \
547 #define POPL(ssp, sp, sp_mask, val) \
549 val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \
553 /* protected mode interrupt */
554 static void do_interrupt_protected(CPUX86State
*env
, int intno
, int is_int
,
555 int error_code
, unsigned int next_eip
,
559 target_ulong ptr
, ssp
;
560 int type
, dpl
, selector
, ss_dpl
, cpl
;
561 int has_error_code
, new_stack
, shift
;
562 uint32_t e1
, e2
, offset
, ss
= 0, esp
, ss_e1
= 0, ss_e2
= 0;
563 uint32_t old_eip
, sp_mask
;
566 if (!is_int
&& !is_hw
) {
567 has_error_code
= exception_has_error_code(intno
);
576 if (intno
* 8 + 7 > dt
->limit
) {
577 raise_exception_err(env
, EXCP0D_GPF
, intno
* 8 + 2);
579 ptr
= dt
->base
+ intno
* 8;
580 e1
= cpu_ldl_kernel(env
, ptr
);
581 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
582 /* check gate type */
583 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
585 case 5: /* task gate */
586 /* must do that check here to return the correct error code */
587 if (!(e2
& DESC_P_MASK
)) {
588 raise_exception_err(env
, EXCP0B_NOSEG
, intno
* 8 + 2);
590 switch_tss(env
, intno
* 8, e1
, e2
, SWITCH_TSS_CALL
, old_eip
);
591 if (has_error_code
) {
595 /* push the error code */
596 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
598 if (env
->segs
[R_SS
].flags
& DESC_B_MASK
) {
603 esp
= (env
->regs
[R_ESP
] - (2 << shift
)) & mask
;
604 ssp
= env
->segs
[R_SS
].base
+ esp
;
606 cpu_stl_kernel(env
, ssp
, error_code
);
608 cpu_stw_kernel(env
, ssp
, error_code
);
613 case 6: /* 286 interrupt gate */
614 case 7: /* 286 trap gate */
615 case 14: /* 386 interrupt gate */
616 case 15: /* 386 trap gate */
619 raise_exception_err(env
, EXCP0D_GPF
, intno
* 8 + 2);
622 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
623 cpl
= env
->hflags
& HF_CPL_MASK
;
624 /* check privilege if software int */
625 if (is_int
&& dpl
< cpl
) {
626 raise_exception_err(env
, EXCP0D_GPF
, intno
* 8 + 2);
628 /* check valid bit */
629 if (!(e2
& DESC_P_MASK
)) {
630 raise_exception_err(env
, EXCP0B_NOSEG
, intno
* 8 + 2);
633 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
634 if ((selector
& 0xfffc) == 0) {
635 raise_exception_err(env
, EXCP0D_GPF
, 0);
637 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
638 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
640 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
))) {
641 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
643 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
645 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
647 if (!(e2
& DESC_P_MASK
)) {
648 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
650 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
651 /* to inner privilege */
652 get_ss_esp_from_tss(env
, &ss
, &esp
, dpl
);
653 if ((ss
& 0xfffc) == 0) {
654 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
656 if ((ss
& 3) != dpl
) {
657 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
659 if (load_segment(env
, &ss_e1
, &ss_e2
, ss
) != 0) {
660 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
662 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
664 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
666 if (!(ss_e2
& DESC_S_MASK
) ||
667 (ss_e2
& DESC_CS_MASK
) ||
668 !(ss_e2
& DESC_W_MASK
)) {
669 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
671 if (!(ss_e2
& DESC_P_MASK
)) {
672 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
675 sp_mask
= get_sp_mask(ss_e2
);
676 ssp
= get_seg_base(ss_e1
, ss_e2
);
677 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
678 /* to same privilege */
679 if (env
->eflags
& VM_MASK
) {
680 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
683 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
684 ssp
= env
->segs
[R_SS
].base
;
685 esp
= env
->regs
[R_ESP
];
688 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
689 new_stack
= 0; /* avoid warning */
690 sp_mask
= 0; /* avoid warning */
691 ssp
= 0; /* avoid warning */
692 esp
= 0; /* avoid warning */
698 /* XXX: check that enough room is available */
699 push_size
= 6 + (new_stack
<< 2) + (has_error_code
<< 1);
700 if (env
->eflags
& VM_MASK
) {
707 if (env
->eflags
& VM_MASK
) {
708 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
709 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
710 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
711 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
713 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
714 PUSHL(ssp
, esp
, sp_mask
, env
->regs
[R_ESP
]);
716 PUSHL(ssp
, esp
, sp_mask
, cpu_compute_eflags(env
));
717 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
718 PUSHL(ssp
, esp
, sp_mask
, old_eip
);
719 if (has_error_code
) {
720 PUSHL(ssp
, esp
, sp_mask
, error_code
);
724 if (env
->eflags
& VM_MASK
) {
725 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
726 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
727 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
728 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
730 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
731 PUSHW(ssp
, esp
, sp_mask
, env
->regs
[R_ESP
]);
733 PUSHW(ssp
, esp
, sp_mask
, cpu_compute_eflags(env
));
734 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
735 PUSHW(ssp
, esp
, sp_mask
, old_eip
);
736 if (has_error_code
) {
737 PUSHW(ssp
, esp
, sp_mask
, error_code
);
742 if (env
->eflags
& VM_MASK
) {
743 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0, 0);
744 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0, 0);
745 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0, 0);
746 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0, 0);
748 ss
= (ss
& ~3) | dpl
;
749 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
750 ssp
, get_seg_limit(ss_e1
, ss_e2
), ss_e2
);
752 SET_ESP(esp
, sp_mask
);
754 selector
= (selector
& ~3) | dpl
;
755 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
756 get_seg_base(e1
, e2
),
757 get_seg_limit(e1
, e2
),
759 cpu_x86_set_cpl(env
, dpl
);
762 /* interrupt gate clear IF mask */
763 if ((type
& 1) == 0) {
764 env
->eflags
&= ~IF_MASK
;
766 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
771 #define PUSHQ(sp, val) \
774 cpu_stq_kernel(env, sp, (val)); \
777 #define POPQ(sp, val) \
779 val = cpu_ldq_kernel(env, sp); \
783 static inline target_ulong
get_rsp_from_tss(CPUX86State
*env
, int level
)
788 printf("TR: base=" TARGET_FMT_lx
" limit=%x\n",
789 env
->tr
.base
, env
->tr
.limit
);
792 if (!(env
->tr
.flags
& DESC_P_MASK
)) {
793 cpu_abort(env
, "invalid tss");
795 index
= 8 * level
+ 4;
796 if ((index
+ 7) > env
->tr
.limit
) {
797 raise_exception_err(env
, EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
799 return cpu_ldq_kernel(env
, env
->tr
.base
+ index
);
802 /* 64 bit interrupt */
803 static void do_interrupt64(CPUX86State
*env
, int intno
, int is_int
,
804 int error_code
, target_ulong next_eip
, int is_hw
)
808 int type
, dpl
, selector
, cpl
, ist
;
809 int has_error_code
, new_stack
;
810 uint32_t e1
, e2
, e3
, ss
;
811 target_ulong old_eip
, esp
, offset
;
814 if (!is_int
&& !is_hw
) {
815 has_error_code
= exception_has_error_code(intno
);
824 if (intno
* 16 + 15 > dt
->limit
) {
825 raise_exception_err(env
, EXCP0D_GPF
, intno
* 16 + 2);
827 ptr
= dt
->base
+ intno
* 16;
828 e1
= cpu_ldl_kernel(env
, ptr
);
829 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
830 e3
= cpu_ldl_kernel(env
, ptr
+ 8);
831 /* check gate type */
832 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
834 case 14: /* 386 interrupt gate */
835 case 15: /* 386 trap gate */
838 raise_exception_err(env
, EXCP0D_GPF
, intno
* 16 + 2);
841 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
842 cpl
= env
->hflags
& HF_CPL_MASK
;
843 /* check privilege if software int */
844 if (is_int
&& dpl
< cpl
) {
845 raise_exception_err(env
, EXCP0D_GPF
, intno
* 16 + 2);
847 /* check valid bit */
848 if (!(e2
& DESC_P_MASK
)) {
849 raise_exception_err(env
, EXCP0B_NOSEG
, intno
* 16 + 2);
852 offset
= ((target_ulong
)e3
<< 32) | (e2
& 0xffff0000) | (e1
& 0x0000ffff);
854 if ((selector
& 0xfffc) == 0) {
855 raise_exception_err(env
, EXCP0D_GPF
, 0);
858 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
859 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
861 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
))) {
862 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
864 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
866 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
868 if (!(e2
& DESC_P_MASK
)) {
869 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
871 if (!(e2
& DESC_L_MASK
) || (e2
& DESC_B_MASK
)) {
872 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
874 if ((!(e2
& DESC_C_MASK
) && dpl
< cpl
) || ist
!= 0) {
875 /* to inner privilege */
877 esp
= get_rsp_from_tss(env
, ist
+ 3);
879 esp
= get_rsp_from_tss(env
, dpl
);
881 esp
&= ~0xfLL
; /* align stack */
884 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
885 /* to same privilege */
886 if (env
->eflags
& VM_MASK
) {
887 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
891 esp
= get_rsp_from_tss(env
, ist
+ 3);
893 esp
= env
->regs
[R_ESP
];
895 esp
&= ~0xfLL
; /* align stack */
898 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
899 new_stack
= 0; /* avoid warning */
900 esp
= 0; /* avoid warning */
903 PUSHQ(esp
, env
->segs
[R_SS
].selector
);
904 PUSHQ(esp
, env
->regs
[R_ESP
]);
905 PUSHQ(esp
, cpu_compute_eflags(env
));
906 PUSHQ(esp
, env
->segs
[R_CS
].selector
);
908 if (has_error_code
) {
909 PUSHQ(esp
, error_code
);
914 cpu_x86_load_seg_cache(env
, R_SS
, ss
, 0, 0, 0);
916 env
->regs
[R_ESP
] = esp
;
918 selector
= (selector
& ~3) | dpl
;
919 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
920 get_seg_base(e1
, e2
),
921 get_seg_limit(e1
, e2
),
923 cpu_x86_set_cpl(env
, dpl
);
926 /* interrupt gate clear IF mask */
927 if ((type
& 1) == 0) {
928 env
->eflags
&= ~IF_MASK
;
930 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
935 #if defined(CONFIG_USER_ONLY)
936 void helper_syscall(CPUX86State
*env
, int next_eip_addend
)
938 env
->exception_index
= EXCP_SYSCALL
;
939 env
->exception_next_eip
= env
->eip
+ next_eip_addend
;
943 void helper_syscall(CPUX86State
*env
, int next_eip_addend
)
947 if (!(env
->efer
& MSR_EFER_SCE
)) {
948 raise_exception_err(env
, EXCP06_ILLOP
, 0);
950 selector
= (env
->star
>> 32) & 0xffff;
951 if (env
->hflags
& HF_LMA_MASK
) {
954 env
->regs
[R_ECX
] = env
->eip
+ next_eip_addend
;
955 env
->regs
[11] = cpu_compute_eflags(env
);
957 code64
= env
->hflags
& HF_CS64_MASK
;
959 cpu_x86_set_cpl(env
, 0);
960 cpu_x86_load_seg_cache(env
, R_CS
, selector
& 0xfffc,
962 DESC_G_MASK
| DESC_P_MASK
|
964 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
|
966 cpu_x86_load_seg_cache(env
, R_SS
, (selector
+ 8) & 0xfffc,
968 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
970 DESC_W_MASK
| DESC_A_MASK
);
971 env
->eflags
&= ~env
->fmask
;
972 cpu_load_eflags(env
, env
->eflags
, 0);
974 env
->eip
= env
->lstar
;
976 env
->eip
= env
->cstar
;
979 env
->regs
[R_ECX
] = (uint32_t)(env
->eip
+ next_eip_addend
);
981 cpu_x86_set_cpl(env
, 0);
982 cpu_x86_load_seg_cache(env
, R_CS
, selector
& 0xfffc,
984 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
986 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
987 cpu_x86_load_seg_cache(env
, R_SS
, (selector
+ 8) & 0xfffc,
989 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
991 DESC_W_MASK
| DESC_A_MASK
);
992 env
->eflags
&= ~(IF_MASK
| RF_MASK
| VM_MASK
);
993 env
->eip
= (uint32_t)env
->star
;
1000 void helper_sysret(CPUX86State
*env
, int dflag
)
1004 if (!(env
->efer
& MSR_EFER_SCE
)) {
1005 raise_exception_err(env
, EXCP06_ILLOP
, 0);
1007 cpl
= env
->hflags
& HF_CPL_MASK
;
1008 if (!(env
->cr
[0] & CR0_PE_MASK
) || cpl
!= 0) {
1009 raise_exception_err(env
, EXCP0D_GPF
, 0);
1011 selector
= (env
->star
>> 48) & 0xffff;
1012 if (env
->hflags
& HF_LMA_MASK
) {
1014 cpu_x86_load_seg_cache(env
, R_CS
, (selector
+ 16) | 3,
1016 DESC_G_MASK
| DESC_P_MASK
|
1017 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1018 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
|
1020 env
->eip
= env
->regs
[R_ECX
];
1022 cpu_x86_load_seg_cache(env
, R_CS
, selector
| 3,
1024 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1025 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1026 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
1027 env
->eip
= (uint32_t)env
->regs
[R_ECX
];
1029 cpu_x86_load_seg_cache(env
, R_SS
, selector
+ 8,
1031 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1032 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1033 DESC_W_MASK
| DESC_A_MASK
);
1034 cpu_load_eflags(env
, (uint32_t)(env
->regs
[11]), TF_MASK
| AC_MASK
1035 | ID_MASK
| IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
|
1037 cpu_x86_set_cpl(env
, 3);
1039 cpu_x86_load_seg_cache(env
, R_CS
, selector
| 3,
1041 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1042 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1043 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
1044 env
->eip
= (uint32_t)env
->regs
[R_ECX
];
1045 cpu_x86_load_seg_cache(env
, R_SS
, selector
+ 8,
1047 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1048 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1049 DESC_W_MASK
| DESC_A_MASK
);
1050 env
->eflags
|= IF_MASK
;
1051 cpu_x86_set_cpl(env
, 3);
1056 /* real mode interrupt */
1057 static void do_interrupt_real(CPUX86State
*env
, int intno
, int is_int
,
1058 int error_code
, unsigned int next_eip
)
1061 target_ulong ptr
, ssp
;
1063 uint32_t offset
, esp
;
1064 uint32_t old_cs
, old_eip
;
1066 /* real mode (simpler!) */
1068 if (intno
* 4 + 3 > dt
->limit
) {
1069 raise_exception_err(env
, EXCP0D_GPF
, intno
* 8 + 2);
1071 ptr
= dt
->base
+ intno
* 4;
1072 offset
= cpu_lduw_kernel(env
, ptr
);
1073 selector
= cpu_lduw_kernel(env
, ptr
+ 2);
1074 esp
= env
->regs
[R_ESP
];
1075 ssp
= env
->segs
[R_SS
].base
;
1081 old_cs
= env
->segs
[R_CS
].selector
;
1082 /* XXX: use SS segment size? */
1083 PUSHW(ssp
, esp
, 0xffff, cpu_compute_eflags(env
));
1084 PUSHW(ssp
, esp
, 0xffff, old_cs
);
1085 PUSHW(ssp
, esp
, 0xffff, old_eip
);
1087 /* update processor state */
1088 env
->regs
[R_ESP
] = (env
->regs
[R_ESP
] & ~0xffff) | (esp
& 0xffff);
1090 env
->segs
[R_CS
].selector
= selector
;
1091 env
->segs
[R_CS
].base
= (selector
<< 4);
1092 env
->eflags
&= ~(IF_MASK
| TF_MASK
| AC_MASK
| RF_MASK
);
1095 #if defined(CONFIG_USER_ONLY)
1096 /* fake user mode interrupt */
1097 static void do_interrupt_user(CPUX86State
*env
, int intno
, int is_int
,
1098 int error_code
, target_ulong next_eip
)
1102 int dpl
, cpl
, shift
;
1106 if (env
->hflags
& HF_LMA_MASK
) {
1111 ptr
= dt
->base
+ (intno
<< shift
);
1112 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
1114 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1115 cpl
= env
->hflags
& HF_CPL_MASK
;
1116 /* check privilege if software int */
1117 if (is_int
&& dpl
< cpl
) {
1118 raise_exception_err(env
, EXCP0D_GPF
, (intno
<< shift
) + 2);
1121 /* Since we emulate only user space, we cannot do more than
1122 exiting the emulation with the suitable exception and error
1125 env
->eip
= next_eip
;
1131 static void handle_even_inj(CPUX86State
*env
, int intno
, int is_int
,
1132 int error_code
, int is_hw
, int rm
)
1134 CPUState
*cs
= ENV_GET_CPU(env
);
1135 uint32_t event_inj
= ldl_phys(cs
->as
, env
->vm_vmcb
+ offsetof(struct vmcb
,
1136 control
.event_inj
));
1138 if (!(event_inj
& SVM_EVTINJ_VALID
)) {
1142 type
= SVM_EVTINJ_TYPE_SOFT
;
1144 type
= SVM_EVTINJ_TYPE_EXEPT
;
1146 event_inj
= intno
| type
| SVM_EVTINJ_VALID
;
1147 if (!rm
&& exception_has_error_code(intno
)) {
1148 event_inj
|= SVM_EVTINJ_VALID_ERR
;
1149 stl_phys(cs
->as
, env
->vm_vmcb
+ offsetof(struct vmcb
,
1150 control
.event_inj_err
),
1154 env
->vm_vmcb
+ offsetof(struct vmcb
, control
.event_inj
),
1161 * Begin execution of an interruption. is_int is TRUE if coming from
1162 * the int instruction. next_eip is the env->eip value AFTER the interrupt
1163 * instruction. It is only relevant if is_int is TRUE.
1165 static void do_interrupt_all(X86CPU
*cpu
, int intno
, int is_int
,
1166 int error_code
, target_ulong next_eip
, int is_hw
)
1168 CPUX86State
*env
= &cpu
->env
;
1170 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
1171 if ((env
->cr
[0] & CR0_PE_MASK
)) {
1174 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1175 " pc=" TARGET_FMT_lx
" SP=%04x:" TARGET_FMT_lx
,
1176 count
, intno
, error_code
, is_int
,
1177 env
->hflags
& HF_CPL_MASK
,
1178 env
->segs
[R_CS
].selector
, env
->eip
,
1179 (int)env
->segs
[R_CS
].base
+ env
->eip
,
1180 env
->segs
[R_SS
].selector
, env
->regs
[R_ESP
]);
1181 if (intno
== 0x0e) {
1182 qemu_log(" CR2=" TARGET_FMT_lx
, env
->cr
[2]);
1184 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx
, env
->regs
[R_EAX
]);
1187 log_cpu_state(CPU(cpu
), CPU_DUMP_CCOP
);
1194 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
1195 for (i
= 0; i
< 16; i
++) {
1196 qemu_log(" %02x", ldub(ptr
+ i
));
1204 if (env
->cr
[0] & CR0_PE_MASK
) {
1205 #if !defined(CONFIG_USER_ONLY)
1206 if (env
->hflags
& HF_SVMI_MASK
) {
1207 handle_even_inj(env
, intno
, is_int
, error_code
, is_hw
, 0);
1210 #ifdef TARGET_X86_64
1211 if (env
->hflags
& HF_LMA_MASK
) {
1212 do_interrupt64(env
, intno
, is_int
, error_code
, next_eip
, is_hw
);
1216 do_interrupt_protected(env
, intno
, is_int
, error_code
, next_eip
,
1220 #if !defined(CONFIG_USER_ONLY)
1221 if (env
->hflags
& HF_SVMI_MASK
) {
1222 handle_even_inj(env
, intno
, is_int
, error_code
, is_hw
, 1);
1225 do_interrupt_real(env
, intno
, is_int
, error_code
, next_eip
);
1228 #if !defined(CONFIG_USER_ONLY)
1229 if (env
->hflags
& HF_SVMI_MASK
) {
1230 CPUState
*cs
= CPU(cpu
);
1231 uint32_t event_inj
= ldl_phys(cs
->as
, env
->vm_vmcb
+
1232 offsetof(struct vmcb
,
1233 control
.event_inj
));
1236 env
->vm_vmcb
+ offsetof(struct vmcb
, control
.event_inj
),
1237 event_inj
& ~SVM_EVTINJ_VALID
);
1242 void x86_cpu_do_interrupt(CPUState
*cs
)
1244 X86CPU
*cpu
= X86_CPU(cs
);
1245 CPUX86State
*env
= &cpu
->env
;
1247 #if defined(CONFIG_USER_ONLY)
1248 /* if user mode only, we simulate a fake exception
1249 which will be handled outside the cpu execution
1251 do_interrupt_user(env
, env
->exception_index
,
1252 env
->exception_is_int
,
1254 env
->exception_next_eip
);
1255 /* successfully delivered */
1256 env
->old_exception
= -1;
1258 /* simulate a real cpu exception. On i386, it can
1259 trigger new exceptions, but we do not handle
1260 double or triple faults yet. */
1261 do_interrupt_all(cpu
, env
->exception_index
,
1262 env
->exception_is_int
,
1264 env
->exception_next_eip
, 0);
1265 /* successfully delivered */
1266 env
->old_exception
= -1;
1270 void do_interrupt_x86_hardirq(CPUX86State
*env
, int intno
, int is_hw
)
1272 do_interrupt_all(x86_env_get_cpu(env
), intno
, 0, 0, 0, is_hw
);
1275 void helper_enter_level(CPUX86State
*env
, int level
, int data32
,
1279 uint32_t esp_mask
, esp
, ebp
;
1281 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1282 ssp
= env
->segs
[R_SS
].base
;
1283 ebp
= env
->regs
[R_EBP
];
1284 esp
= env
->regs
[R_ESP
];
1291 cpu_stl_data(env
, ssp
+ (esp
& esp_mask
),
1292 cpu_ldl_data(env
, ssp
+ (ebp
& esp_mask
)));
1295 cpu_stl_data(env
, ssp
+ (esp
& esp_mask
), t1
);
1302 cpu_stw_data(env
, ssp
+ (esp
& esp_mask
),
1303 cpu_lduw_data(env
, ssp
+ (ebp
& esp_mask
)));
1306 cpu_stw_data(env
, ssp
+ (esp
& esp_mask
), t1
);
1310 #ifdef TARGET_X86_64
1311 void helper_enter64_level(CPUX86State
*env
, int level
, int data64
,
1314 target_ulong esp
, ebp
;
1316 ebp
= env
->regs
[R_EBP
];
1317 esp
= env
->regs
[R_ESP
];
1325 cpu_stq_data(env
, esp
, cpu_ldq_data(env
, ebp
));
1328 cpu_stq_data(env
, esp
, t1
);
1335 cpu_stw_data(env
, esp
, cpu_lduw_data(env
, ebp
));
1338 cpu_stw_data(env
, esp
, t1
);
1343 void helper_lldt(CPUX86State
*env
, int selector
)
1347 int index
, entry_limit
;
1351 if ((selector
& 0xfffc) == 0) {
1352 /* XXX: NULL selector case: invalid LDT */
1356 if (selector
& 0x4) {
1357 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1360 index
= selector
& ~7;
1361 #ifdef TARGET_X86_64
1362 if (env
->hflags
& HF_LMA_MASK
) {
1369 if ((index
+ entry_limit
) > dt
->limit
) {
1370 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1372 ptr
= dt
->base
+ index
;
1373 e1
= cpu_ldl_kernel(env
, ptr
);
1374 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
1375 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2) {
1376 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1378 if (!(e2
& DESC_P_MASK
)) {
1379 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
1381 #ifdef TARGET_X86_64
1382 if (env
->hflags
& HF_LMA_MASK
) {
1385 e3
= cpu_ldl_kernel(env
, ptr
+ 8);
1386 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1387 env
->ldt
.base
|= (target_ulong
)e3
<< 32;
1391 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1394 env
->ldt
.selector
= selector
;
1397 void helper_ltr(CPUX86State
*env
, int selector
)
1401 int index
, type
, entry_limit
;
1405 if ((selector
& 0xfffc) == 0) {
1406 /* NULL selector case: invalid TR */
1411 if (selector
& 0x4) {
1412 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1415 index
= selector
& ~7;
1416 #ifdef TARGET_X86_64
1417 if (env
->hflags
& HF_LMA_MASK
) {
1424 if ((index
+ entry_limit
) > dt
->limit
) {
1425 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1427 ptr
= dt
->base
+ index
;
1428 e1
= cpu_ldl_kernel(env
, ptr
);
1429 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
1430 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1431 if ((e2
& DESC_S_MASK
) ||
1432 (type
!= 1 && type
!= 9)) {
1433 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1435 if (!(e2
& DESC_P_MASK
)) {
1436 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
1438 #ifdef TARGET_X86_64
1439 if (env
->hflags
& HF_LMA_MASK
) {
1442 e3
= cpu_ldl_kernel(env
, ptr
+ 8);
1443 e4
= cpu_ldl_kernel(env
, ptr
+ 12);
1444 if ((e4
>> DESC_TYPE_SHIFT
) & 0xf) {
1445 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1447 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1448 env
->tr
.base
|= (target_ulong
)e3
<< 32;
1452 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1454 e2
|= DESC_TSS_BUSY_MASK
;
1455 cpu_stl_kernel(env
, ptr
+ 4, e2
);
1457 env
->tr
.selector
= selector
;
1460 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1461 void helper_load_seg(CPUX86State
*env
, int seg_reg
, int selector
)
1470 cpl
= env
->hflags
& HF_CPL_MASK
;
1471 if ((selector
& 0xfffc) == 0) {
1472 /* null selector case */
1474 #ifdef TARGET_X86_64
1475 && (!(env
->hflags
& HF_CS64_MASK
) || cpl
== 3)
1478 raise_exception_err(env
, EXCP0D_GPF
, 0);
1480 cpu_x86_load_seg_cache(env
, seg_reg
, selector
, 0, 0, 0);
1483 if (selector
& 0x4) {
1488 index
= selector
& ~7;
1489 if ((index
+ 7) > dt
->limit
) {
1490 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1492 ptr
= dt
->base
+ index
;
1493 e1
= cpu_ldl_kernel(env
, ptr
);
1494 e2
= cpu_ldl_kernel(env
, ptr
+ 4);
1496 if (!(e2
& DESC_S_MASK
)) {
1497 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1500 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1501 if (seg_reg
== R_SS
) {
1502 /* must be writable segment */
1503 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
)) {
1504 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1506 if (rpl
!= cpl
|| dpl
!= cpl
) {
1507 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1510 /* must be readable segment */
1511 if ((e2
& (DESC_CS_MASK
| DESC_R_MASK
)) == DESC_CS_MASK
) {
1512 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1515 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1516 /* if not conforming code, test rights */
1517 if (dpl
< cpl
|| dpl
< rpl
) {
1518 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1523 if (!(e2
& DESC_P_MASK
)) {
1524 if (seg_reg
== R_SS
) {
1525 raise_exception_err(env
, EXCP0C_STACK
, selector
& 0xfffc);
1527 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
1531 /* set the access bit if not already set */
1532 if (!(e2
& DESC_A_MASK
)) {
1534 cpu_stl_kernel(env
, ptr
+ 4, e2
);
1537 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
1538 get_seg_base(e1
, e2
),
1539 get_seg_limit(e1
, e2
),
1542 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1543 selector
, (unsigned long)sc
->base
, sc
->limit
, sc
->flags
);
1548 /* protected mode jump */
1549 void helper_ljmp_protected(CPUX86State
*env
, int new_cs
, target_ulong new_eip
,
1550 int next_eip_addend
)
1553 uint32_t e1
, e2
, cpl
, dpl
, rpl
, limit
;
1554 target_ulong next_eip
;
1556 if ((new_cs
& 0xfffc) == 0) {
1557 raise_exception_err(env
, EXCP0D_GPF
, 0);
1559 if (load_segment(env
, &e1
, &e2
, new_cs
) != 0) {
1560 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1562 cpl
= env
->hflags
& HF_CPL_MASK
;
1563 if (e2
& DESC_S_MASK
) {
1564 if (!(e2
& DESC_CS_MASK
)) {
1565 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1567 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1568 if (e2
& DESC_C_MASK
) {
1569 /* conforming code segment */
1571 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1574 /* non conforming code segment */
1577 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1580 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1583 if (!(e2
& DESC_P_MASK
)) {
1584 raise_exception_err(env
, EXCP0B_NOSEG
, new_cs
& 0xfffc);
1586 limit
= get_seg_limit(e1
, e2
);
1587 if (new_eip
> limit
&&
1588 !(env
->hflags
& HF_LMA_MASK
) && !(e2
& DESC_L_MASK
)) {
1589 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1591 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1592 get_seg_base(e1
, e2
), limit
, e2
);
1595 /* jump to call or task gate */
1596 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1598 cpl
= env
->hflags
& HF_CPL_MASK
;
1599 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1601 case 1: /* 286 TSS */
1602 case 9: /* 386 TSS */
1603 case 5: /* task gate */
1604 if (dpl
< cpl
|| dpl
< rpl
) {
1605 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1607 next_eip
= env
->eip
+ next_eip_addend
;
1608 switch_tss(env
, new_cs
, e1
, e2
, SWITCH_TSS_JMP
, next_eip
);
1609 CC_OP
= CC_OP_EFLAGS
;
1611 case 4: /* 286 call gate */
1612 case 12: /* 386 call gate */
1613 if ((dpl
< cpl
) || (dpl
< rpl
)) {
1614 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1616 if (!(e2
& DESC_P_MASK
)) {
1617 raise_exception_err(env
, EXCP0B_NOSEG
, new_cs
& 0xfffc);
1620 new_eip
= (e1
& 0xffff);
1622 new_eip
|= (e2
& 0xffff0000);
1624 if (load_segment(env
, &e1
, &e2
, gate_cs
) != 0) {
1625 raise_exception_err(env
, EXCP0D_GPF
, gate_cs
& 0xfffc);
1627 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1628 /* must be code segment */
1629 if (((e2
& (DESC_S_MASK
| DESC_CS_MASK
)) !=
1630 (DESC_S_MASK
| DESC_CS_MASK
))) {
1631 raise_exception_err(env
, EXCP0D_GPF
, gate_cs
& 0xfffc);
1633 if (((e2
& DESC_C_MASK
) && (dpl
> cpl
)) ||
1634 (!(e2
& DESC_C_MASK
) && (dpl
!= cpl
))) {
1635 raise_exception_err(env
, EXCP0D_GPF
, gate_cs
& 0xfffc);
1637 if (!(e2
& DESC_P_MASK
)) {
1638 raise_exception_err(env
, EXCP0D_GPF
, gate_cs
& 0xfffc);
1640 limit
= get_seg_limit(e1
, e2
);
1641 if (new_eip
> limit
) {
1642 raise_exception_err(env
, EXCP0D_GPF
, 0);
1644 cpu_x86_load_seg_cache(env
, R_CS
, (gate_cs
& 0xfffc) | cpl
,
1645 get_seg_base(e1
, e2
), limit
, e2
);
1649 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1655 /* real mode call */
1656 void helper_lcall_real(CPUX86State
*env
, int new_cs
, target_ulong new_eip1
,
1657 int shift
, int next_eip
)
1660 uint32_t esp
, esp_mask
;
1664 esp
= env
->regs
[R_ESP
];
1665 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1666 ssp
= env
->segs
[R_SS
].base
;
1668 PUSHL(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1669 PUSHL(ssp
, esp
, esp_mask
, next_eip
);
1671 PUSHW(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1672 PUSHW(ssp
, esp
, esp_mask
, next_eip
);
1675 SET_ESP(esp
, esp_mask
);
1677 env
->segs
[R_CS
].selector
= new_cs
;
1678 env
->segs
[R_CS
].base
= (new_cs
<< 4);
1681 /* protected mode call */
1682 void helper_lcall_protected(CPUX86State
*env
, int new_cs
, target_ulong new_eip
,
1683 int shift
, int next_eip_addend
)
1686 uint32_t e1
, e2
, cpl
, dpl
, rpl
, selector
, offset
, param_count
;
1687 uint32_t ss
= 0, ss_e1
= 0, ss_e2
= 0, sp
, type
, ss_dpl
, sp_mask
;
1688 uint32_t val
, limit
, old_sp_mask
;
1689 target_ulong ssp
, old_ssp
, next_eip
;
1691 next_eip
= env
->eip
+ next_eip_addend
;
1692 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs
, (uint32_t)new_eip
, shift
);
1693 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env
)));
1694 if ((new_cs
& 0xfffc) == 0) {
1695 raise_exception_err(env
, EXCP0D_GPF
, 0);
1697 if (load_segment(env
, &e1
, &e2
, new_cs
) != 0) {
1698 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1700 cpl
= env
->hflags
& HF_CPL_MASK
;
1701 LOG_PCALL("desc=%08x:%08x\n", e1
, e2
);
1702 if (e2
& DESC_S_MASK
) {
1703 if (!(e2
& DESC_CS_MASK
)) {
1704 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1706 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1707 if (e2
& DESC_C_MASK
) {
1708 /* conforming code segment */
1710 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1713 /* non conforming code segment */
1716 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1719 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1722 if (!(e2
& DESC_P_MASK
)) {
1723 raise_exception_err(env
, EXCP0B_NOSEG
, new_cs
& 0xfffc);
1726 #ifdef TARGET_X86_64
1727 /* XXX: check 16/32 bit cases in long mode */
1732 rsp
= env
->regs
[R_ESP
];
1733 PUSHQ(rsp
, env
->segs
[R_CS
].selector
);
1734 PUSHQ(rsp
, next_eip
);
1735 /* from this point, not restartable */
1736 env
->regs
[R_ESP
] = rsp
;
1737 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1738 get_seg_base(e1
, e2
),
1739 get_seg_limit(e1
, e2
), e2
);
1744 sp
= env
->regs
[R_ESP
];
1745 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1746 ssp
= env
->segs
[R_SS
].base
;
1748 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1749 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1751 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1752 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1755 limit
= get_seg_limit(e1
, e2
);
1756 if (new_eip
> limit
) {
1757 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1759 /* from this point, not restartable */
1760 SET_ESP(sp
, sp_mask
);
1761 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1762 get_seg_base(e1
, e2
), limit
, e2
);
1766 /* check gate type */
1767 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
1768 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1771 case 1: /* available 286 TSS */
1772 case 9: /* available 386 TSS */
1773 case 5: /* task gate */
1774 if (dpl
< cpl
|| dpl
< rpl
) {
1775 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1777 switch_tss(env
, new_cs
, e1
, e2
, SWITCH_TSS_CALL
, next_eip
);
1778 CC_OP
= CC_OP_EFLAGS
;
1780 case 4: /* 286 call gate */
1781 case 12: /* 386 call gate */
1784 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1789 if (dpl
< cpl
|| dpl
< rpl
) {
1790 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
1792 /* check valid bit */
1793 if (!(e2
& DESC_P_MASK
)) {
1794 raise_exception_err(env
, EXCP0B_NOSEG
, new_cs
& 0xfffc);
1796 selector
= e1
>> 16;
1797 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
1798 param_count
= e2
& 0x1f;
1799 if ((selector
& 0xfffc) == 0) {
1800 raise_exception_err(env
, EXCP0D_GPF
, 0);
1803 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
1804 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1806 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
))) {
1807 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1809 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1811 raise_exception_err(env
, EXCP0D_GPF
, selector
& 0xfffc);
1813 if (!(e2
& DESC_P_MASK
)) {
1814 raise_exception_err(env
, EXCP0B_NOSEG
, selector
& 0xfffc);
1817 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
1818 /* to inner privilege */
1819 get_ss_esp_from_tss(env
, &ss
, &sp
, dpl
);
1820 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1821 TARGET_FMT_lx
"\n", ss
, sp
, param_count
,
1823 if ((ss
& 0xfffc) == 0) {
1824 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
1826 if ((ss
& 3) != dpl
) {
1827 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
1829 if (load_segment(env
, &ss_e1
, &ss_e2
, ss
) != 0) {
1830 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
1832 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1833 if (ss_dpl
!= dpl
) {
1834 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
1836 if (!(ss_e2
& DESC_S_MASK
) ||
1837 (ss_e2
& DESC_CS_MASK
) ||
1838 !(ss_e2
& DESC_W_MASK
)) {
1839 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
1841 if (!(ss_e2
& DESC_P_MASK
)) {
1842 raise_exception_err(env
, EXCP0A_TSS
, ss
& 0xfffc);
1845 /* push_size = ((param_count * 2) + 8) << shift; */
1847 old_sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1848 old_ssp
= env
->segs
[R_SS
].base
;
1850 sp_mask
= get_sp_mask(ss_e2
);
1851 ssp
= get_seg_base(ss_e1
, ss_e2
);
1853 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1854 PUSHL(ssp
, sp
, sp_mask
, env
->regs
[R_ESP
]);
1855 for (i
= param_count
- 1; i
>= 0; i
--) {
1856 val
= cpu_ldl_kernel(env
, old_ssp
+
1857 ((env
->regs
[R_ESP
] + i
* 4) &
1859 PUSHL(ssp
, sp
, sp_mask
, val
);
1862 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1863 PUSHW(ssp
, sp
, sp_mask
, env
->regs
[R_ESP
]);
1864 for (i
= param_count
- 1; i
>= 0; i
--) {
1865 val
= cpu_lduw_kernel(env
, old_ssp
+
1866 ((env
->regs
[R_ESP
] + i
* 2) &
1868 PUSHW(ssp
, sp
, sp_mask
, val
);
1873 /* to same privilege */
1874 sp
= env
->regs
[R_ESP
];
1875 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1876 ssp
= env
->segs
[R_SS
].base
;
1877 /* push_size = (4 << shift); */
1882 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1883 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1885 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1886 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1889 /* from this point, not restartable */
1892 ss
= (ss
& ~3) | dpl
;
1893 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
1895 get_seg_limit(ss_e1
, ss_e2
),
1899 selector
= (selector
& ~3) | dpl
;
1900 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
1901 get_seg_base(e1
, e2
),
1902 get_seg_limit(e1
, e2
),
1904 cpu_x86_set_cpl(env
, dpl
);
1905 SET_ESP(sp
, sp_mask
);
1910 /* real and vm86 mode iret */
1911 void helper_iret_real(CPUX86State
*env
, int shift
)
1913 uint32_t sp
, new_cs
, new_eip
, new_eflags
, sp_mask
;
1917 sp_mask
= 0xffff; /* XXXX: use SS segment size? */
1918 sp
= env
->regs
[R_ESP
];
1919 ssp
= env
->segs
[R_SS
].base
;
1922 POPL(ssp
, sp
, sp_mask
, new_eip
);
1923 POPL(ssp
, sp
, sp_mask
, new_cs
);
1925 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1928 POPW(ssp
, sp
, sp_mask
, new_eip
);
1929 POPW(ssp
, sp
, sp_mask
, new_cs
);
1930 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1932 env
->regs
[R_ESP
] = (env
->regs
[R_ESP
] & ~sp_mask
) | (sp
& sp_mask
);
1933 env
->segs
[R_CS
].selector
= new_cs
;
1934 env
->segs
[R_CS
].base
= (new_cs
<< 4);
1936 if (env
->eflags
& VM_MASK
) {
1937 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| RF_MASK
|
1940 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| IOPL_MASK
|
1944 eflags_mask
&= 0xffff;
1946 cpu_load_eflags(env
, new_eflags
, eflags_mask
);
1947 env
->hflags2
&= ~HF2_NMI_MASK
;
1950 static inline void validate_seg(CPUX86State
*env
, int seg_reg
, int cpl
)
1955 /* XXX: on x86_64, we do not want to nullify FS and GS because
1956 they may still contain a valid base. I would be interested to
1957 know how a real x86_64 CPU behaves */
1958 if ((seg_reg
== R_FS
|| seg_reg
== R_GS
) &&
1959 (env
->segs
[seg_reg
].selector
& 0xfffc) == 0) {
1963 e2
= env
->segs
[seg_reg
].flags
;
1964 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1965 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1966 /* data or non conforming code segment */
1968 cpu_x86_load_seg_cache(env
, seg_reg
, 0, 0, 0, 0);
1973 /* protected mode iret */
1974 static inline void helper_ret_protected(CPUX86State
*env
, int shift
,
1975 int is_iret
, int addend
)
1977 uint32_t new_cs
, new_eflags
, new_ss
;
1978 uint32_t new_es
, new_ds
, new_fs
, new_gs
;
1979 uint32_t e1
, e2
, ss_e1
, ss_e2
;
1980 int cpl
, dpl
, rpl
, eflags_mask
, iopl
;
1981 target_ulong ssp
, sp
, new_eip
, new_esp
, sp_mask
;
1983 #ifdef TARGET_X86_64
1989 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1991 sp
= env
->regs
[R_ESP
];
1992 ssp
= env
->segs
[R_SS
].base
;
1993 new_eflags
= 0; /* avoid warning */
1994 #ifdef TARGET_X86_64
2000 POPQ(sp
, new_eflags
);
2007 POPL(ssp
, sp
, sp_mask
, new_eip
);
2008 POPL(ssp
, sp
, sp_mask
, new_cs
);
2011 POPL(ssp
, sp
, sp_mask
, new_eflags
);
2012 if (new_eflags
& VM_MASK
) {
2013 goto return_to_vm86
;
2018 POPW(ssp
, sp
, sp_mask
, new_eip
);
2019 POPW(ssp
, sp
, sp_mask
, new_cs
);
2021 POPW(ssp
, sp
, sp_mask
, new_eflags
);
2025 LOG_PCALL("lret new %04x:" TARGET_FMT_lx
" s=%d addend=0x%x\n",
2026 new_cs
, new_eip
, shift
, addend
);
2027 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env
)));
2028 if ((new_cs
& 0xfffc) == 0) {
2029 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
2031 if (load_segment(env
, &e1
, &e2
, new_cs
) != 0) {
2032 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
2034 if (!(e2
& DESC_S_MASK
) ||
2035 !(e2
& DESC_CS_MASK
)) {
2036 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
2038 cpl
= env
->hflags
& HF_CPL_MASK
;
2041 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
2043 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2044 if (e2
& DESC_C_MASK
) {
2046 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
2050 raise_exception_err(env
, EXCP0D_GPF
, new_cs
& 0xfffc);
2053 if (!(e2
& DESC_P_MASK
)) {
2054 raise_exception_err(env
, EXCP0B_NOSEG
, new_cs
& 0xfffc);
2058 if (rpl
== cpl
&& (!(env
->hflags
& HF_CS64_MASK
) ||
2059 ((env
->hflags
& HF_CS64_MASK
) && !is_iret
))) {
2060 /* return to same privilege level */
2061 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
2062 get_seg_base(e1
, e2
),
2063 get_seg_limit(e1
, e2
),
2066 /* return to different privilege level */
2067 #ifdef TARGET_X86_64
2077 POPL(ssp
, sp
, sp_mask
, new_esp
);
2078 POPL(ssp
, sp
, sp_mask
, new_ss
);
2082 POPW(ssp
, sp
, sp_mask
, new_esp
);
2083 POPW(ssp
, sp
, sp_mask
, new_ss
);
2086 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx
"\n",
2088 if ((new_ss
& 0xfffc) == 0) {
2089 #ifdef TARGET_X86_64
2090 /* NULL ss is allowed in long mode if cpl != 3 */
2091 /* XXX: test CS64? */
2092 if ((env
->hflags
& HF_LMA_MASK
) && rpl
!= 3) {
2093 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
2095 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2096 DESC_S_MASK
| (rpl
<< DESC_DPL_SHIFT
) |
2097 DESC_W_MASK
| DESC_A_MASK
);
2098 ss_e2
= DESC_B_MASK
; /* XXX: should not be needed? */
2102 raise_exception_err(env
, EXCP0D_GPF
, 0);
2105 if ((new_ss
& 3) != rpl
) {
2106 raise_exception_err(env
, EXCP0D_GPF
, new_ss
& 0xfffc);
2108 if (load_segment(env
, &ss_e1
, &ss_e2
, new_ss
) != 0) {
2109 raise_exception_err(env
, EXCP0D_GPF
, new_ss
& 0xfffc);
2111 if (!(ss_e2
& DESC_S_MASK
) ||
2112 (ss_e2
& DESC_CS_MASK
) ||
2113 !(ss_e2
& DESC_W_MASK
)) {
2114 raise_exception_err(env
, EXCP0D_GPF
, new_ss
& 0xfffc);
2116 dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
2118 raise_exception_err(env
, EXCP0D_GPF
, new_ss
& 0xfffc);
2120 if (!(ss_e2
& DESC_P_MASK
)) {
2121 raise_exception_err(env
, EXCP0B_NOSEG
, new_ss
& 0xfffc);
2123 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
2124 get_seg_base(ss_e1
, ss_e2
),
2125 get_seg_limit(ss_e1
, ss_e2
),
2129 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
2130 get_seg_base(e1
, e2
),
2131 get_seg_limit(e1
, e2
),
2133 cpu_x86_set_cpl(env
, rpl
);
2135 #ifdef TARGET_X86_64
2136 if (env
->hflags
& HF_CS64_MASK
) {
2141 sp_mask
= get_sp_mask(ss_e2
);
2144 /* validate data segments */
2145 validate_seg(env
, R_ES
, rpl
);
2146 validate_seg(env
, R_DS
, rpl
);
2147 validate_seg(env
, R_FS
, rpl
);
2148 validate_seg(env
, R_GS
, rpl
);
2152 SET_ESP(sp
, sp_mask
);
2155 /* NOTE: 'cpl' is the _old_ CPL */
2156 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| RF_MASK
| NT_MASK
;
2158 eflags_mask
|= IOPL_MASK
;
2160 iopl
= (env
->eflags
>> IOPL_SHIFT
) & 3;
2162 eflags_mask
|= IF_MASK
;
2165 eflags_mask
&= 0xffff;
2167 cpu_load_eflags(env
, new_eflags
, eflags_mask
);
2172 POPL(ssp
, sp
, sp_mask
, new_esp
);
2173 POPL(ssp
, sp
, sp_mask
, new_ss
);
2174 POPL(ssp
, sp
, sp_mask
, new_es
);
2175 POPL(ssp
, sp
, sp_mask
, new_ds
);
2176 POPL(ssp
, sp
, sp_mask
, new_fs
);
2177 POPL(ssp
, sp
, sp_mask
, new_gs
);
2179 /* modify processor state */
2180 cpu_load_eflags(env
, new_eflags
, TF_MASK
| AC_MASK
| ID_MASK
|
2181 IF_MASK
| IOPL_MASK
| VM_MASK
| NT_MASK
| VIF_MASK
|
2183 load_seg_vm(env
, R_CS
, new_cs
& 0xffff);
2184 cpu_x86_set_cpl(env
, 3);
2185 load_seg_vm(env
, R_SS
, new_ss
& 0xffff);
2186 load_seg_vm(env
, R_ES
, new_es
& 0xffff);
2187 load_seg_vm(env
, R_DS
, new_ds
& 0xffff);
2188 load_seg_vm(env
, R_FS
, new_fs
& 0xffff);
2189 load_seg_vm(env
, R_GS
, new_gs
& 0xffff);
2191 env
->eip
= new_eip
& 0xffff;
2192 env
->regs
[R_ESP
] = new_esp
;
2195 void helper_iret_protected(CPUX86State
*env
, int shift
, int next_eip
)
2197 int tss_selector
, type
;
2200 /* specific case for TSS */
2201 if (env
->eflags
& NT_MASK
) {
2202 #ifdef TARGET_X86_64
2203 if (env
->hflags
& HF_LMA_MASK
) {
2204 raise_exception_err(env
, EXCP0D_GPF
, 0);
2207 tss_selector
= cpu_lduw_kernel(env
, env
->tr
.base
+ 0);
2208 if (tss_selector
& 4) {
2209 raise_exception_err(env
, EXCP0A_TSS
, tss_selector
& 0xfffc);
2211 if (load_segment(env
, &e1
, &e2
, tss_selector
) != 0) {
2212 raise_exception_err(env
, EXCP0A_TSS
, tss_selector
& 0xfffc);
2214 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x17;
2215 /* NOTE: we check both segment and busy TSS */
2217 raise_exception_err(env
, EXCP0A_TSS
, tss_selector
& 0xfffc);
2219 switch_tss(env
, tss_selector
, e1
, e2
, SWITCH_TSS_IRET
, next_eip
);
2221 helper_ret_protected(env
, shift
, 1, 0);
2223 env
->hflags2
&= ~HF2_NMI_MASK
;
2226 void helper_lret_protected(CPUX86State
*env
, int shift
, int addend
)
2228 helper_ret_protected(env
, shift
, 0, addend
);
2231 void helper_sysenter(CPUX86State
*env
)
2233 if (env
->sysenter_cs
== 0) {
2234 raise_exception_err(env
, EXCP0D_GPF
, 0);
2236 env
->eflags
&= ~(VM_MASK
| IF_MASK
| RF_MASK
);
2237 cpu_x86_set_cpl(env
, 0);
2239 #ifdef TARGET_X86_64
2240 if (env
->hflags
& HF_LMA_MASK
) {
2241 cpu_x86_load_seg_cache(env
, R_CS
, env
->sysenter_cs
& 0xfffc,
2243 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2245 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
|
2250 cpu_x86_load_seg_cache(env
, R_CS
, env
->sysenter_cs
& 0xfffc,
2252 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2254 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
2256 cpu_x86_load_seg_cache(env
, R_SS
, (env
->sysenter_cs
+ 8) & 0xfffc,
2258 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2260 DESC_W_MASK
| DESC_A_MASK
);
2261 env
->regs
[R_ESP
] = env
->sysenter_esp
;
2262 env
->eip
= env
->sysenter_eip
;
2265 void helper_sysexit(CPUX86State
*env
, int dflag
)
2269 cpl
= env
->hflags
& HF_CPL_MASK
;
2270 if (env
->sysenter_cs
== 0 || cpl
!= 0) {
2271 raise_exception_err(env
, EXCP0D_GPF
, 0);
2273 cpu_x86_set_cpl(env
, 3);
2274 #ifdef TARGET_X86_64
2276 cpu_x86_load_seg_cache(env
, R_CS
, ((env
->sysenter_cs
+ 32) & 0xfffc) |
2278 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2279 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
2280 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
|
2282 cpu_x86_load_seg_cache(env
, R_SS
, ((env
->sysenter_cs
+ 40) & 0xfffc) |
2284 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2285 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
2286 DESC_W_MASK
| DESC_A_MASK
);
2290 cpu_x86_load_seg_cache(env
, R_CS
, ((env
->sysenter_cs
+ 16) & 0xfffc) |
2292 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2293 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
2294 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
2295 cpu_x86_load_seg_cache(env
, R_SS
, ((env
->sysenter_cs
+ 24) & 0xfffc) |
2297 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2298 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
2299 DESC_W_MASK
| DESC_A_MASK
);
2301 env
->regs
[R_ESP
] = env
->regs
[R_ECX
];
2302 env
->eip
= env
->regs
[R_EDX
];
2305 target_ulong
helper_lsl(CPUX86State
*env
, target_ulong selector1
)
2308 uint32_t e1
, e2
, eflags
, selector
;
2309 int rpl
, dpl
, cpl
, type
;
2311 selector
= selector1
& 0xffff;
2312 eflags
= cpu_cc_compute_all(env
, CC_OP
);
2313 if ((selector
& 0xfffc) == 0) {
2316 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
2320 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2321 cpl
= env
->hflags
& HF_CPL_MASK
;
2322 if (e2
& DESC_S_MASK
) {
2323 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
2326 if (dpl
< cpl
|| dpl
< rpl
) {
2331 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
2342 if (dpl
< cpl
|| dpl
< rpl
) {
2344 CC_SRC
= eflags
& ~CC_Z
;
2348 limit
= get_seg_limit(e1
, e2
);
2349 CC_SRC
= eflags
| CC_Z
;
2353 target_ulong
helper_lar(CPUX86State
*env
, target_ulong selector1
)
2355 uint32_t e1
, e2
, eflags
, selector
;
2356 int rpl
, dpl
, cpl
, type
;
2358 selector
= selector1
& 0xffff;
2359 eflags
= cpu_cc_compute_all(env
, CC_OP
);
2360 if ((selector
& 0xfffc) == 0) {
2363 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
2367 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2368 cpl
= env
->hflags
& HF_CPL_MASK
;
2369 if (e2
& DESC_S_MASK
) {
2370 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
2373 if (dpl
< cpl
|| dpl
< rpl
) {
2378 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
2392 if (dpl
< cpl
|| dpl
< rpl
) {
2394 CC_SRC
= eflags
& ~CC_Z
;
2398 CC_SRC
= eflags
| CC_Z
;
2399 return e2
& 0x00f0ff00;
2402 void helper_verr(CPUX86State
*env
, target_ulong selector1
)
2404 uint32_t e1
, e2
, eflags
, selector
;
2407 selector
= selector1
& 0xffff;
2408 eflags
= cpu_cc_compute_all(env
, CC_OP
);
2409 if ((selector
& 0xfffc) == 0) {
2412 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
2415 if (!(e2
& DESC_S_MASK
)) {
2419 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2420 cpl
= env
->hflags
& HF_CPL_MASK
;
2421 if (e2
& DESC_CS_MASK
) {
2422 if (!(e2
& DESC_R_MASK
)) {
2425 if (!(e2
& DESC_C_MASK
)) {
2426 if (dpl
< cpl
|| dpl
< rpl
) {
2431 if (dpl
< cpl
|| dpl
< rpl
) {
2433 CC_SRC
= eflags
& ~CC_Z
;
2437 CC_SRC
= eflags
| CC_Z
;
2440 void helper_verw(CPUX86State
*env
, target_ulong selector1
)
2442 uint32_t e1
, e2
, eflags
, selector
;
2445 selector
= selector1
& 0xffff;
2446 eflags
= cpu_cc_compute_all(env
, CC_OP
);
2447 if ((selector
& 0xfffc) == 0) {
2450 if (load_segment(env
, &e1
, &e2
, selector
) != 0) {
2453 if (!(e2
& DESC_S_MASK
)) {
2457 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2458 cpl
= env
->hflags
& HF_CPL_MASK
;
2459 if (e2
& DESC_CS_MASK
) {
2462 if (dpl
< cpl
|| dpl
< rpl
) {
2465 if (!(e2
& DESC_W_MASK
)) {
2467 CC_SRC
= eflags
& ~CC_Z
;
2471 CC_SRC
= eflags
| CC_Z
;
2474 #if defined(CONFIG_USER_ONLY)
2475 void cpu_x86_load_seg(CPUX86State
*env
, int seg_reg
, int selector
)
2477 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
2479 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
2480 (selector
<< 4), 0xffff, 0);
2482 helper_load_seg(env
, seg_reg
, selector
);