hw/arm/virt: introduce DEFINE_VIRT_MACHINE
[qemu/ar7.git] / tests / tcg / mips / mips32-dsp / extr_w.c
blobcf926146d54c26b793c6dcaeaeeef2c5170e720d
1 #include<stdio.h>
2 #include<assert.h>
4 int main()
6 int rt, ach, acl, dsp;
7 int result;
9 ach = 0x05;
10 acl = 0xB4CB;
11 result = 0xA0001699;
12 __asm
13 ("mthi %2, $ac1\n\t"
14 "mtlo %3, $ac1\n\t"
15 "extr.w %0, $ac1, 0x03\n\t"
16 "rddsp %1\n\t"
17 : "=r"(rt), "=r"(dsp)
18 : "r"(ach), "r"(acl)
20 dsp = (dsp >> 23) & 0x01;
21 assert(dsp == 1);
22 assert(result == rt);
24 /* Clear dspcontrol */
25 dsp = 0;
26 __asm
27 ("wrdsp %0\n\t"
29 : "r"(dsp)
32 ach = 0x01;
33 acl = 0xB4CB;
34 result = 0x10000B4C;
35 __asm
36 ("mthi %2, $ac1\n\t"
37 "mtlo %3, $ac1\n\t"
38 "extr.w %0, $ac1, 0x04\n\t"
39 "rddsp %1\n\t"
40 : "=r"(rt), "=r"(dsp)
41 : "r"(ach), "r"(acl)
43 dsp = (dsp >> 23) & 0x01;
44 assert(dsp == 0);
45 assert(result == rt);
47 /* Clear dspcontrol */
48 dsp = 0;
49 __asm
50 ("wrdsp %0\n\t"
52 : "r"(dsp)
55 ach = 0x3fffffff;
56 acl = 0x2bcdef01;
57 result = 0x7ffffffe;
58 __asm
59 ("mthi %2, $ac1\n\t"
60 "mtlo %3, $ac1\n\t"
61 "extr.w %0, $ac1, 0x1F\n\t"
62 "rddsp %1\n\t"
63 : "=r"(rt), "=r"(dsp)
64 : "r"(ach), "r"(acl)
66 dsp = (dsp >> 23) & 0x01;
67 assert(dsp == 0);
68 assert(result == rt);
70 /* Clear dspcontrol */
71 dsp = 0;
72 __asm
73 ("wrdsp %0\n\t"
75 : "r"(dsp)
78 ach = 0xFFFFFFFF;
79 acl = 0xFFFFFFFF;
80 result = 0xFFFFFFFF;
81 __asm
82 ("mthi %2, $ac1\n\t"
83 "mtlo %3, $ac1\n\t"
84 "extr.w %0, $ac1, 0x1F\n\t"
85 "rddsp %1\n\t"
86 : "=r"(rt), "=r"(dsp)
87 : "r"(ach), "r"(acl)
89 dsp = (dsp >> 23) & 0x01;
90 assert(dsp == 0);
91 assert(result == rt);
93 return 0;