hw/arm/ast2400.c

   1 /*
   2  * AST2400 SoC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/ast2400.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22
  23 #define AST2400_UART_5_BASE      0x00184000
  24 #define AST2400_IOMEM_SIZE       0x00200000
  25 #define AST2400_IOMEM_BASE       0x1E600000
  26 #define AST2400_VIC_BASE         0x1E6C0000
  27 #define AST2400_TIMER_BASE       0x1E782000
  28 #define AST2400_I2C_BASE         0x1E78A000
  29
  30 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  31 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  32
  33 /*
  34  * IO handlers: simply catch any reads/writes to IO addresses that aren't
  35  * handled by a device mapping.
  36  */
  37
  38 static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
  39 {
  40     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  41                   __func__, offset, size);
  42     return 0;
  43 }
  44
  45 static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
  46                 unsigned size)
  47 {
  48     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  49                   __func__, offset, value, size);
  50 }
  51
  52 static const MemoryRegionOps ast2400_io_ops = {
  53     .read = ast2400_io_read,
  54     .write = ast2400_io_write,
  55     .endianness = DEVICE_LITTLE_ENDIAN,
  56 };
  57
  58 static void ast2400_init(Object *obj)
  59 {
  60     AST2400State *s = AST2400(obj);
  61
  62     s->cpu = cpu_arm_init("arm926");
  63
  64     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
  65     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
  66     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
  67
  68     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
  69     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
  70     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
  71
  72     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
  73     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
  74     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
  75 }
  76
  77 static void ast2400_realize(DeviceState *dev, Error **errp)
  78 {
  79     int i;
  80     AST2400State *s = AST2400(dev);
  81     Error *err = NULL;
  82
  83     /* IO space */
  84     memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
  85             "ast2400.io", AST2400_IOMEM_SIZE);
  86     memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
  87             &s->iomem, -1);
  88
  89     /* VIC */
  90     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
  91     if (err) {
  92         error_propagate(errp, err);
  93         return;
  94     }
  95     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
  96     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
  97                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
  98     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
  99                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
 100
 101     /* Timer */
 102     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 103     if (err) {
 104         error_propagate(errp, err);
 105         return;
 106     }
 107     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
 108     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 109         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 110         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 111     }
 112
 113     /* UART - attach an 8250 to the IO space as our UART5 */
 114     if (serial_hds[0]) {
 115         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 116         serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
 117                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 118     }
 119
 120     /* I2C */
 121     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 122     if (err) {
 123         error_propagate(errp, err);
 124         return;
 125     }
 126     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);
 127     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 128                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 129 }
 130
 131 static void ast2400_class_init(ObjectClass *oc, void *data)
 132 {
 133     DeviceClass *dc = DEVICE_CLASS(oc);
 134
 135     dc->realize = ast2400_realize;
 136
 137     /*
 138      * Reason: creates an ARM CPU, thus use after free(), see
 139      * arm_cpu_class_init()
 140      */
 141     dc->cannot_destroy_with_object_finalize_yet = true;
 142 }
 143
 144 static const TypeInfo ast2400_type_info = {
 145     .name = TYPE_AST2400,
 146     .parent = TYPE_SYS_BUS_DEVICE,
 147     .instance_size = sizeof(AST2400State),
 148     .instance_init = ast2400_init,
 149     .class_init = ast2400_class_init,
 150 };
 151
 152 static void ast2400_register_types(void)
 153 {
 154     type_register_static(&ast2400_type_info);
 155 }
 156
 157 type_init(ast2400_register_types)