4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Return a "clean" address for ADDR according to TBID.
208 * This is always a fresh temporary, as we need to be able to
209 * increment this independently of a dirty write-back address.
211 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
213 TCGv_i64 clean
= new_tmp_a64(s
);
215 * In order to get the correct value in the FAR_ELx register,
216 * we must present the memory subsystem with the "dirty" address
217 * including the TBI. In system mode we can make this work via
218 * the TLB, dropping the TBI during translation. But for user-only
219 * mode we don't have that option, and must remove the top byte now.
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 typedef struct DisasCompare64
{
234 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
238 arm_test_cc(&c32
, cc
);
240 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
241 * properly. The NE/EQ comparisons are also fine with this choice. */
242 c64
->cond
= c32
.cond
;
243 c64
->value
= tcg_temp_new_i64();
244 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
249 static void a64_free_cc(DisasCompare64
*c64
)
251 tcg_temp_free_i64(c64
->value
);
254 static void gen_exception_internal(int excp
)
256 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
258 assert(excp_is_internal(excp
));
259 gen_helper_exception_internal(cpu_env
, tcg_excp
);
260 tcg_temp_free_i32(tcg_excp
);
263 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
265 gen_a64_set_pc_im(pc
);
266 gen_exception_internal(excp
);
267 s
->base
.is_jmp
= DISAS_NORETURN
;
270 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
271 uint32_t syndrome
, uint32_t target_el
)
273 gen_a64_set_pc_im(pc
);
274 gen_exception(excp
, syndrome
, target_el
);
275 s
->base
.is_jmp
= DISAS_NORETURN
;
278 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
282 gen_a64_set_pc_im(s
->pc_curr
);
283 tcg_syn
= tcg_const_i32(syndrome
);
284 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
285 tcg_temp_free_i32(tcg_syn
);
286 s
->base
.is_jmp
= DISAS_NORETURN
;
289 static void gen_step_complete_exception(DisasContext
*s
)
291 /* We just completed step of an insn. Move from Active-not-pending
292 * to Active-pending, and then also take the swstep exception.
293 * This corresponds to making the (IMPDEF) choice to prioritize
294 * swstep exceptions over asynchronous exceptions taken to an exception
295 * level where debug is disabled. This choice has the advantage that
296 * we do not need to maintain internal state corresponding to the
297 * ISV/EX syndrome bits between completion of the step and generation
298 * of the exception, and our syndrome information is always correct.
301 gen_swstep_exception(s
, 1, s
->is_ldex
);
302 s
->base
.is_jmp
= DISAS_NORETURN
;
305 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
307 /* No direct tb linking with singlestep (either QEMU's or the ARM
308 * debug architecture kind) or deterministic io
310 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
311 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
315 #ifndef CONFIG_USER_ONLY
316 /* Only link tbs from inside the same guest page */
317 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
325 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
327 TranslationBlock
*tb
;
330 if (use_goto_tb(s
, n
, dest
)) {
332 gen_a64_set_pc_im(dest
);
333 tcg_gen_exit_tb(tb
, n
);
334 s
->base
.is_jmp
= DISAS_NORETURN
;
336 gen_a64_set_pc_im(dest
);
338 gen_step_complete_exception(s
);
339 } else if (s
->base
.singlestep_enabled
) {
340 gen_exception_internal(EXCP_DEBUG
);
342 tcg_gen_lookup_and_goto_ptr();
343 s
->base
.is_jmp
= DISAS_NORETURN
;
348 void unallocated_encoding(DisasContext
*s
)
350 /* Unallocated and reserved encodings are uncategorized */
351 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
352 default_exception_el(s
));
355 static void init_tmp_a64_array(DisasContext
*s
)
357 #ifdef CONFIG_DEBUG_TCG
358 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
360 s
->tmp_a64_count
= 0;
363 static void free_tmp_a64(DisasContext
*s
)
366 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
367 tcg_temp_free_i64(s
->tmp_a64
[i
]);
369 init_tmp_a64_array(s
);
372 TCGv_i64
new_tmp_a64(DisasContext
*s
)
374 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
375 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
378 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
380 TCGv_i64 t
= new_tmp_a64(s
);
381 tcg_gen_movi_i64(t
, 0);
386 * Register access functions
388 * These functions are used for directly accessing a register in where
389 * changes to the final register value are likely to be made. If you
390 * need to use a register for temporary calculation (e.g. index type
391 * operations) use the read_* form.
393 * B1.2.1 Register mappings
395 * In instruction register encoding 31 can refer to ZR (zero register) or
396 * the SP (stack pointer) depending on context. In QEMU's case we map SP
397 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
398 * This is the point of the _sp forms.
400 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
403 return new_tmp_a64_zero(s
);
409 /* register access for when 31 == SP */
410 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
415 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
416 * representing the register contents. This TCGv is an auto-freed
417 * temporary so it need not be explicitly freed, and may be modified.
419 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
421 TCGv_i64 v
= new_tmp_a64(s
);
424 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
426 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
429 tcg_gen_movi_i64(v
, 0);
434 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
436 TCGv_i64 v
= new_tmp_a64(s
);
438 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
440 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
445 /* Return the offset into CPUARMState of a slice (from
446 * the least significant end) of FP register Qn (ie
448 * (Note that this is not the same mapping as for A32; see cpu.h)
450 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
452 return vec_reg_offset(s
, regno
, 0, size
);
455 /* Offset of the high half of the 128 bit vector Qn */
456 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
458 return vec_reg_offset(s
, regno
, 1, MO_64
);
461 /* Convenience accessors for reading and writing single and double
462 * FP registers. Writing clears the upper parts of the associated
463 * 128 bit vector register, as required by the architecture.
464 * Note that unlike the GP register accessors, the values returned
465 * by the read functions must be manually freed.
467 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
469 TCGv_i64 v
= tcg_temp_new_i64();
471 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
475 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
477 TCGv_i32 v
= tcg_temp_new_i32();
479 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
483 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
485 TCGv_i32 v
= tcg_temp_new_i32();
487 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
491 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
492 * If SVE is not enabled, then there are only 128 bits in the vector.
494 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
496 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
497 unsigned vsz
= vec_full_reg_size(s
);
499 /* Nop move, with side effect of clearing the tail. */
500 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
503 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
505 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
507 tcg_gen_st_i64(v
, cpu_env
, ofs
);
508 clear_vec_high(s
, false, reg
);
511 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
513 TCGv_i64 tmp
= tcg_temp_new_i64();
515 tcg_gen_extu_i32_i64(tmp
, v
);
516 write_fp_dreg(s
, reg
, tmp
);
517 tcg_temp_free_i64(tmp
);
520 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
522 TCGv_ptr statusptr
= tcg_temp_new_ptr();
525 /* In A64 all instructions (both FP and Neon) use the FPCR; there
526 * is no equivalent of the A32 Neon "standard FPSCR value".
527 * However half-precision operations operate under a different
528 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
531 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
533 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
535 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
539 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
540 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
541 GVecGen2Fn
*gvec_fn
, int vece
)
543 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
544 is_q
? 16 : 8, vec_full_reg_size(s
));
547 /* Expand a 2-operand + immediate AdvSIMD vector operation using
548 * an expander function.
550 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
551 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
553 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
554 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
557 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
558 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
559 GVecGen3Fn
*gvec_fn
, int vece
)
561 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
562 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
565 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
566 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
567 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
569 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
570 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
571 is_q
? 16 : 8, vec_full_reg_size(s
));
574 /* Expand a 2-operand operation using an out-of-line helper. */
575 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
576 int rn
, int data
, gen_helper_gvec_2
*fn
)
578 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
579 vec_full_reg_offset(s
, rn
),
580 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
583 /* Expand a 3-operand operation using an out-of-line helper. */
584 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
585 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
587 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
588 vec_full_reg_offset(s
, rn
),
589 vec_full_reg_offset(s
, rm
),
590 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
593 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
594 * an out-of-line helper.
596 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
597 int rm
, bool is_fp16
, int data
,
598 gen_helper_gvec_3_ptr
*fn
)
600 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
601 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
602 vec_full_reg_offset(s
, rn
),
603 vec_full_reg_offset(s
, rm
), fpst
,
604 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
605 tcg_temp_free_ptr(fpst
);
608 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
609 * than the 32 bit equivalent.
611 static inline void gen_set_NZ64(TCGv_i64 result
)
613 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
614 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
617 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
618 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
621 gen_set_NZ64(result
);
623 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
624 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
626 tcg_gen_movi_i32(cpu_CF
, 0);
627 tcg_gen_movi_i32(cpu_VF
, 0);
630 /* dest = T0 + T1; compute C, N, V and Z flags */
631 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
634 TCGv_i64 result
, flag
, tmp
;
635 result
= tcg_temp_new_i64();
636 flag
= tcg_temp_new_i64();
637 tmp
= tcg_temp_new_i64();
639 tcg_gen_movi_i64(tmp
, 0);
640 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
642 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
644 gen_set_NZ64(result
);
646 tcg_gen_xor_i64(flag
, result
, t0
);
647 tcg_gen_xor_i64(tmp
, t0
, t1
);
648 tcg_gen_andc_i64(flag
, flag
, tmp
);
649 tcg_temp_free_i64(tmp
);
650 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
652 tcg_gen_mov_i64(dest
, result
);
653 tcg_temp_free_i64(result
);
654 tcg_temp_free_i64(flag
);
656 /* 32 bit arithmetic */
657 TCGv_i32 t0_32
= tcg_temp_new_i32();
658 TCGv_i32 t1_32
= tcg_temp_new_i32();
659 TCGv_i32 tmp
= tcg_temp_new_i32();
661 tcg_gen_movi_i32(tmp
, 0);
662 tcg_gen_extrl_i64_i32(t0_32
, t0
);
663 tcg_gen_extrl_i64_i32(t1_32
, t1
);
664 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
665 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
666 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
667 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
668 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
669 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
671 tcg_temp_free_i32(tmp
);
672 tcg_temp_free_i32(t0_32
);
673 tcg_temp_free_i32(t1_32
);
677 /* dest = T0 - T1; compute C, N, V and Z flags */
678 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
681 /* 64 bit arithmetic */
682 TCGv_i64 result
, flag
, tmp
;
684 result
= tcg_temp_new_i64();
685 flag
= tcg_temp_new_i64();
686 tcg_gen_sub_i64(result
, t0
, t1
);
688 gen_set_NZ64(result
);
690 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
691 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
693 tcg_gen_xor_i64(flag
, result
, t0
);
694 tmp
= tcg_temp_new_i64();
695 tcg_gen_xor_i64(tmp
, t0
, t1
);
696 tcg_gen_and_i64(flag
, flag
, tmp
);
697 tcg_temp_free_i64(tmp
);
698 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
699 tcg_gen_mov_i64(dest
, result
);
700 tcg_temp_free_i64(flag
);
701 tcg_temp_free_i64(result
);
703 /* 32 bit arithmetic */
704 TCGv_i32 t0_32
= tcg_temp_new_i32();
705 TCGv_i32 t1_32
= tcg_temp_new_i32();
708 tcg_gen_extrl_i64_i32(t0_32
, t0
);
709 tcg_gen_extrl_i64_i32(t1_32
, t1
);
710 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
711 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
712 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
713 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
714 tmp
= tcg_temp_new_i32();
715 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
716 tcg_temp_free_i32(t0_32
);
717 tcg_temp_free_i32(t1_32
);
718 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
719 tcg_temp_free_i32(tmp
);
720 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
724 /* dest = T0 + T1 + CF; do not compute flags. */
725 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
727 TCGv_i64 flag
= tcg_temp_new_i64();
728 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
729 tcg_gen_add_i64(dest
, t0
, t1
);
730 tcg_gen_add_i64(dest
, dest
, flag
);
731 tcg_temp_free_i64(flag
);
734 tcg_gen_ext32u_i64(dest
, dest
);
738 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
739 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
742 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
743 result
= tcg_temp_new_i64();
744 cf_64
= tcg_temp_new_i64();
745 vf_64
= tcg_temp_new_i64();
746 tmp
= tcg_const_i64(0);
748 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
749 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
750 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
751 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
752 gen_set_NZ64(result
);
754 tcg_gen_xor_i64(vf_64
, result
, t0
);
755 tcg_gen_xor_i64(tmp
, t0
, t1
);
756 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
757 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
759 tcg_gen_mov_i64(dest
, result
);
761 tcg_temp_free_i64(tmp
);
762 tcg_temp_free_i64(vf_64
);
763 tcg_temp_free_i64(cf_64
);
764 tcg_temp_free_i64(result
);
766 TCGv_i32 t0_32
, t1_32
, tmp
;
767 t0_32
= tcg_temp_new_i32();
768 t1_32
= tcg_temp_new_i32();
769 tmp
= tcg_const_i32(0);
771 tcg_gen_extrl_i64_i32(t0_32
, t0
);
772 tcg_gen_extrl_i64_i32(t1_32
, t1
);
773 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
774 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
776 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
777 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
778 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
779 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
780 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
782 tcg_temp_free_i32(tmp
);
783 tcg_temp_free_i32(t1_32
);
784 tcg_temp_free_i32(t0_32
);
789 * Load/Store generators
793 * Store from GPR register to memory.
795 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
796 TCGv_i64 tcg_addr
, int size
, int memidx
,
798 unsigned int iss_srt
,
799 bool iss_sf
, bool iss_ar
)
802 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
807 syn
= syn_data_abort_with_iss(0,
813 0, 0, 0, 0, 0, false);
814 disas_set_insn_syndrome(s
, syn
);
818 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
819 TCGv_i64 tcg_addr
, int size
,
821 unsigned int iss_srt
,
822 bool iss_sf
, bool iss_ar
)
824 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
825 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
829 * Load from memory to GPR register
831 static void do_gpr_ld_memidx(DisasContext
*s
,
832 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
833 int size
, bool is_signed
,
834 bool extend
, int memidx
,
835 bool iss_valid
, unsigned int iss_srt
,
836 bool iss_sf
, bool iss_ar
)
838 MemOp memop
= s
->be_data
+ size
;
846 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
848 if (extend
&& is_signed
) {
850 tcg_gen_ext32u_i64(dest
, dest
);
856 syn
= syn_data_abort_with_iss(0,
862 0, 0, 0, 0, 0, false);
863 disas_set_insn_syndrome(s
, syn
);
867 static void do_gpr_ld(DisasContext
*s
,
868 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
869 int size
, bool is_signed
, bool extend
,
870 bool iss_valid
, unsigned int iss_srt
,
871 bool iss_sf
, bool iss_ar
)
873 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
875 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
879 * Store from FP register to memory
881 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
883 /* This writes the bottom N bits of a 128 bit wide vector to memory */
884 TCGv_i64 tmp
= tcg_temp_new_i64();
885 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
887 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
890 bool be
= s
->be_data
== MO_BE
;
891 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
893 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
894 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
896 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
897 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
899 tcg_temp_free_i64(tcg_hiaddr
);
902 tcg_temp_free_i64(tmp
);
906 * Load from memory to FP register
908 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
910 /* This always zero-extends and writes to a full 128 bit wide vector */
911 TCGv_i64 tmplo
= tcg_temp_new_i64();
912 TCGv_i64 tmphi
= NULL
;
915 MemOp memop
= s
->be_data
+ size
;
916 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
918 bool be
= s
->be_data
== MO_BE
;
921 tmphi
= tcg_temp_new_i64();
922 tcg_hiaddr
= tcg_temp_new_i64();
924 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
925 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
927 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
929 tcg_temp_free_i64(tcg_hiaddr
);
932 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
933 tcg_temp_free_i64(tmplo
);
936 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
937 tcg_temp_free_i64(tmphi
);
939 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
943 * Vector load/store helpers.
945 * The principal difference between this and a FP load is that we don't
946 * zero extend as we are filling a partial chunk of the vector register.
947 * These functions don't support 128 bit loads/stores, which would be
948 * normal load/store operations.
950 * The _i32 versions are useful when operating on 32 bit quantities
951 * (eg for floating point single or using Neon helper functions).
954 /* Get value of an element within a vector register */
955 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
956 int element
, MemOp memop
)
958 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
961 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
964 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
967 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
983 g_assert_not_reached();
987 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
988 int element
, MemOp memop
)
990 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
993 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
996 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
999 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1009 g_assert_not_reached();
1013 /* Set value of an element within a vector register */
1014 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1015 int element
, MemOp memop
)
1017 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1020 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1023 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1026 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1032 g_assert_not_reached();
1036 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1037 int destidx
, int element
, MemOp memop
)
1039 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1042 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1045 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1048 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1051 g_assert_not_reached();
1055 /* Store from vector register to memory */
1056 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1057 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1059 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1061 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1062 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1064 tcg_temp_free_i64(tcg_tmp
);
1067 /* Load from memory to vector register */
1068 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1069 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1071 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1073 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1074 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1076 tcg_temp_free_i64(tcg_tmp
);
1079 /* Check that FP/Neon access is enabled. If it is, return
1080 * true. If not, emit code to generate an appropriate exception,
1081 * and return false; the caller should not emit any code for
1082 * the instruction. Note that this check must happen after all
1083 * unallocated-encoding checks (otherwise the syndrome information
1084 * for the resulting exception will be incorrect).
1086 static inline bool fp_access_check(DisasContext
*s
)
1088 assert(!s
->fp_access_checked
);
1089 s
->fp_access_checked
= true;
1091 if (!s
->fp_excp_el
) {
1095 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1096 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1100 /* Check that SVE access is enabled. If it is, return true.
1101 * If not, emit code to generate an appropriate exception and return false.
1103 bool sve_access_check(DisasContext
*s
)
1105 if (s
->sve_excp_el
) {
1106 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1110 return fp_access_check(s
);
1114 * This utility function is for doing register extension with an
1115 * optional shift. You will likely want to pass a temporary for the
1116 * destination register. See DecodeRegExtend() in the ARM ARM.
1118 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1119 int option
, unsigned int shift
)
1121 int extsize
= extract32(option
, 0, 2);
1122 bool is_signed
= extract32(option
, 2, 1);
1127 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1130 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1133 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1142 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1145 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1157 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1161 static inline void gen_check_sp_alignment(DisasContext
*s
)
1163 /* The AArch64 architecture mandates that (if enabled via PSTATE
1164 * or SCTLR bits) there is a check that SP is 16-aligned on every
1165 * SP-relative load or store (with an exception generated if it is not).
1166 * In line with general QEMU practice regarding misaligned accesses,
1167 * we omit these checks for the sake of guest program performance.
1168 * This function is provided as a hook so we can more easily add these
1169 * checks in future (possibly as a "favour catching guest program bugs
1170 * over speed" user selectable option).
1175 * This provides a simple table based table lookup decoder. It is
1176 * intended to be used when the relevant bits for decode are too
1177 * awkwardly placed and switch/if based logic would be confusing and
1178 * deeply nested. Since it's a linear search through the table, tables
1179 * should be kept small.
1181 * It returns the first handler where insn & mask == pattern, or
1182 * NULL if there is no match.
1183 * The table is terminated by an empty mask (i.e. 0)
1185 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1188 const AArch64DecodeTable
*tptr
= table
;
1190 while (tptr
->mask
) {
1191 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1192 return tptr
->disas_fn
;
1200 * The instruction disassembly implemented here matches
1201 * the instruction encoding classifications in chapter C4
1202 * of the ARM Architecture Reference Manual (DDI0487B_a);
1203 * classification names and decode diagrams here should generally
1204 * match up with those in the manual.
1207 /* Unconditional branch (immediate)
1209 * +----+-----------+-------------------------------------+
1210 * | op | 0 0 1 0 1 | imm26 |
1211 * +----+-----------+-------------------------------------+
1213 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1215 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1217 if (insn
& (1U << 31)) {
1218 /* BL Branch with link */
1219 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1222 /* B Branch / BL Branch with link */
1224 gen_goto_tb(s
, 0, addr
);
1227 /* Compare and branch (immediate)
1228 * 31 30 25 24 23 5 4 0
1229 * +----+-------------+----+---------------------+--------+
1230 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1231 * +----+-------------+----+---------------------+--------+
1233 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1235 unsigned int sf
, op
, rt
;
1237 TCGLabel
*label_match
;
1240 sf
= extract32(insn
, 31, 1);
1241 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1242 rt
= extract32(insn
, 0, 5);
1243 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1245 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1246 label_match
= gen_new_label();
1249 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1250 tcg_cmp
, 0, label_match
);
1252 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1253 gen_set_label(label_match
);
1254 gen_goto_tb(s
, 1, addr
);
1257 /* Test and branch (immediate)
1258 * 31 30 25 24 23 19 18 5 4 0
1259 * +----+-------------+----+-------+-------------+------+
1260 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1261 * +----+-------------+----+-------+-------------+------+
1263 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1265 unsigned int bit_pos
, op
, rt
;
1267 TCGLabel
*label_match
;
1270 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1271 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1272 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1273 rt
= extract32(insn
, 0, 5);
1275 tcg_cmp
= tcg_temp_new_i64();
1276 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1277 label_match
= gen_new_label();
1280 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1281 tcg_cmp
, 0, label_match
);
1282 tcg_temp_free_i64(tcg_cmp
);
1283 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1284 gen_set_label(label_match
);
1285 gen_goto_tb(s
, 1, addr
);
1288 /* Conditional branch (immediate)
1289 * 31 25 24 23 5 4 3 0
1290 * +---------------+----+---------------------+----+------+
1291 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1292 * +---------------+----+---------------------+----+------+
1294 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1299 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1300 unallocated_encoding(s
);
1303 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1304 cond
= extract32(insn
, 0, 4);
1308 /* genuinely conditional branches */
1309 TCGLabel
*label_match
= gen_new_label();
1310 arm_gen_test_cc(cond
, label_match
);
1311 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1312 gen_set_label(label_match
);
1313 gen_goto_tb(s
, 1, addr
);
1315 /* 0xe and 0xf are both "always" conditions */
1316 gen_goto_tb(s
, 0, addr
);
1320 /* HINT instruction group, including various allocated HINTs */
1321 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1322 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1324 unsigned int selector
= crm
<< 3 | op2
;
1327 unallocated_encoding(s
);
1332 case 0b00000: /* NOP */
1334 case 0b00011: /* WFI */
1335 s
->base
.is_jmp
= DISAS_WFI
;
1337 case 0b00001: /* YIELD */
1338 /* When running in MTTCG we don't generate jumps to the yield and
1339 * WFE helpers as it won't affect the scheduling of other vCPUs.
1340 * If we wanted to more completely model WFE/SEV so we don't busy
1341 * spin unnecessarily we would need to do something more involved.
1343 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1344 s
->base
.is_jmp
= DISAS_YIELD
;
1347 case 0b00010: /* WFE */
1348 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1349 s
->base
.is_jmp
= DISAS_WFE
;
1352 case 0b00100: /* SEV */
1353 case 0b00101: /* SEVL */
1354 /* we treat all as NOP at least for now */
1356 case 0b00111: /* XPACLRI */
1357 if (s
->pauth_active
) {
1358 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1361 case 0b01000: /* PACIA1716 */
1362 if (s
->pauth_active
) {
1363 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1366 case 0b01010: /* PACIB1716 */
1367 if (s
->pauth_active
) {
1368 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1371 case 0b01100: /* AUTIA1716 */
1372 if (s
->pauth_active
) {
1373 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1376 case 0b01110: /* AUTIB1716 */
1377 if (s
->pauth_active
) {
1378 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1381 case 0b11000: /* PACIAZ */
1382 if (s
->pauth_active
) {
1383 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1384 new_tmp_a64_zero(s
));
1387 case 0b11001: /* PACIASP */
1388 if (s
->pauth_active
) {
1389 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1392 case 0b11010: /* PACIBZ */
1393 if (s
->pauth_active
) {
1394 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1395 new_tmp_a64_zero(s
));
1398 case 0b11011: /* PACIBSP */
1399 if (s
->pauth_active
) {
1400 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1403 case 0b11100: /* AUTIAZ */
1404 if (s
->pauth_active
) {
1405 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1406 new_tmp_a64_zero(s
));
1409 case 0b11101: /* AUTIASP */
1410 if (s
->pauth_active
) {
1411 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1414 case 0b11110: /* AUTIBZ */
1415 if (s
->pauth_active
) {
1416 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1417 new_tmp_a64_zero(s
));
1420 case 0b11111: /* AUTIBSP */
1421 if (s
->pauth_active
) {
1422 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1426 /* default specified as NOP equivalent */
1431 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1433 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1436 /* CLREX, DSB, DMB, ISB */
1437 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1438 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1443 unallocated_encoding(s
);
1454 case 1: /* MBReqTypes_Reads */
1455 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1457 case 2: /* MBReqTypes_Writes */
1458 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1460 default: /* MBReqTypes_All */
1461 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1467 /* We need to break the TB after this insn to execute
1468 * a self-modified code correctly and also to take
1469 * any pending interrupts immediately.
1472 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1476 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1477 goto do_unallocated
;
1480 * TODO: There is no speculation barrier opcode for TCG;
1481 * MB and end the TB instead.
1483 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1484 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1489 unallocated_encoding(s
);
1494 static void gen_xaflag(void)
1496 TCGv_i32 z
= tcg_temp_new_i32();
1498 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1507 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1508 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1511 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1512 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1514 /* (!C & Z) << 31 -> -(Z & ~C) */
1515 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1516 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1519 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1521 tcg_temp_free_i32(z
);
1524 static void gen_axflag(void)
1526 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1527 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1529 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1530 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1532 tcg_gen_movi_i32(cpu_NF
, 0);
1533 tcg_gen_movi_i32(cpu_VF
, 0);
1536 /* MSR (immediate) - move immediate to processor state field */
1537 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1538 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1541 int op
= op1
<< 3 | op2
;
1543 /* End the TB by default, chaining is ok. */
1544 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1547 case 0x00: /* CFINV */
1548 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1549 goto do_unallocated
;
1551 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1552 s
->base
.is_jmp
= DISAS_NEXT
;
1555 case 0x01: /* XAFlag */
1556 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1557 goto do_unallocated
;
1560 s
->base
.is_jmp
= DISAS_NEXT
;
1563 case 0x02: /* AXFlag */
1564 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1565 goto do_unallocated
;
1568 s
->base
.is_jmp
= DISAS_NEXT
;
1571 case 0x03: /* UAO */
1572 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1573 goto do_unallocated
;
1576 set_pstate_bits(PSTATE_UAO
);
1578 clear_pstate_bits(PSTATE_UAO
);
1580 t1
= tcg_const_i32(s
->current_el
);
1581 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1582 tcg_temp_free_i32(t1
);
1585 case 0x04: /* PAN */
1586 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1587 goto do_unallocated
;
1590 set_pstate_bits(PSTATE_PAN
);
1592 clear_pstate_bits(PSTATE_PAN
);
1594 t1
= tcg_const_i32(s
->current_el
);
1595 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1596 tcg_temp_free_i32(t1
);
1599 case 0x05: /* SPSel */
1600 if (s
->current_el
== 0) {
1601 goto do_unallocated
;
1603 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1604 gen_helper_msr_i_spsel(cpu_env
, t1
);
1605 tcg_temp_free_i32(t1
);
1608 case 0x1e: /* DAIFSet */
1609 t1
= tcg_const_i32(crm
);
1610 gen_helper_msr_i_daifset(cpu_env
, t1
);
1611 tcg_temp_free_i32(t1
);
1614 case 0x1f: /* DAIFClear */
1615 t1
= tcg_const_i32(crm
);
1616 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1617 tcg_temp_free_i32(t1
);
1618 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1619 s
->base
.is_jmp
= DISAS_UPDATE
;
1624 unallocated_encoding(s
);
1629 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1631 TCGv_i32 tmp
= tcg_temp_new_i32();
1632 TCGv_i32 nzcv
= tcg_temp_new_i32();
1634 /* build bit 31, N */
1635 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1636 /* build bit 30, Z */
1637 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1638 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1639 /* build bit 29, C */
1640 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1641 /* build bit 28, V */
1642 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1643 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1644 /* generate result */
1645 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1647 tcg_temp_free_i32(nzcv
);
1648 tcg_temp_free_i32(tmp
);
1651 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1653 TCGv_i32 nzcv
= tcg_temp_new_i32();
1655 /* take NZCV from R[t] */
1656 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1659 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1661 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1662 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1664 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1665 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1667 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1668 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1669 tcg_temp_free_i32(nzcv
);
1672 /* MRS - move from system register
1673 * MSR (register) - move to system register
1676 * These are all essentially the same insn in 'read' and 'write'
1677 * versions, with varying op0 fields.
1679 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1680 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1681 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1683 const ARMCPRegInfo
*ri
;
1686 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1687 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1688 crn
, crm
, op0
, op1
, op2
));
1691 /* Unknown register; this might be a guest error or a QEMU
1692 * unimplemented feature.
1694 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1695 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1696 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1697 unallocated_encoding(s
);
1701 /* Check access permissions */
1702 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1703 unallocated_encoding(s
);
1708 /* Emit code to perform further access permissions checks at
1709 * runtime; this may result in an exception.
1712 TCGv_i32 tcg_syn
, tcg_isread
;
1715 gen_a64_set_pc_im(s
->pc_curr
);
1716 tmpptr
= tcg_const_ptr(ri
);
1717 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1718 tcg_syn
= tcg_const_i32(syndrome
);
1719 tcg_isread
= tcg_const_i32(isread
);
1720 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1721 tcg_temp_free_ptr(tmpptr
);
1722 tcg_temp_free_i32(tcg_syn
);
1723 tcg_temp_free_i32(tcg_isread
);
1724 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1726 * The readfn or writefn might raise an exception;
1727 * synchronize the CPU state in case it does.
1729 gen_a64_set_pc_im(s
->pc_curr
);
1732 /* Handle special cases first */
1733 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1737 tcg_rt
= cpu_reg(s
, rt
);
1739 gen_get_nzcv(tcg_rt
);
1741 gen_set_nzcv(tcg_rt
);
1744 case ARM_CP_CURRENTEL
:
1745 /* Reads as current EL value from pstate, which is
1746 * guaranteed to be constant by the tb flags.
1748 tcg_rt
= cpu_reg(s
, rt
);
1749 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1752 /* Writes clear the aligned block of memory which rt points into. */
1753 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1754 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1759 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1761 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1765 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1769 tcg_rt
= cpu_reg(s
, rt
);
1772 if (ri
->type
& ARM_CP_CONST
) {
1773 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1774 } else if (ri
->readfn
) {
1776 tmpptr
= tcg_const_ptr(ri
);
1777 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1778 tcg_temp_free_ptr(tmpptr
);
1780 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1783 if (ri
->type
& ARM_CP_CONST
) {
1784 /* If not forbidden by access permissions, treat as WI */
1786 } else if (ri
->writefn
) {
1788 tmpptr
= tcg_const_ptr(ri
);
1789 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1790 tcg_temp_free_ptr(tmpptr
);
1792 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1796 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1797 /* I/O operations must end the TB here (whether read or write) */
1798 s
->base
.is_jmp
= DISAS_UPDATE
;
1800 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1802 * A write to any coprocessor regiser that ends a TB
1803 * must rebuild the hflags for the next TB.
1805 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1806 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1807 tcg_temp_free_i32(tcg_el
);
1809 * We default to ending the TB on a coprocessor register write,
1810 * but allow this to be suppressed by the register definition
1811 * (usually only necessary to work around guest bugs).
1813 s
->base
.is_jmp
= DISAS_UPDATE
;
1818 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1819 * +---------------------+---+-----+-----+-------+-------+-----+------+
1820 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1821 * +---------------------+---+-----+-----+-------+-------+-----+------+
1823 static void disas_system(DisasContext
*s
, uint32_t insn
)
1825 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1826 l
= extract32(insn
, 21, 1);
1827 op0
= extract32(insn
, 19, 2);
1828 op1
= extract32(insn
, 16, 3);
1829 crn
= extract32(insn
, 12, 4);
1830 crm
= extract32(insn
, 8, 4);
1831 op2
= extract32(insn
, 5, 3);
1832 rt
= extract32(insn
, 0, 5);
1835 if (l
|| rt
!= 31) {
1836 unallocated_encoding(s
);
1840 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1841 handle_hint(s
, insn
, op1
, op2
, crm
);
1843 case 3: /* CLREX, DSB, DMB, ISB */
1844 handle_sync(s
, insn
, op1
, op2
, crm
);
1846 case 4: /* MSR (immediate) */
1847 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1850 unallocated_encoding(s
);
1855 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1858 /* Exception generation
1860 * 31 24 23 21 20 5 4 2 1 0
1861 * +-----------------+-----+------------------------+-----+----+
1862 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1863 * +-----------------------+------------------------+----------+
1865 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1867 int opc
= extract32(insn
, 21, 3);
1868 int op2_ll
= extract32(insn
, 0, 5);
1869 int imm16
= extract32(insn
, 5, 16);
1874 /* For SVC, HVC and SMC we advance the single-step state
1875 * machine before taking the exception. This is architecturally
1876 * mandated, to ensure that single-stepping a system call
1877 * instruction works properly.
1882 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1883 syn_aa64_svc(imm16
), default_exception_el(s
));
1886 if (s
->current_el
== 0) {
1887 unallocated_encoding(s
);
1890 /* The pre HVC helper handles cases when HVC gets trapped
1891 * as an undefined insn by runtime configuration.
1893 gen_a64_set_pc_im(s
->pc_curr
);
1894 gen_helper_pre_hvc(cpu_env
);
1896 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1897 syn_aa64_hvc(imm16
), 2);
1900 if (s
->current_el
== 0) {
1901 unallocated_encoding(s
);
1904 gen_a64_set_pc_im(s
->pc_curr
);
1905 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1906 gen_helper_pre_smc(cpu_env
, tmp
);
1907 tcg_temp_free_i32(tmp
);
1909 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1910 syn_aa64_smc(imm16
), 3);
1913 unallocated_encoding(s
);
1919 unallocated_encoding(s
);
1923 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1927 unallocated_encoding(s
);
1930 /* HLT. This has two purposes.
1931 * Architecturally, it is an external halting debug instruction.
1932 * Since QEMU doesn't implement external debug, we treat this as
1933 * it is required for halting debug disabled: it will UNDEF.
1934 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1936 if (semihosting_enabled() && imm16
== 0xf000) {
1937 #ifndef CONFIG_USER_ONLY
1938 /* In system mode, don't allow userspace access to semihosting,
1939 * to provide some semblance of security (and for consistency
1940 * with our 32-bit semihosting).
1942 if (s
->current_el
== 0) {
1943 unsupported_encoding(s
, insn
);
1947 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1949 unsupported_encoding(s
, insn
);
1953 if (op2_ll
< 1 || op2_ll
> 3) {
1954 unallocated_encoding(s
);
1957 /* DCPS1, DCPS2, DCPS3 */
1958 unsupported_encoding(s
, insn
);
1961 unallocated_encoding(s
);
1966 /* Unconditional branch (register)
1967 * 31 25 24 21 20 16 15 10 9 5 4 0
1968 * +---------------+-------+-------+-------+------+-------+
1969 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1970 * +---------------+-------+-------+-------+------+-------+
1972 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1974 unsigned int opc
, op2
, op3
, rn
, op4
;
1975 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
1979 opc
= extract32(insn
, 21, 4);
1980 op2
= extract32(insn
, 16, 5);
1981 op3
= extract32(insn
, 10, 6);
1982 rn
= extract32(insn
, 5, 5);
1983 op4
= extract32(insn
, 0, 5);
1986 goto do_unallocated
;
1998 goto do_unallocated
;
2000 dst
= cpu_reg(s
, rn
);
2005 if (!dc_isar_feature(aa64_pauth
, s
)) {
2006 goto do_unallocated
;
2010 if (rn
!= 0x1f || op4
!= 0x1f) {
2011 goto do_unallocated
;
2014 modifier
= cpu_X
[31];
2016 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2018 goto do_unallocated
;
2020 modifier
= new_tmp_a64_zero(s
);
2022 if (s
->pauth_active
) {
2023 dst
= new_tmp_a64(s
);
2025 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2027 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2030 dst
= cpu_reg(s
, rn
);
2035 goto do_unallocated
;
2037 gen_a64_set_pc(s
, dst
);
2038 /* BLR also needs to load return address */
2040 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2046 if (!dc_isar_feature(aa64_pauth
, s
)) {
2047 goto do_unallocated
;
2049 if ((op3
& ~1) != 2) {
2050 goto do_unallocated
;
2052 btype_mod
= opc
& 1;
2053 if (s
->pauth_active
) {
2054 dst
= new_tmp_a64(s
);
2055 modifier
= cpu_reg_sp(s
, op4
);
2057 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2059 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2062 dst
= cpu_reg(s
, rn
);
2064 gen_a64_set_pc(s
, dst
);
2065 /* BLRAA also needs to load return address */
2067 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2072 if (s
->current_el
== 0) {
2073 goto do_unallocated
;
2078 goto do_unallocated
;
2080 dst
= tcg_temp_new_i64();
2081 tcg_gen_ld_i64(dst
, cpu_env
,
2082 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2085 case 2: /* ERETAA */
2086 case 3: /* ERETAB */
2087 if (!dc_isar_feature(aa64_pauth
, s
)) {
2088 goto do_unallocated
;
2090 if (rn
!= 0x1f || op4
!= 0x1f) {
2091 goto do_unallocated
;
2093 dst
= tcg_temp_new_i64();
2094 tcg_gen_ld_i64(dst
, cpu_env
,
2095 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2096 if (s
->pauth_active
) {
2097 modifier
= cpu_X
[31];
2099 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2101 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2107 goto do_unallocated
;
2109 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2113 gen_helper_exception_return(cpu_env
, dst
);
2114 tcg_temp_free_i64(dst
);
2115 /* Must exit loop to check un-masked IRQs */
2116 s
->base
.is_jmp
= DISAS_EXIT
;
2120 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2121 goto do_unallocated
;
2123 unsupported_encoding(s
, insn
);
2129 unallocated_encoding(s
);
2133 switch (btype_mod
) {
2135 if (dc_isar_feature(aa64_bti
, s
)) {
2136 /* BR to {x16,x17} or !guard -> 1, else 3. */
2137 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2142 if (dc_isar_feature(aa64_bti
, s
)) {
2143 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2148 default: /* RET or none of the above. */
2149 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2153 s
->base
.is_jmp
= DISAS_JUMP
;
2156 /* Branches, exception generating and system instructions */
2157 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2159 switch (extract32(insn
, 25, 7)) {
2160 case 0x0a: case 0x0b:
2161 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2162 disas_uncond_b_imm(s
, insn
);
2164 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2165 disas_comp_b_imm(s
, insn
);
2167 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2168 disas_test_b_imm(s
, insn
);
2170 case 0x2a: /* Conditional branch (immediate) */
2171 disas_cond_b_imm(s
, insn
);
2173 case 0x6a: /* Exception generation / System */
2174 if (insn
& (1 << 24)) {
2175 if (extract32(insn
, 22, 2) == 0) {
2176 disas_system(s
, insn
);
2178 unallocated_encoding(s
);
2184 case 0x6b: /* Unconditional branch (register) */
2185 disas_uncond_b_reg(s
, insn
);
2188 unallocated_encoding(s
);
2194 * Load/Store exclusive instructions are implemented by remembering
2195 * the value/address loaded, and seeing if these are the same
2196 * when the store is performed. This is not actually the architecturally
2197 * mandated semantics, but it works for typical guest code sequences
2198 * and avoids having to monitor regular stores.
2200 * The store exclusive uses the atomic cmpxchg primitives to avoid
2201 * races in multi-threaded linux-user and when MTTCG softmmu is
2204 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2205 TCGv_i64 addr
, int size
, bool is_pair
)
2207 int idx
= get_mem_index(s
);
2208 MemOp memop
= s
->be_data
;
2210 g_assert(size
<= 3);
2212 g_assert(size
>= 2);
2214 /* The pair must be single-copy atomic for the doubleword. */
2215 memop
|= MO_64
| MO_ALIGN
;
2216 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2217 if (s
->be_data
== MO_LE
) {
2218 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2219 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2221 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2222 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2225 /* The pair must be single-copy atomic for *each* doubleword, not
2226 the entire quadword, however it must be quadword aligned. */
2228 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2229 memop
| MO_ALIGN_16
);
2231 TCGv_i64 addr2
= tcg_temp_new_i64();
2232 tcg_gen_addi_i64(addr2
, addr
, 8);
2233 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2234 tcg_temp_free_i64(addr2
);
2236 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2237 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2240 memop
|= size
| MO_ALIGN
;
2241 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2242 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2244 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2247 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2248 TCGv_i64 addr
, int size
, int is_pair
)
2250 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2251 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2254 * [addr + datasize] = {Rt2};
2260 * env->exclusive_addr = -1;
2262 TCGLabel
*fail_label
= gen_new_label();
2263 TCGLabel
*done_label
= gen_new_label();
2266 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2268 tmp
= tcg_temp_new_i64();
2271 if (s
->be_data
== MO_LE
) {
2272 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2274 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2276 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2277 cpu_exclusive_val
, tmp
,
2279 MO_64
| MO_ALIGN
| s
->be_data
);
2280 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2281 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2282 if (!HAVE_CMPXCHG128
) {
2283 gen_helper_exit_atomic(cpu_env
);
2284 s
->base
.is_jmp
= DISAS_NORETURN
;
2285 } else if (s
->be_data
== MO_LE
) {
2286 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2291 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2296 } else if (s
->be_data
== MO_LE
) {
2297 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2298 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2300 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2301 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2304 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2305 cpu_reg(s
, rt
), get_mem_index(s
),
2306 size
| MO_ALIGN
| s
->be_data
);
2307 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2309 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2310 tcg_temp_free_i64(tmp
);
2311 tcg_gen_br(done_label
);
2313 gen_set_label(fail_label
);
2314 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2315 gen_set_label(done_label
);
2316 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2319 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2322 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2323 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2324 int memidx
= get_mem_index(s
);
2325 TCGv_i64 clean_addr
;
2328 gen_check_sp_alignment(s
);
2330 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2331 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2332 size
| MO_ALIGN
| s
->be_data
);
2335 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2338 TCGv_i64 s1
= cpu_reg(s
, rs
);
2339 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2340 TCGv_i64 t1
= cpu_reg(s
, rt
);
2341 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2342 TCGv_i64 clean_addr
;
2343 int memidx
= get_mem_index(s
);
2346 gen_check_sp_alignment(s
);
2348 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2351 TCGv_i64 cmp
= tcg_temp_new_i64();
2352 TCGv_i64 val
= tcg_temp_new_i64();
2354 if (s
->be_data
== MO_LE
) {
2355 tcg_gen_concat32_i64(val
, t1
, t2
);
2356 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2358 tcg_gen_concat32_i64(val
, t2
, t1
);
2359 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2362 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2363 MO_64
| MO_ALIGN
| s
->be_data
);
2364 tcg_temp_free_i64(val
);
2366 if (s
->be_data
== MO_LE
) {
2367 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2369 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2371 tcg_temp_free_i64(cmp
);
2372 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2373 if (HAVE_CMPXCHG128
) {
2374 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2375 if (s
->be_data
== MO_LE
) {
2376 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2377 clean_addr
, t1
, t2
);
2379 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2380 clean_addr
, t1
, t2
);
2382 tcg_temp_free_i32(tcg_rs
);
2384 gen_helper_exit_atomic(cpu_env
);
2385 s
->base
.is_jmp
= DISAS_NORETURN
;
2388 TCGv_i64 d1
= tcg_temp_new_i64();
2389 TCGv_i64 d2
= tcg_temp_new_i64();
2390 TCGv_i64 a2
= tcg_temp_new_i64();
2391 TCGv_i64 c1
= tcg_temp_new_i64();
2392 TCGv_i64 c2
= tcg_temp_new_i64();
2393 TCGv_i64 zero
= tcg_const_i64(0);
2395 /* Load the two words, in memory order. */
2396 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2397 MO_64
| MO_ALIGN_16
| s
->be_data
);
2398 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2399 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2401 /* Compare the two words, also in memory order. */
2402 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2403 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2404 tcg_gen_and_i64(c2
, c2
, c1
);
2406 /* If compare equal, write back new data, else write back old data. */
2407 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2408 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2409 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2410 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2411 tcg_temp_free_i64(a2
);
2412 tcg_temp_free_i64(c1
);
2413 tcg_temp_free_i64(c2
);
2414 tcg_temp_free_i64(zero
);
2416 /* Write back the data from memory to Rs. */
2417 tcg_gen_mov_i64(s1
, d1
);
2418 tcg_gen_mov_i64(s2
, d2
);
2419 tcg_temp_free_i64(d1
);
2420 tcg_temp_free_i64(d2
);
2424 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2425 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2427 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2429 int opc0
= extract32(opc
, 0, 1);
2433 regsize
= opc0
? 32 : 64;
2435 regsize
= size
== 3 ? 64 : 32;
2437 return regsize
== 64;
2440 /* Load/store exclusive
2442 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2443 * +-----+-------------+----+---+----+------+----+-------+------+------+
2444 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2445 * +-----+-------------+----+---+----+------+----+-------+------+------+
2447 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2448 * L: 0 -> store, 1 -> load
2449 * o2: 0 -> exclusive, 1 -> not
2450 * o1: 0 -> single register, 1 -> register pair
2451 * o0: 1 -> load-acquire/store-release, 0 -> not
2453 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2455 int rt
= extract32(insn
, 0, 5);
2456 int rn
= extract32(insn
, 5, 5);
2457 int rt2
= extract32(insn
, 10, 5);
2458 int rs
= extract32(insn
, 16, 5);
2459 int is_lasr
= extract32(insn
, 15, 1);
2460 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2461 int size
= extract32(insn
, 30, 2);
2462 TCGv_i64 clean_addr
;
2464 switch (o2_L_o1_o0
) {
2465 case 0x0: /* STXR */
2466 case 0x1: /* STLXR */
2468 gen_check_sp_alignment(s
);
2471 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2473 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2474 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2477 case 0x4: /* LDXR */
2478 case 0x5: /* LDAXR */
2480 gen_check_sp_alignment(s
);
2482 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2484 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2486 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2490 case 0x8: /* STLLR */
2491 if (!dc_isar_feature(aa64_lor
, s
)) {
2494 /* StoreLORelease is the same as Store-Release for QEMU. */
2496 case 0x9: /* STLR */
2497 /* Generate ISS for non-exclusive accesses including LASR. */
2499 gen_check_sp_alignment(s
);
2501 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2502 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2503 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2504 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2507 case 0xc: /* LDLAR */
2508 if (!dc_isar_feature(aa64_lor
, s
)) {
2511 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2513 case 0xd: /* LDAR */
2514 /* Generate ISS for non-exclusive accesses including LASR. */
2516 gen_check_sp_alignment(s
);
2518 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2519 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2520 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2521 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2524 case 0x2: case 0x3: /* CASP / STXP */
2525 if (size
& 2) { /* STXP / STLXP */
2527 gen_check_sp_alignment(s
);
2530 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2532 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2533 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2537 && ((rt
| rs
) & 1) == 0
2538 && dc_isar_feature(aa64_atomics
, s
)) {
2540 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2545 case 0x6: case 0x7: /* CASPA / LDXP */
2546 if (size
& 2) { /* LDXP / LDAXP */
2548 gen_check_sp_alignment(s
);
2550 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2552 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2554 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2559 && ((rt
| rs
) & 1) == 0
2560 && dc_isar_feature(aa64_atomics
, s
)) {
2561 /* CASPA / CASPAL */
2562 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2568 case 0xb: /* CASL */
2569 case 0xe: /* CASA */
2570 case 0xf: /* CASAL */
2571 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2572 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2577 unallocated_encoding(s
);
2581 * Load register (literal)
2583 * 31 30 29 27 26 25 24 23 5 4 0
2584 * +-----+-------+---+-----+-------------------+-------+
2585 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2586 * +-----+-------+---+-----+-------------------+-------+
2588 * V: 1 -> vector (simd/fp)
2589 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2590 * 10-> 32 bit signed, 11 -> prefetch
2591 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2593 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2595 int rt
= extract32(insn
, 0, 5);
2596 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2597 bool is_vector
= extract32(insn
, 26, 1);
2598 int opc
= extract32(insn
, 30, 2);
2599 bool is_signed
= false;
2601 TCGv_i64 tcg_rt
, clean_addr
;
2605 unallocated_encoding(s
);
2609 if (!fp_access_check(s
)) {
2614 /* PRFM (literal) : prefetch */
2617 size
= 2 + extract32(opc
, 0, 1);
2618 is_signed
= extract32(opc
, 1, 1);
2621 tcg_rt
= cpu_reg(s
, rt
);
2623 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2625 do_fp_ld(s
, rt
, clean_addr
, size
);
2627 /* Only unsigned 32bit loads target 32bit registers. */
2628 bool iss_sf
= opc
!= 0;
2630 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2631 true, rt
, iss_sf
, false);
2633 tcg_temp_free_i64(clean_addr
);
2637 * LDNP (Load Pair - non-temporal hint)
2638 * LDP (Load Pair - non vector)
2639 * LDPSW (Load Pair Signed Word - non vector)
2640 * STNP (Store Pair - non-temporal hint)
2641 * STP (Store Pair - non vector)
2642 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2643 * LDP (Load Pair of SIMD&FP)
2644 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2645 * STP (Store Pair of SIMD&FP)
2647 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2648 * +-----+-------+---+---+-------+---+-----------------------------+
2649 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2650 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2652 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2654 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2655 * V: 0 -> GPR, 1 -> Vector
2656 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2657 * 10 -> signed offset, 11 -> pre-index
2658 * L: 0 -> Store 1 -> Load
2660 * Rt, Rt2 = GPR or SIMD registers to be stored
2661 * Rn = general purpose register containing address
2662 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2664 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2666 int rt
= extract32(insn
, 0, 5);
2667 int rn
= extract32(insn
, 5, 5);
2668 int rt2
= extract32(insn
, 10, 5);
2669 uint64_t offset
= sextract64(insn
, 15, 7);
2670 int index
= extract32(insn
, 23, 2);
2671 bool is_vector
= extract32(insn
, 26, 1);
2672 bool is_load
= extract32(insn
, 22, 1);
2673 int opc
= extract32(insn
, 30, 2);
2675 bool is_signed
= false;
2676 bool postindex
= false;
2679 TCGv_i64 clean_addr
, dirty_addr
;
2684 unallocated_encoding(s
);
2691 size
= 2 + extract32(opc
, 1, 1);
2692 is_signed
= extract32(opc
, 0, 1);
2693 if (!is_load
&& is_signed
) {
2694 unallocated_encoding(s
);
2700 case 1: /* post-index */
2705 /* signed offset with "non-temporal" hint. Since we don't emulate
2706 * caches we don't care about hints to the cache system about
2707 * data access patterns, and handle this identically to plain
2711 /* There is no non-temporal-hint version of LDPSW */
2712 unallocated_encoding(s
);
2717 case 2: /* signed offset, rn not updated */
2720 case 3: /* pre-index */
2726 if (is_vector
&& !fp_access_check(s
)) {
2733 gen_check_sp_alignment(s
);
2736 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2738 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2740 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2744 do_fp_ld(s
, rt
, clean_addr
, size
);
2746 do_fp_st(s
, rt
, clean_addr
, size
);
2748 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2750 do_fp_ld(s
, rt2
, clean_addr
, size
);
2752 do_fp_st(s
, rt2
, clean_addr
, size
);
2755 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2756 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2759 TCGv_i64 tmp
= tcg_temp_new_i64();
2761 /* Do not modify tcg_rt before recognizing any exception
2762 * from the second load.
2764 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2765 false, 0, false, false);
2766 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2767 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2768 false, 0, false, false);
2770 tcg_gen_mov_i64(tcg_rt
, tmp
);
2771 tcg_temp_free_i64(tmp
);
2773 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2774 false, 0, false, false);
2775 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2776 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2777 false, 0, false, false);
2783 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2785 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2790 * Load/store (immediate post-indexed)
2791 * Load/store (immediate pre-indexed)
2792 * Load/store (unscaled immediate)
2794 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2795 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2796 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2797 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2799 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2801 * V = 0 -> non-vector
2802 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2803 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2805 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2811 int rn
= extract32(insn
, 5, 5);
2812 int imm9
= sextract32(insn
, 12, 9);
2813 int idx
= extract32(insn
, 10, 2);
2814 bool is_signed
= false;
2815 bool is_store
= false;
2816 bool is_extended
= false;
2817 bool is_unpriv
= (idx
== 2);
2818 bool iss_valid
= !is_vector
;
2822 TCGv_i64 clean_addr
, dirty_addr
;
2825 size
|= (opc
& 2) << 1;
2826 if (size
> 4 || is_unpriv
) {
2827 unallocated_encoding(s
);
2830 is_store
= ((opc
& 1) == 0);
2831 if (!fp_access_check(s
)) {
2835 if (size
== 3 && opc
== 2) {
2836 /* PRFM - prefetch */
2838 unallocated_encoding(s
);
2843 if (opc
== 3 && size
> 1) {
2844 unallocated_encoding(s
);
2847 is_store
= (opc
== 0);
2848 is_signed
= extract32(opc
, 1, 1);
2849 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2867 g_assert_not_reached();
2871 gen_check_sp_alignment(s
);
2874 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2876 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2878 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2882 do_fp_st(s
, rt
, clean_addr
, size
);
2884 do_fp_ld(s
, rt
, clean_addr
, size
);
2887 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2888 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2889 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2892 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2893 iss_valid
, rt
, iss_sf
, false);
2895 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2896 is_signed
, is_extended
, memidx
,
2897 iss_valid
, rt
, iss_sf
, false);
2902 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2904 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2906 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2911 * Load/store (register offset)
2913 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2914 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2915 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2916 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2919 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2920 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2922 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2923 * opc<0>: 0 -> store, 1 -> load
2924 * V: 1 -> vector/simd
2925 * opt: extend encoding (see DecodeRegExtend)
2926 * S: if S=1 then scale (essentially index by sizeof(size))
2927 * Rt: register to transfer into/out of
2928 * Rn: address register or SP for base
2929 * Rm: offset register or ZR for offset
2931 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2937 int rn
= extract32(insn
, 5, 5);
2938 int shift
= extract32(insn
, 12, 1);
2939 int rm
= extract32(insn
, 16, 5);
2940 int opt
= extract32(insn
, 13, 3);
2941 bool is_signed
= false;
2942 bool is_store
= false;
2943 bool is_extended
= false;
2945 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2947 if (extract32(opt
, 1, 1) == 0) {
2948 unallocated_encoding(s
);
2953 size
|= (opc
& 2) << 1;
2955 unallocated_encoding(s
);
2958 is_store
= !extract32(opc
, 0, 1);
2959 if (!fp_access_check(s
)) {
2963 if (size
== 3 && opc
== 2) {
2964 /* PRFM - prefetch */
2967 if (opc
== 3 && size
> 1) {
2968 unallocated_encoding(s
);
2971 is_store
= (opc
== 0);
2972 is_signed
= extract32(opc
, 1, 1);
2973 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2977 gen_check_sp_alignment(s
);
2979 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2981 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2982 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2984 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
2985 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2989 do_fp_st(s
, rt
, clean_addr
, size
);
2991 do_fp_ld(s
, rt
, clean_addr
, size
);
2994 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2995 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2997 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2998 true, rt
, iss_sf
, false);
3000 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3001 is_signed
, is_extended
,
3002 true, rt
, iss_sf
, false);
3008 * Load/store (unsigned immediate)
3010 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3011 * +----+-------+---+-----+-----+------------+-------+------+
3012 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3013 * +----+-------+---+-----+-----+------------+-------+------+
3016 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3017 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3019 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3020 * opc<0>: 0 -> store, 1 -> load
3021 * Rn: base address register (inc SP)
3022 * Rt: target register
3024 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3030 int rn
= extract32(insn
, 5, 5);
3031 unsigned int imm12
= extract32(insn
, 10, 12);
3032 unsigned int offset
;
3034 TCGv_i64 clean_addr
, dirty_addr
;
3037 bool is_signed
= false;
3038 bool is_extended
= false;
3041 size
|= (opc
& 2) << 1;
3043 unallocated_encoding(s
);
3046 is_store
= !extract32(opc
, 0, 1);
3047 if (!fp_access_check(s
)) {
3051 if (size
== 3 && opc
== 2) {
3052 /* PRFM - prefetch */
3055 if (opc
== 3 && size
> 1) {
3056 unallocated_encoding(s
);
3059 is_store
= (opc
== 0);
3060 is_signed
= extract32(opc
, 1, 1);
3061 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3065 gen_check_sp_alignment(s
);
3067 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3068 offset
= imm12
<< size
;
3069 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3070 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3074 do_fp_st(s
, rt
, clean_addr
, size
);
3076 do_fp_ld(s
, rt
, clean_addr
, size
);
3079 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3080 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3082 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3083 true, rt
, iss_sf
, false);
3085 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3086 true, rt
, iss_sf
, false);
3091 /* Atomic memory operations
3093 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3094 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3095 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3096 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3098 * Rt: the result register
3099 * Rn: base address or SP
3100 * Rs: the source register for the operation
3101 * V: vector flag (always 0 as of v8.3)
3105 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3106 int size
, int rt
, bool is_vector
)
3108 int rs
= extract32(insn
, 16, 5);
3109 int rn
= extract32(insn
, 5, 5);
3110 int o3_opc
= extract32(insn
, 12, 4);
3111 bool r
= extract32(insn
, 22, 1);
3112 bool a
= extract32(insn
, 23, 1);
3113 TCGv_i64 tcg_rs
, clean_addr
;
3114 AtomicThreeOpFn
*fn
;
3116 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3117 unallocated_encoding(s
);
3121 case 000: /* LDADD */
3122 fn
= tcg_gen_atomic_fetch_add_i64
;
3124 case 001: /* LDCLR */
3125 fn
= tcg_gen_atomic_fetch_and_i64
;
3127 case 002: /* LDEOR */
3128 fn
= tcg_gen_atomic_fetch_xor_i64
;
3130 case 003: /* LDSET */
3131 fn
= tcg_gen_atomic_fetch_or_i64
;
3133 case 004: /* LDSMAX */
3134 fn
= tcg_gen_atomic_fetch_smax_i64
;
3136 case 005: /* LDSMIN */
3137 fn
= tcg_gen_atomic_fetch_smin_i64
;
3139 case 006: /* LDUMAX */
3140 fn
= tcg_gen_atomic_fetch_umax_i64
;
3142 case 007: /* LDUMIN */
3143 fn
= tcg_gen_atomic_fetch_umin_i64
;
3146 fn
= tcg_gen_atomic_xchg_i64
;
3148 case 014: /* LDAPR, LDAPRH, LDAPRB */
3149 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3150 rs
!= 31 || a
!= 1 || r
!= 0) {
3151 unallocated_encoding(s
);
3156 unallocated_encoding(s
);
3161 gen_check_sp_alignment(s
);
3163 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3165 if (o3_opc
== 014) {
3167 * LDAPR* are a special case because they are a simple load, not a
3168 * fetch-and-do-something op.
3169 * The architectural consistency requirements here are weaker than
3170 * full load-acquire (we only need "load-acquire processor consistent"),
3171 * but we choose to implement them as full LDAQ.
3173 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3174 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3175 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3179 tcg_rs
= read_cpu_reg(s
, rs
, true);
3181 if (o3_opc
== 1) { /* LDCLR */
3182 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3185 /* The tcg atomic primitives are all full barriers. Therefore we
3186 * can ignore the Acquire and Release bits of this instruction.
3188 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3189 s
->be_data
| size
| MO_ALIGN
);
3193 * PAC memory operations
3195 * 31 30 27 26 24 22 21 12 11 10 5 0
3196 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3197 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3198 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3200 * Rt: the result register
3201 * Rn: base address or SP
3202 * V: vector flag (always 0 as of v8.3)
3203 * M: clear for key DA, set for key DB
3204 * W: pre-indexing flag
3207 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3208 int size
, int rt
, bool is_vector
)
3210 int rn
= extract32(insn
, 5, 5);
3211 bool is_wback
= extract32(insn
, 11, 1);
3212 bool use_key_a
= !extract32(insn
, 23, 1);
3214 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3216 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3217 unallocated_encoding(s
);
3222 gen_check_sp_alignment(s
);
3224 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3226 if (s
->pauth_active
) {
3228 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3230 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3234 /* Form the 10-bit signed, scaled offset. */
3235 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3236 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3237 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3239 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3240 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3242 tcg_rt
= cpu_reg(s
, rt
);
3243 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3244 /* extend */ false, /* iss_valid */ !is_wback
,
3245 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3248 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3253 * LDAPR/STLR (unscaled immediate)
3255 * 31 30 24 22 21 12 10 5 0
3256 * +------+-------------+-----+---+--------+-----+----+-----+
3257 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3258 * +------+-------------+-----+---+--------+-----+----+-----+
3260 * Rt: source or destination register
3262 * imm9: unscaled immediate offset
3263 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3264 * size: size of load/store
3266 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3268 int rt
= extract32(insn
, 0, 5);
3269 int rn
= extract32(insn
, 5, 5);
3270 int offset
= sextract32(insn
, 12, 9);
3271 int opc
= extract32(insn
, 22, 2);
3272 int size
= extract32(insn
, 30, 2);
3273 TCGv_i64 clean_addr
, dirty_addr
;
3274 bool is_store
= false;
3275 bool is_signed
= false;
3276 bool extend
= false;
3279 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3280 unallocated_encoding(s
);
3285 case 0: /* STLURB */
3288 case 1: /* LDAPUR* */
3290 case 2: /* LDAPURS* 64-bit variant */
3292 unallocated_encoding(s
);
3297 case 3: /* LDAPURS* 32-bit variant */
3299 unallocated_encoding(s
);
3303 extend
= true; /* zero-extend 32->64 after signed load */
3306 g_assert_not_reached();
3309 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3312 gen_check_sp_alignment(s
);
3315 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3316 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3317 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3320 /* Store-Release semantics */
3321 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3322 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3325 * Load-AcquirePC semantics; we implement as the slightly more
3326 * restrictive Load-Acquire.
3328 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3329 true, rt
, iss_sf
, true);
3330 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3334 /* Load/store register (all forms) */
3335 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3337 int rt
= extract32(insn
, 0, 5);
3338 int opc
= extract32(insn
, 22, 2);
3339 bool is_vector
= extract32(insn
, 26, 1);
3340 int size
= extract32(insn
, 30, 2);
3342 switch (extract32(insn
, 24, 2)) {
3344 if (extract32(insn
, 21, 1) == 0) {
3345 /* Load/store register (unscaled immediate)
3346 * Load/store immediate pre/post-indexed
3347 * Load/store register unprivileged
3349 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3352 switch (extract32(insn
, 10, 2)) {
3354 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3357 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3360 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3365 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3368 unallocated_encoding(s
);
3371 /* AdvSIMD load/store multiple structures
3373 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3374 * +---+---+---------------+---+-------------+--------+------+------+------+
3375 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3376 * +---+---+---------------+---+-------------+--------+------+------+------+
3378 * AdvSIMD load/store multiple structures (post-indexed)
3380 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3381 * +---+---+---------------+---+---+---------+--------+------+------+------+
3382 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3383 * +---+---+---------------+---+---+---------+--------+------+------+------+
3385 * Rt: first (or only) SIMD&FP register to be transferred
3386 * Rn: base address or SP
3387 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3389 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3391 int rt
= extract32(insn
, 0, 5);
3392 int rn
= extract32(insn
, 5, 5);
3393 int rm
= extract32(insn
, 16, 5);
3394 int size
= extract32(insn
, 10, 2);
3395 int opcode
= extract32(insn
, 12, 4);
3396 bool is_store
= !extract32(insn
, 22, 1);
3397 bool is_postidx
= extract32(insn
, 23, 1);
3398 bool is_q
= extract32(insn
, 30, 1);
3399 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3400 MemOp endian
= s
->be_data
;
3402 int ebytes
; /* bytes per element */
3403 int elements
; /* elements per vector */
3404 int rpt
; /* num iterations */
3405 int selem
; /* structure elements */
3408 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3409 unallocated_encoding(s
);
3413 if (!is_postidx
&& rm
!= 0) {
3414 unallocated_encoding(s
);
3418 /* From the shared decode logic */
3449 unallocated_encoding(s
);
3453 if (size
== 3 && !is_q
&& selem
!= 1) {
3455 unallocated_encoding(s
);
3459 if (!fp_access_check(s
)) {
3464 gen_check_sp_alignment(s
);
3467 /* For our purposes, bytes are always little-endian. */
3472 /* Consecutive little-endian elements from a single register
3473 * can be promoted to a larger little-endian operation.
3475 if (selem
== 1 && endian
== MO_LE
) {
3479 elements
= (is_q
? 16 : 8) / ebytes
;
3481 tcg_rn
= cpu_reg_sp(s
, rn
);
3482 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3483 tcg_ebytes
= tcg_const_i64(ebytes
);
3485 for (r
= 0; r
< rpt
; r
++) {
3487 for (e
= 0; e
< elements
; e
++) {
3489 for (xs
= 0; xs
< selem
; xs
++) {
3490 int tt
= (rt
+ r
+ xs
) % 32;
3492 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3494 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3496 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3500 tcg_temp_free_i64(tcg_ebytes
);
3503 /* For non-quad operations, setting a slice of the low
3504 * 64 bits of the register clears the high 64 bits (in
3505 * the ARM ARM pseudocode this is implicit in the fact
3506 * that 'rval' is a 64 bit wide variable).
3507 * For quad operations, we might still need to zero the
3510 for (r
= 0; r
< rpt
* selem
; r
++) {
3511 int tt
= (rt
+ r
) % 32;
3512 clear_vec_high(s
, is_q
, tt
);
3518 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3520 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3525 /* AdvSIMD load/store single structure
3527 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3528 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3529 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3530 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3532 * AdvSIMD load/store single structure (post-indexed)
3534 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3535 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3536 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3537 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3539 * Rt: first (or only) SIMD&FP register to be transferred
3540 * Rn: base address or SP
3541 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3542 * index = encoded in Q:S:size dependent on size
3544 * lane_size = encoded in R, opc
3545 * transfer width = encoded in opc, S, size
3547 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3549 int rt
= extract32(insn
, 0, 5);
3550 int rn
= extract32(insn
, 5, 5);
3551 int rm
= extract32(insn
, 16, 5);
3552 int size
= extract32(insn
, 10, 2);
3553 int S
= extract32(insn
, 12, 1);
3554 int opc
= extract32(insn
, 13, 3);
3555 int R
= extract32(insn
, 21, 1);
3556 int is_load
= extract32(insn
, 22, 1);
3557 int is_postidx
= extract32(insn
, 23, 1);
3558 int is_q
= extract32(insn
, 30, 1);
3560 int scale
= extract32(opc
, 1, 2);
3561 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3562 bool replicate
= false;
3563 int index
= is_q
<< 3 | S
<< 2 | size
;
3565 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3567 if (extract32(insn
, 31, 1)) {
3568 unallocated_encoding(s
);
3571 if (!is_postidx
&& rm
!= 0) {
3572 unallocated_encoding(s
);
3578 if (!is_load
|| S
) {
3579 unallocated_encoding(s
);
3588 if (extract32(size
, 0, 1)) {
3589 unallocated_encoding(s
);
3595 if (extract32(size
, 1, 1)) {
3596 unallocated_encoding(s
);
3599 if (!extract32(size
, 0, 1)) {
3603 unallocated_encoding(s
);
3611 g_assert_not_reached();
3614 if (!fp_access_check(s
)) {
3618 ebytes
= 1 << scale
;
3621 gen_check_sp_alignment(s
);
3624 tcg_rn
= cpu_reg_sp(s
, rn
);
3625 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3626 tcg_ebytes
= tcg_const_i64(ebytes
);
3628 for (xs
= 0; xs
< selem
; xs
++) {
3630 /* Load and replicate to all elements */
3631 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3633 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3634 get_mem_index(s
), s
->be_data
+ scale
);
3635 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3636 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3638 tcg_temp_free_i64(tcg_tmp
);
3640 /* Load/store one element per register */
3642 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3644 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3647 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3650 tcg_temp_free_i64(tcg_ebytes
);
3654 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3656 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3661 /* Loads and stores */
3662 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3664 switch (extract32(insn
, 24, 6)) {
3665 case 0x08: /* Load/store exclusive */
3666 disas_ldst_excl(s
, insn
);
3668 case 0x18: case 0x1c: /* Load register (literal) */
3669 disas_ld_lit(s
, insn
);
3671 case 0x28: case 0x29:
3672 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3673 disas_ldst_pair(s
, insn
);
3675 case 0x38: case 0x39:
3676 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3677 disas_ldst_reg(s
, insn
);
3679 case 0x0c: /* AdvSIMD load/store multiple structures */
3680 disas_ldst_multiple_struct(s
, insn
);
3682 case 0x0d: /* AdvSIMD load/store single structure */
3683 disas_ldst_single_struct(s
, insn
);
3685 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3686 if (extract32(insn
, 10, 2) != 0 ||
3687 extract32(insn
, 21, 1) != 0) {
3688 unallocated_encoding(s
);
3691 disas_ldst_ldapr_stlr(s
, insn
);
3694 unallocated_encoding(s
);
3699 /* PC-rel. addressing
3700 * 31 30 29 28 24 23 5 4 0
3701 * +----+-------+-----------+-------------------+------+
3702 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3703 * +----+-------+-----------+-------------------+------+
3705 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3707 unsigned int page
, rd
;
3711 page
= extract32(insn
, 31, 1);
3712 /* SignExtend(immhi:immlo) -> offset */
3713 offset
= sextract64(insn
, 5, 19);
3714 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3715 rd
= extract32(insn
, 0, 5);
3719 /* ADRP (page based) */
3724 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3728 * Add/subtract (immediate)
3730 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3731 * +--+--+--+-----------+-----+-------------+-----+-----+
3732 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3733 * +--+--+--+-----------+-----+-------------+-----+-----+
3735 * sf: 0 -> 32bit, 1 -> 64bit
3736 * op: 0 -> add , 1 -> sub
3738 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3740 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3742 int rd
= extract32(insn
, 0, 5);
3743 int rn
= extract32(insn
, 5, 5);
3744 uint64_t imm
= extract32(insn
, 10, 12);
3745 int shift
= extract32(insn
, 22, 2);
3746 bool setflags
= extract32(insn
, 29, 1);
3747 bool sub_op
= extract32(insn
, 30, 1);
3748 bool is_64bit
= extract32(insn
, 31, 1);
3750 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3751 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3752 TCGv_i64 tcg_result
;
3761 unallocated_encoding(s
);
3765 tcg_result
= tcg_temp_new_i64();
3768 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3770 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3773 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3775 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3777 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3779 tcg_temp_free_i64(tcg_imm
);
3783 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3785 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3788 tcg_temp_free_i64(tcg_result
);
3791 /* The input should be a value in the bottom e bits (with higher
3792 * bits zero); returns that value replicated into every element
3793 * of size e in a 64 bit integer.
3795 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3805 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3806 static inline uint64_t bitmask64(unsigned int length
)
3808 assert(length
> 0 && length
<= 64);
3809 return ~0ULL >> (64 - length
);
3812 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3813 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3814 * value (ie should cause a guest UNDEF exception), and true if they are
3815 * valid, in which case the decoded bit pattern is written to result.
3817 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3818 unsigned int imms
, unsigned int immr
)
3821 unsigned e
, levels
, s
, r
;
3824 assert(immn
< 2 && imms
< 64 && immr
< 64);
3826 /* The bit patterns we create here are 64 bit patterns which
3827 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3828 * 64 bits each. Each element contains the same value: a run
3829 * of between 1 and e-1 non-zero bits, rotated within the
3830 * element by between 0 and e-1 bits.
3832 * The element size and run length are encoded into immn (1 bit)
3833 * and imms (6 bits) as follows:
3834 * 64 bit elements: immn = 1, imms = <length of run - 1>
3835 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3836 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3837 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3838 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3839 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3840 * Notice that immn = 0, imms = 11111x is the only combination
3841 * not covered by one of the above options; this is reserved.
3842 * Further, <length of run - 1> all-ones is a reserved pattern.
3844 * In all cases the rotation is by immr % e (and immr is 6 bits).
3847 /* First determine the element size */
3848 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3850 /* This is the immn == 0, imms == 0x11111x case */
3860 /* <length of run - 1> mustn't be all-ones. */
3864 /* Create the value of one element: s+1 set bits rotated
3865 * by r within the element (which is e bits wide)...
3867 mask
= bitmask64(s
+ 1);
3869 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3870 mask
&= bitmask64(e
);
3872 /* ...then replicate the element over the whole 64 bit value */
3873 mask
= bitfield_replicate(mask
, e
);
3878 /* Logical (immediate)
3879 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3880 * +----+-----+-------------+---+------+------+------+------+
3881 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3882 * +----+-----+-------------+---+------+------+------+------+
3884 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3886 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3887 TCGv_i64 tcg_rd
, tcg_rn
;
3889 bool is_and
= false;
3891 sf
= extract32(insn
, 31, 1);
3892 opc
= extract32(insn
, 29, 2);
3893 is_n
= extract32(insn
, 22, 1);
3894 immr
= extract32(insn
, 16, 6);
3895 imms
= extract32(insn
, 10, 6);
3896 rn
= extract32(insn
, 5, 5);
3897 rd
= extract32(insn
, 0, 5);
3900 unallocated_encoding(s
);
3904 if (opc
== 0x3) { /* ANDS */
3905 tcg_rd
= cpu_reg(s
, rd
);
3907 tcg_rd
= cpu_reg_sp(s
, rd
);
3909 tcg_rn
= cpu_reg(s
, rn
);
3911 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3912 /* some immediate field values are reserved */
3913 unallocated_encoding(s
);
3918 wmask
&= 0xffffffff;
3922 case 0x3: /* ANDS */
3924 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3928 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3931 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3934 assert(FALSE
); /* must handle all above */
3938 if (!sf
&& !is_and
) {
3939 /* zero extend final result; we know we can skip this for AND
3940 * since the immediate had the high 32 bits clear.
3942 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3945 if (opc
== 3) { /* ANDS */
3946 gen_logic_CC(sf
, tcg_rd
);
3951 * Move wide (immediate)
3953 * 31 30 29 28 23 22 21 20 5 4 0
3954 * +--+-----+-------------+-----+----------------+------+
3955 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3956 * +--+-----+-------------+-----+----------------+------+
3958 * sf: 0 -> 32 bit, 1 -> 64 bit
3959 * opc: 00 -> N, 10 -> Z, 11 -> K
3960 * hw: shift/16 (0,16, and sf only 32, 48)
3962 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3964 int rd
= extract32(insn
, 0, 5);
3965 uint64_t imm
= extract32(insn
, 5, 16);
3966 int sf
= extract32(insn
, 31, 1);
3967 int opc
= extract32(insn
, 29, 2);
3968 int pos
= extract32(insn
, 21, 2) << 4;
3969 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3972 if (!sf
&& (pos
>= 32)) {
3973 unallocated_encoding(s
);
3987 tcg_gen_movi_i64(tcg_rd
, imm
);
3990 tcg_imm
= tcg_const_i64(imm
);
3991 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3992 tcg_temp_free_i64(tcg_imm
);
3994 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3998 unallocated_encoding(s
);
4004 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4005 * +----+-----+-------------+---+------+------+------+------+
4006 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4007 * +----+-----+-------------+---+------+------+------+------+
4009 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4011 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4012 TCGv_i64 tcg_rd
, tcg_tmp
;
4014 sf
= extract32(insn
, 31, 1);
4015 opc
= extract32(insn
, 29, 2);
4016 n
= extract32(insn
, 22, 1);
4017 ri
= extract32(insn
, 16, 6);
4018 si
= extract32(insn
, 10, 6);
4019 rn
= extract32(insn
, 5, 5);
4020 rd
= extract32(insn
, 0, 5);
4021 bitsize
= sf
? 64 : 32;
4023 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4024 unallocated_encoding(s
);
4028 tcg_rd
= cpu_reg(s
, rd
);
4030 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4031 to be smaller than bitsize, we'll never reference data outside the
4032 low 32-bits anyway. */
4033 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4035 /* Recognize simple(r) extractions. */
4037 /* Wd<s-r:0> = Wn<s:r> */
4038 len
= (si
- ri
) + 1;
4039 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4040 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4042 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4043 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4046 /* opc == 1, BFXIL fall through to deposit */
4047 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4050 /* Handle the ri > si case with a deposit
4051 * Wd<32+s-r,32-r> = Wn<s:0>
4054 pos
= (bitsize
- ri
) & (bitsize
- 1);
4057 if (opc
== 0 && len
< ri
) {
4058 /* SBFM: sign extend the destination field from len to fill
4059 the balance of the word. Let the deposit below insert all
4060 of those sign bits. */
4061 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4065 if (opc
== 1) { /* BFM, BFXIL */
4066 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4068 /* SBFM or UBFM: We start with zero, and we haven't modified
4069 any bits outside bitsize, therefore the zero-extension
4070 below is unneeded. */
4071 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4076 if (!sf
) { /* zero extend final result */
4077 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4082 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4083 * +----+------+-------------+---+----+------+--------+------+------+
4084 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4085 * +----+------+-------------+---+----+------+--------+------+------+
4087 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4089 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4091 sf
= extract32(insn
, 31, 1);
4092 n
= extract32(insn
, 22, 1);
4093 rm
= extract32(insn
, 16, 5);
4094 imm
= extract32(insn
, 10, 6);
4095 rn
= extract32(insn
, 5, 5);
4096 rd
= extract32(insn
, 0, 5);
4097 op21
= extract32(insn
, 29, 2);
4098 op0
= extract32(insn
, 21, 1);
4099 bitsize
= sf
? 64 : 32;
4101 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4102 unallocated_encoding(s
);
4104 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4106 tcg_rd
= cpu_reg(s
, rd
);
4108 if (unlikely(imm
== 0)) {
4109 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4110 * so an extract from bit 0 is a special case.
4113 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4115 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4118 tcg_rm
= cpu_reg(s
, rm
);
4119 tcg_rn
= cpu_reg(s
, rn
);
4122 /* Specialization to ROR happens in EXTRACT2. */
4123 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4125 TCGv_i32 t0
= tcg_temp_new_i32();
4127 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4129 tcg_gen_rotri_i32(t0
, t0
, imm
);
4131 TCGv_i32 t1
= tcg_temp_new_i32();
4132 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4133 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4134 tcg_temp_free_i32(t1
);
4136 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4137 tcg_temp_free_i32(t0
);
4143 /* Data processing - immediate */
4144 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4146 switch (extract32(insn
, 23, 6)) {
4147 case 0x20: case 0x21: /* PC-rel. addressing */
4148 disas_pc_rel_adr(s
, insn
);
4150 case 0x22: case 0x23: /* Add/subtract (immediate) */
4151 disas_add_sub_imm(s
, insn
);
4153 case 0x24: /* Logical (immediate) */
4154 disas_logic_imm(s
, insn
);
4156 case 0x25: /* Move wide (immediate) */
4157 disas_movw_imm(s
, insn
);
4159 case 0x26: /* Bitfield */
4160 disas_bitfield(s
, insn
);
4162 case 0x27: /* Extract */
4163 disas_extract(s
, insn
);
4166 unallocated_encoding(s
);
4171 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4172 * Note that it is the caller's responsibility to ensure that the
4173 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4174 * mandated semantics for out of range shifts.
4176 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4177 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4179 switch (shift_type
) {
4180 case A64_SHIFT_TYPE_LSL
:
4181 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4183 case A64_SHIFT_TYPE_LSR
:
4184 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4186 case A64_SHIFT_TYPE_ASR
:
4188 tcg_gen_ext32s_i64(dst
, src
);
4190 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4192 case A64_SHIFT_TYPE_ROR
:
4194 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4197 t0
= tcg_temp_new_i32();
4198 t1
= tcg_temp_new_i32();
4199 tcg_gen_extrl_i64_i32(t0
, src
);
4200 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4201 tcg_gen_rotr_i32(t0
, t0
, t1
);
4202 tcg_gen_extu_i32_i64(dst
, t0
);
4203 tcg_temp_free_i32(t0
);
4204 tcg_temp_free_i32(t1
);
4208 assert(FALSE
); /* all shift types should be handled */
4212 if (!sf
) { /* zero extend final result */
4213 tcg_gen_ext32u_i64(dst
, dst
);
4217 /* Shift a TCGv src by immediate, put result in dst.
4218 * The shift amount must be in range (this should always be true as the
4219 * relevant instructions will UNDEF on bad shift immediates).
4221 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4222 enum a64_shift_type shift_type
, unsigned int shift_i
)
4224 assert(shift_i
< (sf
? 64 : 32));
4227 tcg_gen_mov_i64(dst
, src
);
4229 TCGv_i64 shift_const
;
4231 shift_const
= tcg_const_i64(shift_i
);
4232 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4233 tcg_temp_free_i64(shift_const
);
4237 /* Logical (shifted register)
4238 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4239 * +----+-----+-----------+-------+---+------+--------+------+------+
4240 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4241 * +----+-----+-----------+-------+---+------+--------+------+------+
4243 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4245 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4246 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4248 sf
= extract32(insn
, 31, 1);
4249 opc
= extract32(insn
, 29, 2);
4250 shift_type
= extract32(insn
, 22, 2);
4251 invert
= extract32(insn
, 21, 1);
4252 rm
= extract32(insn
, 16, 5);
4253 shift_amount
= extract32(insn
, 10, 6);
4254 rn
= extract32(insn
, 5, 5);
4255 rd
= extract32(insn
, 0, 5);
4257 if (!sf
&& (shift_amount
& (1 << 5))) {
4258 unallocated_encoding(s
);
4262 tcg_rd
= cpu_reg(s
, rd
);
4264 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4265 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4266 * register-register MOV and MVN, so it is worth special casing.
4268 tcg_rm
= cpu_reg(s
, rm
);
4270 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4272 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4276 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4278 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4284 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4287 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4290 tcg_rn
= cpu_reg(s
, rn
);
4292 switch (opc
| (invert
<< 2)) {
4295 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4298 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4301 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4305 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4308 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4311 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4319 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4323 gen_logic_CC(sf
, tcg_rd
);
4328 * Add/subtract (extended register)
4330 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4331 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4332 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4333 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4335 * sf: 0 -> 32bit, 1 -> 64bit
4336 * op: 0 -> add , 1 -> sub
4339 * option: extension type (see DecodeRegExtend)
4340 * imm3: optional shift to Rm
4342 * Rd = Rn + LSL(extend(Rm), amount)
4344 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4346 int rd
= extract32(insn
, 0, 5);
4347 int rn
= extract32(insn
, 5, 5);
4348 int imm3
= extract32(insn
, 10, 3);
4349 int option
= extract32(insn
, 13, 3);
4350 int rm
= extract32(insn
, 16, 5);
4351 int opt
= extract32(insn
, 22, 2);
4352 bool setflags
= extract32(insn
, 29, 1);
4353 bool sub_op
= extract32(insn
, 30, 1);
4354 bool sf
= extract32(insn
, 31, 1);
4356 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4358 TCGv_i64 tcg_result
;
4360 if (imm3
> 4 || opt
!= 0) {
4361 unallocated_encoding(s
);
4365 /* non-flag setting ops may use SP */
4367 tcg_rd
= cpu_reg_sp(s
, rd
);
4369 tcg_rd
= cpu_reg(s
, rd
);
4371 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4373 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4374 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4376 tcg_result
= tcg_temp_new_i64();
4380 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4382 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4386 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4388 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4393 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4395 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4398 tcg_temp_free_i64(tcg_result
);
4402 * Add/subtract (shifted register)
4404 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4405 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4406 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4407 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4409 * sf: 0 -> 32bit, 1 -> 64bit
4410 * op: 0 -> add , 1 -> sub
4412 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4413 * imm6: Shift amount to apply to Rm before the add/sub
4415 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4417 int rd
= extract32(insn
, 0, 5);
4418 int rn
= extract32(insn
, 5, 5);
4419 int imm6
= extract32(insn
, 10, 6);
4420 int rm
= extract32(insn
, 16, 5);
4421 int shift_type
= extract32(insn
, 22, 2);
4422 bool setflags
= extract32(insn
, 29, 1);
4423 bool sub_op
= extract32(insn
, 30, 1);
4424 bool sf
= extract32(insn
, 31, 1);
4426 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4427 TCGv_i64 tcg_rn
, tcg_rm
;
4428 TCGv_i64 tcg_result
;
4430 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4431 unallocated_encoding(s
);
4435 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4436 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4438 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4440 tcg_result
= tcg_temp_new_i64();
4444 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4446 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4450 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4452 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4457 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4459 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4462 tcg_temp_free_i64(tcg_result
);
4465 /* Data-processing (3 source)
4467 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4468 * +--+------+-----------+------+------+----+------+------+------+
4469 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4470 * +--+------+-----------+------+------+----+------+------+------+
4472 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4474 int rd
= extract32(insn
, 0, 5);
4475 int rn
= extract32(insn
, 5, 5);
4476 int ra
= extract32(insn
, 10, 5);
4477 int rm
= extract32(insn
, 16, 5);
4478 int op_id
= (extract32(insn
, 29, 3) << 4) |
4479 (extract32(insn
, 21, 3) << 1) |
4480 extract32(insn
, 15, 1);
4481 bool sf
= extract32(insn
, 31, 1);
4482 bool is_sub
= extract32(op_id
, 0, 1);
4483 bool is_high
= extract32(op_id
, 2, 1);
4484 bool is_signed
= false;
4489 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4491 case 0x42: /* SMADDL */
4492 case 0x43: /* SMSUBL */
4493 case 0x44: /* SMULH */
4496 case 0x0: /* MADD (32bit) */
4497 case 0x1: /* MSUB (32bit) */
4498 case 0x40: /* MADD (64bit) */
4499 case 0x41: /* MSUB (64bit) */
4500 case 0x4a: /* UMADDL */
4501 case 0x4b: /* UMSUBL */
4502 case 0x4c: /* UMULH */
4505 unallocated_encoding(s
);
4510 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4511 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4512 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4513 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4516 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4518 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4521 tcg_temp_free_i64(low_bits
);
4525 tcg_op1
= tcg_temp_new_i64();
4526 tcg_op2
= tcg_temp_new_i64();
4527 tcg_tmp
= tcg_temp_new_i64();
4530 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4531 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4534 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4535 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4537 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4538 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4542 if (ra
== 31 && !is_sub
) {
4543 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4544 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4546 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4548 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4550 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4555 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4558 tcg_temp_free_i64(tcg_op1
);
4559 tcg_temp_free_i64(tcg_op2
);
4560 tcg_temp_free_i64(tcg_tmp
);
4563 /* Add/subtract (with carry)
4564 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4565 * +--+--+--+------------------------+------+-------------+------+-----+
4566 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4567 * +--+--+--+------------------------+------+-------------+------+-----+
4570 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4572 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4573 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4575 sf
= extract32(insn
, 31, 1);
4576 op
= extract32(insn
, 30, 1);
4577 setflags
= extract32(insn
, 29, 1);
4578 rm
= extract32(insn
, 16, 5);
4579 rn
= extract32(insn
, 5, 5);
4580 rd
= extract32(insn
, 0, 5);
4582 tcg_rd
= cpu_reg(s
, rd
);
4583 tcg_rn
= cpu_reg(s
, rn
);
4586 tcg_y
= new_tmp_a64(s
);
4587 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4589 tcg_y
= cpu_reg(s
, rm
);
4593 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4595 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4600 * Rotate right into flags
4601 * 31 30 29 21 15 10 5 4 0
4602 * +--+--+--+-----------------+--------+-----------+------+--+------+
4603 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4604 * +--+--+--+-----------------+--------+-----------+------+--+------+
4606 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4608 int mask
= extract32(insn
, 0, 4);
4609 int o2
= extract32(insn
, 4, 1);
4610 int rn
= extract32(insn
, 5, 5);
4611 int imm6
= extract32(insn
, 15, 6);
4612 int sf_op_s
= extract32(insn
, 29, 3);
4616 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4617 unallocated_encoding(s
);
4621 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4622 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4624 nzcv
= tcg_temp_new_i32();
4625 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4627 if (mask
& 8) { /* N */
4628 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4630 if (mask
& 4) { /* Z */
4631 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4632 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4634 if (mask
& 2) { /* C */
4635 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4637 if (mask
& 1) { /* V */
4638 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4641 tcg_temp_free_i32(nzcv
);
4645 * Evaluate into flags
4646 * 31 30 29 21 15 14 10 5 4 0
4647 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4648 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4649 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4651 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4653 int o3_mask
= extract32(insn
, 0, 5);
4654 int rn
= extract32(insn
, 5, 5);
4655 int o2
= extract32(insn
, 15, 6);
4656 int sz
= extract32(insn
, 14, 1);
4657 int sf_op_s
= extract32(insn
, 29, 3);
4661 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4662 !dc_isar_feature(aa64_condm_4
, s
)) {
4663 unallocated_encoding(s
);
4666 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4668 tmp
= tcg_temp_new_i32();
4669 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4670 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4671 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4672 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4673 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4674 tcg_temp_free_i32(tmp
);
4677 /* Conditional compare (immediate / register)
4678 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4679 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4680 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4681 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4684 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4686 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4687 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4688 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4691 if (!extract32(insn
, 29, 1)) {
4692 unallocated_encoding(s
);
4695 if (insn
& (1 << 10 | 1 << 4)) {
4696 unallocated_encoding(s
);
4699 sf
= extract32(insn
, 31, 1);
4700 op
= extract32(insn
, 30, 1);
4701 is_imm
= extract32(insn
, 11, 1);
4702 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4703 cond
= extract32(insn
, 12, 4);
4704 rn
= extract32(insn
, 5, 5);
4705 nzcv
= extract32(insn
, 0, 4);
4707 /* Set T0 = !COND. */
4708 tcg_t0
= tcg_temp_new_i32();
4709 arm_test_cc(&c
, cond
);
4710 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4713 /* Load the arguments for the new comparison. */
4715 tcg_y
= new_tmp_a64(s
);
4716 tcg_gen_movi_i64(tcg_y
, y
);
4718 tcg_y
= cpu_reg(s
, y
);
4720 tcg_rn
= cpu_reg(s
, rn
);
4722 /* Set the flags for the new comparison. */
4723 tcg_tmp
= tcg_temp_new_i64();
4725 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4727 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4729 tcg_temp_free_i64(tcg_tmp
);
4731 /* If COND was false, force the flags to #nzcv. Compute two masks
4732 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4733 * For tcg hosts that support ANDC, we can make do with just T1.
4734 * In either case, allow the tcg optimizer to delete any unused mask.
4736 tcg_t1
= tcg_temp_new_i32();
4737 tcg_t2
= tcg_temp_new_i32();
4738 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4739 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4741 if (nzcv
& 8) { /* N */
4742 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4744 if (TCG_TARGET_HAS_andc_i32
) {
4745 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4747 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4750 if (nzcv
& 4) { /* Z */
4751 if (TCG_TARGET_HAS_andc_i32
) {
4752 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4754 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4757 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4759 if (nzcv
& 2) { /* C */
4760 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4762 if (TCG_TARGET_HAS_andc_i32
) {
4763 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4765 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4768 if (nzcv
& 1) { /* V */
4769 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4771 if (TCG_TARGET_HAS_andc_i32
) {
4772 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4774 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4777 tcg_temp_free_i32(tcg_t0
);
4778 tcg_temp_free_i32(tcg_t1
);
4779 tcg_temp_free_i32(tcg_t2
);
4782 /* Conditional select
4783 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4784 * +----+----+---+-----------------+------+------+-----+------+------+
4785 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4786 * +----+----+---+-----------------+------+------+-----+------+------+
4788 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4790 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4791 TCGv_i64 tcg_rd
, zero
;
4794 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4795 /* S == 1 or op2<1> == 1 */
4796 unallocated_encoding(s
);
4799 sf
= extract32(insn
, 31, 1);
4800 else_inv
= extract32(insn
, 30, 1);
4801 rm
= extract32(insn
, 16, 5);
4802 cond
= extract32(insn
, 12, 4);
4803 else_inc
= extract32(insn
, 10, 1);
4804 rn
= extract32(insn
, 5, 5);
4805 rd
= extract32(insn
, 0, 5);
4807 tcg_rd
= cpu_reg(s
, rd
);
4809 a64_test_cc(&c
, cond
);
4810 zero
= tcg_const_i64(0);
4812 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4814 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4816 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4819 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4820 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4821 if (else_inv
&& else_inc
) {
4822 tcg_gen_neg_i64(t_false
, t_false
);
4823 } else if (else_inv
) {
4824 tcg_gen_not_i64(t_false
, t_false
);
4825 } else if (else_inc
) {
4826 tcg_gen_addi_i64(t_false
, t_false
, 1);
4828 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4831 tcg_temp_free_i64(zero
);
4835 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4839 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4840 unsigned int rn
, unsigned int rd
)
4842 TCGv_i64 tcg_rd
, tcg_rn
;
4843 tcg_rd
= cpu_reg(s
, rd
);
4844 tcg_rn
= cpu_reg(s
, rn
);
4847 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4849 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4850 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4851 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4852 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4853 tcg_temp_free_i32(tcg_tmp32
);
4857 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4858 unsigned int rn
, unsigned int rd
)
4860 TCGv_i64 tcg_rd
, tcg_rn
;
4861 tcg_rd
= cpu_reg(s
, rd
);
4862 tcg_rn
= cpu_reg(s
, rn
);
4865 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4867 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4868 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4869 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4870 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4871 tcg_temp_free_i32(tcg_tmp32
);
4875 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4876 unsigned int rn
, unsigned int rd
)
4878 TCGv_i64 tcg_rd
, tcg_rn
;
4879 tcg_rd
= cpu_reg(s
, rd
);
4880 tcg_rn
= cpu_reg(s
, rn
);
4883 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4885 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4886 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4887 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4888 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4889 tcg_temp_free_i32(tcg_tmp32
);
4893 /* REV with sf==1, opcode==3 ("REV64") */
4894 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4895 unsigned int rn
, unsigned int rd
)
4898 unallocated_encoding(s
);
4901 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4904 /* REV with sf==0, opcode==2
4905 * REV32 (sf==1, opcode==2)
4907 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4908 unsigned int rn
, unsigned int rd
)
4910 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4913 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4914 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4916 /* bswap32_i64 requires zero high word */
4917 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4918 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4919 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4920 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4921 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4923 tcg_temp_free_i64(tcg_tmp
);
4925 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4926 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4930 /* REV16 (opcode==1) */
4931 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4932 unsigned int rn
, unsigned int rd
)
4934 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4935 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4936 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4937 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4939 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4940 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4941 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4942 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4943 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4945 tcg_temp_free_i64(mask
);
4946 tcg_temp_free_i64(tcg_tmp
);
4949 /* Data-processing (1 source)
4950 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4951 * +----+---+---+-----------------+---------+--------+------+------+
4952 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4953 * +----+---+---+-----------------+---------+--------+------+------+
4955 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4957 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4960 if (extract32(insn
, 29, 1)) {
4961 unallocated_encoding(s
);
4965 sf
= extract32(insn
, 31, 1);
4966 opcode
= extract32(insn
, 10, 6);
4967 opcode2
= extract32(insn
, 16, 5);
4968 rn
= extract32(insn
, 5, 5);
4969 rd
= extract32(insn
, 0, 5);
4971 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4973 switch (MAP(sf
, opcode2
, opcode
)) {
4974 case MAP(0, 0x00, 0x00): /* RBIT */
4975 case MAP(1, 0x00, 0x00):
4976 handle_rbit(s
, sf
, rn
, rd
);
4978 case MAP(0, 0x00, 0x01): /* REV16 */
4979 case MAP(1, 0x00, 0x01):
4980 handle_rev16(s
, sf
, rn
, rd
);
4982 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4983 case MAP(1, 0x00, 0x02):
4984 handle_rev32(s
, sf
, rn
, rd
);
4986 case MAP(1, 0x00, 0x03): /* REV64 */
4987 handle_rev64(s
, sf
, rn
, rd
);
4989 case MAP(0, 0x00, 0x04): /* CLZ */
4990 case MAP(1, 0x00, 0x04):
4991 handle_clz(s
, sf
, rn
, rd
);
4993 case MAP(0, 0x00, 0x05): /* CLS */
4994 case MAP(1, 0x00, 0x05):
4995 handle_cls(s
, sf
, rn
, rd
);
4997 case MAP(1, 0x01, 0x00): /* PACIA */
4998 if (s
->pauth_active
) {
4999 tcg_rd
= cpu_reg(s
, rd
);
5000 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5001 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5002 goto do_unallocated
;
5005 case MAP(1, 0x01, 0x01): /* PACIB */
5006 if (s
->pauth_active
) {
5007 tcg_rd
= cpu_reg(s
, rd
);
5008 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5009 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5010 goto do_unallocated
;
5013 case MAP(1, 0x01, 0x02): /* PACDA */
5014 if (s
->pauth_active
) {
5015 tcg_rd
= cpu_reg(s
, rd
);
5016 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5017 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5018 goto do_unallocated
;
5021 case MAP(1, 0x01, 0x03): /* PACDB */
5022 if (s
->pauth_active
) {
5023 tcg_rd
= cpu_reg(s
, rd
);
5024 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5025 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5026 goto do_unallocated
;
5029 case MAP(1, 0x01, 0x04): /* AUTIA */
5030 if (s
->pauth_active
) {
5031 tcg_rd
= cpu_reg(s
, rd
);
5032 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5033 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5034 goto do_unallocated
;
5037 case MAP(1, 0x01, 0x05): /* AUTIB */
5038 if (s
->pauth_active
) {
5039 tcg_rd
= cpu_reg(s
, rd
);
5040 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5041 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5042 goto do_unallocated
;
5045 case MAP(1, 0x01, 0x06): /* AUTDA */
5046 if (s
->pauth_active
) {
5047 tcg_rd
= cpu_reg(s
, rd
);
5048 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5049 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5050 goto do_unallocated
;
5053 case MAP(1, 0x01, 0x07): /* AUTDB */
5054 if (s
->pauth_active
) {
5055 tcg_rd
= cpu_reg(s
, rd
);
5056 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5057 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5058 goto do_unallocated
;
5061 case MAP(1, 0x01, 0x08): /* PACIZA */
5062 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5063 goto do_unallocated
;
5064 } else if (s
->pauth_active
) {
5065 tcg_rd
= cpu_reg(s
, rd
);
5066 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5069 case MAP(1, 0x01, 0x09): /* PACIZB */
5070 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5071 goto do_unallocated
;
5072 } else if (s
->pauth_active
) {
5073 tcg_rd
= cpu_reg(s
, rd
);
5074 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5077 case MAP(1, 0x01, 0x0a): /* PACDZA */
5078 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5079 goto do_unallocated
;
5080 } else if (s
->pauth_active
) {
5081 tcg_rd
= cpu_reg(s
, rd
);
5082 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5085 case MAP(1, 0x01, 0x0b): /* PACDZB */
5086 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5087 goto do_unallocated
;
5088 } else if (s
->pauth_active
) {
5089 tcg_rd
= cpu_reg(s
, rd
);
5090 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5093 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5094 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5095 goto do_unallocated
;
5096 } else if (s
->pauth_active
) {
5097 tcg_rd
= cpu_reg(s
, rd
);
5098 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5101 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5102 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5103 goto do_unallocated
;
5104 } else if (s
->pauth_active
) {
5105 tcg_rd
= cpu_reg(s
, rd
);
5106 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5109 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5110 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5111 goto do_unallocated
;
5112 } else if (s
->pauth_active
) {
5113 tcg_rd
= cpu_reg(s
, rd
);
5114 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5117 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5118 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5119 goto do_unallocated
;
5120 } else if (s
->pauth_active
) {
5121 tcg_rd
= cpu_reg(s
, rd
);
5122 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5125 case MAP(1, 0x01, 0x10): /* XPACI */
5126 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5127 goto do_unallocated
;
5128 } else if (s
->pauth_active
) {
5129 tcg_rd
= cpu_reg(s
, rd
);
5130 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5133 case MAP(1, 0x01, 0x11): /* XPACD */
5134 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5135 goto do_unallocated
;
5136 } else if (s
->pauth_active
) {
5137 tcg_rd
= cpu_reg(s
, rd
);
5138 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5143 unallocated_encoding(s
);
5150 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5151 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5153 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5154 tcg_rd
= cpu_reg(s
, rd
);
5156 if (!sf
&& is_signed
) {
5157 tcg_n
= new_tmp_a64(s
);
5158 tcg_m
= new_tmp_a64(s
);
5159 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5160 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5162 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5163 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5167 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5169 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5172 if (!sf
) { /* zero extend final result */
5173 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5177 /* LSLV, LSRV, ASRV, RORV */
5178 static void handle_shift_reg(DisasContext
*s
,
5179 enum a64_shift_type shift_type
, unsigned int sf
,
5180 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5182 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5183 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5184 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5186 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5187 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5188 tcg_temp_free_i64(tcg_shift
);
5191 /* CRC32[BHWX], CRC32C[BHWX] */
5192 static void handle_crc32(DisasContext
*s
,
5193 unsigned int sf
, unsigned int sz
, bool crc32c
,
5194 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5196 TCGv_i64 tcg_acc
, tcg_val
;
5199 if (!dc_isar_feature(aa64_crc32
, s
)
5200 || (sf
== 1 && sz
!= 3)
5201 || (sf
== 0 && sz
== 3)) {
5202 unallocated_encoding(s
);
5207 tcg_val
= cpu_reg(s
, rm
);
5221 g_assert_not_reached();
5223 tcg_val
= new_tmp_a64(s
);
5224 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5227 tcg_acc
= cpu_reg(s
, rn
);
5228 tcg_bytes
= tcg_const_i32(1 << sz
);
5231 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5233 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5236 tcg_temp_free_i32(tcg_bytes
);
5239 /* Data-processing (2 source)
5240 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5241 * +----+---+---+-----------------+------+--------+------+------+
5242 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5243 * +----+---+---+-----------------+------+--------+------+------+
5245 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5247 unsigned int sf
, rm
, opcode
, rn
, rd
;
5248 sf
= extract32(insn
, 31, 1);
5249 rm
= extract32(insn
, 16, 5);
5250 opcode
= extract32(insn
, 10, 6);
5251 rn
= extract32(insn
, 5, 5);
5252 rd
= extract32(insn
, 0, 5);
5254 if (extract32(insn
, 29, 1)) {
5255 unallocated_encoding(s
);
5261 handle_div(s
, false, sf
, rm
, rn
, rd
);
5264 handle_div(s
, true, sf
, rm
, rn
, rd
);
5267 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5270 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5273 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5276 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5278 case 12: /* PACGA */
5279 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5280 goto do_unallocated
;
5282 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5283 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5292 case 23: /* CRC32 */
5294 int sz
= extract32(opcode
, 0, 2);
5295 bool crc32c
= extract32(opcode
, 2, 1);
5296 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5301 unallocated_encoding(s
);
5307 * Data processing - register
5308 * 31 30 29 28 25 21 20 16 10 0
5309 * +--+---+--+---+-------+-----+-------+-------+---------+
5310 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5311 * +--+---+--+---+-------+-----+-------+-------+---------+
5313 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5315 int op0
= extract32(insn
, 30, 1);
5316 int op1
= extract32(insn
, 28, 1);
5317 int op2
= extract32(insn
, 21, 4);
5318 int op3
= extract32(insn
, 10, 6);
5323 /* Add/sub (extended register) */
5324 disas_add_sub_ext_reg(s
, insn
);
5326 /* Add/sub (shifted register) */
5327 disas_add_sub_reg(s
, insn
);
5330 /* Logical (shifted register) */
5331 disas_logic_reg(s
, insn
);
5339 case 0x00: /* Add/subtract (with carry) */
5340 disas_adc_sbc(s
, insn
);
5343 case 0x01: /* Rotate right into flags */
5345 disas_rotate_right_into_flags(s
, insn
);
5348 case 0x02: /* Evaluate into flags */
5352 disas_evaluate_into_flags(s
, insn
);
5356 goto do_unallocated
;
5360 case 0x2: /* Conditional compare */
5361 disas_cc(s
, insn
); /* both imm and reg forms */
5364 case 0x4: /* Conditional select */
5365 disas_cond_select(s
, insn
);
5368 case 0x6: /* Data-processing */
5369 if (op0
) { /* (1 source) */
5370 disas_data_proc_1src(s
, insn
);
5371 } else { /* (2 source) */
5372 disas_data_proc_2src(s
, insn
);
5375 case 0x8 ... 0xf: /* (3 source) */
5376 disas_data_proc_3src(s
, insn
);
5381 unallocated_encoding(s
);
5386 static void handle_fp_compare(DisasContext
*s
, int size
,
5387 unsigned int rn
, unsigned int rm
,
5388 bool cmp_with_zero
, bool signal_all_nans
)
5390 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5391 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5393 if (size
== MO_64
) {
5394 TCGv_i64 tcg_vn
, tcg_vm
;
5396 tcg_vn
= read_fp_dreg(s
, rn
);
5397 if (cmp_with_zero
) {
5398 tcg_vm
= tcg_const_i64(0);
5400 tcg_vm
= read_fp_dreg(s
, rm
);
5402 if (signal_all_nans
) {
5403 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5405 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5407 tcg_temp_free_i64(tcg_vn
);
5408 tcg_temp_free_i64(tcg_vm
);
5410 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5411 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5413 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5414 if (cmp_with_zero
) {
5415 tcg_gen_movi_i32(tcg_vm
, 0);
5417 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5422 if (signal_all_nans
) {
5423 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5425 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5429 if (signal_all_nans
) {
5430 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5432 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5436 g_assert_not_reached();
5439 tcg_temp_free_i32(tcg_vn
);
5440 tcg_temp_free_i32(tcg_vm
);
5443 tcg_temp_free_ptr(fpst
);
5445 gen_set_nzcv(tcg_flags
);
5447 tcg_temp_free_i64(tcg_flags
);
5450 /* Floating point compare
5451 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5452 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5453 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5454 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5456 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5458 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5461 mos
= extract32(insn
, 29, 3);
5462 type
= extract32(insn
, 22, 2);
5463 rm
= extract32(insn
, 16, 5);
5464 op
= extract32(insn
, 14, 2);
5465 rn
= extract32(insn
, 5, 5);
5466 opc
= extract32(insn
, 3, 2);
5467 op2r
= extract32(insn
, 0, 3);
5469 if (mos
|| op
|| op2r
) {
5470 unallocated_encoding(s
);
5483 if (dc_isar_feature(aa64_fp16
, s
)) {
5488 unallocated_encoding(s
);
5492 if (!fp_access_check(s
)) {
5496 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5499 /* Floating point conditional compare
5500 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5501 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5502 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5503 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5505 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5507 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5509 TCGLabel
*label_continue
= NULL
;
5512 mos
= extract32(insn
, 29, 3);
5513 type
= extract32(insn
, 22, 2);
5514 rm
= extract32(insn
, 16, 5);
5515 cond
= extract32(insn
, 12, 4);
5516 rn
= extract32(insn
, 5, 5);
5517 op
= extract32(insn
, 4, 1);
5518 nzcv
= extract32(insn
, 0, 4);
5521 unallocated_encoding(s
);
5534 if (dc_isar_feature(aa64_fp16
, s
)) {
5539 unallocated_encoding(s
);
5543 if (!fp_access_check(s
)) {
5547 if (cond
< 0x0e) { /* not always */
5548 TCGLabel
*label_match
= gen_new_label();
5549 label_continue
= gen_new_label();
5550 arm_gen_test_cc(cond
, label_match
);
5552 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5553 gen_set_nzcv(tcg_flags
);
5554 tcg_temp_free_i64(tcg_flags
);
5555 tcg_gen_br(label_continue
);
5556 gen_set_label(label_match
);
5559 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5562 gen_set_label(label_continue
);
5566 /* Floating point conditional select
5567 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5568 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5569 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5570 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5572 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5574 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5575 TCGv_i64 t_true
, t_false
, t_zero
;
5579 mos
= extract32(insn
, 29, 3);
5580 type
= extract32(insn
, 22, 2);
5581 rm
= extract32(insn
, 16, 5);
5582 cond
= extract32(insn
, 12, 4);
5583 rn
= extract32(insn
, 5, 5);
5584 rd
= extract32(insn
, 0, 5);
5587 unallocated_encoding(s
);
5600 if (dc_isar_feature(aa64_fp16
, s
)) {
5605 unallocated_encoding(s
);
5609 if (!fp_access_check(s
)) {
5613 /* Zero extend sreg & hreg inputs to 64 bits now. */
5614 t_true
= tcg_temp_new_i64();
5615 t_false
= tcg_temp_new_i64();
5616 read_vec_element(s
, t_true
, rn
, 0, sz
);
5617 read_vec_element(s
, t_false
, rm
, 0, sz
);
5619 a64_test_cc(&c
, cond
);
5620 t_zero
= tcg_const_i64(0);
5621 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5622 tcg_temp_free_i64(t_zero
);
5623 tcg_temp_free_i64(t_false
);
5626 /* Note that sregs & hregs write back zeros to the high bits,
5627 and we've already done the zero-extension. */
5628 write_fp_dreg(s
, rd
, t_true
);
5629 tcg_temp_free_i64(t_true
);
5632 /* Floating-point data-processing (1 source) - half precision */
5633 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5635 TCGv_ptr fpst
= NULL
;
5636 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5637 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5640 case 0x0: /* FMOV */
5641 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5643 case 0x1: /* FABS */
5644 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5646 case 0x2: /* FNEG */
5647 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5649 case 0x3: /* FSQRT */
5650 fpst
= get_fpstatus_ptr(true);
5651 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5653 case 0x8: /* FRINTN */
5654 case 0x9: /* FRINTP */
5655 case 0xa: /* FRINTM */
5656 case 0xb: /* FRINTZ */
5657 case 0xc: /* FRINTA */
5659 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5660 fpst
= get_fpstatus_ptr(true);
5662 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5663 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5665 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5666 tcg_temp_free_i32(tcg_rmode
);
5669 case 0xe: /* FRINTX */
5670 fpst
= get_fpstatus_ptr(true);
5671 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5673 case 0xf: /* FRINTI */
5674 fpst
= get_fpstatus_ptr(true);
5675 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5681 write_fp_sreg(s
, rd
, tcg_res
);
5684 tcg_temp_free_ptr(fpst
);
5686 tcg_temp_free_i32(tcg_op
);
5687 tcg_temp_free_i32(tcg_res
);
5690 /* Floating-point data-processing (1 source) - single precision */
5691 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5693 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5694 TCGv_i32 tcg_op
, tcg_res
;
5698 tcg_op
= read_fp_sreg(s
, rn
);
5699 tcg_res
= tcg_temp_new_i32();
5702 case 0x0: /* FMOV */
5703 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5705 case 0x1: /* FABS */
5706 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5708 case 0x2: /* FNEG */
5709 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5711 case 0x3: /* FSQRT */
5712 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5714 case 0x8: /* FRINTN */
5715 case 0x9: /* FRINTP */
5716 case 0xa: /* FRINTM */
5717 case 0xb: /* FRINTZ */
5718 case 0xc: /* FRINTA */
5719 rmode
= arm_rmode_to_sf(opcode
& 7);
5720 gen_fpst
= gen_helper_rints
;
5722 case 0xe: /* FRINTX */
5723 gen_fpst
= gen_helper_rints_exact
;
5725 case 0xf: /* FRINTI */
5726 gen_fpst
= gen_helper_rints
;
5728 case 0x10: /* FRINT32Z */
5729 rmode
= float_round_to_zero
;
5730 gen_fpst
= gen_helper_frint32_s
;
5732 case 0x11: /* FRINT32X */
5733 gen_fpst
= gen_helper_frint32_s
;
5735 case 0x12: /* FRINT64Z */
5736 rmode
= float_round_to_zero
;
5737 gen_fpst
= gen_helper_frint64_s
;
5739 case 0x13: /* FRINT64X */
5740 gen_fpst
= gen_helper_frint64_s
;
5743 g_assert_not_reached();
5746 fpst
= get_fpstatus_ptr(false);
5748 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5749 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5750 gen_fpst(tcg_res
, tcg_op
, fpst
);
5751 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5752 tcg_temp_free_i32(tcg_rmode
);
5754 gen_fpst(tcg_res
, tcg_op
, fpst
);
5756 tcg_temp_free_ptr(fpst
);
5759 write_fp_sreg(s
, rd
, tcg_res
);
5760 tcg_temp_free_i32(tcg_op
);
5761 tcg_temp_free_i32(tcg_res
);
5764 /* Floating-point data-processing (1 source) - double precision */
5765 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5767 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5768 TCGv_i64 tcg_op
, tcg_res
;
5773 case 0x0: /* FMOV */
5774 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5778 tcg_op
= read_fp_dreg(s
, rn
);
5779 tcg_res
= tcg_temp_new_i64();
5782 case 0x1: /* FABS */
5783 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5785 case 0x2: /* FNEG */
5786 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5788 case 0x3: /* FSQRT */
5789 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5791 case 0x8: /* FRINTN */
5792 case 0x9: /* FRINTP */
5793 case 0xa: /* FRINTM */
5794 case 0xb: /* FRINTZ */
5795 case 0xc: /* FRINTA */
5796 rmode
= arm_rmode_to_sf(opcode
& 7);
5797 gen_fpst
= gen_helper_rintd
;
5799 case 0xe: /* FRINTX */
5800 gen_fpst
= gen_helper_rintd_exact
;
5802 case 0xf: /* FRINTI */
5803 gen_fpst
= gen_helper_rintd
;
5805 case 0x10: /* FRINT32Z */
5806 rmode
= float_round_to_zero
;
5807 gen_fpst
= gen_helper_frint32_d
;
5809 case 0x11: /* FRINT32X */
5810 gen_fpst
= gen_helper_frint32_d
;
5812 case 0x12: /* FRINT64Z */
5813 rmode
= float_round_to_zero
;
5814 gen_fpst
= gen_helper_frint64_d
;
5816 case 0x13: /* FRINT64X */
5817 gen_fpst
= gen_helper_frint64_d
;
5820 g_assert_not_reached();
5823 fpst
= get_fpstatus_ptr(false);
5825 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5826 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5827 gen_fpst(tcg_res
, tcg_op
, fpst
);
5828 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5829 tcg_temp_free_i32(tcg_rmode
);
5831 gen_fpst(tcg_res
, tcg_op
, fpst
);
5833 tcg_temp_free_ptr(fpst
);
5836 write_fp_dreg(s
, rd
, tcg_res
);
5837 tcg_temp_free_i64(tcg_op
);
5838 tcg_temp_free_i64(tcg_res
);
5841 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5842 int rd
, int rn
, int dtype
, int ntype
)
5847 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5849 /* Single to double */
5850 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5851 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5852 write_fp_dreg(s
, rd
, tcg_rd
);
5853 tcg_temp_free_i64(tcg_rd
);
5855 /* Single to half */
5856 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5857 TCGv_i32 ahp
= get_ahp_flag();
5858 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5860 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5861 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5862 write_fp_sreg(s
, rd
, tcg_rd
);
5863 tcg_temp_free_i32(tcg_rd
);
5864 tcg_temp_free_i32(ahp
);
5865 tcg_temp_free_ptr(fpst
);
5867 tcg_temp_free_i32(tcg_rn
);
5872 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5873 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5875 /* Double to single */
5876 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5878 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5879 TCGv_i32 ahp
= get_ahp_flag();
5880 /* Double to half */
5881 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5882 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5883 tcg_temp_free_ptr(fpst
);
5884 tcg_temp_free_i32(ahp
);
5886 write_fp_sreg(s
, rd
, tcg_rd
);
5887 tcg_temp_free_i32(tcg_rd
);
5888 tcg_temp_free_i64(tcg_rn
);
5893 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5894 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5895 TCGv_i32 tcg_ahp
= get_ahp_flag();
5896 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5898 /* Half to single */
5899 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5900 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5901 write_fp_sreg(s
, rd
, tcg_rd
);
5902 tcg_temp_free_i32(tcg_rd
);
5904 /* Half to double */
5905 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5906 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5907 write_fp_dreg(s
, rd
, tcg_rd
);
5908 tcg_temp_free_i64(tcg_rd
);
5910 tcg_temp_free_i32(tcg_rn
);
5911 tcg_temp_free_ptr(tcg_fpst
);
5912 tcg_temp_free_i32(tcg_ahp
);
5920 /* Floating point data-processing (1 source)
5921 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5922 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5923 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5924 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5926 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5928 int mos
= extract32(insn
, 29, 3);
5929 int type
= extract32(insn
, 22, 2);
5930 int opcode
= extract32(insn
, 15, 6);
5931 int rn
= extract32(insn
, 5, 5);
5932 int rd
= extract32(insn
, 0, 5);
5935 unallocated_encoding(s
);
5940 case 0x4: case 0x5: case 0x7:
5942 /* FCVT between half, single and double precision */
5943 int dtype
= extract32(opcode
, 0, 2);
5944 if (type
== 2 || dtype
== type
) {
5945 unallocated_encoding(s
);
5948 if (!fp_access_check(s
)) {
5952 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5956 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5957 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5958 unallocated_encoding(s
);
5965 /* 32-to-32 and 64-to-64 ops */
5968 if (!fp_access_check(s
)) {
5971 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5974 if (!fp_access_check(s
)) {
5977 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5980 if (!dc_isar_feature(aa64_fp16
, s
)) {
5981 unallocated_encoding(s
);
5985 if (!fp_access_check(s
)) {
5988 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5991 unallocated_encoding(s
);
5996 unallocated_encoding(s
);
6001 /* Floating-point data-processing (2 source) - single precision */
6002 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6003 int rd
, int rn
, int rm
)
6010 tcg_res
= tcg_temp_new_i32();
6011 fpst
= get_fpstatus_ptr(false);
6012 tcg_op1
= read_fp_sreg(s
, rn
);
6013 tcg_op2
= read_fp_sreg(s
, rm
);
6016 case 0x0: /* FMUL */
6017 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6019 case 0x1: /* FDIV */
6020 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6022 case 0x2: /* FADD */
6023 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6025 case 0x3: /* FSUB */
6026 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6028 case 0x4: /* FMAX */
6029 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6031 case 0x5: /* FMIN */
6032 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6034 case 0x6: /* FMAXNM */
6035 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6037 case 0x7: /* FMINNM */
6038 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6040 case 0x8: /* FNMUL */
6041 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6042 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6046 write_fp_sreg(s
, rd
, tcg_res
);
6048 tcg_temp_free_ptr(fpst
);
6049 tcg_temp_free_i32(tcg_op1
);
6050 tcg_temp_free_i32(tcg_op2
);
6051 tcg_temp_free_i32(tcg_res
);
6054 /* Floating-point data-processing (2 source) - double precision */
6055 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6056 int rd
, int rn
, int rm
)
6063 tcg_res
= tcg_temp_new_i64();
6064 fpst
= get_fpstatus_ptr(false);
6065 tcg_op1
= read_fp_dreg(s
, rn
);
6066 tcg_op2
= read_fp_dreg(s
, rm
);
6069 case 0x0: /* FMUL */
6070 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6072 case 0x1: /* FDIV */
6073 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6075 case 0x2: /* FADD */
6076 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6078 case 0x3: /* FSUB */
6079 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6081 case 0x4: /* FMAX */
6082 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6084 case 0x5: /* FMIN */
6085 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6087 case 0x6: /* FMAXNM */
6088 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6090 case 0x7: /* FMINNM */
6091 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6093 case 0x8: /* FNMUL */
6094 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6095 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6099 write_fp_dreg(s
, rd
, tcg_res
);
6101 tcg_temp_free_ptr(fpst
);
6102 tcg_temp_free_i64(tcg_op1
);
6103 tcg_temp_free_i64(tcg_op2
);
6104 tcg_temp_free_i64(tcg_res
);
6107 /* Floating-point data-processing (2 source) - half precision */
6108 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6109 int rd
, int rn
, int rm
)
6116 tcg_res
= tcg_temp_new_i32();
6117 fpst
= get_fpstatus_ptr(true);
6118 tcg_op1
= read_fp_hreg(s
, rn
);
6119 tcg_op2
= read_fp_hreg(s
, rm
);
6122 case 0x0: /* FMUL */
6123 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6125 case 0x1: /* FDIV */
6126 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6128 case 0x2: /* FADD */
6129 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6131 case 0x3: /* FSUB */
6132 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6134 case 0x4: /* FMAX */
6135 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6137 case 0x5: /* FMIN */
6138 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6140 case 0x6: /* FMAXNM */
6141 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6143 case 0x7: /* FMINNM */
6144 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6146 case 0x8: /* FNMUL */
6147 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6148 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6151 g_assert_not_reached();
6154 write_fp_sreg(s
, rd
, tcg_res
);
6156 tcg_temp_free_ptr(fpst
);
6157 tcg_temp_free_i32(tcg_op1
);
6158 tcg_temp_free_i32(tcg_op2
);
6159 tcg_temp_free_i32(tcg_res
);
6162 /* Floating point data-processing (2 source)
6163 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6164 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6165 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6166 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6168 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6170 int mos
= extract32(insn
, 29, 3);
6171 int type
= extract32(insn
, 22, 2);
6172 int rd
= extract32(insn
, 0, 5);
6173 int rn
= extract32(insn
, 5, 5);
6174 int rm
= extract32(insn
, 16, 5);
6175 int opcode
= extract32(insn
, 12, 4);
6177 if (opcode
> 8 || mos
) {
6178 unallocated_encoding(s
);
6184 if (!fp_access_check(s
)) {
6187 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6190 if (!fp_access_check(s
)) {
6193 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6196 if (!dc_isar_feature(aa64_fp16
, s
)) {
6197 unallocated_encoding(s
);
6200 if (!fp_access_check(s
)) {
6203 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6206 unallocated_encoding(s
);
6210 /* Floating-point data-processing (3 source) - single precision */
6211 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6212 int rd
, int rn
, int rm
, int ra
)
6214 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6215 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6216 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6218 tcg_op1
= read_fp_sreg(s
, rn
);
6219 tcg_op2
= read_fp_sreg(s
, rm
);
6220 tcg_op3
= read_fp_sreg(s
, ra
);
6222 /* These are fused multiply-add, and must be done as one
6223 * floating point operation with no rounding between the
6224 * multiplication and addition steps.
6225 * NB that doing the negations here as separate steps is
6226 * correct : an input NaN should come out with its sign bit
6227 * flipped if it is a negated-input.
6230 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6234 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6237 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6239 write_fp_sreg(s
, rd
, tcg_res
);
6241 tcg_temp_free_ptr(fpst
);
6242 tcg_temp_free_i32(tcg_op1
);
6243 tcg_temp_free_i32(tcg_op2
);
6244 tcg_temp_free_i32(tcg_op3
);
6245 tcg_temp_free_i32(tcg_res
);
6248 /* Floating-point data-processing (3 source) - double precision */
6249 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6250 int rd
, int rn
, int rm
, int ra
)
6252 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6253 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6254 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6256 tcg_op1
= read_fp_dreg(s
, rn
);
6257 tcg_op2
= read_fp_dreg(s
, rm
);
6258 tcg_op3
= read_fp_dreg(s
, ra
);
6260 /* These are fused multiply-add, and must be done as one
6261 * floating point operation with no rounding between the
6262 * multiplication and addition steps.
6263 * NB that doing the negations here as separate steps is
6264 * correct : an input NaN should come out with its sign bit
6265 * flipped if it is a negated-input.
6268 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6272 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6275 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6277 write_fp_dreg(s
, rd
, tcg_res
);
6279 tcg_temp_free_ptr(fpst
);
6280 tcg_temp_free_i64(tcg_op1
);
6281 tcg_temp_free_i64(tcg_op2
);
6282 tcg_temp_free_i64(tcg_op3
);
6283 tcg_temp_free_i64(tcg_res
);
6286 /* Floating-point data-processing (3 source) - half precision */
6287 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6288 int rd
, int rn
, int rm
, int ra
)
6290 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6291 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6292 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6294 tcg_op1
= read_fp_hreg(s
, rn
);
6295 tcg_op2
= read_fp_hreg(s
, rm
);
6296 tcg_op3
= read_fp_hreg(s
, ra
);
6298 /* These are fused multiply-add, and must be done as one
6299 * floating point operation with no rounding between the
6300 * multiplication and addition steps.
6301 * NB that doing the negations here as separate steps is
6302 * correct : an input NaN should come out with its sign bit
6303 * flipped if it is a negated-input.
6306 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6310 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6313 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6315 write_fp_sreg(s
, rd
, tcg_res
);
6317 tcg_temp_free_ptr(fpst
);
6318 tcg_temp_free_i32(tcg_op1
);
6319 tcg_temp_free_i32(tcg_op2
);
6320 tcg_temp_free_i32(tcg_op3
);
6321 tcg_temp_free_i32(tcg_res
);
6324 /* Floating point data-processing (3 source)
6325 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6326 * +---+---+---+-----------+------+----+------+----+------+------+------+
6327 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6328 * +---+---+---+-----------+------+----+------+----+------+------+------+
6330 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6332 int mos
= extract32(insn
, 29, 3);
6333 int type
= extract32(insn
, 22, 2);
6334 int rd
= extract32(insn
, 0, 5);
6335 int rn
= extract32(insn
, 5, 5);
6336 int ra
= extract32(insn
, 10, 5);
6337 int rm
= extract32(insn
, 16, 5);
6338 bool o0
= extract32(insn
, 15, 1);
6339 bool o1
= extract32(insn
, 21, 1);
6342 unallocated_encoding(s
);
6348 if (!fp_access_check(s
)) {
6351 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6354 if (!fp_access_check(s
)) {
6357 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6360 if (!dc_isar_feature(aa64_fp16
, s
)) {
6361 unallocated_encoding(s
);
6364 if (!fp_access_check(s
)) {
6367 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6370 unallocated_encoding(s
);
6374 /* Floating point immediate
6375 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6376 * +---+---+---+-----------+------+---+------------+-------+------+------+
6377 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6378 * +---+---+---+-----------+------+---+------------+-------+------+------+
6380 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6382 int rd
= extract32(insn
, 0, 5);
6383 int imm5
= extract32(insn
, 5, 5);
6384 int imm8
= extract32(insn
, 13, 8);
6385 int type
= extract32(insn
, 22, 2);
6386 int mos
= extract32(insn
, 29, 3);
6392 unallocated_encoding(s
);
6405 if (dc_isar_feature(aa64_fp16
, s
)) {
6410 unallocated_encoding(s
);
6414 if (!fp_access_check(s
)) {
6418 imm
= vfp_expand_imm(sz
, imm8
);
6420 tcg_res
= tcg_const_i64(imm
);
6421 write_fp_dreg(s
, rd
, tcg_res
);
6422 tcg_temp_free_i64(tcg_res
);
6425 /* Handle floating point <=> fixed point conversions. Note that we can
6426 * also deal with fp <=> integer conversions as a special case (scale == 64)
6427 * OPTME: consider handling that special case specially or at least skipping
6428 * the call to scalbn in the helpers for zero shifts.
6430 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6431 bool itof
, int rmode
, int scale
, int sf
, int type
)
6433 bool is_signed
= !(opcode
& 1);
6434 TCGv_ptr tcg_fpstatus
;
6435 TCGv_i32 tcg_shift
, tcg_single
;
6436 TCGv_i64 tcg_double
;
6438 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6440 tcg_shift
= tcg_const_i32(64 - scale
);
6443 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6445 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6448 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6450 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6453 tcg_int
= tcg_extend
;
6457 case 1: /* float64 */
6458 tcg_double
= tcg_temp_new_i64();
6460 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6461 tcg_shift
, tcg_fpstatus
);
6463 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6464 tcg_shift
, tcg_fpstatus
);
6466 write_fp_dreg(s
, rd
, tcg_double
);
6467 tcg_temp_free_i64(tcg_double
);
6470 case 0: /* float32 */
6471 tcg_single
= tcg_temp_new_i32();
6473 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6474 tcg_shift
, tcg_fpstatus
);
6476 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6477 tcg_shift
, tcg_fpstatus
);
6479 write_fp_sreg(s
, rd
, tcg_single
);
6480 tcg_temp_free_i32(tcg_single
);
6483 case 3: /* float16 */
6484 tcg_single
= tcg_temp_new_i32();
6486 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6487 tcg_shift
, tcg_fpstatus
);
6489 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6490 tcg_shift
, tcg_fpstatus
);
6492 write_fp_sreg(s
, rd
, tcg_single
);
6493 tcg_temp_free_i32(tcg_single
);
6497 g_assert_not_reached();
6500 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6503 if (extract32(opcode
, 2, 1)) {
6504 /* There are too many rounding modes to all fit into rmode,
6505 * so FCVTA[US] is a special case.
6507 rmode
= FPROUNDING_TIEAWAY
;
6510 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6512 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6515 case 1: /* float64 */
6516 tcg_double
= read_fp_dreg(s
, rn
);
6519 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6520 tcg_shift
, tcg_fpstatus
);
6522 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6523 tcg_shift
, tcg_fpstatus
);
6527 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6528 tcg_shift
, tcg_fpstatus
);
6530 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6531 tcg_shift
, tcg_fpstatus
);
6535 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6537 tcg_temp_free_i64(tcg_double
);
6540 case 0: /* float32 */
6541 tcg_single
= read_fp_sreg(s
, rn
);
6544 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6545 tcg_shift
, tcg_fpstatus
);
6547 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6548 tcg_shift
, tcg_fpstatus
);
6551 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6553 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6554 tcg_shift
, tcg_fpstatus
);
6556 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6557 tcg_shift
, tcg_fpstatus
);
6559 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6560 tcg_temp_free_i32(tcg_dest
);
6562 tcg_temp_free_i32(tcg_single
);
6565 case 3: /* float16 */
6566 tcg_single
= read_fp_sreg(s
, rn
);
6569 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6570 tcg_shift
, tcg_fpstatus
);
6572 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6573 tcg_shift
, tcg_fpstatus
);
6576 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6578 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6579 tcg_shift
, tcg_fpstatus
);
6581 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6582 tcg_shift
, tcg_fpstatus
);
6584 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6585 tcg_temp_free_i32(tcg_dest
);
6587 tcg_temp_free_i32(tcg_single
);
6591 g_assert_not_reached();
6594 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6595 tcg_temp_free_i32(tcg_rmode
);
6598 tcg_temp_free_ptr(tcg_fpstatus
);
6599 tcg_temp_free_i32(tcg_shift
);
6602 /* Floating point <-> fixed point conversions
6603 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6604 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6605 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6606 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6608 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6610 int rd
= extract32(insn
, 0, 5);
6611 int rn
= extract32(insn
, 5, 5);
6612 int scale
= extract32(insn
, 10, 6);
6613 int opcode
= extract32(insn
, 16, 3);
6614 int rmode
= extract32(insn
, 19, 2);
6615 int type
= extract32(insn
, 22, 2);
6616 bool sbit
= extract32(insn
, 29, 1);
6617 bool sf
= extract32(insn
, 31, 1);
6620 if (sbit
|| (!sf
&& scale
< 32)) {
6621 unallocated_encoding(s
);
6626 case 0: /* float32 */
6627 case 1: /* float64 */
6629 case 3: /* float16 */
6630 if (dc_isar_feature(aa64_fp16
, s
)) {
6635 unallocated_encoding(s
);
6639 switch ((rmode
<< 3) | opcode
) {
6640 case 0x2: /* SCVTF */
6641 case 0x3: /* UCVTF */
6644 case 0x18: /* FCVTZS */
6645 case 0x19: /* FCVTZU */
6649 unallocated_encoding(s
);
6653 if (!fp_access_check(s
)) {
6657 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6660 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6662 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6663 * without conversion.
6667 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6673 tmp
= tcg_temp_new_i64();
6674 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6675 write_fp_dreg(s
, rd
, tmp
);
6676 tcg_temp_free_i64(tmp
);
6680 write_fp_dreg(s
, rd
, tcg_rn
);
6683 /* 64 bit to top half. */
6684 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6685 clear_vec_high(s
, true, rd
);
6689 tmp
= tcg_temp_new_i64();
6690 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6691 write_fp_dreg(s
, rd
, tmp
);
6692 tcg_temp_free_i64(tmp
);
6695 g_assert_not_reached();
6698 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6703 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6707 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6710 /* 64 bits from top half */
6711 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6715 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6718 g_assert_not_reached();
6723 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6725 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6726 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6728 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6730 tcg_temp_free_ptr(fpstatus
);
6732 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6733 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6734 tcg_gen_movi_i32(cpu_CF
, 0);
6735 tcg_gen_movi_i32(cpu_NF
, 0);
6736 tcg_gen_movi_i32(cpu_VF
, 0);
6738 tcg_temp_free_i64(t
);
6741 /* Floating point <-> integer conversions
6742 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6743 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6744 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6745 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6747 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6749 int rd
= extract32(insn
, 0, 5);
6750 int rn
= extract32(insn
, 5, 5);
6751 int opcode
= extract32(insn
, 16, 3);
6752 int rmode
= extract32(insn
, 19, 2);
6753 int type
= extract32(insn
, 22, 2);
6754 bool sbit
= extract32(insn
, 29, 1);
6755 bool sf
= extract32(insn
, 31, 1);
6759 goto do_unallocated
;
6767 case 4: /* FCVTAS */
6768 case 5: /* FCVTAU */
6770 goto do_unallocated
;
6773 case 0: /* FCVT[NPMZ]S */
6774 case 1: /* FCVT[NPMZ]U */
6776 case 0: /* float32 */
6777 case 1: /* float64 */
6779 case 3: /* float16 */
6780 if (!dc_isar_feature(aa64_fp16
, s
)) {
6781 goto do_unallocated
;
6785 goto do_unallocated
;
6787 if (!fp_access_check(s
)) {
6790 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6794 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6795 case 0b01100110: /* FMOV half <-> 32-bit int */
6797 case 0b11100110: /* FMOV half <-> 64-bit int */
6799 if (!dc_isar_feature(aa64_fp16
, s
)) {
6800 goto do_unallocated
;
6803 case 0b00000110: /* FMOV 32-bit */
6805 case 0b10100110: /* FMOV 64-bit */
6807 case 0b11001110: /* FMOV top half of 128-bit */
6809 if (!fp_access_check(s
)) {
6813 handle_fmov(s
, rd
, rn
, type
, itof
);
6816 case 0b00111110: /* FJCVTZS */
6817 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6818 goto do_unallocated
;
6819 } else if (fp_access_check(s
)) {
6820 handle_fjcvtzs(s
, rd
, rn
);
6826 unallocated_encoding(s
);
6833 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6834 * 31 30 29 28 25 24 0
6835 * +---+---+---+---------+-----------------------------+
6836 * | | 0 | | 1 1 1 1 | |
6837 * +---+---+---+---------+-----------------------------+
6839 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6841 if (extract32(insn
, 24, 1)) {
6842 /* Floating point data-processing (3 source) */
6843 disas_fp_3src(s
, insn
);
6844 } else if (extract32(insn
, 21, 1) == 0) {
6845 /* Floating point to fixed point conversions */
6846 disas_fp_fixed_conv(s
, insn
);
6848 switch (extract32(insn
, 10, 2)) {
6850 /* Floating point conditional compare */
6851 disas_fp_ccomp(s
, insn
);
6854 /* Floating point data-processing (2 source) */
6855 disas_fp_2src(s
, insn
);
6858 /* Floating point conditional select */
6859 disas_fp_csel(s
, insn
);
6862 switch (ctz32(extract32(insn
, 12, 4))) {
6863 case 0: /* [15:12] == xxx1 */
6864 /* Floating point immediate */
6865 disas_fp_imm(s
, insn
);
6867 case 1: /* [15:12] == xx10 */
6868 /* Floating point compare */
6869 disas_fp_compare(s
, insn
);
6871 case 2: /* [15:12] == x100 */
6872 /* Floating point data-processing (1 source) */
6873 disas_fp_1src(s
, insn
);
6875 case 3: /* [15:12] == 1000 */
6876 unallocated_encoding(s
);
6878 default: /* [15:12] == 0000 */
6879 /* Floating point <-> integer conversions */
6880 disas_fp_int_conv(s
, insn
);
6888 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6891 /* Extract 64 bits from the middle of two concatenated 64 bit
6892 * vector register slices left:right. The extracted bits start
6893 * at 'pos' bits into the right (least significant) side.
6894 * We return the result in tcg_right, and guarantee not to
6897 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6898 assert(pos
> 0 && pos
< 64);
6900 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6901 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6902 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6904 tcg_temp_free_i64(tcg_tmp
);
6908 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6909 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6910 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6911 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6913 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6915 int is_q
= extract32(insn
, 30, 1);
6916 int op2
= extract32(insn
, 22, 2);
6917 int imm4
= extract32(insn
, 11, 4);
6918 int rm
= extract32(insn
, 16, 5);
6919 int rn
= extract32(insn
, 5, 5);
6920 int rd
= extract32(insn
, 0, 5);
6921 int pos
= imm4
<< 3;
6922 TCGv_i64 tcg_resl
, tcg_resh
;
6924 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6925 unallocated_encoding(s
);
6929 if (!fp_access_check(s
)) {
6933 tcg_resh
= tcg_temp_new_i64();
6934 tcg_resl
= tcg_temp_new_i64();
6936 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6937 * either extracting 128 bits from a 128:128 concatenation, or
6938 * extracting 64 bits from a 64:64 concatenation.
6941 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6943 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6944 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6952 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6953 EltPosns
*elt
= eltposns
;
6960 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6962 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6965 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6966 tcg_hh
= tcg_temp_new_i64();
6967 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6968 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6969 tcg_temp_free_i64(tcg_hh
);
6973 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6974 tcg_temp_free_i64(tcg_resl
);
6976 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6978 tcg_temp_free_i64(tcg_resh
);
6979 clear_vec_high(s
, is_q
, rd
);
6983 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6984 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6985 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6986 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6988 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6990 int op2
= extract32(insn
, 22, 2);
6991 int is_q
= extract32(insn
, 30, 1);
6992 int rm
= extract32(insn
, 16, 5);
6993 int rn
= extract32(insn
, 5, 5);
6994 int rd
= extract32(insn
, 0, 5);
6995 int is_tblx
= extract32(insn
, 12, 1);
6996 int len
= extract32(insn
, 13, 2);
6997 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6998 TCGv_i32 tcg_regno
, tcg_numregs
;
7001 unallocated_encoding(s
);
7005 if (!fp_access_check(s
)) {
7009 /* This does a table lookup: for every byte element in the input
7010 * we index into a table formed from up to four vector registers,
7011 * and then the output is the result of the lookups. Our helper
7012 * function does the lookup operation for a single 64 bit part of
7015 tcg_resl
= tcg_temp_new_i64();
7019 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7021 tcg_gen_movi_i64(tcg_resl
, 0);
7025 tcg_resh
= tcg_temp_new_i64();
7027 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7029 tcg_gen_movi_i64(tcg_resh
, 0);
7033 tcg_idx
= tcg_temp_new_i64();
7034 tcg_regno
= tcg_const_i32(rn
);
7035 tcg_numregs
= tcg_const_i32(len
+ 1);
7036 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7037 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7038 tcg_regno
, tcg_numregs
);
7040 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7041 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7042 tcg_regno
, tcg_numregs
);
7044 tcg_temp_free_i64(tcg_idx
);
7045 tcg_temp_free_i32(tcg_regno
);
7046 tcg_temp_free_i32(tcg_numregs
);
7048 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7049 tcg_temp_free_i64(tcg_resl
);
7052 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7053 tcg_temp_free_i64(tcg_resh
);
7055 clear_vec_high(s
, is_q
, rd
);
7059 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7060 * +---+---+-------------+------+---+------+---+------------------+------+
7061 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7062 * +---+---+-------------+------+---+------+---+------------------+------+
7064 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7066 int rd
= extract32(insn
, 0, 5);
7067 int rn
= extract32(insn
, 5, 5);
7068 int rm
= extract32(insn
, 16, 5);
7069 int size
= extract32(insn
, 22, 2);
7070 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7071 * bit 2 indicates 1 vs 2 variant of the insn.
7073 int opcode
= extract32(insn
, 12, 2);
7074 bool part
= extract32(insn
, 14, 1);
7075 bool is_q
= extract32(insn
, 30, 1);
7076 int esize
= 8 << size
;
7078 int datasize
= is_q
? 128 : 64;
7079 int elements
= datasize
/ esize
;
7080 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7082 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7083 unallocated_encoding(s
);
7087 if (!fp_access_check(s
)) {
7091 tcg_resl
= tcg_const_i64(0);
7092 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7093 tcg_res
= tcg_temp_new_i64();
7095 for (i
= 0; i
< elements
; i
++) {
7097 case 1: /* UZP1/2 */
7099 int midpoint
= elements
/ 2;
7101 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7103 read_vec_element(s
, tcg_res
, rm
,
7104 2 * (i
- midpoint
) + part
, size
);
7108 case 2: /* TRN1/2 */
7110 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7112 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7115 case 3: /* ZIP1/2 */
7117 int base
= part
* elements
/ 2;
7119 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7121 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7126 g_assert_not_reached();
7131 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7132 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7134 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7135 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7139 tcg_temp_free_i64(tcg_res
);
7141 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7142 tcg_temp_free_i64(tcg_resl
);
7145 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7146 tcg_temp_free_i64(tcg_resh
);
7148 clear_vec_high(s
, is_q
, rd
);
7152 * do_reduction_op helper
7154 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7155 * important for correct NaN propagation that we do these
7156 * operations in exactly the order specified by the pseudocode.
7158 * This is a recursive function, TCG temps should be freed by the
7159 * calling function once it is done with the values.
7161 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7162 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7164 if (esize
== size
) {
7166 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7169 /* We should have one register left here */
7170 assert(ctpop8(vmap
) == 1);
7171 element
= ctz32(vmap
);
7172 assert(element
< 8);
7174 tcg_elem
= tcg_temp_new_i32();
7175 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7178 int bits
= size
/ 2;
7179 int shift
= ctpop8(vmap
) / 2;
7180 int vmap_lo
= (vmap
>> shift
) & vmap
;
7181 int vmap_hi
= (vmap
& ~vmap_lo
);
7182 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7184 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7185 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7186 tcg_res
= tcg_temp_new_i32();
7189 case 0x0c: /* fmaxnmv half-precision */
7190 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7192 case 0x0f: /* fmaxv half-precision */
7193 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7195 case 0x1c: /* fminnmv half-precision */
7196 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7198 case 0x1f: /* fminv half-precision */
7199 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7201 case 0x2c: /* fmaxnmv */
7202 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7204 case 0x2f: /* fmaxv */
7205 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7207 case 0x3c: /* fminnmv */
7208 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7210 case 0x3f: /* fminv */
7211 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7214 g_assert_not_reached();
7217 tcg_temp_free_i32(tcg_hi
);
7218 tcg_temp_free_i32(tcg_lo
);
7223 /* AdvSIMD across lanes
7224 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7225 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7226 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7227 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7229 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7231 int rd
= extract32(insn
, 0, 5);
7232 int rn
= extract32(insn
, 5, 5);
7233 int size
= extract32(insn
, 22, 2);
7234 int opcode
= extract32(insn
, 12, 5);
7235 bool is_q
= extract32(insn
, 30, 1);
7236 bool is_u
= extract32(insn
, 29, 1);
7238 bool is_min
= false;
7242 TCGv_i64 tcg_res
, tcg_elt
;
7245 case 0x1b: /* ADDV */
7247 unallocated_encoding(s
);
7251 case 0x3: /* SADDLV, UADDLV */
7252 case 0xa: /* SMAXV, UMAXV */
7253 case 0x1a: /* SMINV, UMINV */
7254 if (size
== 3 || (size
== 2 && !is_q
)) {
7255 unallocated_encoding(s
);
7259 case 0xc: /* FMAXNMV, FMINNMV */
7260 case 0xf: /* FMAXV, FMINV */
7261 /* Bit 1 of size field encodes min vs max and the actual size
7262 * depends on the encoding of the U bit. If not set (and FP16
7263 * enabled) then we do half-precision float instead of single
7266 is_min
= extract32(size
, 1, 1);
7268 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7270 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7271 unallocated_encoding(s
);
7278 unallocated_encoding(s
);
7282 if (!fp_access_check(s
)) {
7287 elements
= (is_q
? 128 : 64) / esize
;
7289 tcg_res
= tcg_temp_new_i64();
7290 tcg_elt
= tcg_temp_new_i64();
7292 /* These instructions operate across all lanes of a vector
7293 * to produce a single result. We can guarantee that a 64
7294 * bit intermediate is sufficient:
7295 * + for [US]ADDLV the maximum element size is 32 bits, and
7296 * the result type is 64 bits
7297 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7298 * same as the element size, which is 32 bits at most
7299 * For the integer operations we can choose to work at 64
7300 * or 32 bits and truncate at the end; for simplicity
7301 * we use 64 bits always. The floating point
7302 * ops do require 32 bit intermediates, though.
7305 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7307 for (i
= 1; i
< elements
; i
++) {
7308 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7311 case 0x03: /* SADDLV / UADDLV */
7312 case 0x1b: /* ADDV */
7313 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7315 case 0x0a: /* SMAXV / UMAXV */
7317 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7319 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7322 case 0x1a: /* SMINV / UMINV */
7324 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7326 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7330 g_assert_not_reached();
7335 /* Floating point vector reduction ops which work across 32
7336 * bit (single) or 16 bit (half-precision) intermediates.
7337 * Note that correct NaN propagation requires that we do these
7338 * operations in exactly the order specified by the pseudocode.
7340 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7341 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7342 int vmap
= (1 << elements
) - 1;
7343 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7344 (is_q
? 128 : 64), vmap
, fpst
);
7345 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7346 tcg_temp_free_i32(tcg_res32
);
7347 tcg_temp_free_ptr(fpst
);
7350 tcg_temp_free_i64(tcg_elt
);
7352 /* Now truncate the result to the width required for the final output */
7353 if (opcode
== 0x03) {
7354 /* SADDLV, UADDLV: result is 2*esize */
7360 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7363 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7366 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7371 g_assert_not_reached();
7374 write_fp_dreg(s
, rd
, tcg_res
);
7375 tcg_temp_free_i64(tcg_res
);
7378 /* DUP (Element, Vector)
7380 * 31 30 29 21 20 16 15 10 9 5 4 0
7381 * +---+---+-------------------+--------+-------------+------+------+
7382 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7383 * +---+---+-------------------+--------+-------------+------+------+
7385 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7387 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7390 int size
= ctz32(imm5
);
7393 if (size
> 3 || (size
== 3 && !is_q
)) {
7394 unallocated_encoding(s
);
7398 if (!fp_access_check(s
)) {
7402 index
= imm5
>> (size
+ 1);
7403 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7404 vec_reg_offset(s
, rn
, index
, size
),
7405 is_q
? 16 : 8, vec_full_reg_size(s
));
7408 /* DUP (element, scalar)
7409 * 31 21 20 16 15 10 9 5 4 0
7410 * +-----------------------+--------+-------------+------+------+
7411 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7412 * +-----------------------+--------+-------------+------+------+
7414 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7417 int size
= ctz32(imm5
);
7422 unallocated_encoding(s
);
7426 if (!fp_access_check(s
)) {
7430 index
= imm5
>> (size
+ 1);
7432 /* This instruction just extracts the specified element and
7433 * zero-extends it into the bottom of the destination register.
7435 tmp
= tcg_temp_new_i64();
7436 read_vec_element(s
, tmp
, rn
, index
, size
);
7437 write_fp_dreg(s
, rd
, tmp
);
7438 tcg_temp_free_i64(tmp
);
7443 * 31 30 29 21 20 16 15 10 9 5 4 0
7444 * +---+---+-------------------+--------+-------------+------+------+
7445 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7446 * +---+---+-------------------+--------+-------------+------+------+
7448 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7450 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7453 int size
= ctz32(imm5
);
7454 uint32_t dofs
, oprsz
, maxsz
;
7456 if (size
> 3 || ((size
== 3) && !is_q
)) {
7457 unallocated_encoding(s
);
7461 if (!fp_access_check(s
)) {
7465 dofs
= vec_full_reg_offset(s
, rd
);
7466 oprsz
= is_q
? 16 : 8;
7467 maxsz
= vec_full_reg_size(s
);
7469 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7474 * 31 21 20 16 15 14 11 10 9 5 4 0
7475 * +-----------------------+--------+------------+---+------+------+
7476 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7477 * +-----------------------+--------+------------+---+------+------+
7479 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7480 * index: encoded in imm5<4:size+1>
7482 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7485 int size
= ctz32(imm5
);
7486 int src_index
, dst_index
;
7490 unallocated_encoding(s
);
7494 if (!fp_access_check(s
)) {
7498 dst_index
= extract32(imm5
, 1+size
, 5);
7499 src_index
= extract32(imm4
, size
, 4);
7501 tmp
= tcg_temp_new_i64();
7503 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7504 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7506 tcg_temp_free_i64(tmp
);
7508 /* INS is considered a 128-bit write for SVE. */
7509 clear_vec_high(s
, true, rd
);
7515 * 31 21 20 16 15 10 9 5 4 0
7516 * +-----------------------+--------+-------------+------+------+
7517 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7518 * +-----------------------+--------+-------------+------+------+
7520 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7521 * index: encoded in imm5<4:size+1>
7523 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7525 int size
= ctz32(imm5
);
7529 unallocated_encoding(s
);
7533 if (!fp_access_check(s
)) {
7537 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7538 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7540 /* INS is considered a 128-bit write for SVE. */
7541 clear_vec_high(s
, true, rd
);
7548 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7549 * +---+---+-------------------+--------+-------------+------+------+
7550 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7551 * +---+---+-------------------+--------+-------------+------+------+
7553 * U: unsigned when set
7554 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7556 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7557 int rn
, int rd
, int imm5
)
7559 int size
= ctz32(imm5
);
7563 /* Check for UnallocatedEncodings */
7565 if (size
> 2 || (size
== 2 && !is_q
)) {
7566 unallocated_encoding(s
);
7571 || (size
< 3 && is_q
)
7572 || (size
== 3 && !is_q
)) {
7573 unallocated_encoding(s
);
7578 if (!fp_access_check(s
)) {
7582 element
= extract32(imm5
, 1+size
, 4);
7584 tcg_rd
= cpu_reg(s
, rd
);
7585 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7586 if (is_signed
&& !is_q
) {
7587 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7592 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7593 * +---+---+----+-----------------+------+---+------+---+------+------+
7594 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7595 * +---+---+----+-----------------+------+---+------+---+------+------+
7597 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7599 int rd
= extract32(insn
, 0, 5);
7600 int rn
= extract32(insn
, 5, 5);
7601 int imm4
= extract32(insn
, 11, 4);
7602 int op
= extract32(insn
, 29, 1);
7603 int is_q
= extract32(insn
, 30, 1);
7604 int imm5
= extract32(insn
, 16, 5);
7609 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7611 unallocated_encoding(s
);
7616 /* DUP (element - vector) */
7617 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7621 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7626 handle_simd_insg(s
, rd
, rn
, imm5
);
7628 unallocated_encoding(s
);
7633 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7634 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7637 unallocated_encoding(s
);
7643 /* AdvSIMD modified immediate
7644 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7645 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7646 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7647 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7649 * There are a number of operations that can be carried out here:
7650 * MOVI - move (shifted) imm into register
7651 * MVNI - move inverted (shifted) imm into register
7652 * ORR - bitwise OR of (shifted) imm with register
7653 * BIC - bitwise clear of (shifted) imm with register
7654 * With ARMv8.2 we also have:
7655 * FMOV half-precision
7657 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7659 int rd
= extract32(insn
, 0, 5);
7660 int cmode
= extract32(insn
, 12, 4);
7661 int cmode_3_1
= extract32(cmode
, 1, 3);
7662 int cmode_0
= extract32(cmode
, 0, 1);
7663 int o2
= extract32(insn
, 11, 1);
7664 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7665 bool is_neg
= extract32(insn
, 29, 1);
7666 bool is_q
= extract32(insn
, 30, 1);
7669 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7670 /* Check for FMOV (vector, immediate) - half-precision */
7671 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7672 unallocated_encoding(s
);
7677 if (!fp_access_check(s
)) {
7681 /* See AdvSIMDExpandImm() in ARM ARM */
7682 switch (cmode_3_1
) {
7683 case 0: /* Replicate(Zeros(24):imm8, 2) */
7684 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7685 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7686 case 3: /* Replicate(imm8:Zeros(24), 2) */
7688 int shift
= cmode_3_1
* 8;
7689 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7692 case 4: /* Replicate(Zeros(8):imm8, 4) */
7693 case 5: /* Replicate(imm8:Zeros(8), 4) */
7695 int shift
= (cmode_3_1
& 0x1) * 8;
7696 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7701 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7702 imm
= (abcdefgh
<< 16) | 0xffff;
7704 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7705 imm
= (abcdefgh
<< 8) | 0xff;
7707 imm
= bitfield_replicate(imm
, 32);
7710 if (!cmode_0
&& !is_neg
) {
7711 imm
= bitfield_replicate(abcdefgh
, 8);
7712 } else if (!cmode_0
&& is_neg
) {
7715 for (i
= 0; i
< 8; i
++) {
7716 if ((abcdefgh
) & (1 << i
)) {
7717 imm
|= 0xffULL
<< (i
* 8);
7720 } else if (cmode_0
) {
7722 imm
= (abcdefgh
& 0x3f) << 48;
7723 if (abcdefgh
& 0x80) {
7724 imm
|= 0x8000000000000000ULL
;
7726 if (abcdefgh
& 0x40) {
7727 imm
|= 0x3fc0000000000000ULL
;
7729 imm
|= 0x4000000000000000ULL
;
7733 /* FMOV (vector, immediate) - half-precision */
7734 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7735 /* now duplicate across the lanes */
7736 imm
= bitfield_replicate(imm
, 16);
7738 imm
= (abcdefgh
& 0x3f) << 19;
7739 if (abcdefgh
& 0x80) {
7742 if (abcdefgh
& 0x40) {
7753 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7754 g_assert_not_reached();
7757 if (cmode_3_1
!= 7 && is_neg
) {
7761 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7762 /* MOVI or MVNI, with MVNI negation handled above. */
7763 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7764 vec_full_reg_size(s
), imm
);
7766 /* ORR or BIC, with BIC negation to AND handled above. */
7768 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7770 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7775 /* AdvSIMD scalar copy
7776 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7777 * +-----+----+-----------------+------+---+------+---+------+------+
7778 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7779 * +-----+----+-----------------+------+---+------+---+------+------+
7781 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7783 int rd
= extract32(insn
, 0, 5);
7784 int rn
= extract32(insn
, 5, 5);
7785 int imm4
= extract32(insn
, 11, 4);
7786 int imm5
= extract32(insn
, 16, 5);
7787 int op
= extract32(insn
, 29, 1);
7789 if (op
!= 0 || imm4
!= 0) {
7790 unallocated_encoding(s
);
7794 /* DUP (element, scalar) */
7795 handle_simd_dupes(s
, rd
, rn
, imm5
);
7798 /* AdvSIMD scalar pairwise
7799 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7800 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7801 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7802 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7804 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7806 int u
= extract32(insn
, 29, 1);
7807 int size
= extract32(insn
, 22, 2);
7808 int opcode
= extract32(insn
, 12, 5);
7809 int rn
= extract32(insn
, 5, 5);
7810 int rd
= extract32(insn
, 0, 5);
7813 /* For some ops (the FP ones), size[1] is part of the encoding.
7814 * For ADDP strictly it is not but size[1] is always 1 for valid
7817 opcode
|= (extract32(size
, 1, 1) << 5);
7820 case 0x3b: /* ADDP */
7821 if (u
|| size
!= 3) {
7822 unallocated_encoding(s
);
7825 if (!fp_access_check(s
)) {
7831 case 0xc: /* FMAXNMP */
7832 case 0xd: /* FADDP */
7833 case 0xf: /* FMAXP */
7834 case 0x2c: /* FMINNMP */
7835 case 0x2f: /* FMINP */
7836 /* FP op, size[0] is 32 or 64 bit*/
7838 if (!dc_isar_feature(aa64_fp16
, s
)) {
7839 unallocated_encoding(s
);
7845 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7848 if (!fp_access_check(s
)) {
7852 fpst
= get_fpstatus_ptr(size
== MO_16
);
7855 unallocated_encoding(s
);
7859 if (size
== MO_64
) {
7860 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7861 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7862 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7864 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7865 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7868 case 0x3b: /* ADDP */
7869 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7871 case 0xc: /* FMAXNMP */
7872 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7874 case 0xd: /* FADDP */
7875 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7877 case 0xf: /* FMAXP */
7878 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7880 case 0x2c: /* FMINNMP */
7881 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7883 case 0x2f: /* FMINP */
7884 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7887 g_assert_not_reached();
7890 write_fp_dreg(s
, rd
, tcg_res
);
7892 tcg_temp_free_i64(tcg_op1
);
7893 tcg_temp_free_i64(tcg_op2
);
7894 tcg_temp_free_i64(tcg_res
);
7896 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7897 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7898 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7900 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7901 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7903 if (size
== MO_16
) {
7905 case 0xc: /* FMAXNMP */
7906 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7908 case 0xd: /* FADDP */
7909 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7911 case 0xf: /* FMAXP */
7912 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7914 case 0x2c: /* FMINNMP */
7915 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7917 case 0x2f: /* FMINP */
7918 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7921 g_assert_not_reached();
7925 case 0xc: /* FMAXNMP */
7926 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7928 case 0xd: /* FADDP */
7929 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7931 case 0xf: /* FMAXP */
7932 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7934 case 0x2c: /* FMINNMP */
7935 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7937 case 0x2f: /* FMINP */
7938 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7941 g_assert_not_reached();
7945 write_fp_sreg(s
, rd
, tcg_res
);
7947 tcg_temp_free_i32(tcg_op1
);
7948 tcg_temp_free_i32(tcg_op2
);
7949 tcg_temp_free_i32(tcg_res
);
7953 tcg_temp_free_ptr(fpst
);
7958 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7960 * This code is handles the common shifting code and is used by both
7961 * the vector and scalar code.
7963 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7964 TCGv_i64 tcg_rnd
, bool accumulate
,
7965 bool is_u
, int size
, int shift
)
7967 bool extended_result
= false;
7968 bool round
= tcg_rnd
!= NULL
;
7970 TCGv_i64 tcg_src_hi
;
7972 if (round
&& size
== 3) {
7973 extended_result
= true;
7974 ext_lshift
= 64 - shift
;
7975 tcg_src_hi
= tcg_temp_new_i64();
7976 } else if (shift
== 64) {
7977 if (!accumulate
&& is_u
) {
7978 /* result is zero */
7979 tcg_gen_movi_i64(tcg_res
, 0);
7984 /* Deal with the rounding step */
7986 if (extended_result
) {
7987 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7989 /* take care of sign extending tcg_res */
7990 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7991 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7992 tcg_src
, tcg_src_hi
,
7995 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7999 tcg_temp_free_i64(tcg_zero
);
8001 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8005 /* Now do the shift right */
8006 if (round
&& extended_result
) {
8007 /* extended case, >64 bit precision required */
8008 if (ext_lshift
== 0) {
8009 /* special case, only high bits matter */
8010 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8012 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8013 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8014 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8019 /* essentially shifting in 64 zeros */
8020 tcg_gen_movi_i64(tcg_src
, 0);
8022 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8026 /* effectively extending the sign-bit */
8027 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8029 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8035 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8037 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8040 if (extended_result
) {
8041 tcg_temp_free_i64(tcg_src_hi
);
8045 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8046 static void handle_scalar_simd_shri(DisasContext
*s
,
8047 bool is_u
, int immh
, int immb
,
8048 int opcode
, int rn
, int rd
)
8051 int immhb
= immh
<< 3 | immb
;
8052 int shift
= 2 * (8 << size
) - immhb
;
8053 bool accumulate
= false;
8055 bool insert
= false;
8060 if (!extract32(immh
, 3, 1)) {
8061 unallocated_encoding(s
);
8065 if (!fp_access_check(s
)) {
8070 case 0x02: /* SSRA / USRA (accumulate) */
8073 case 0x04: /* SRSHR / URSHR (rounding) */
8076 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8077 accumulate
= round
= true;
8079 case 0x08: /* SRI */
8085 uint64_t round_const
= 1ULL << (shift
- 1);
8086 tcg_round
= tcg_const_i64(round_const
);
8091 tcg_rn
= read_fp_dreg(s
, rn
);
8092 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8095 /* shift count same as element size is valid but does nothing;
8096 * special case to avoid potential shift by 64.
8098 int esize
= 8 << size
;
8099 if (shift
!= esize
) {
8100 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8101 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8104 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8105 accumulate
, is_u
, size
, shift
);
8108 write_fp_dreg(s
, rd
, tcg_rd
);
8110 tcg_temp_free_i64(tcg_rn
);
8111 tcg_temp_free_i64(tcg_rd
);
8113 tcg_temp_free_i64(tcg_round
);
8117 /* SHL/SLI - Scalar shift left */
8118 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8119 int immh
, int immb
, int opcode
,
8122 int size
= 32 - clz32(immh
) - 1;
8123 int immhb
= immh
<< 3 | immb
;
8124 int shift
= immhb
- (8 << size
);
8125 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8126 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8128 if (!extract32(immh
, 3, 1)) {
8129 unallocated_encoding(s
);
8133 if (!fp_access_check(s
)) {
8137 tcg_rn
= read_fp_dreg(s
, rn
);
8138 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8141 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8143 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8146 write_fp_dreg(s
, rd
, tcg_rd
);
8148 tcg_temp_free_i64(tcg_rn
);
8149 tcg_temp_free_i64(tcg_rd
);
8152 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8153 * (signed/unsigned) narrowing */
8154 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8155 bool is_u_shift
, bool is_u_narrow
,
8156 int immh
, int immb
, int opcode
,
8159 int immhb
= immh
<< 3 | immb
;
8160 int size
= 32 - clz32(immh
) - 1;
8161 int esize
= 8 << size
;
8162 int shift
= (2 * esize
) - immhb
;
8163 int elements
= is_scalar
? 1 : (64 / esize
);
8164 bool round
= extract32(opcode
, 0, 1);
8165 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8166 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8167 TCGv_i32 tcg_rd_narrowed
;
8170 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8171 { gen_helper_neon_narrow_sat_s8
,
8172 gen_helper_neon_unarrow_sat8
},
8173 { gen_helper_neon_narrow_sat_s16
,
8174 gen_helper_neon_unarrow_sat16
},
8175 { gen_helper_neon_narrow_sat_s32
,
8176 gen_helper_neon_unarrow_sat32
},
8179 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8180 gen_helper_neon_narrow_sat_u8
,
8181 gen_helper_neon_narrow_sat_u16
,
8182 gen_helper_neon_narrow_sat_u32
,
8185 NeonGenNarrowEnvFn
*narrowfn
;
8191 if (extract32(immh
, 3, 1)) {
8192 unallocated_encoding(s
);
8196 if (!fp_access_check(s
)) {
8201 narrowfn
= unsigned_narrow_fns
[size
];
8203 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8206 tcg_rn
= tcg_temp_new_i64();
8207 tcg_rd
= tcg_temp_new_i64();
8208 tcg_rd_narrowed
= tcg_temp_new_i32();
8209 tcg_final
= tcg_const_i64(0);
8212 uint64_t round_const
= 1ULL << (shift
- 1);
8213 tcg_round
= tcg_const_i64(round_const
);
8218 for (i
= 0; i
< elements
; i
++) {
8219 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8220 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8221 false, is_u_shift
, size
+1, shift
);
8222 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8223 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8224 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8228 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8230 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8234 tcg_temp_free_i64(tcg_round
);
8236 tcg_temp_free_i64(tcg_rn
);
8237 tcg_temp_free_i64(tcg_rd
);
8238 tcg_temp_free_i32(tcg_rd_narrowed
);
8239 tcg_temp_free_i64(tcg_final
);
8241 clear_vec_high(s
, is_q
, rd
);
8244 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8245 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8246 bool src_unsigned
, bool dst_unsigned
,
8247 int immh
, int immb
, int rn
, int rd
)
8249 int immhb
= immh
<< 3 | immb
;
8250 int size
= 32 - clz32(immh
) - 1;
8251 int shift
= immhb
- (8 << size
);
8255 assert(!(scalar
&& is_q
));
8258 if (!is_q
&& extract32(immh
, 3, 1)) {
8259 unallocated_encoding(s
);
8263 /* Since we use the variable-shift helpers we must
8264 * replicate the shift count into each element of
8265 * the tcg_shift value.
8269 shift
|= shift
<< 8;
8272 shift
|= shift
<< 16;
8278 g_assert_not_reached();
8282 if (!fp_access_check(s
)) {
8287 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8288 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8289 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8290 { NULL
, gen_helper_neon_qshl_u64
},
8292 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8293 int maxpass
= is_q
? 2 : 1;
8295 for (pass
= 0; pass
< maxpass
; pass
++) {
8296 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8298 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8299 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8300 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8302 tcg_temp_free_i64(tcg_op
);
8304 tcg_temp_free_i64(tcg_shift
);
8305 clear_vec_high(s
, is_q
, rd
);
8307 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8308 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8310 { gen_helper_neon_qshl_s8
,
8311 gen_helper_neon_qshl_s16
,
8312 gen_helper_neon_qshl_s32
},
8313 { gen_helper_neon_qshlu_s8
,
8314 gen_helper_neon_qshlu_s16
,
8315 gen_helper_neon_qshlu_s32
}
8317 { NULL
, NULL
, NULL
},
8318 { gen_helper_neon_qshl_u8
,
8319 gen_helper_neon_qshl_u16
,
8320 gen_helper_neon_qshl_u32
}
8323 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8324 MemOp memop
= scalar
? size
: MO_32
;
8325 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8327 for (pass
= 0; pass
< maxpass
; pass
++) {
8328 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8330 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8331 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8335 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8338 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8343 g_assert_not_reached();
8345 write_fp_sreg(s
, rd
, tcg_op
);
8347 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8350 tcg_temp_free_i32(tcg_op
);
8352 tcg_temp_free_i32(tcg_shift
);
8355 clear_vec_high(s
, is_q
, rd
);
8360 /* Common vector code for handling integer to FP conversion */
8361 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8362 int elements
, int is_signed
,
8363 int fracbits
, int size
)
8365 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8366 TCGv_i32 tcg_shift
= NULL
;
8368 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8371 if (fracbits
|| size
== MO_64
) {
8372 tcg_shift
= tcg_const_i32(fracbits
);
8375 if (size
== MO_64
) {
8376 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8377 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8379 for (pass
= 0; pass
< elements
; pass
++) {
8380 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8383 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8384 tcg_shift
, tcg_fpst
);
8386 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8387 tcg_shift
, tcg_fpst
);
8389 if (elements
== 1) {
8390 write_fp_dreg(s
, rd
, tcg_double
);
8392 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8396 tcg_temp_free_i64(tcg_int64
);
8397 tcg_temp_free_i64(tcg_double
);
8400 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8401 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8403 for (pass
= 0; pass
< elements
; pass
++) {
8404 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8410 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8411 tcg_shift
, tcg_fpst
);
8413 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8414 tcg_shift
, tcg_fpst
);
8418 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8420 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8427 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8428 tcg_shift
, tcg_fpst
);
8430 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8431 tcg_shift
, tcg_fpst
);
8435 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8437 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8442 g_assert_not_reached();
8445 if (elements
== 1) {
8446 write_fp_sreg(s
, rd
, tcg_float
);
8448 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8452 tcg_temp_free_i32(tcg_int32
);
8453 tcg_temp_free_i32(tcg_float
);
8456 tcg_temp_free_ptr(tcg_fpst
);
8458 tcg_temp_free_i32(tcg_shift
);
8461 clear_vec_high(s
, elements
<< size
== 16, rd
);
8464 /* UCVTF/SCVTF - Integer to FP conversion */
8465 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8466 bool is_q
, bool is_u
,
8467 int immh
, int immb
, int opcode
,
8470 int size
, elements
, fracbits
;
8471 int immhb
= immh
<< 3 | immb
;
8475 if (!is_scalar
&& !is_q
) {
8476 unallocated_encoding(s
);
8479 } else if (immh
& 4) {
8481 } else if (immh
& 2) {
8483 if (!dc_isar_feature(aa64_fp16
, s
)) {
8484 unallocated_encoding(s
);
8488 /* immh == 0 would be a failure of the decode logic */
8489 g_assert(immh
== 1);
8490 unallocated_encoding(s
);
8497 elements
= (8 << is_q
) >> size
;
8499 fracbits
= (16 << size
) - immhb
;
8501 if (!fp_access_check(s
)) {
8505 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8508 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8509 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8510 bool is_q
, bool is_u
,
8511 int immh
, int immb
, int rn
, int rd
)
8513 int immhb
= immh
<< 3 | immb
;
8514 int pass
, size
, fracbits
;
8515 TCGv_ptr tcg_fpstatus
;
8516 TCGv_i32 tcg_rmode
, tcg_shift
;
8520 if (!is_scalar
&& !is_q
) {
8521 unallocated_encoding(s
);
8524 } else if (immh
& 0x4) {
8526 } else if (immh
& 0x2) {
8528 if (!dc_isar_feature(aa64_fp16
, s
)) {
8529 unallocated_encoding(s
);
8533 /* Should have split out AdvSIMD modified immediate earlier. */
8535 unallocated_encoding(s
);
8539 if (!fp_access_check(s
)) {
8543 assert(!(is_scalar
&& is_q
));
8545 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8546 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8547 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8548 fracbits
= (16 << size
) - immhb
;
8549 tcg_shift
= tcg_const_i32(fracbits
);
8551 if (size
== MO_64
) {
8552 int maxpass
= is_scalar
? 1 : 2;
8554 for (pass
= 0; pass
< maxpass
; pass
++) {
8555 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8557 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8559 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8561 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8563 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8564 tcg_temp_free_i64(tcg_op
);
8566 clear_vec_high(s
, is_q
, rd
);
8568 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8569 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8574 fn
= gen_helper_vfp_touhh
;
8576 fn
= gen_helper_vfp_toshh
;
8581 fn
= gen_helper_vfp_touls
;
8583 fn
= gen_helper_vfp_tosls
;
8587 g_assert_not_reached();
8590 for (pass
= 0; pass
< maxpass
; pass
++) {
8591 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8593 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8594 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8596 write_fp_sreg(s
, rd
, tcg_op
);
8598 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8600 tcg_temp_free_i32(tcg_op
);
8603 clear_vec_high(s
, is_q
, rd
);
8607 tcg_temp_free_ptr(tcg_fpstatus
);
8608 tcg_temp_free_i32(tcg_shift
);
8609 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8610 tcg_temp_free_i32(tcg_rmode
);
8613 /* AdvSIMD scalar shift by immediate
8614 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8615 * +-----+---+-------------+------+------+--------+---+------+------+
8616 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8617 * +-----+---+-------------+------+------+--------+---+------+------+
8619 * This is the scalar version so it works on a fixed sized registers
8621 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8623 int rd
= extract32(insn
, 0, 5);
8624 int rn
= extract32(insn
, 5, 5);
8625 int opcode
= extract32(insn
, 11, 5);
8626 int immb
= extract32(insn
, 16, 3);
8627 int immh
= extract32(insn
, 19, 4);
8628 bool is_u
= extract32(insn
, 29, 1);
8631 unallocated_encoding(s
);
8636 case 0x08: /* SRI */
8638 unallocated_encoding(s
);
8642 case 0x00: /* SSHR / USHR */
8643 case 0x02: /* SSRA / USRA */
8644 case 0x04: /* SRSHR / URSHR */
8645 case 0x06: /* SRSRA / URSRA */
8646 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8648 case 0x0a: /* SHL / SLI */
8649 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8651 case 0x1c: /* SCVTF, UCVTF */
8652 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8655 case 0x10: /* SQSHRUN, SQSHRUN2 */
8656 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8658 unallocated_encoding(s
);
8661 handle_vec_simd_sqshrn(s
, true, false, false, true,
8662 immh
, immb
, opcode
, rn
, rd
);
8664 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8665 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8666 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8667 immh
, immb
, opcode
, rn
, rd
);
8669 case 0xc: /* SQSHLU */
8671 unallocated_encoding(s
);
8674 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8676 case 0xe: /* SQSHL, UQSHL */
8677 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8679 case 0x1f: /* FCVTZS, FCVTZU */
8680 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8683 unallocated_encoding(s
);
8688 /* AdvSIMD scalar three different
8689 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8690 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8691 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8692 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8694 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8696 bool is_u
= extract32(insn
, 29, 1);
8697 int size
= extract32(insn
, 22, 2);
8698 int opcode
= extract32(insn
, 12, 4);
8699 int rm
= extract32(insn
, 16, 5);
8700 int rn
= extract32(insn
, 5, 5);
8701 int rd
= extract32(insn
, 0, 5);
8704 unallocated_encoding(s
);
8709 case 0x9: /* SQDMLAL, SQDMLAL2 */
8710 case 0xb: /* SQDMLSL, SQDMLSL2 */
8711 case 0xd: /* SQDMULL, SQDMULL2 */
8712 if (size
== 0 || size
== 3) {
8713 unallocated_encoding(s
);
8718 unallocated_encoding(s
);
8722 if (!fp_access_check(s
)) {
8727 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8728 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8729 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8731 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8732 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8734 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8735 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8738 case 0xd: /* SQDMULL, SQDMULL2 */
8740 case 0xb: /* SQDMLSL, SQDMLSL2 */
8741 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8743 case 0x9: /* SQDMLAL, SQDMLAL2 */
8744 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8745 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8749 g_assert_not_reached();
8752 write_fp_dreg(s
, rd
, tcg_res
);
8754 tcg_temp_free_i64(tcg_op1
);
8755 tcg_temp_free_i64(tcg_op2
);
8756 tcg_temp_free_i64(tcg_res
);
8758 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8759 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8760 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8762 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8763 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8766 case 0xd: /* SQDMULL, SQDMULL2 */
8768 case 0xb: /* SQDMLSL, SQDMLSL2 */
8769 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8771 case 0x9: /* SQDMLAL, SQDMLAL2 */
8773 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8774 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8775 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8777 tcg_temp_free_i64(tcg_op3
);
8781 g_assert_not_reached();
8784 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8785 write_fp_dreg(s
, rd
, tcg_res
);
8787 tcg_temp_free_i32(tcg_op1
);
8788 tcg_temp_free_i32(tcg_op2
);
8789 tcg_temp_free_i64(tcg_res
);
8793 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8794 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8796 /* Handle 64x64->64 opcodes which are shared between the scalar
8797 * and vector 3-same groups. We cover every opcode where size == 3
8798 * is valid in either the three-reg-same (integer, not pairwise)
8799 * or scalar-three-reg-same groups.
8804 case 0x1: /* SQADD */
8806 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8808 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8811 case 0x5: /* SQSUB */
8813 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8815 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8818 case 0x6: /* CMGT, CMHI */
8819 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8820 * We implement this using setcond (test) and then negating.
8822 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8824 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8825 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8827 case 0x7: /* CMGE, CMHS */
8828 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8830 case 0x11: /* CMTST, CMEQ */
8835 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8837 case 0x8: /* SSHL, USHL */
8839 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8841 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8844 case 0x9: /* SQSHL, UQSHL */
8846 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8848 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8851 case 0xa: /* SRSHL, URSHL */
8853 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8855 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8858 case 0xb: /* SQRSHL, UQRSHL */
8860 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8862 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8865 case 0x10: /* ADD, SUB */
8867 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8869 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8873 g_assert_not_reached();
8877 /* Handle the 3-same-operands float operations; shared by the scalar
8878 * and vector encodings. The caller must filter out any encodings
8879 * not allocated for the encoding it is dealing with.
8881 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8882 int fpopcode
, int rd
, int rn
, int rm
)
8885 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8887 for (pass
= 0; pass
< elements
; pass
++) {
8890 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8891 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8892 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8894 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8895 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8898 case 0x39: /* FMLS */
8899 /* As usual for ARM, separate negation for fused multiply-add */
8900 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8902 case 0x19: /* FMLA */
8903 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8904 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8907 case 0x18: /* FMAXNM */
8908 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8910 case 0x1a: /* FADD */
8911 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8913 case 0x1b: /* FMULX */
8914 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8916 case 0x1c: /* FCMEQ */
8917 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8919 case 0x1e: /* FMAX */
8920 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8922 case 0x1f: /* FRECPS */
8923 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8925 case 0x38: /* FMINNM */
8926 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8928 case 0x3a: /* FSUB */
8929 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8931 case 0x3e: /* FMIN */
8932 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8934 case 0x3f: /* FRSQRTS */
8935 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8937 case 0x5b: /* FMUL */
8938 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8940 case 0x5c: /* FCMGE */
8941 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8943 case 0x5d: /* FACGE */
8944 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8946 case 0x5f: /* FDIV */
8947 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8949 case 0x7a: /* FABD */
8950 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8951 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8953 case 0x7c: /* FCMGT */
8954 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8956 case 0x7d: /* FACGT */
8957 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8960 g_assert_not_reached();
8963 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8965 tcg_temp_free_i64(tcg_res
);
8966 tcg_temp_free_i64(tcg_op1
);
8967 tcg_temp_free_i64(tcg_op2
);
8970 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8971 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8972 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8974 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8975 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8978 case 0x39: /* FMLS */
8979 /* As usual for ARM, separate negation for fused multiply-add */
8980 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8982 case 0x19: /* FMLA */
8983 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8984 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8987 case 0x1a: /* FADD */
8988 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8990 case 0x1b: /* FMULX */
8991 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8993 case 0x1c: /* FCMEQ */
8994 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8996 case 0x1e: /* FMAX */
8997 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8999 case 0x1f: /* FRECPS */
9000 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9002 case 0x18: /* FMAXNM */
9003 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9005 case 0x38: /* FMINNM */
9006 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9008 case 0x3a: /* FSUB */
9009 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9011 case 0x3e: /* FMIN */
9012 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9014 case 0x3f: /* FRSQRTS */
9015 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9017 case 0x5b: /* FMUL */
9018 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9020 case 0x5c: /* FCMGE */
9021 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9023 case 0x5d: /* FACGE */
9024 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9026 case 0x5f: /* FDIV */
9027 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9029 case 0x7a: /* FABD */
9030 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9031 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9033 case 0x7c: /* FCMGT */
9034 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9036 case 0x7d: /* FACGT */
9037 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9040 g_assert_not_reached();
9043 if (elements
== 1) {
9044 /* scalar single so clear high part */
9045 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9047 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9048 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9049 tcg_temp_free_i64(tcg_tmp
);
9051 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9054 tcg_temp_free_i32(tcg_res
);
9055 tcg_temp_free_i32(tcg_op1
);
9056 tcg_temp_free_i32(tcg_op2
);
9060 tcg_temp_free_ptr(fpst
);
9062 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9065 /* AdvSIMD scalar three same
9066 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9067 * +-----+---+-----------+------+---+------+--------+---+------+------+
9068 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9069 * +-----+---+-----------+------+---+------+--------+---+------+------+
9071 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9073 int rd
= extract32(insn
, 0, 5);
9074 int rn
= extract32(insn
, 5, 5);
9075 int opcode
= extract32(insn
, 11, 5);
9076 int rm
= extract32(insn
, 16, 5);
9077 int size
= extract32(insn
, 22, 2);
9078 bool u
= extract32(insn
, 29, 1);
9081 if (opcode
>= 0x18) {
9082 /* Floating point: U, size[1] and opcode indicate operation */
9083 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9085 case 0x1b: /* FMULX */
9086 case 0x1f: /* FRECPS */
9087 case 0x3f: /* FRSQRTS */
9088 case 0x5d: /* FACGE */
9089 case 0x7d: /* FACGT */
9090 case 0x1c: /* FCMEQ */
9091 case 0x5c: /* FCMGE */
9092 case 0x7c: /* FCMGT */
9093 case 0x7a: /* FABD */
9096 unallocated_encoding(s
);
9100 if (!fp_access_check(s
)) {
9104 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9109 case 0x1: /* SQADD, UQADD */
9110 case 0x5: /* SQSUB, UQSUB */
9111 case 0x9: /* SQSHL, UQSHL */
9112 case 0xb: /* SQRSHL, UQRSHL */
9114 case 0x8: /* SSHL, USHL */
9115 case 0xa: /* SRSHL, URSHL */
9116 case 0x6: /* CMGT, CMHI */
9117 case 0x7: /* CMGE, CMHS */
9118 case 0x11: /* CMTST, CMEQ */
9119 case 0x10: /* ADD, SUB (vector) */
9121 unallocated_encoding(s
);
9125 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9126 if (size
!= 1 && size
!= 2) {
9127 unallocated_encoding(s
);
9132 unallocated_encoding(s
);
9136 if (!fp_access_check(s
)) {
9140 tcg_rd
= tcg_temp_new_i64();
9143 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9144 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9146 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9147 tcg_temp_free_i64(tcg_rn
);
9148 tcg_temp_free_i64(tcg_rm
);
9150 /* Do a single operation on the lowest element in the vector.
9151 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9152 * no side effects for all these operations.
9153 * OPTME: special-purpose helpers would avoid doing some
9154 * unnecessary work in the helper for the 8 and 16 bit cases.
9156 NeonGenTwoOpEnvFn
*genenvfn
;
9157 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9158 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9159 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9161 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9162 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9165 case 0x1: /* SQADD, UQADD */
9167 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9168 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9169 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9170 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9172 genenvfn
= fns
[size
][u
];
9175 case 0x5: /* SQSUB, UQSUB */
9177 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9178 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9179 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9180 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9182 genenvfn
= fns
[size
][u
];
9185 case 0x9: /* SQSHL, UQSHL */
9187 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9188 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9189 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9190 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9192 genenvfn
= fns
[size
][u
];
9195 case 0xb: /* SQRSHL, UQRSHL */
9197 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9198 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9199 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9200 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9202 genenvfn
= fns
[size
][u
];
9205 case 0x16: /* SQDMULH, SQRDMULH */
9207 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9208 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9209 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9211 assert(size
== 1 || size
== 2);
9212 genenvfn
= fns
[size
- 1][u
];
9216 g_assert_not_reached();
9219 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9220 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9221 tcg_temp_free_i32(tcg_rd32
);
9222 tcg_temp_free_i32(tcg_rn
);
9223 tcg_temp_free_i32(tcg_rm
);
9226 write_fp_dreg(s
, rd
, tcg_rd
);
9228 tcg_temp_free_i64(tcg_rd
);
9231 /* AdvSIMD scalar three same FP16
9232 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9233 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9234 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9235 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9236 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9237 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9239 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9242 int rd
= extract32(insn
, 0, 5);
9243 int rn
= extract32(insn
, 5, 5);
9244 int opcode
= extract32(insn
, 11, 3);
9245 int rm
= extract32(insn
, 16, 5);
9246 bool u
= extract32(insn
, 29, 1);
9247 bool a
= extract32(insn
, 23, 1);
9248 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9255 case 0x03: /* FMULX */
9256 case 0x04: /* FCMEQ (reg) */
9257 case 0x07: /* FRECPS */
9258 case 0x0f: /* FRSQRTS */
9259 case 0x14: /* FCMGE (reg) */
9260 case 0x15: /* FACGE */
9261 case 0x1a: /* FABD */
9262 case 0x1c: /* FCMGT (reg) */
9263 case 0x1d: /* FACGT */
9266 unallocated_encoding(s
);
9270 if (!dc_isar_feature(aa64_fp16
, s
)) {
9271 unallocated_encoding(s
);
9274 if (!fp_access_check(s
)) {
9278 fpst
= get_fpstatus_ptr(true);
9280 tcg_op1
= read_fp_hreg(s
, rn
);
9281 tcg_op2
= read_fp_hreg(s
, rm
);
9282 tcg_res
= tcg_temp_new_i32();
9285 case 0x03: /* FMULX */
9286 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9288 case 0x04: /* FCMEQ (reg) */
9289 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9291 case 0x07: /* FRECPS */
9292 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9294 case 0x0f: /* FRSQRTS */
9295 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9297 case 0x14: /* FCMGE (reg) */
9298 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9300 case 0x15: /* FACGE */
9301 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9303 case 0x1a: /* FABD */
9304 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9305 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9307 case 0x1c: /* FCMGT (reg) */
9308 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9310 case 0x1d: /* FACGT */
9311 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9314 g_assert_not_reached();
9317 write_fp_sreg(s
, rd
, tcg_res
);
9320 tcg_temp_free_i32(tcg_res
);
9321 tcg_temp_free_i32(tcg_op1
);
9322 tcg_temp_free_i32(tcg_op2
);
9323 tcg_temp_free_ptr(fpst
);
9326 /* AdvSIMD scalar three same extra
9327 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9328 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9329 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9330 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9332 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9335 int rd
= extract32(insn
, 0, 5);
9336 int rn
= extract32(insn
, 5, 5);
9337 int opcode
= extract32(insn
, 11, 4);
9338 int rm
= extract32(insn
, 16, 5);
9339 int size
= extract32(insn
, 22, 2);
9340 bool u
= extract32(insn
, 29, 1);
9341 TCGv_i32 ele1
, ele2
, ele3
;
9345 switch (u
* 16 + opcode
) {
9346 case 0x10: /* SQRDMLAH (vector) */
9347 case 0x11: /* SQRDMLSH (vector) */
9348 if (size
!= 1 && size
!= 2) {
9349 unallocated_encoding(s
);
9352 feature
= dc_isar_feature(aa64_rdm
, s
);
9355 unallocated_encoding(s
);
9359 unallocated_encoding(s
);
9362 if (!fp_access_check(s
)) {
9366 /* Do a single operation on the lowest element in the vector.
9367 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9368 * with no side effects for all these operations.
9369 * OPTME: special-purpose helpers would avoid doing some
9370 * unnecessary work in the helper for the 16 bit cases.
9372 ele1
= tcg_temp_new_i32();
9373 ele2
= tcg_temp_new_i32();
9374 ele3
= tcg_temp_new_i32();
9376 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9377 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9378 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9381 case 0x0: /* SQRDMLAH */
9383 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9385 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9388 case 0x1: /* SQRDMLSH */
9390 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9392 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9396 g_assert_not_reached();
9398 tcg_temp_free_i32(ele1
);
9399 tcg_temp_free_i32(ele2
);
9401 res
= tcg_temp_new_i64();
9402 tcg_gen_extu_i32_i64(res
, ele3
);
9403 tcg_temp_free_i32(ele3
);
9405 write_fp_dreg(s
, rd
, res
);
9406 tcg_temp_free_i64(res
);
9409 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9410 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9411 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9413 /* Handle 64->64 opcodes which are shared between the scalar and
9414 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9415 * is valid in either group and also the double-precision fp ops.
9416 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9422 case 0x4: /* CLS, CLZ */
9424 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9426 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9430 /* This opcode is shared with CNT and RBIT but we have earlier
9431 * enforced that size == 3 if and only if this is the NOT insn.
9433 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9435 case 0x7: /* SQABS, SQNEG */
9437 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9439 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9442 case 0xa: /* CMLT */
9443 /* 64 bit integer comparison against zero, result is
9444 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9449 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9450 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9452 case 0x8: /* CMGT, CMGE */
9453 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9455 case 0x9: /* CMEQ, CMLE */
9456 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9458 case 0xb: /* ABS, NEG */
9460 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9462 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9465 case 0x2f: /* FABS */
9466 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9468 case 0x6f: /* FNEG */
9469 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9471 case 0x7f: /* FSQRT */
9472 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9474 case 0x1a: /* FCVTNS */
9475 case 0x1b: /* FCVTMS */
9476 case 0x1c: /* FCVTAS */
9477 case 0x3a: /* FCVTPS */
9478 case 0x3b: /* FCVTZS */
9480 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9481 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9482 tcg_temp_free_i32(tcg_shift
);
9485 case 0x5a: /* FCVTNU */
9486 case 0x5b: /* FCVTMU */
9487 case 0x5c: /* FCVTAU */
9488 case 0x7a: /* FCVTPU */
9489 case 0x7b: /* FCVTZU */
9491 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9492 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9493 tcg_temp_free_i32(tcg_shift
);
9496 case 0x18: /* FRINTN */
9497 case 0x19: /* FRINTM */
9498 case 0x38: /* FRINTP */
9499 case 0x39: /* FRINTZ */
9500 case 0x58: /* FRINTA */
9501 case 0x79: /* FRINTI */
9502 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9504 case 0x59: /* FRINTX */
9505 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9507 case 0x1e: /* FRINT32Z */
9508 case 0x5e: /* FRINT32X */
9509 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9511 case 0x1f: /* FRINT64Z */
9512 case 0x5f: /* FRINT64X */
9513 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9516 g_assert_not_reached();
9520 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9521 bool is_scalar
, bool is_u
, bool is_q
,
9522 int size
, int rn
, int rd
)
9524 bool is_double
= (size
== MO_64
);
9527 if (!fp_access_check(s
)) {
9531 fpst
= get_fpstatus_ptr(size
== MO_16
);
9534 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9535 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9536 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9537 NeonGenTwoDoubleOPFn
*genfn
;
9542 case 0x2e: /* FCMLT (zero) */
9545 case 0x2c: /* FCMGT (zero) */
9546 genfn
= gen_helper_neon_cgt_f64
;
9548 case 0x2d: /* FCMEQ (zero) */
9549 genfn
= gen_helper_neon_ceq_f64
;
9551 case 0x6d: /* FCMLE (zero) */
9554 case 0x6c: /* FCMGE (zero) */
9555 genfn
= gen_helper_neon_cge_f64
;
9558 g_assert_not_reached();
9561 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9562 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9564 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9566 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9568 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9570 tcg_temp_free_i64(tcg_res
);
9571 tcg_temp_free_i64(tcg_zero
);
9572 tcg_temp_free_i64(tcg_op
);
9574 clear_vec_high(s
, !is_scalar
, rd
);
9576 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9577 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9578 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9579 NeonGenTwoSingleOPFn
*genfn
;
9581 int pass
, maxpasses
;
9583 if (size
== MO_16
) {
9585 case 0x2e: /* FCMLT (zero) */
9588 case 0x2c: /* FCMGT (zero) */
9589 genfn
= gen_helper_advsimd_cgt_f16
;
9591 case 0x2d: /* FCMEQ (zero) */
9592 genfn
= gen_helper_advsimd_ceq_f16
;
9594 case 0x6d: /* FCMLE (zero) */
9597 case 0x6c: /* FCMGE (zero) */
9598 genfn
= gen_helper_advsimd_cge_f16
;
9601 g_assert_not_reached();
9605 case 0x2e: /* FCMLT (zero) */
9608 case 0x2c: /* FCMGT (zero) */
9609 genfn
= gen_helper_neon_cgt_f32
;
9611 case 0x2d: /* FCMEQ (zero) */
9612 genfn
= gen_helper_neon_ceq_f32
;
9614 case 0x6d: /* FCMLE (zero) */
9617 case 0x6c: /* FCMGE (zero) */
9618 genfn
= gen_helper_neon_cge_f32
;
9621 g_assert_not_reached();
9628 int vector_size
= 8 << is_q
;
9629 maxpasses
= vector_size
>> size
;
9632 for (pass
= 0; pass
< maxpasses
; pass
++) {
9633 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9635 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9637 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9640 write_fp_sreg(s
, rd
, tcg_res
);
9642 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9645 tcg_temp_free_i32(tcg_res
);
9646 tcg_temp_free_i32(tcg_zero
);
9647 tcg_temp_free_i32(tcg_op
);
9649 clear_vec_high(s
, is_q
, rd
);
9653 tcg_temp_free_ptr(fpst
);
9656 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9657 bool is_scalar
, bool is_u
, bool is_q
,
9658 int size
, int rn
, int rd
)
9660 bool is_double
= (size
== 3);
9661 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9664 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9665 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9668 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9669 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9671 case 0x3d: /* FRECPE */
9672 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9674 case 0x3f: /* FRECPX */
9675 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9677 case 0x7d: /* FRSQRTE */
9678 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9681 g_assert_not_reached();
9683 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9685 tcg_temp_free_i64(tcg_res
);
9686 tcg_temp_free_i64(tcg_op
);
9687 clear_vec_high(s
, !is_scalar
, rd
);
9689 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9690 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9691 int pass
, maxpasses
;
9696 maxpasses
= is_q
? 4 : 2;
9699 for (pass
= 0; pass
< maxpasses
; pass
++) {
9700 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9703 case 0x3c: /* URECPE */
9704 gen_helper_recpe_u32(tcg_res
, tcg_op
);
9706 case 0x3d: /* FRECPE */
9707 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9709 case 0x3f: /* FRECPX */
9710 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9712 case 0x7d: /* FRSQRTE */
9713 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9716 g_assert_not_reached();
9720 write_fp_sreg(s
, rd
, tcg_res
);
9722 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9725 tcg_temp_free_i32(tcg_res
);
9726 tcg_temp_free_i32(tcg_op
);
9728 clear_vec_high(s
, is_q
, rd
);
9731 tcg_temp_free_ptr(fpst
);
9734 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9735 int opcode
, bool u
, bool is_q
,
9736 int size
, int rn
, int rd
)
9738 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9739 * in the source becomes a size element in the destination).
9742 TCGv_i32 tcg_res
[2];
9743 int destelt
= is_q
? 2 : 0;
9744 int passes
= scalar
? 1 : 2;
9747 tcg_res
[1] = tcg_const_i32(0);
9750 for (pass
= 0; pass
< passes
; pass
++) {
9751 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9752 NeonGenNarrowFn
*genfn
= NULL
;
9753 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9756 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9758 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9760 tcg_res
[pass
] = tcg_temp_new_i32();
9763 case 0x12: /* XTN, SQXTUN */
9765 static NeonGenNarrowFn
* const xtnfns
[3] = {
9766 gen_helper_neon_narrow_u8
,
9767 gen_helper_neon_narrow_u16
,
9768 tcg_gen_extrl_i64_i32
,
9770 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9771 gen_helper_neon_unarrow_sat8
,
9772 gen_helper_neon_unarrow_sat16
,
9773 gen_helper_neon_unarrow_sat32
,
9776 genenvfn
= sqxtunfns
[size
];
9778 genfn
= xtnfns
[size
];
9782 case 0x14: /* SQXTN, UQXTN */
9784 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9785 { gen_helper_neon_narrow_sat_s8
,
9786 gen_helper_neon_narrow_sat_u8
},
9787 { gen_helper_neon_narrow_sat_s16
,
9788 gen_helper_neon_narrow_sat_u16
},
9789 { gen_helper_neon_narrow_sat_s32
,
9790 gen_helper_neon_narrow_sat_u32
},
9792 genenvfn
= fns
[size
][u
];
9795 case 0x16: /* FCVTN, FCVTN2 */
9796 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9798 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9800 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9801 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9802 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9803 TCGv_i32 ahp
= get_ahp_flag();
9805 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9806 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9807 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9808 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9809 tcg_temp_free_i32(tcg_lo
);
9810 tcg_temp_free_i32(tcg_hi
);
9811 tcg_temp_free_ptr(fpst
);
9812 tcg_temp_free_i32(ahp
);
9815 case 0x56: /* FCVTXN, FCVTXN2 */
9816 /* 64 bit to 32 bit float conversion
9817 * with von Neumann rounding (round to odd)
9820 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9823 g_assert_not_reached();
9827 genfn(tcg_res
[pass
], tcg_op
);
9828 } else if (genenvfn
) {
9829 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9832 tcg_temp_free_i64(tcg_op
);
9835 for (pass
= 0; pass
< 2; pass
++) {
9836 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9837 tcg_temp_free_i32(tcg_res
[pass
]);
9839 clear_vec_high(s
, is_q
, rd
);
9842 /* Remaining saturating accumulating ops */
9843 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9844 bool is_q
, int size
, int rn
, int rd
)
9846 bool is_double
= (size
== 3);
9849 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9850 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9853 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9854 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9855 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9857 if (is_u
) { /* USQADD */
9858 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9859 } else { /* SUQADD */
9860 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9862 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9864 tcg_temp_free_i64(tcg_rd
);
9865 tcg_temp_free_i64(tcg_rn
);
9866 clear_vec_high(s
, !is_scalar
, rd
);
9868 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9869 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9870 int pass
, maxpasses
;
9875 maxpasses
= is_q
? 4 : 2;
9878 for (pass
= 0; pass
< maxpasses
; pass
++) {
9880 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9881 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9883 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9884 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9887 if (is_u
) { /* USQADD */
9890 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9893 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9896 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9899 g_assert_not_reached();
9901 } else { /* SUQADD */
9904 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9907 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9910 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9913 g_assert_not_reached();
9918 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9919 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9920 tcg_temp_free_i64(tcg_zero
);
9922 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9924 tcg_temp_free_i32(tcg_rd
);
9925 tcg_temp_free_i32(tcg_rn
);
9926 clear_vec_high(s
, is_q
, rd
);
9930 /* AdvSIMD scalar two reg misc
9931 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9932 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9933 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9934 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9936 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9938 int rd
= extract32(insn
, 0, 5);
9939 int rn
= extract32(insn
, 5, 5);
9940 int opcode
= extract32(insn
, 12, 5);
9941 int size
= extract32(insn
, 22, 2);
9942 bool u
= extract32(insn
, 29, 1);
9943 bool is_fcvt
= false;
9946 TCGv_ptr tcg_fpstatus
;
9949 case 0x3: /* USQADD / SUQADD*/
9950 if (!fp_access_check(s
)) {
9953 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9955 case 0x7: /* SQABS / SQNEG */
9957 case 0xa: /* CMLT */
9959 unallocated_encoding(s
);
9963 case 0x8: /* CMGT, CMGE */
9964 case 0x9: /* CMEQ, CMLE */
9965 case 0xb: /* ABS, NEG */
9967 unallocated_encoding(s
);
9971 case 0x12: /* SQXTUN */
9973 unallocated_encoding(s
);
9977 case 0x14: /* SQXTN, UQXTN */
9979 unallocated_encoding(s
);
9982 if (!fp_access_check(s
)) {
9985 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9990 /* Floating point: U, size[1] and opcode indicate operation;
9991 * size[0] indicates single or double precision.
9993 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9994 size
= extract32(size
, 0, 1) ? 3 : 2;
9996 case 0x2c: /* FCMGT (zero) */
9997 case 0x2d: /* FCMEQ (zero) */
9998 case 0x2e: /* FCMLT (zero) */
9999 case 0x6c: /* FCMGE (zero) */
10000 case 0x6d: /* FCMLE (zero) */
10001 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10003 case 0x1d: /* SCVTF */
10004 case 0x5d: /* UCVTF */
10006 bool is_signed
= (opcode
== 0x1d);
10007 if (!fp_access_check(s
)) {
10010 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10013 case 0x3d: /* FRECPE */
10014 case 0x3f: /* FRECPX */
10015 case 0x7d: /* FRSQRTE */
10016 if (!fp_access_check(s
)) {
10019 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10021 case 0x1a: /* FCVTNS */
10022 case 0x1b: /* FCVTMS */
10023 case 0x3a: /* FCVTPS */
10024 case 0x3b: /* FCVTZS */
10025 case 0x5a: /* FCVTNU */
10026 case 0x5b: /* FCVTMU */
10027 case 0x7a: /* FCVTPU */
10028 case 0x7b: /* FCVTZU */
10030 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10032 case 0x1c: /* FCVTAS */
10033 case 0x5c: /* FCVTAU */
10034 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10036 rmode
= FPROUNDING_TIEAWAY
;
10038 case 0x56: /* FCVTXN, FCVTXN2 */
10040 unallocated_encoding(s
);
10043 if (!fp_access_check(s
)) {
10046 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10049 unallocated_encoding(s
);
10054 unallocated_encoding(s
);
10058 if (!fp_access_check(s
)) {
10063 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10064 tcg_fpstatus
= get_fpstatus_ptr(false);
10065 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10068 tcg_fpstatus
= NULL
;
10072 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10073 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10075 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10076 write_fp_dreg(s
, rd
, tcg_rd
);
10077 tcg_temp_free_i64(tcg_rd
);
10078 tcg_temp_free_i64(tcg_rn
);
10080 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10081 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10083 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10086 case 0x7: /* SQABS, SQNEG */
10088 NeonGenOneOpEnvFn
*genfn
;
10089 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10090 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10091 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10092 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10094 genfn
= fns
[size
][u
];
10095 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10098 case 0x1a: /* FCVTNS */
10099 case 0x1b: /* FCVTMS */
10100 case 0x1c: /* FCVTAS */
10101 case 0x3a: /* FCVTPS */
10102 case 0x3b: /* FCVTZS */
10104 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10105 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10106 tcg_temp_free_i32(tcg_shift
);
10109 case 0x5a: /* FCVTNU */
10110 case 0x5b: /* FCVTMU */
10111 case 0x5c: /* FCVTAU */
10112 case 0x7a: /* FCVTPU */
10113 case 0x7b: /* FCVTZU */
10115 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10116 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10117 tcg_temp_free_i32(tcg_shift
);
10121 g_assert_not_reached();
10124 write_fp_sreg(s
, rd
, tcg_rd
);
10125 tcg_temp_free_i32(tcg_rd
);
10126 tcg_temp_free_i32(tcg_rn
);
10130 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10131 tcg_temp_free_i32(tcg_rmode
);
10132 tcg_temp_free_ptr(tcg_fpstatus
);
10136 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10137 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10138 int immh
, int immb
, int opcode
, int rn
, int rd
)
10140 int size
= 32 - clz32(immh
) - 1;
10141 int immhb
= immh
<< 3 | immb
;
10142 int shift
= 2 * (8 << size
) - immhb
;
10143 GVecGen2iFn
*gvec_fn
;
10145 if (extract32(immh
, 3, 1) && !is_q
) {
10146 unallocated_encoding(s
);
10149 tcg_debug_assert(size
<= 3);
10151 if (!fp_access_check(s
)) {
10156 case 0x02: /* SSRA / USRA (accumulate) */
10157 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10160 case 0x08: /* SRI */
10161 gvec_fn
= gen_gvec_sri
;
10164 case 0x00: /* SSHR / USHR */
10166 if (shift
== 8 << size
) {
10167 /* Shift count the same size as element size produces zero. */
10168 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10169 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10172 gvec_fn
= tcg_gen_gvec_shri
;
10174 /* Shift count the same size as element size produces all sign. */
10175 if (shift
== 8 << size
) {
10178 gvec_fn
= tcg_gen_gvec_sari
;
10182 case 0x04: /* SRSHR / URSHR (rounding) */
10183 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10186 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10187 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10191 g_assert_not_reached();
10194 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10197 /* SHL/SLI - Vector shift left */
10198 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10199 int immh
, int immb
, int opcode
, int rn
, int rd
)
10201 int size
= 32 - clz32(immh
) - 1;
10202 int immhb
= immh
<< 3 | immb
;
10203 int shift
= immhb
- (8 << size
);
10205 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10206 assert(size
>= 0 && size
<= 3);
10208 if (extract32(immh
, 3, 1) && !is_q
) {
10209 unallocated_encoding(s
);
10213 if (!fp_access_check(s
)) {
10218 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10220 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10224 /* USHLL/SHLL - Vector shift left with widening */
10225 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10226 int immh
, int immb
, int opcode
, int rn
, int rd
)
10228 int size
= 32 - clz32(immh
) - 1;
10229 int immhb
= immh
<< 3 | immb
;
10230 int shift
= immhb
- (8 << size
);
10232 int esize
= 8 << size
;
10233 int elements
= dsize
/esize
;
10234 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10235 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10239 unallocated_encoding(s
);
10243 if (!fp_access_check(s
)) {
10247 /* For the LL variants the store is larger than the load,
10248 * so if rd == rn we would overwrite parts of our input.
10249 * So load everything right now and use shifts in the main loop.
10251 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10253 for (i
= 0; i
< elements
; i
++) {
10254 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10255 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10256 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10257 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10261 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10262 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10263 int immh
, int immb
, int opcode
, int rn
, int rd
)
10265 int immhb
= immh
<< 3 | immb
;
10266 int size
= 32 - clz32(immh
) - 1;
10268 int esize
= 8 << size
;
10269 int elements
= dsize
/esize
;
10270 int shift
= (2 * esize
) - immhb
;
10271 bool round
= extract32(opcode
, 0, 1);
10272 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10273 TCGv_i64 tcg_round
;
10276 if (extract32(immh
, 3, 1)) {
10277 unallocated_encoding(s
);
10281 if (!fp_access_check(s
)) {
10285 tcg_rn
= tcg_temp_new_i64();
10286 tcg_rd
= tcg_temp_new_i64();
10287 tcg_final
= tcg_temp_new_i64();
10288 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10291 uint64_t round_const
= 1ULL << (shift
- 1);
10292 tcg_round
= tcg_const_i64(round_const
);
10297 for (i
= 0; i
< elements
; i
++) {
10298 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10299 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10300 false, true, size
+1, shift
);
10302 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10306 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10308 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10311 tcg_temp_free_i64(tcg_round
);
10313 tcg_temp_free_i64(tcg_rn
);
10314 tcg_temp_free_i64(tcg_rd
);
10315 tcg_temp_free_i64(tcg_final
);
10317 clear_vec_high(s
, is_q
, rd
);
10321 /* AdvSIMD shift by immediate
10322 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10323 * +---+---+---+-------------+------+------+--------+---+------+------+
10324 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10325 * +---+---+---+-------------+------+------+--------+---+------+------+
10327 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10329 int rd
= extract32(insn
, 0, 5);
10330 int rn
= extract32(insn
, 5, 5);
10331 int opcode
= extract32(insn
, 11, 5);
10332 int immb
= extract32(insn
, 16, 3);
10333 int immh
= extract32(insn
, 19, 4);
10334 bool is_u
= extract32(insn
, 29, 1);
10335 bool is_q
= extract32(insn
, 30, 1);
10337 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10341 case 0x08: /* SRI */
10343 unallocated_encoding(s
);
10347 case 0x00: /* SSHR / USHR */
10348 case 0x02: /* SSRA / USRA (accumulate) */
10349 case 0x04: /* SRSHR / URSHR (rounding) */
10350 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10351 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10353 case 0x0a: /* SHL / SLI */
10354 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10356 case 0x10: /* SHRN */
10357 case 0x11: /* RSHRN / SQRSHRUN */
10359 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10362 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10365 case 0x12: /* SQSHRN / UQSHRN */
10366 case 0x13: /* SQRSHRN / UQRSHRN */
10367 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10370 case 0x14: /* SSHLL / USHLL */
10371 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10373 case 0x1c: /* SCVTF / UCVTF */
10374 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10377 case 0xc: /* SQSHLU */
10379 unallocated_encoding(s
);
10382 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10384 case 0xe: /* SQSHL, UQSHL */
10385 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10387 case 0x1f: /* FCVTZS/ FCVTZU */
10388 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10391 unallocated_encoding(s
);
10396 /* Generate code to do a "long" addition or subtraction, ie one done in
10397 * TCGv_i64 on vector lanes twice the width specified by size.
10399 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10400 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10402 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10403 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10404 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10405 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10407 NeonGenTwo64OpFn
*genfn
;
10410 genfn
= fns
[size
][is_sub
];
10411 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10414 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10415 int opcode
, int rd
, int rn
, int rm
)
10417 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10418 TCGv_i64 tcg_res
[2];
10421 tcg_res
[0] = tcg_temp_new_i64();
10422 tcg_res
[1] = tcg_temp_new_i64();
10424 /* Does this op do an adding accumulate, a subtracting accumulate,
10425 * or no accumulate at all?
10443 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10444 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10447 /* size == 2 means two 32x32->64 operations; this is worth special
10448 * casing because we can generally handle it inline.
10451 for (pass
= 0; pass
< 2; pass
++) {
10452 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10453 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10454 TCGv_i64 tcg_passres
;
10455 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10457 int elt
= pass
+ is_q
* 2;
10459 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10460 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10463 tcg_passres
= tcg_res
[pass
];
10465 tcg_passres
= tcg_temp_new_i64();
10469 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10470 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10472 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10473 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10475 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10476 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10478 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10479 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10481 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10482 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10483 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10485 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10486 tcg_temp_free_i64(tcg_tmp1
);
10487 tcg_temp_free_i64(tcg_tmp2
);
10490 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10491 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10492 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10493 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10495 case 9: /* SQDMLAL, SQDMLAL2 */
10496 case 11: /* SQDMLSL, SQDMLSL2 */
10497 case 13: /* SQDMULL, SQDMULL2 */
10498 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10499 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10500 tcg_passres
, tcg_passres
);
10503 g_assert_not_reached();
10506 if (opcode
== 9 || opcode
== 11) {
10507 /* saturating accumulate ops */
10509 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10511 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10512 tcg_res
[pass
], tcg_passres
);
10513 } else if (accop
> 0) {
10514 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10515 } else if (accop
< 0) {
10516 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10520 tcg_temp_free_i64(tcg_passres
);
10523 tcg_temp_free_i64(tcg_op1
);
10524 tcg_temp_free_i64(tcg_op2
);
10527 /* size 0 or 1, generally helper functions */
10528 for (pass
= 0; pass
< 2; pass
++) {
10529 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10530 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10531 TCGv_i64 tcg_passres
;
10532 int elt
= pass
+ is_q
* 2;
10534 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10535 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10538 tcg_passres
= tcg_res
[pass
];
10540 tcg_passres
= tcg_temp_new_i64();
10544 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10545 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10547 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10548 static NeonGenWidenFn
* const widenfns
[2][2] = {
10549 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10550 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10552 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10554 widenfn(tcg_op2_64
, tcg_op2
);
10555 widenfn(tcg_passres
, tcg_op1
);
10556 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10557 tcg_passres
, tcg_op2_64
);
10558 tcg_temp_free_i64(tcg_op2_64
);
10561 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10562 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10565 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10567 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10571 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10573 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10577 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10578 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10579 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10582 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10584 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10588 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10590 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10594 case 9: /* SQDMLAL, SQDMLAL2 */
10595 case 11: /* SQDMLSL, SQDMLSL2 */
10596 case 13: /* SQDMULL, SQDMULL2 */
10598 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10599 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10600 tcg_passres
, tcg_passres
);
10603 g_assert_not_reached();
10605 tcg_temp_free_i32(tcg_op1
);
10606 tcg_temp_free_i32(tcg_op2
);
10609 if (opcode
== 9 || opcode
== 11) {
10610 /* saturating accumulate ops */
10612 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10614 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10618 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10619 tcg_res
[pass
], tcg_passres
);
10621 tcg_temp_free_i64(tcg_passres
);
10626 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10627 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10628 tcg_temp_free_i64(tcg_res
[0]);
10629 tcg_temp_free_i64(tcg_res
[1]);
10632 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10633 int opcode
, int rd
, int rn
, int rm
)
10635 TCGv_i64 tcg_res
[2];
10636 int part
= is_q
? 2 : 0;
10639 for (pass
= 0; pass
< 2; pass
++) {
10640 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10641 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10642 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10643 static NeonGenWidenFn
* const widenfns
[3][2] = {
10644 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10645 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10646 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10648 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10650 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10651 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10652 widenfn(tcg_op2_wide
, tcg_op2
);
10653 tcg_temp_free_i32(tcg_op2
);
10654 tcg_res
[pass
] = tcg_temp_new_i64();
10655 gen_neon_addl(size
, (opcode
== 3),
10656 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10657 tcg_temp_free_i64(tcg_op1
);
10658 tcg_temp_free_i64(tcg_op2_wide
);
10661 for (pass
= 0; pass
< 2; pass
++) {
10662 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10663 tcg_temp_free_i64(tcg_res
[pass
]);
10667 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10669 tcg_gen_addi_i64(in
, in
, 1U << 31);
10670 tcg_gen_extrh_i64_i32(res
, in
);
10673 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10674 int opcode
, int rd
, int rn
, int rm
)
10676 TCGv_i32 tcg_res
[2];
10677 int part
= is_q
? 2 : 0;
10680 for (pass
= 0; pass
< 2; pass
++) {
10681 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10682 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10683 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10684 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10685 { gen_helper_neon_narrow_high_u8
,
10686 gen_helper_neon_narrow_round_high_u8
},
10687 { gen_helper_neon_narrow_high_u16
,
10688 gen_helper_neon_narrow_round_high_u16
},
10689 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10691 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10693 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10694 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10696 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10698 tcg_temp_free_i64(tcg_op1
);
10699 tcg_temp_free_i64(tcg_op2
);
10701 tcg_res
[pass
] = tcg_temp_new_i32();
10702 gennarrow(tcg_res
[pass
], tcg_wideres
);
10703 tcg_temp_free_i64(tcg_wideres
);
10706 for (pass
= 0; pass
< 2; pass
++) {
10707 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10708 tcg_temp_free_i32(tcg_res
[pass
]);
10710 clear_vec_high(s
, is_q
, rd
);
10713 /* AdvSIMD three different
10714 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10715 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10716 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10717 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10719 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10721 /* Instructions in this group fall into three basic classes
10722 * (in each case with the operation working on each element in
10723 * the input vectors):
10724 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10726 * (2) wide 64 x 128 -> 128
10727 * (3) narrowing 128 x 128 -> 64
10728 * Here we do initial decode, catch unallocated cases and
10729 * dispatch to separate functions for each class.
10731 int is_q
= extract32(insn
, 30, 1);
10732 int is_u
= extract32(insn
, 29, 1);
10733 int size
= extract32(insn
, 22, 2);
10734 int opcode
= extract32(insn
, 12, 4);
10735 int rm
= extract32(insn
, 16, 5);
10736 int rn
= extract32(insn
, 5, 5);
10737 int rd
= extract32(insn
, 0, 5);
10740 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10741 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10742 /* 64 x 128 -> 128 */
10744 unallocated_encoding(s
);
10747 if (!fp_access_check(s
)) {
10750 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10752 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10753 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10754 /* 128 x 128 -> 64 */
10756 unallocated_encoding(s
);
10759 if (!fp_access_check(s
)) {
10762 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10764 case 14: /* PMULL, PMULL2 */
10766 unallocated_encoding(s
);
10770 case 0: /* PMULL.P8 */
10771 if (!fp_access_check(s
)) {
10774 /* The Q field specifies lo/hi half input for this insn. */
10775 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10776 gen_helper_neon_pmull_h
);
10779 case 3: /* PMULL.P64 */
10780 if (!dc_isar_feature(aa64_pmull
, s
)) {
10781 unallocated_encoding(s
);
10784 if (!fp_access_check(s
)) {
10787 /* The Q field specifies lo/hi half input for this insn. */
10788 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10789 gen_helper_gvec_pmull_q
);
10793 unallocated_encoding(s
);
10797 case 9: /* SQDMLAL, SQDMLAL2 */
10798 case 11: /* SQDMLSL, SQDMLSL2 */
10799 case 13: /* SQDMULL, SQDMULL2 */
10800 if (is_u
|| size
== 0) {
10801 unallocated_encoding(s
);
10805 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10806 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10807 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10808 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10809 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10810 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10811 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10812 /* 64 x 64 -> 128 */
10814 unallocated_encoding(s
);
10817 if (!fp_access_check(s
)) {
10821 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10824 /* opcode 15 not allocated */
10825 unallocated_encoding(s
);
10830 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10831 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10833 int rd
= extract32(insn
, 0, 5);
10834 int rn
= extract32(insn
, 5, 5);
10835 int rm
= extract32(insn
, 16, 5);
10836 int size
= extract32(insn
, 22, 2);
10837 bool is_u
= extract32(insn
, 29, 1);
10838 bool is_q
= extract32(insn
, 30, 1);
10840 if (!fp_access_check(s
)) {
10844 switch (size
+ 4 * is_u
) {
10846 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10849 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10852 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10855 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10858 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10861 case 5: /* BSL bitwise select */
10862 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10864 case 6: /* BIT, bitwise insert if true */
10865 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10867 case 7: /* BIF, bitwise insert if false */
10868 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10872 g_assert_not_reached();
10876 /* Pairwise op subgroup of C3.6.16.
10878 * This is called directly or via the handle_3same_float for float pairwise
10879 * operations where the opcode and size are calculated differently.
10881 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10882 int size
, int rn
, int rm
, int rd
)
10887 /* Floating point operations need fpst */
10888 if (opcode
>= 0x58) {
10889 fpst
= get_fpstatus_ptr(false);
10894 if (!fp_access_check(s
)) {
10898 /* These operations work on the concatenated rm:rn, with each pair of
10899 * adjacent elements being operated on to produce an element in the result.
10902 TCGv_i64 tcg_res
[2];
10904 for (pass
= 0; pass
< 2; pass
++) {
10905 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10906 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10907 int passreg
= (pass
== 0) ? rn
: rm
;
10909 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10910 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10911 tcg_res
[pass
] = tcg_temp_new_i64();
10914 case 0x17: /* ADDP */
10915 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10917 case 0x58: /* FMAXNMP */
10918 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10920 case 0x5a: /* FADDP */
10921 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10923 case 0x5e: /* FMAXP */
10924 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10926 case 0x78: /* FMINNMP */
10927 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10929 case 0x7e: /* FMINP */
10930 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10933 g_assert_not_reached();
10936 tcg_temp_free_i64(tcg_op1
);
10937 tcg_temp_free_i64(tcg_op2
);
10940 for (pass
= 0; pass
< 2; pass
++) {
10941 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10942 tcg_temp_free_i64(tcg_res
[pass
]);
10945 int maxpass
= is_q
? 4 : 2;
10946 TCGv_i32 tcg_res
[4];
10948 for (pass
= 0; pass
< maxpass
; pass
++) {
10949 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10950 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10951 NeonGenTwoOpFn
*genfn
= NULL
;
10952 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10953 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10955 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10956 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10957 tcg_res
[pass
] = tcg_temp_new_i32();
10960 case 0x17: /* ADDP */
10962 static NeonGenTwoOpFn
* const fns
[3] = {
10963 gen_helper_neon_padd_u8
,
10964 gen_helper_neon_padd_u16
,
10970 case 0x14: /* SMAXP, UMAXP */
10972 static NeonGenTwoOpFn
* const fns
[3][2] = {
10973 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10974 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10975 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10977 genfn
= fns
[size
][u
];
10980 case 0x15: /* SMINP, UMINP */
10982 static NeonGenTwoOpFn
* const fns
[3][2] = {
10983 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10984 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10985 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10987 genfn
= fns
[size
][u
];
10990 /* The FP operations are all on single floats (32 bit) */
10991 case 0x58: /* FMAXNMP */
10992 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10994 case 0x5a: /* FADDP */
10995 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10997 case 0x5e: /* FMAXP */
10998 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11000 case 0x78: /* FMINNMP */
11001 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11003 case 0x7e: /* FMINP */
11004 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11007 g_assert_not_reached();
11010 /* FP ops called directly, otherwise call now */
11012 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11015 tcg_temp_free_i32(tcg_op1
);
11016 tcg_temp_free_i32(tcg_op2
);
11019 for (pass
= 0; pass
< maxpass
; pass
++) {
11020 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11021 tcg_temp_free_i32(tcg_res
[pass
]);
11023 clear_vec_high(s
, is_q
, rd
);
11027 tcg_temp_free_ptr(fpst
);
11031 /* Floating point op subgroup of C3.6.16. */
11032 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11034 /* For floating point ops, the U, size[1] and opcode bits
11035 * together indicate the operation. size[0] indicates single
11038 int fpopcode
= extract32(insn
, 11, 5)
11039 | (extract32(insn
, 23, 1) << 5)
11040 | (extract32(insn
, 29, 1) << 6);
11041 int is_q
= extract32(insn
, 30, 1);
11042 int size
= extract32(insn
, 22, 1);
11043 int rm
= extract32(insn
, 16, 5);
11044 int rn
= extract32(insn
, 5, 5);
11045 int rd
= extract32(insn
, 0, 5);
11047 int datasize
= is_q
? 128 : 64;
11048 int esize
= 32 << size
;
11049 int elements
= datasize
/ esize
;
11051 if (size
== 1 && !is_q
) {
11052 unallocated_encoding(s
);
11056 switch (fpopcode
) {
11057 case 0x58: /* FMAXNMP */
11058 case 0x5a: /* FADDP */
11059 case 0x5e: /* FMAXP */
11060 case 0x78: /* FMINNMP */
11061 case 0x7e: /* FMINP */
11062 if (size
&& !is_q
) {
11063 unallocated_encoding(s
);
11066 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11069 case 0x1b: /* FMULX */
11070 case 0x1f: /* FRECPS */
11071 case 0x3f: /* FRSQRTS */
11072 case 0x5d: /* FACGE */
11073 case 0x7d: /* FACGT */
11074 case 0x19: /* FMLA */
11075 case 0x39: /* FMLS */
11076 case 0x18: /* FMAXNM */
11077 case 0x1a: /* FADD */
11078 case 0x1c: /* FCMEQ */
11079 case 0x1e: /* FMAX */
11080 case 0x38: /* FMINNM */
11081 case 0x3a: /* FSUB */
11082 case 0x3e: /* FMIN */
11083 case 0x5b: /* FMUL */
11084 case 0x5c: /* FCMGE */
11085 case 0x5f: /* FDIV */
11086 case 0x7a: /* FABD */
11087 case 0x7c: /* FCMGT */
11088 if (!fp_access_check(s
)) {
11091 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11094 case 0x1d: /* FMLAL */
11095 case 0x3d: /* FMLSL */
11096 case 0x59: /* FMLAL2 */
11097 case 0x79: /* FMLSL2 */
11098 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11099 unallocated_encoding(s
);
11102 if (fp_access_check(s
)) {
11103 int is_s
= extract32(insn
, 23, 1);
11104 int is_2
= extract32(insn
, 29, 1);
11105 int data
= (is_2
<< 1) | is_s
;
11106 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11107 vec_full_reg_offset(s
, rn
),
11108 vec_full_reg_offset(s
, rm
), cpu_env
,
11109 is_q
? 16 : 8, vec_full_reg_size(s
),
11110 data
, gen_helper_gvec_fmlal_a64
);
11115 unallocated_encoding(s
);
11120 /* Integer op subgroup of C3.6.16. */
11121 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11123 int is_q
= extract32(insn
, 30, 1);
11124 int u
= extract32(insn
, 29, 1);
11125 int size
= extract32(insn
, 22, 2);
11126 int opcode
= extract32(insn
, 11, 5);
11127 int rm
= extract32(insn
, 16, 5);
11128 int rn
= extract32(insn
, 5, 5);
11129 int rd
= extract32(insn
, 0, 5);
11134 case 0x13: /* MUL, PMUL */
11135 if (u
&& size
!= 0) {
11136 unallocated_encoding(s
);
11140 case 0x0: /* SHADD, UHADD */
11141 case 0x2: /* SRHADD, URHADD */
11142 case 0x4: /* SHSUB, UHSUB */
11143 case 0xc: /* SMAX, UMAX */
11144 case 0xd: /* SMIN, UMIN */
11145 case 0xe: /* SABD, UABD */
11146 case 0xf: /* SABA, UABA */
11147 case 0x12: /* MLA, MLS */
11149 unallocated_encoding(s
);
11153 case 0x16: /* SQDMULH, SQRDMULH */
11154 if (size
== 0 || size
== 3) {
11155 unallocated_encoding(s
);
11160 if (size
== 3 && !is_q
) {
11161 unallocated_encoding(s
);
11167 if (!fp_access_check(s
)) {
11172 case 0x01: /* SQADD, UQADD */
11174 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11176 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11179 case 0x05: /* SQSUB, UQSUB */
11181 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11183 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11186 case 0x08: /* SSHL, USHL */
11188 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11190 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11193 case 0x0c: /* SMAX, UMAX */
11195 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11197 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11200 case 0x0d: /* SMIN, UMIN */
11202 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11204 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11207 case 0xe: /* SABD, UABD */
11209 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11211 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11214 case 0xf: /* SABA, UABA */
11216 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11218 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11221 case 0x10: /* ADD, SUB */
11223 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11225 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11228 case 0x13: /* MUL, PMUL */
11229 if (!u
) { /* MUL */
11230 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11231 } else { /* PMUL */
11232 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11235 case 0x12: /* MLA, MLS */
11237 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11239 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11243 if (!u
) { /* CMTST */
11244 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11248 cond
= TCG_COND_EQ
;
11250 case 0x06: /* CMGT, CMHI */
11251 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11253 case 0x07: /* CMGE, CMHS */
11254 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11256 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11257 vec_full_reg_offset(s
, rn
),
11258 vec_full_reg_offset(s
, rm
),
11259 is_q
? 16 : 8, vec_full_reg_size(s
));
11265 for (pass
= 0; pass
< 2; pass
++) {
11266 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11267 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11268 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11270 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11271 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11273 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11275 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11277 tcg_temp_free_i64(tcg_res
);
11278 tcg_temp_free_i64(tcg_op1
);
11279 tcg_temp_free_i64(tcg_op2
);
11282 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11283 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11284 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11285 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11286 NeonGenTwoOpFn
*genfn
= NULL
;
11287 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11289 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11290 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11293 case 0x0: /* SHADD, UHADD */
11295 static NeonGenTwoOpFn
* const fns
[3][2] = {
11296 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11297 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11298 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11300 genfn
= fns
[size
][u
];
11303 case 0x2: /* SRHADD, URHADD */
11305 static NeonGenTwoOpFn
* const fns
[3][2] = {
11306 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11307 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11308 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11310 genfn
= fns
[size
][u
];
11313 case 0x4: /* SHSUB, UHSUB */
11315 static NeonGenTwoOpFn
* const fns
[3][2] = {
11316 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11317 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11318 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11320 genfn
= fns
[size
][u
];
11323 case 0x9: /* SQSHL, UQSHL */
11325 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11326 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11327 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11328 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11330 genenvfn
= fns
[size
][u
];
11333 case 0xa: /* SRSHL, URSHL */
11335 static NeonGenTwoOpFn
* const fns
[3][2] = {
11336 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11337 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11338 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11340 genfn
= fns
[size
][u
];
11343 case 0xb: /* SQRSHL, UQRSHL */
11345 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11346 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11347 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11348 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11350 genenvfn
= fns
[size
][u
];
11353 case 0x16: /* SQDMULH, SQRDMULH */
11355 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11356 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11357 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11359 assert(size
== 1 || size
== 2);
11360 genenvfn
= fns
[size
- 1][u
];
11364 g_assert_not_reached();
11368 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11370 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11373 if (opcode
== 0xf) {
11374 /* SABA, UABA: accumulating ops */
11375 static NeonGenTwoOpFn
* const fns
[3] = {
11376 gen_helper_neon_add_u8
,
11377 gen_helper_neon_add_u16
,
11381 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11382 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11385 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11387 tcg_temp_free_i32(tcg_res
);
11388 tcg_temp_free_i32(tcg_op1
);
11389 tcg_temp_free_i32(tcg_op2
);
11392 clear_vec_high(s
, is_q
, rd
);
11395 /* AdvSIMD three same
11396 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11397 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11398 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11399 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11401 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11403 int opcode
= extract32(insn
, 11, 5);
11406 case 0x3: /* logic ops */
11407 disas_simd_3same_logic(s
, insn
);
11409 case 0x17: /* ADDP */
11410 case 0x14: /* SMAXP, UMAXP */
11411 case 0x15: /* SMINP, UMINP */
11413 /* Pairwise operations */
11414 int is_q
= extract32(insn
, 30, 1);
11415 int u
= extract32(insn
, 29, 1);
11416 int size
= extract32(insn
, 22, 2);
11417 int rm
= extract32(insn
, 16, 5);
11418 int rn
= extract32(insn
, 5, 5);
11419 int rd
= extract32(insn
, 0, 5);
11420 if (opcode
== 0x17) {
11421 if (u
|| (size
== 3 && !is_q
)) {
11422 unallocated_encoding(s
);
11427 unallocated_encoding(s
);
11431 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11434 case 0x18 ... 0x31:
11435 /* floating point ops, sz[1] and U are part of opcode */
11436 disas_simd_3same_float(s
, insn
);
11439 disas_simd_3same_int(s
, insn
);
11445 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11447 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11448 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11449 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11450 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11452 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11453 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11456 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11458 int opcode
, fpopcode
;
11459 int is_q
, u
, a
, rm
, rn
, rd
;
11460 int datasize
, elements
;
11463 bool pairwise
= false;
11465 if (!dc_isar_feature(aa64_fp16
, s
)) {
11466 unallocated_encoding(s
);
11470 if (!fp_access_check(s
)) {
11474 /* For these floating point ops, the U, a and opcode bits
11475 * together indicate the operation.
11477 opcode
= extract32(insn
, 11, 3);
11478 u
= extract32(insn
, 29, 1);
11479 a
= extract32(insn
, 23, 1);
11480 is_q
= extract32(insn
, 30, 1);
11481 rm
= extract32(insn
, 16, 5);
11482 rn
= extract32(insn
, 5, 5);
11483 rd
= extract32(insn
, 0, 5);
11485 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11486 datasize
= is_q
? 128 : 64;
11487 elements
= datasize
/ 16;
11489 switch (fpopcode
) {
11490 case 0x10: /* FMAXNMP */
11491 case 0x12: /* FADDP */
11492 case 0x16: /* FMAXP */
11493 case 0x18: /* FMINNMP */
11494 case 0x1e: /* FMINP */
11499 fpst
= get_fpstatus_ptr(true);
11502 int maxpass
= is_q
? 8 : 4;
11503 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11504 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11505 TCGv_i32 tcg_res
[8];
11507 for (pass
= 0; pass
< maxpass
; pass
++) {
11508 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11509 int passelt
= (pass
<< 1) & (maxpass
- 1);
11511 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11512 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11513 tcg_res
[pass
] = tcg_temp_new_i32();
11515 switch (fpopcode
) {
11516 case 0x10: /* FMAXNMP */
11517 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11520 case 0x12: /* FADDP */
11521 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11523 case 0x16: /* FMAXP */
11524 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11526 case 0x18: /* FMINNMP */
11527 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11530 case 0x1e: /* FMINP */
11531 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11534 g_assert_not_reached();
11538 for (pass
= 0; pass
< maxpass
; pass
++) {
11539 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11540 tcg_temp_free_i32(tcg_res
[pass
]);
11543 tcg_temp_free_i32(tcg_op1
);
11544 tcg_temp_free_i32(tcg_op2
);
11547 for (pass
= 0; pass
< elements
; pass
++) {
11548 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11549 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11550 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11552 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11553 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11555 switch (fpopcode
) {
11556 case 0x0: /* FMAXNM */
11557 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11559 case 0x1: /* FMLA */
11560 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11561 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11564 case 0x2: /* FADD */
11565 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11567 case 0x3: /* FMULX */
11568 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11570 case 0x4: /* FCMEQ */
11571 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11573 case 0x6: /* FMAX */
11574 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11576 case 0x7: /* FRECPS */
11577 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11579 case 0x8: /* FMINNM */
11580 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11582 case 0x9: /* FMLS */
11583 /* As usual for ARM, separate negation for fused multiply-add */
11584 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11585 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11586 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11589 case 0xa: /* FSUB */
11590 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11592 case 0xe: /* FMIN */
11593 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11595 case 0xf: /* FRSQRTS */
11596 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11598 case 0x13: /* FMUL */
11599 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11601 case 0x14: /* FCMGE */
11602 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11604 case 0x15: /* FACGE */
11605 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11607 case 0x17: /* FDIV */
11608 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11610 case 0x1a: /* FABD */
11611 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11612 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11614 case 0x1c: /* FCMGT */
11615 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11617 case 0x1d: /* FACGT */
11618 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11621 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11622 __func__
, insn
, fpopcode
, s
->pc_curr
);
11623 g_assert_not_reached();
11626 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11627 tcg_temp_free_i32(tcg_res
);
11628 tcg_temp_free_i32(tcg_op1
);
11629 tcg_temp_free_i32(tcg_op2
);
11633 tcg_temp_free_ptr(fpst
);
11635 clear_vec_high(s
, is_q
, rd
);
11638 /* AdvSIMD three same extra
11639 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11640 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11641 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11642 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11644 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11646 int rd
= extract32(insn
, 0, 5);
11647 int rn
= extract32(insn
, 5, 5);
11648 int opcode
= extract32(insn
, 11, 4);
11649 int rm
= extract32(insn
, 16, 5);
11650 int size
= extract32(insn
, 22, 2);
11651 bool u
= extract32(insn
, 29, 1);
11652 bool is_q
= extract32(insn
, 30, 1);
11656 switch (u
* 16 + opcode
) {
11657 case 0x10: /* SQRDMLAH (vector) */
11658 case 0x11: /* SQRDMLSH (vector) */
11659 if (size
!= 1 && size
!= 2) {
11660 unallocated_encoding(s
);
11663 feature
= dc_isar_feature(aa64_rdm
, s
);
11665 case 0x02: /* SDOT (vector) */
11666 case 0x12: /* UDOT (vector) */
11667 if (size
!= MO_32
) {
11668 unallocated_encoding(s
);
11671 feature
= dc_isar_feature(aa64_dp
, s
);
11673 case 0x18: /* FCMLA, #0 */
11674 case 0x19: /* FCMLA, #90 */
11675 case 0x1a: /* FCMLA, #180 */
11676 case 0x1b: /* FCMLA, #270 */
11677 case 0x1c: /* FCADD, #90 */
11678 case 0x1e: /* FCADD, #270 */
11680 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11681 || (size
== 3 && !is_q
)) {
11682 unallocated_encoding(s
);
11685 feature
= dc_isar_feature(aa64_fcma
, s
);
11688 unallocated_encoding(s
);
11692 unallocated_encoding(s
);
11695 if (!fp_access_check(s
)) {
11700 case 0x0: /* SQRDMLAH (vector) */
11701 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
11704 case 0x1: /* SQRDMLSH (vector) */
11705 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
11708 case 0x2: /* SDOT / UDOT */
11709 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11710 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11713 case 0x8: /* FCMLA, #0 */
11714 case 0x9: /* FCMLA, #90 */
11715 case 0xa: /* FCMLA, #180 */
11716 case 0xb: /* FCMLA, #270 */
11717 rot
= extract32(opcode
, 0, 2);
11720 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11721 gen_helper_gvec_fcmlah
);
11724 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11725 gen_helper_gvec_fcmlas
);
11728 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11729 gen_helper_gvec_fcmlad
);
11732 g_assert_not_reached();
11736 case 0xc: /* FCADD, #90 */
11737 case 0xe: /* FCADD, #270 */
11738 rot
= extract32(opcode
, 1, 1);
11741 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11742 gen_helper_gvec_fcaddh
);
11745 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11746 gen_helper_gvec_fcadds
);
11749 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11750 gen_helper_gvec_fcaddd
);
11753 g_assert_not_reached();
11758 g_assert_not_reached();
11762 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11763 int size
, int rn
, int rd
)
11765 /* Handle 2-reg-misc ops which are widening (so each size element
11766 * in the source becomes a 2*size element in the destination.
11767 * The only instruction like this is FCVTL.
11772 /* 32 -> 64 bit fp conversion */
11773 TCGv_i64 tcg_res
[2];
11774 int srcelt
= is_q
? 2 : 0;
11776 for (pass
= 0; pass
< 2; pass
++) {
11777 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11778 tcg_res
[pass
] = tcg_temp_new_i64();
11780 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11781 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11782 tcg_temp_free_i32(tcg_op
);
11784 for (pass
= 0; pass
< 2; pass
++) {
11785 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11786 tcg_temp_free_i64(tcg_res
[pass
]);
11789 /* 16 -> 32 bit fp conversion */
11790 int srcelt
= is_q
? 4 : 0;
11791 TCGv_i32 tcg_res
[4];
11792 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11793 TCGv_i32 ahp
= get_ahp_flag();
11795 for (pass
= 0; pass
< 4; pass
++) {
11796 tcg_res
[pass
] = tcg_temp_new_i32();
11798 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11799 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11802 for (pass
= 0; pass
< 4; pass
++) {
11803 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11804 tcg_temp_free_i32(tcg_res
[pass
]);
11807 tcg_temp_free_ptr(fpst
);
11808 tcg_temp_free_i32(ahp
);
11812 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11813 bool is_q
, int size
, int rn
, int rd
)
11815 int op
= (opcode
<< 1) | u
;
11816 int opsz
= op
+ size
;
11817 int grp_size
= 3 - opsz
;
11818 int dsize
= is_q
? 128 : 64;
11822 unallocated_encoding(s
);
11826 if (!fp_access_check(s
)) {
11831 /* Special case bytes, use bswap op on each group of elements */
11832 int groups
= dsize
/ (8 << grp_size
);
11834 for (i
= 0; i
< groups
; i
++) {
11835 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11837 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11838 switch (grp_size
) {
11840 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11843 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11846 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11849 g_assert_not_reached();
11851 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11852 tcg_temp_free_i64(tcg_tmp
);
11854 clear_vec_high(s
, is_q
, rd
);
11856 int revmask
= (1 << grp_size
) - 1;
11857 int esize
= 8 << size
;
11858 int elements
= dsize
/ esize
;
11859 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11860 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11861 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11863 for (i
= 0; i
< elements
; i
++) {
11864 int e_rev
= (i
& 0xf) ^ revmask
;
11865 int off
= e_rev
* esize
;
11866 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11868 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11869 tcg_rn
, off
- 64, esize
);
11871 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11874 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11875 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11877 tcg_temp_free_i64(tcg_rd_hi
);
11878 tcg_temp_free_i64(tcg_rd
);
11879 tcg_temp_free_i64(tcg_rn
);
11883 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11884 bool is_q
, int size
, int rn
, int rd
)
11886 /* Implement the pairwise operations from 2-misc:
11887 * SADDLP, UADDLP, SADALP, UADALP.
11888 * These all add pairs of elements in the input to produce a
11889 * double-width result element in the output (possibly accumulating).
11891 bool accum
= (opcode
== 0x6);
11892 int maxpass
= is_q
? 2 : 1;
11894 TCGv_i64 tcg_res
[2];
11897 /* 32 + 32 -> 64 op */
11898 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11900 for (pass
= 0; pass
< maxpass
; pass
++) {
11901 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11902 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11904 tcg_res
[pass
] = tcg_temp_new_i64();
11906 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11907 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11908 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11910 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11911 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11914 tcg_temp_free_i64(tcg_op1
);
11915 tcg_temp_free_i64(tcg_op2
);
11918 for (pass
= 0; pass
< maxpass
; pass
++) {
11919 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11920 NeonGenOneOpFn
*genfn
;
11921 static NeonGenOneOpFn
* const fns
[2][2] = {
11922 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11923 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11926 genfn
= fns
[size
][u
];
11928 tcg_res
[pass
] = tcg_temp_new_i64();
11930 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11931 genfn(tcg_res
[pass
], tcg_op
);
11934 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11936 gen_helper_neon_addl_u16(tcg_res
[pass
],
11937 tcg_res
[pass
], tcg_op
);
11939 gen_helper_neon_addl_u32(tcg_res
[pass
],
11940 tcg_res
[pass
], tcg_op
);
11943 tcg_temp_free_i64(tcg_op
);
11947 tcg_res
[1] = tcg_const_i64(0);
11949 for (pass
= 0; pass
< 2; pass
++) {
11950 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11951 tcg_temp_free_i64(tcg_res
[pass
]);
11955 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11957 /* Implement SHLL and SHLL2 */
11959 int part
= is_q
? 2 : 0;
11960 TCGv_i64 tcg_res
[2];
11962 for (pass
= 0; pass
< 2; pass
++) {
11963 static NeonGenWidenFn
* const widenfns
[3] = {
11964 gen_helper_neon_widen_u8
,
11965 gen_helper_neon_widen_u16
,
11966 tcg_gen_extu_i32_i64
,
11968 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11969 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11971 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11972 tcg_res
[pass
] = tcg_temp_new_i64();
11973 widenfn(tcg_res
[pass
], tcg_op
);
11974 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11976 tcg_temp_free_i32(tcg_op
);
11979 for (pass
= 0; pass
< 2; pass
++) {
11980 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11981 tcg_temp_free_i64(tcg_res
[pass
]);
11985 /* AdvSIMD two reg misc
11986 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11987 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11988 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11989 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11991 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11993 int size
= extract32(insn
, 22, 2);
11994 int opcode
= extract32(insn
, 12, 5);
11995 bool u
= extract32(insn
, 29, 1);
11996 bool is_q
= extract32(insn
, 30, 1);
11997 int rn
= extract32(insn
, 5, 5);
11998 int rd
= extract32(insn
, 0, 5);
11999 bool need_fpstatus
= false;
12000 bool need_rmode
= false;
12002 TCGv_i32 tcg_rmode
;
12003 TCGv_ptr tcg_fpstatus
;
12006 case 0x0: /* REV64, REV32 */
12007 case 0x1: /* REV16 */
12008 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12010 case 0x5: /* CNT, NOT, RBIT */
12011 if (u
&& size
== 0) {
12014 } else if (u
&& size
== 1) {
12017 } else if (!u
&& size
== 0) {
12021 unallocated_encoding(s
);
12023 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12024 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12026 unallocated_encoding(s
);
12029 if (!fp_access_check(s
)) {
12033 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12035 case 0x4: /* CLS, CLZ */
12037 unallocated_encoding(s
);
12041 case 0x2: /* SADDLP, UADDLP */
12042 case 0x6: /* SADALP, UADALP */
12044 unallocated_encoding(s
);
12047 if (!fp_access_check(s
)) {
12050 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12052 case 0x13: /* SHLL, SHLL2 */
12053 if (u
== 0 || size
== 3) {
12054 unallocated_encoding(s
);
12057 if (!fp_access_check(s
)) {
12060 handle_shll(s
, is_q
, size
, rn
, rd
);
12062 case 0xa: /* CMLT */
12064 unallocated_encoding(s
);
12068 case 0x8: /* CMGT, CMGE */
12069 case 0x9: /* CMEQ, CMLE */
12070 case 0xb: /* ABS, NEG */
12071 if (size
== 3 && !is_q
) {
12072 unallocated_encoding(s
);
12076 case 0x3: /* SUQADD, USQADD */
12077 if (size
== 3 && !is_q
) {
12078 unallocated_encoding(s
);
12081 if (!fp_access_check(s
)) {
12084 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12086 case 0x7: /* SQABS, SQNEG */
12087 if (size
== 3 && !is_q
) {
12088 unallocated_encoding(s
);
12093 case 0x16 ... 0x1f:
12095 /* Floating point: U, size[1] and opcode indicate operation;
12096 * size[0] indicates single or double precision.
12098 int is_double
= extract32(size
, 0, 1);
12099 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12100 size
= is_double
? 3 : 2;
12102 case 0x2f: /* FABS */
12103 case 0x6f: /* FNEG */
12104 if (size
== 3 && !is_q
) {
12105 unallocated_encoding(s
);
12109 case 0x1d: /* SCVTF */
12110 case 0x5d: /* UCVTF */
12112 bool is_signed
= (opcode
== 0x1d) ? true : false;
12113 int elements
= is_double
? 2 : is_q
? 4 : 2;
12114 if (is_double
&& !is_q
) {
12115 unallocated_encoding(s
);
12118 if (!fp_access_check(s
)) {
12121 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12124 case 0x2c: /* FCMGT (zero) */
12125 case 0x2d: /* FCMEQ (zero) */
12126 case 0x2e: /* FCMLT (zero) */
12127 case 0x6c: /* FCMGE (zero) */
12128 case 0x6d: /* FCMLE (zero) */
12129 if (size
== 3 && !is_q
) {
12130 unallocated_encoding(s
);
12133 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12135 case 0x7f: /* FSQRT */
12136 if (size
== 3 && !is_q
) {
12137 unallocated_encoding(s
);
12141 case 0x1a: /* FCVTNS */
12142 case 0x1b: /* FCVTMS */
12143 case 0x3a: /* FCVTPS */
12144 case 0x3b: /* FCVTZS */
12145 case 0x5a: /* FCVTNU */
12146 case 0x5b: /* FCVTMU */
12147 case 0x7a: /* FCVTPU */
12148 case 0x7b: /* FCVTZU */
12149 need_fpstatus
= true;
12151 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12152 if (size
== 3 && !is_q
) {
12153 unallocated_encoding(s
);
12157 case 0x5c: /* FCVTAU */
12158 case 0x1c: /* FCVTAS */
12159 need_fpstatus
= true;
12161 rmode
= FPROUNDING_TIEAWAY
;
12162 if (size
== 3 && !is_q
) {
12163 unallocated_encoding(s
);
12167 case 0x3c: /* URECPE */
12169 unallocated_encoding(s
);
12173 case 0x3d: /* FRECPE */
12174 case 0x7d: /* FRSQRTE */
12175 if (size
== 3 && !is_q
) {
12176 unallocated_encoding(s
);
12179 if (!fp_access_check(s
)) {
12182 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12184 case 0x56: /* FCVTXN, FCVTXN2 */
12186 unallocated_encoding(s
);
12190 case 0x16: /* FCVTN, FCVTN2 */
12191 /* handle_2misc_narrow does a 2*size -> size operation, but these
12192 * instructions encode the source size rather than dest size.
12194 if (!fp_access_check(s
)) {
12197 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12199 case 0x17: /* FCVTL, FCVTL2 */
12200 if (!fp_access_check(s
)) {
12203 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12205 case 0x18: /* FRINTN */
12206 case 0x19: /* FRINTM */
12207 case 0x38: /* FRINTP */
12208 case 0x39: /* FRINTZ */
12210 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12212 case 0x59: /* FRINTX */
12213 case 0x79: /* FRINTI */
12214 need_fpstatus
= true;
12215 if (size
== 3 && !is_q
) {
12216 unallocated_encoding(s
);
12220 case 0x58: /* FRINTA */
12222 rmode
= FPROUNDING_TIEAWAY
;
12223 need_fpstatus
= true;
12224 if (size
== 3 && !is_q
) {
12225 unallocated_encoding(s
);
12229 case 0x7c: /* URSQRTE */
12231 unallocated_encoding(s
);
12235 case 0x1e: /* FRINT32Z */
12236 case 0x1f: /* FRINT64Z */
12238 rmode
= FPROUNDING_ZERO
;
12240 case 0x5e: /* FRINT32X */
12241 case 0x5f: /* FRINT64X */
12242 need_fpstatus
= true;
12243 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12244 unallocated_encoding(s
);
12249 unallocated_encoding(s
);
12255 unallocated_encoding(s
);
12259 if (!fp_access_check(s
)) {
12263 if (need_fpstatus
|| need_rmode
) {
12264 tcg_fpstatus
= get_fpstatus_ptr(false);
12266 tcg_fpstatus
= NULL
;
12269 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12270 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12277 if (u
&& size
== 0) { /* NOT */
12278 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12282 case 0x8: /* CMGT, CMGE */
12284 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12286 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12289 case 0x9: /* CMEQ, CMLE */
12291 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12293 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12296 case 0xa: /* CMLT */
12297 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12300 if (u
) { /* ABS, NEG */
12301 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12303 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12309 /* All 64-bit element operations can be shared with scalar 2misc */
12312 /* Coverity claims (size == 3 && !is_q) has been eliminated
12313 * from all paths leading to here.
12315 tcg_debug_assert(is_q
);
12316 for (pass
= 0; pass
< 2; pass
++) {
12317 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12318 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12320 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12322 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12323 tcg_rmode
, tcg_fpstatus
);
12325 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12327 tcg_temp_free_i64(tcg_res
);
12328 tcg_temp_free_i64(tcg_op
);
12333 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12334 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12335 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12337 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12340 /* Special cases for 32 bit elements */
12342 case 0x4: /* CLS */
12344 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12346 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12349 case 0x7: /* SQABS, SQNEG */
12351 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12353 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12356 case 0x2f: /* FABS */
12357 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12359 case 0x6f: /* FNEG */
12360 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12362 case 0x7f: /* FSQRT */
12363 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12365 case 0x1a: /* FCVTNS */
12366 case 0x1b: /* FCVTMS */
12367 case 0x1c: /* FCVTAS */
12368 case 0x3a: /* FCVTPS */
12369 case 0x3b: /* FCVTZS */
12371 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12372 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12373 tcg_shift
, tcg_fpstatus
);
12374 tcg_temp_free_i32(tcg_shift
);
12377 case 0x5a: /* FCVTNU */
12378 case 0x5b: /* FCVTMU */
12379 case 0x5c: /* FCVTAU */
12380 case 0x7a: /* FCVTPU */
12381 case 0x7b: /* FCVTZU */
12383 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12384 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12385 tcg_shift
, tcg_fpstatus
);
12386 tcg_temp_free_i32(tcg_shift
);
12389 case 0x18: /* FRINTN */
12390 case 0x19: /* FRINTM */
12391 case 0x38: /* FRINTP */
12392 case 0x39: /* FRINTZ */
12393 case 0x58: /* FRINTA */
12394 case 0x79: /* FRINTI */
12395 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12397 case 0x59: /* FRINTX */
12398 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12400 case 0x7c: /* URSQRTE */
12401 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12403 case 0x1e: /* FRINT32Z */
12404 case 0x5e: /* FRINT32X */
12405 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12407 case 0x1f: /* FRINT64Z */
12408 case 0x5f: /* FRINT64X */
12409 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12412 g_assert_not_reached();
12415 /* Use helpers for 8 and 16 bit elements */
12417 case 0x5: /* CNT, RBIT */
12418 /* For these two insns size is part of the opcode specifier
12419 * (handled earlier); they always operate on byte elements.
12422 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12424 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12427 case 0x7: /* SQABS, SQNEG */
12429 NeonGenOneOpEnvFn
*genfn
;
12430 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12431 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12432 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12434 genfn
= fns
[size
][u
];
12435 genfn(tcg_res
, cpu_env
, tcg_op
);
12438 case 0x4: /* CLS, CLZ */
12441 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12443 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12447 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12449 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12454 g_assert_not_reached();
12458 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12460 tcg_temp_free_i32(tcg_res
);
12461 tcg_temp_free_i32(tcg_op
);
12464 clear_vec_high(s
, is_q
, rd
);
12467 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12468 tcg_temp_free_i32(tcg_rmode
);
12470 if (need_fpstatus
) {
12471 tcg_temp_free_ptr(tcg_fpstatus
);
12475 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12477 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12478 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12479 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12480 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12481 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12482 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12484 * This actually covers two groups where scalar access is governed by
12485 * bit 28. A bunch of the instructions (float to integral) only exist
12486 * in the vector form and are un-allocated for the scalar decode. Also
12487 * in the scalar decode Q is always 1.
12489 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12491 int fpop
, opcode
, a
, u
;
12495 bool only_in_vector
= false;
12498 TCGv_i32 tcg_rmode
= NULL
;
12499 TCGv_ptr tcg_fpstatus
= NULL
;
12500 bool need_rmode
= false;
12501 bool need_fpst
= true;
12504 if (!dc_isar_feature(aa64_fp16
, s
)) {
12505 unallocated_encoding(s
);
12509 rd
= extract32(insn
, 0, 5);
12510 rn
= extract32(insn
, 5, 5);
12512 a
= extract32(insn
, 23, 1);
12513 u
= extract32(insn
, 29, 1);
12514 is_scalar
= extract32(insn
, 28, 1);
12515 is_q
= extract32(insn
, 30, 1);
12517 opcode
= extract32(insn
, 12, 5);
12518 fpop
= deposit32(opcode
, 5, 1, a
);
12519 fpop
= deposit32(fpop
, 6, 1, u
);
12521 rd
= extract32(insn
, 0, 5);
12522 rn
= extract32(insn
, 5, 5);
12525 case 0x1d: /* SCVTF */
12526 case 0x5d: /* UCVTF */
12533 elements
= (is_q
? 8 : 4);
12536 if (!fp_access_check(s
)) {
12539 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12543 case 0x2c: /* FCMGT (zero) */
12544 case 0x2d: /* FCMEQ (zero) */
12545 case 0x2e: /* FCMLT (zero) */
12546 case 0x6c: /* FCMGE (zero) */
12547 case 0x6d: /* FCMLE (zero) */
12548 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12550 case 0x3d: /* FRECPE */
12551 case 0x3f: /* FRECPX */
12553 case 0x18: /* FRINTN */
12555 only_in_vector
= true;
12556 rmode
= FPROUNDING_TIEEVEN
;
12558 case 0x19: /* FRINTM */
12560 only_in_vector
= true;
12561 rmode
= FPROUNDING_NEGINF
;
12563 case 0x38: /* FRINTP */
12565 only_in_vector
= true;
12566 rmode
= FPROUNDING_POSINF
;
12568 case 0x39: /* FRINTZ */
12570 only_in_vector
= true;
12571 rmode
= FPROUNDING_ZERO
;
12573 case 0x58: /* FRINTA */
12575 only_in_vector
= true;
12576 rmode
= FPROUNDING_TIEAWAY
;
12578 case 0x59: /* FRINTX */
12579 case 0x79: /* FRINTI */
12580 only_in_vector
= true;
12581 /* current rounding mode */
12583 case 0x1a: /* FCVTNS */
12585 rmode
= FPROUNDING_TIEEVEN
;
12587 case 0x1b: /* FCVTMS */
12589 rmode
= FPROUNDING_NEGINF
;
12591 case 0x1c: /* FCVTAS */
12593 rmode
= FPROUNDING_TIEAWAY
;
12595 case 0x3a: /* FCVTPS */
12597 rmode
= FPROUNDING_POSINF
;
12599 case 0x3b: /* FCVTZS */
12601 rmode
= FPROUNDING_ZERO
;
12603 case 0x5a: /* FCVTNU */
12605 rmode
= FPROUNDING_TIEEVEN
;
12607 case 0x5b: /* FCVTMU */
12609 rmode
= FPROUNDING_NEGINF
;
12611 case 0x5c: /* FCVTAU */
12613 rmode
= FPROUNDING_TIEAWAY
;
12615 case 0x7a: /* FCVTPU */
12617 rmode
= FPROUNDING_POSINF
;
12619 case 0x7b: /* FCVTZU */
12621 rmode
= FPROUNDING_ZERO
;
12623 case 0x2f: /* FABS */
12624 case 0x6f: /* FNEG */
12627 case 0x7d: /* FRSQRTE */
12628 case 0x7f: /* FSQRT (vector) */
12631 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12632 g_assert_not_reached();
12636 /* Check additional constraints for the scalar encoding */
12639 unallocated_encoding(s
);
12642 /* FRINTxx is only in the vector form */
12643 if (only_in_vector
) {
12644 unallocated_encoding(s
);
12649 if (!fp_access_check(s
)) {
12653 if (need_rmode
|| need_fpst
) {
12654 tcg_fpstatus
= get_fpstatus_ptr(true);
12658 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12659 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12663 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12664 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12667 case 0x1a: /* FCVTNS */
12668 case 0x1b: /* FCVTMS */
12669 case 0x1c: /* FCVTAS */
12670 case 0x3a: /* FCVTPS */
12671 case 0x3b: /* FCVTZS */
12672 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12674 case 0x3d: /* FRECPE */
12675 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12677 case 0x3f: /* FRECPX */
12678 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12680 case 0x5a: /* FCVTNU */
12681 case 0x5b: /* FCVTMU */
12682 case 0x5c: /* FCVTAU */
12683 case 0x7a: /* FCVTPU */
12684 case 0x7b: /* FCVTZU */
12685 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12687 case 0x6f: /* FNEG */
12688 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12690 case 0x7d: /* FRSQRTE */
12691 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12694 g_assert_not_reached();
12697 /* limit any sign extension going on */
12698 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12699 write_fp_sreg(s
, rd
, tcg_res
);
12701 tcg_temp_free_i32(tcg_res
);
12702 tcg_temp_free_i32(tcg_op
);
12704 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12705 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12706 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12708 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12711 case 0x1a: /* FCVTNS */
12712 case 0x1b: /* FCVTMS */
12713 case 0x1c: /* FCVTAS */
12714 case 0x3a: /* FCVTPS */
12715 case 0x3b: /* FCVTZS */
12716 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12718 case 0x3d: /* FRECPE */
12719 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12721 case 0x5a: /* FCVTNU */
12722 case 0x5b: /* FCVTMU */
12723 case 0x5c: /* FCVTAU */
12724 case 0x7a: /* FCVTPU */
12725 case 0x7b: /* FCVTZU */
12726 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12728 case 0x18: /* FRINTN */
12729 case 0x19: /* FRINTM */
12730 case 0x38: /* FRINTP */
12731 case 0x39: /* FRINTZ */
12732 case 0x58: /* FRINTA */
12733 case 0x79: /* FRINTI */
12734 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12736 case 0x59: /* FRINTX */
12737 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12739 case 0x2f: /* FABS */
12740 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12742 case 0x6f: /* FNEG */
12743 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12745 case 0x7d: /* FRSQRTE */
12746 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12748 case 0x7f: /* FSQRT */
12749 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12752 g_assert_not_reached();
12755 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12757 tcg_temp_free_i32(tcg_res
);
12758 tcg_temp_free_i32(tcg_op
);
12761 clear_vec_high(s
, is_q
, rd
);
12765 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12766 tcg_temp_free_i32(tcg_rmode
);
12769 if (tcg_fpstatus
) {
12770 tcg_temp_free_ptr(tcg_fpstatus
);
12774 /* AdvSIMD scalar x indexed element
12775 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12776 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12777 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12778 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12779 * AdvSIMD vector x indexed element
12780 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12781 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12782 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12783 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12785 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12787 /* This encoding has two kinds of instruction:
12788 * normal, where we perform elt x idxelt => elt for each
12789 * element in the vector
12790 * long, where we perform elt x idxelt and generate a result of
12791 * double the width of the input element
12792 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12794 bool is_scalar
= extract32(insn
, 28, 1);
12795 bool is_q
= extract32(insn
, 30, 1);
12796 bool u
= extract32(insn
, 29, 1);
12797 int size
= extract32(insn
, 22, 2);
12798 int l
= extract32(insn
, 21, 1);
12799 int m
= extract32(insn
, 20, 1);
12800 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12801 int rm
= extract32(insn
, 16, 4);
12802 int opcode
= extract32(insn
, 12, 4);
12803 int h
= extract32(insn
, 11, 1);
12804 int rn
= extract32(insn
, 5, 5);
12805 int rd
= extract32(insn
, 0, 5);
12806 bool is_long
= false;
12808 bool is_fp16
= false;
12812 switch (16 * u
+ opcode
) {
12813 case 0x08: /* MUL */
12814 case 0x10: /* MLA */
12815 case 0x14: /* MLS */
12817 unallocated_encoding(s
);
12821 case 0x02: /* SMLAL, SMLAL2 */
12822 case 0x12: /* UMLAL, UMLAL2 */
12823 case 0x06: /* SMLSL, SMLSL2 */
12824 case 0x16: /* UMLSL, UMLSL2 */
12825 case 0x0a: /* SMULL, SMULL2 */
12826 case 0x1a: /* UMULL, UMULL2 */
12828 unallocated_encoding(s
);
12833 case 0x03: /* SQDMLAL, SQDMLAL2 */
12834 case 0x07: /* SQDMLSL, SQDMLSL2 */
12835 case 0x0b: /* SQDMULL, SQDMULL2 */
12838 case 0x0c: /* SQDMULH */
12839 case 0x0d: /* SQRDMULH */
12841 case 0x01: /* FMLA */
12842 case 0x05: /* FMLS */
12843 case 0x09: /* FMUL */
12844 case 0x19: /* FMULX */
12847 case 0x1d: /* SQRDMLAH */
12848 case 0x1f: /* SQRDMLSH */
12849 if (!dc_isar_feature(aa64_rdm
, s
)) {
12850 unallocated_encoding(s
);
12854 case 0x0e: /* SDOT */
12855 case 0x1e: /* UDOT */
12856 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12857 unallocated_encoding(s
);
12861 case 0x11: /* FCMLA #0 */
12862 case 0x13: /* FCMLA #90 */
12863 case 0x15: /* FCMLA #180 */
12864 case 0x17: /* FCMLA #270 */
12865 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12866 unallocated_encoding(s
);
12871 case 0x00: /* FMLAL */
12872 case 0x04: /* FMLSL */
12873 case 0x18: /* FMLAL2 */
12874 case 0x1c: /* FMLSL2 */
12875 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12876 unallocated_encoding(s
);
12880 /* is_fp, but we pass cpu_env not fp_status. */
12883 unallocated_encoding(s
);
12888 case 1: /* normal fp */
12889 /* convert insn encoded size to MemOp size */
12891 case 0: /* half-precision */
12895 case MO_32
: /* single precision */
12896 case MO_64
: /* double precision */
12899 unallocated_encoding(s
);
12904 case 2: /* complex fp */
12905 /* Each indexable element is a complex pair. */
12910 unallocated_encoding(s
);
12918 unallocated_encoding(s
);
12923 default: /* integer */
12927 unallocated_encoding(s
);
12932 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12933 unallocated_encoding(s
);
12937 /* Given MemOp size, adjust register and indexing. */
12940 index
= h
<< 2 | l
<< 1 | m
;
12943 index
= h
<< 1 | l
;
12948 unallocated_encoding(s
);
12955 g_assert_not_reached();
12958 if (!fp_access_check(s
)) {
12963 fpst
= get_fpstatus_ptr(is_fp16
);
12968 switch (16 * u
+ opcode
) {
12969 case 0x0e: /* SDOT */
12970 case 0x1e: /* UDOT */
12971 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12972 u
? gen_helper_gvec_udot_idx_b
12973 : gen_helper_gvec_sdot_idx_b
);
12975 case 0x11: /* FCMLA #0 */
12976 case 0x13: /* FCMLA #90 */
12977 case 0x15: /* FCMLA #180 */
12978 case 0x17: /* FCMLA #270 */
12980 int rot
= extract32(insn
, 13, 2);
12981 int data
= (index
<< 2) | rot
;
12982 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12983 vec_full_reg_offset(s
, rn
),
12984 vec_full_reg_offset(s
, rm
), fpst
,
12985 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12987 ? gen_helper_gvec_fcmlas_idx
12988 : gen_helper_gvec_fcmlah_idx
);
12989 tcg_temp_free_ptr(fpst
);
12993 case 0x00: /* FMLAL */
12994 case 0x04: /* FMLSL */
12995 case 0x18: /* FMLAL2 */
12996 case 0x1c: /* FMLSL2 */
12998 int is_s
= extract32(opcode
, 2, 1);
13000 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13001 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13002 vec_full_reg_offset(s
, rn
),
13003 vec_full_reg_offset(s
, rm
), cpu_env
,
13004 is_q
? 16 : 8, vec_full_reg_size(s
),
13005 data
, gen_helper_gvec_fmlal_idx_a64
);
13011 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13014 assert(is_fp
&& is_q
&& !is_long
);
13016 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13018 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13019 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13020 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13022 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13024 switch (16 * u
+ opcode
) {
13025 case 0x05: /* FMLS */
13026 /* As usual for ARM, separate negation for fused multiply-add */
13027 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13029 case 0x01: /* FMLA */
13030 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13031 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13033 case 0x09: /* FMUL */
13034 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13036 case 0x19: /* FMULX */
13037 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13040 g_assert_not_reached();
13043 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13044 tcg_temp_free_i64(tcg_op
);
13045 tcg_temp_free_i64(tcg_res
);
13048 tcg_temp_free_i64(tcg_idx
);
13049 clear_vec_high(s
, !is_scalar
, rd
);
13050 } else if (!is_long
) {
13051 /* 32 bit floating point, or 16 or 32 bit integer.
13052 * For the 16 bit scalar case we use the usual Neon helpers and
13053 * rely on the fact that 0 op 0 == 0 with no side effects.
13055 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13056 int pass
, maxpasses
;
13061 maxpasses
= is_q
? 4 : 2;
13064 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13066 if (size
== 1 && !is_scalar
) {
13067 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13068 * the index into both halves of the 32 bit tcg_idx and then use
13069 * the usual Neon helpers.
13071 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13074 for (pass
= 0; pass
< maxpasses
; pass
++) {
13075 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13076 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13078 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13080 switch (16 * u
+ opcode
) {
13081 case 0x08: /* MUL */
13082 case 0x10: /* MLA */
13083 case 0x14: /* MLS */
13085 static NeonGenTwoOpFn
* const fns
[2][2] = {
13086 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13087 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13089 NeonGenTwoOpFn
*genfn
;
13090 bool is_sub
= opcode
== 0x4;
13093 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13095 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13097 if (opcode
== 0x8) {
13100 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13101 genfn
= fns
[size
- 1][is_sub
];
13102 genfn(tcg_res
, tcg_op
, tcg_res
);
13105 case 0x05: /* FMLS */
13106 case 0x01: /* FMLA */
13107 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13108 is_scalar
? size
: MO_32
);
13111 if (opcode
== 0x5) {
13112 /* As usual for ARM, separate negation for fused
13114 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13117 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13120 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13125 if (opcode
== 0x5) {
13126 /* As usual for ARM, separate negation for
13127 * fused multiply-add */
13128 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13130 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13134 g_assert_not_reached();
13137 case 0x09: /* FMUL */
13141 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13144 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13149 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13152 g_assert_not_reached();
13155 case 0x19: /* FMULX */
13159 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13162 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13167 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13170 g_assert_not_reached();
13173 case 0x0c: /* SQDMULH */
13175 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13178 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13182 case 0x0d: /* SQRDMULH */
13184 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13187 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13191 case 0x1d: /* SQRDMLAH */
13192 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13193 is_scalar
? size
: MO_32
);
13195 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13196 tcg_op
, tcg_idx
, tcg_res
);
13198 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13199 tcg_op
, tcg_idx
, tcg_res
);
13202 case 0x1f: /* SQRDMLSH */
13203 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13204 is_scalar
? size
: MO_32
);
13206 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13207 tcg_op
, tcg_idx
, tcg_res
);
13209 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13210 tcg_op
, tcg_idx
, tcg_res
);
13214 g_assert_not_reached();
13218 write_fp_sreg(s
, rd
, tcg_res
);
13220 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13223 tcg_temp_free_i32(tcg_op
);
13224 tcg_temp_free_i32(tcg_res
);
13227 tcg_temp_free_i32(tcg_idx
);
13228 clear_vec_high(s
, is_q
, rd
);
13230 /* long ops: 16x16->32 or 32x32->64 */
13231 TCGv_i64 tcg_res
[2];
13233 bool satop
= extract32(opcode
, 0, 1);
13234 MemOp memop
= MO_32
;
13241 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13243 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13245 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13246 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13247 TCGv_i64 tcg_passres
;
13253 passelt
= pass
+ (is_q
* 2);
13256 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13258 tcg_res
[pass
] = tcg_temp_new_i64();
13260 if (opcode
== 0xa || opcode
== 0xb) {
13261 /* Non-accumulating ops */
13262 tcg_passres
= tcg_res
[pass
];
13264 tcg_passres
= tcg_temp_new_i64();
13267 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13268 tcg_temp_free_i64(tcg_op
);
13271 /* saturating, doubling */
13272 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13273 tcg_passres
, tcg_passres
);
13276 if (opcode
== 0xa || opcode
== 0xb) {
13280 /* Accumulating op: handle accumulate step */
13281 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13284 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13285 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13287 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13288 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13290 case 0x7: /* SQDMLSL, SQDMLSL2 */
13291 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13293 case 0x3: /* SQDMLAL, SQDMLAL2 */
13294 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13299 g_assert_not_reached();
13301 tcg_temp_free_i64(tcg_passres
);
13303 tcg_temp_free_i64(tcg_idx
);
13305 clear_vec_high(s
, !is_scalar
, rd
);
13307 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13310 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13313 /* The simplest way to handle the 16x16 indexed ops is to
13314 * duplicate the index into both halves of the 32 bit tcg_idx
13315 * and then use the usual Neon helpers.
13317 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13320 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13321 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13322 TCGv_i64 tcg_passres
;
13325 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13327 read_vec_element_i32(s
, tcg_op
, rn
,
13328 pass
+ (is_q
* 2), MO_32
);
13331 tcg_res
[pass
] = tcg_temp_new_i64();
13333 if (opcode
== 0xa || opcode
== 0xb) {
13334 /* Non-accumulating ops */
13335 tcg_passres
= tcg_res
[pass
];
13337 tcg_passres
= tcg_temp_new_i64();
13340 if (memop
& MO_SIGN
) {
13341 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13343 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13346 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13347 tcg_passres
, tcg_passres
);
13349 tcg_temp_free_i32(tcg_op
);
13351 if (opcode
== 0xa || opcode
== 0xb) {
13355 /* Accumulating op: handle accumulate step */
13356 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13359 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13360 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13363 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13364 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13367 case 0x7: /* SQDMLSL, SQDMLSL2 */
13368 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13370 case 0x3: /* SQDMLAL, SQDMLAL2 */
13371 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13376 g_assert_not_reached();
13378 tcg_temp_free_i64(tcg_passres
);
13380 tcg_temp_free_i32(tcg_idx
);
13383 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13388 tcg_res
[1] = tcg_const_i64(0);
13391 for (pass
= 0; pass
< 2; pass
++) {
13392 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13393 tcg_temp_free_i64(tcg_res
[pass
]);
13398 tcg_temp_free_ptr(fpst
);
13403 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13404 * +-----------------+------+-----------+--------+-----+------+------+
13405 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13406 * +-----------------+------+-----------+--------+-----+------+------+
13408 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13410 int size
= extract32(insn
, 22, 2);
13411 int opcode
= extract32(insn
, 12, 5);
13412 int rn
= extract32(insn
, 5, 5);
13413 int rd
= extract32(insn
, 0, 5);
13415 gen_helper_gvec_2
*genfn2
= NULL
;
13416 gen_helper_gvec_3
*genfn3
= NULL
;
13418 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13419 unallocated_encoding(s
);
13424 case 0x4: /* AESE */
13426 genfn3
= gen_helper_crypto_aese
;
13428 case 0x6: /* AESMC */
13430 genfn2
= gen_helper_crypto_aesmc
;
13432 case 0x5: /* AESD */
13434 genfn3
= gen_helper_crypto_aese
;
13436 case 0x7: /* AESIMC */
13438 genfn2
= gen_helper_crypto_aesmc
;
13441 unallocated_encoding(s
);
13445 if (!fp_access_check(s
)) {
13449 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13451 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13455 /* Crypto three-reg SHA
13456 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13457 * +-----------------+------+---+------+---+--------+-----+------+------+
13458 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13459 * +-----------------+------+---+------+---+--------+-----+------+------+
13461 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13463 int size
= extract32(insn
, 22, 2);
13464 int opcode
= extract32(insn
, 12, 3);
13465 int rm
= extract32(insn
, 16, 5);
13466 int rn
= extract32(insn
, 5, 5);
13467 int rd
= extract32(insn
, 0, 5);
13468 CryptoThreeOpFn
*genfn
;
13469 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13473 unallocated_encoding(s
);
13478 case 0: /* SHA1C */
13479 case 1: /* SHA1P */
13480 case 2: /* SHA1M */
13481 case 3: /* SHA1SU0 */
13483 feature
= dc_isar_feature(aa64_sha1
, s
);
13485 case 4: /* SHA256H */
13486 genfn
= gen_helper_crypto_sha256h
;
13487 feature
= dc_isar_feature(aa64_sha256
, s
);
13489 case 5: /* SHA256H2 */
13490 genfn
= gen_helper_crypto_sha256h2
;
13491 feature
= dc_isar_feature(aa64_sha256
, s
);
13493 case 6: /* SHA256SU1 */
13494 genfn
= gen_helper_crypto_sha256su1
;
13495 feature
= dc_isar_feature(aa64_sha256
, s
);
13498 unallocated_encoding(s
);
13503 unallocated_encoding(s
);
13507 if (!fp_access_check(s
)) {
13511 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13512 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13513 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13516 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13518 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13520 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13521 tcg_rm_ptr
, tcg_opcode
);
13522 tcg_temp_free_i32(tcg_opcode
);
13525 tcg_temp_free_ptr(tcg_rd_ptr
);
13526 tcg_temp_free_ptr(tcg_rn_ptr
);
13527 tcg_temp_free_ptr(tcg_rm_ptr
);
13530 /* Crypto two-reg SHA
13531 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13532 * +-----------------+------+-----------+--------+-----+------+------+
13533 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13534 * +-----------------+------+-----------+--------+-----+------+------+
13536 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13538 int size
= extract32(insn
, 22, 2);
13539 int opcode
= extract32(insn
, 12, 5);
13540 int rn
= extract32(insn
, 5, 5);
13541 int rd
= extract32(insn
, 0, 5);
13542 CryptoTwoOpFn
*genfn
;
13544 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13547 unallocated_encoding(s
);
13552 case 0: /* SHA1H */
13553 feature
= dc_isar_feature(aa64_sha1
, s
);
13554 genfn
= gen_helper_crypto_sha1h
;
13556 case 1: /* SHA1SU1 */
13557 feature
= dc_isar_feature(aa64_sha1
, s
);
13558 genfn
= gen_helper_crypto_sha1su1
;
13560 case 2: /* SHA256SU0 */
13561 feature
= dc_isar_feature(aa64_sha256
, s
);
13562 genfn
= gen_helper_crypto_sha256su0
;
13565 unallocated_encoding(s
);
13570 unallocated_encoding(s
);
13574 if (!fp_access_check(s
)) {
13578 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13579 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13581 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13583 tcg_temp_free_ptr(tcg_rd_ptr
);
13584 tcg_temp_free_ptr(tcg_rn_ptr
);
13587 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
13589 tcg_gen_rotli_i64(d
, m
, 1);
13590 tcg_gen_xor_i64(d
, d
, n
);
13593 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
13595 tcg_gen_rotli_vec(vece
, d
, m
, 1);
13596 tcg_gen_xor_vec(vece
, d
, d
, n
);
13599 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
13600 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
13602 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
13603 static const GVecGen3 op
= {
13604 .fni8
= gen_rax1_i64
,
13605 .fniv
= gen_rax1_vec
,
13606 .opt_opc
= vecop_list
,
13607 .fno
= gen_helper_crypto_rax1
,
13610 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
13613 /* Crypto three-reg SHA512
13614 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13615 * +-----------------------+------+---+---+-----+--------+------+------+
13616 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13617 * +-----------------------+------+---+---+-----+--------+------+------+
13619 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13621 int opcode
= extract32(insn
, 10, 2);
13622 int o
= extract32(insn
, 14, 1);
13623 int rm
= extract32(insn
, 16, 5);
13624 int rn
= extract32(insn
, 5, 5);
13625 int rd
= extract32(insn
, 0, 5);
13627 gen_helper_gvec_3
*oolfn
= NULL
;
13628 GVecGen3Fn
*gvecfn
= NULL
;
13632 case 0: /* SHA512H */
13633 feature
= dc_isar_feature(aa64_sha512
, s
);
13634 oolfn
= gen_helper_crypto_sha512h
;
13636 case 1: /* SHA512H2 */
13637 feature
= dc_isar_feature(aa64_sha512
, s
);
13638 oolfn
= gen_helper_crypto_sha512h2
;
13640 case 2: /* SHA512SU1 */
13641 feature
= dc_isar_feature(aa64_sha512
, s
);
13642 oolfn
= gen_helper_crypto_sha512su1
;
13645 feature
= dc_isar_feature(aa64_sha3
, s
);
13646 gvecfn
= gen_gvec_rax1
;
13649 g_assert_not_reached();
13653 case 0: /* SM3PARTW1 */
13654 feature
= dc_isar_feature(aa64_sm3
, s
);
13655 oolfn
= gen_helper_crypto_sm3partw1
;
13657 case 1: /* SM3PARTW2 */
13658 feature
= dc_isar_feature(aa64_sm3
, s
);
13659 oolfn
= gen_helper_crypto_sm3partw2
;
13661 case 2: /* SM4EKEY */
13662 feature
= dc_isar_feature(aa64_sm4
, s
);
13663 oolfn
= gen_helper_crypto_sm4ekey
;
13666 unallocated_encoding(s
);
13672 unallocated_encoding(s
);
13676 if (!fp_access_check(s
)) {
13681 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
13683 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
13687 /* Crypto two-reg SHA512
13688 * 31 12 11 10 9 5 4 0
13689 * +-----------------------------------------+--------+------+------+
13690 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13691 * +-----------------------------------------+--------+------+------+
13693 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13695 int opcode
= extract32(insn
, 10, 2);
13696 int rn
= extract32(insn
, 5, 5);
13697 int rd
= extract32(insn
, 0, 5);
13701 case 0: /* SHA512SU0 */
13702 feature
= dc_isar_feature(aa64_sha512
, s
);
13705 feature
= dc_isar_feature(aa64_sm4
, s
);
13708 unallocated_encoding(s
);
13713 unallocated_encoding(s
);
13717 if (!fp_access_check(s
)) {
13722 case 0: /* SHA512SU0 */
13723 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
13726 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
13729 g_assert_not_reached();
13733 /* Crypto four-register
13734 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13735 * +-------------------+-----+------+---+------+------+------+
13736 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13737 * +-------------------+-----+------+---+------+------+------+
13739 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13741 int op0
= extract32(insn
, 21, 2);
13742 int rm
= extract32(insn
, 16, 5);
13743 int ra
= extract32(insn
, 10, 5);
13744 int rn
= extract32(insn
, 5, 5);
13745 int rd
= extract32(insn
, 0, 5);
13751 feature
= dc_isar_feature(aa64_sha3
, s
);
13753 case 2: /* SM3SS1 */
13754 feature
= dc_isar_feature(aa64_sm3
, s
);
13757 unallocated_encoding(s
);
13762 unallocated_encoding(s
);
13766 if (!fp_access_check(s
)) {
13771 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13774 tcg_op1
= tcg_temp_new_i64();
13775 tcg_op2
= tcg_temp_new_i64();
13776 tcg_op3
= tcg_temp_new_i64();
13777 tcg_res
[0] = tcg_temp_new_i64();
13778 tcg_res
[1] = tcg_temp_new_i64();
13780 for (pass
= 0; pass
< 2; pass
++) {
13781 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13782 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13783 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13787 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13790 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13792 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13794 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13795 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13797 tcg_temp_free_i64(tcg_op1
);
13798 tcg_temp_free_i64(tcg_op2
);
13799 tcg_temp_free_i64(tcg_op3
);
13800 tcg_temp_free_i64(tcg_res
[0]);
13801 tcg_temp_free_i64(tcg_res
[1]);
13803 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13805 tcg_op1
= tcg_temp_new_i32();
13806 tcg_op2
= tcg_temp_new_i32();
13807 tcg_op3
= tcg_temp_new_i32();
13808 tcg_res
= tcg_temp_new_i32();
13809 tcg_zero
= tcg_const_i32(0);
13811 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13812 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13813 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13815 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13816 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13817 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13818 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13820 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13821 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13822 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13823 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13825 tcg_temp_free_i32(tcg_op1
);
13826 tcg_temp_free_i32(tcg_op2
);
13827 tcg_temp_free_i32(tcg_op3
);
13828 tcg_temp_free_i32(tcg_res
);
13829 tcg_temp_free_i32(tcg_zero
);
13834 * 31 21 20 16 15 10 9 5 4 0
13835 * +-----------------------+------+--------+------+------+
13836 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13837 * +-----------------------+------+--------+------+------+
13839 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13841 int rm
= extract32(insn
, 16, 5);
13842 int imm6
= extract32(insn
, 10, 6);
13843 int rn
= extract32(insn
, 5, 5);
13844 int rd
= extract32(insn
, 0, 5);
13845 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13848 if (!dc_isar_feature(aa64_sha3
, s
)) {
13849 unallocated_encoding(s
);
13853 if (!fp_access_check(s
)) {
13857 tcg_op1
= tcg_temp_new_i64();
13858 tcg_op2
= tcg_temp_new_i64();
13859 tcg_res
[0] = tcg_temp_new_i64();
13860 tcg_res
[1] = tcg_temp_new_i64();
13862 for (pass
= 0; pass
< 2; pass
++) {
13863 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13864 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13866 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13867 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13869 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13870 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13872 tcg_temp_free_i64(tcg_op1
);
13873 tcg_temp_free_i64(tcg_op2
);
13874 tcg_temp_free_i64(tcg_res
[0]);
13875 tcg_temp_free_i64(tcg_res
[1]);
13878 /* Crypto three-reg imm2
13879 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13880 * +-----------------------+------+-----+------+--------+------+------+
13881 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13882 * +-----------------------+------+-----+------+--------+------+------+
13884 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13886 int opcode
= extract32(insn
, 10, 2);
13887 int imm2
= extract32(insn
, 12, 2);
13888 int rm
= extract32(insn
, 16, 5);
13889 int rn
= extract32(insn
, 5, 5);
13890 int rd
= extract32(insn
, 0, 5);
13891 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13892 TCGv_i32 tcg_imm2
, tcg_opcode
;
13894 if (!dc_isar_feature(aa64_sm3
, s
)) {
13895 unallocated_encoding(s
);
13899 if (!fp_access_check(s
)) {
13903 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13904 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13905 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13906 tcg_imm2
= tcg_const_i32(imm2
);
13907 tcg_opcode
= tcg_const_i32(opcode
);
13909 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13912 tcg_temp_free_ptr(tcg_rd_ptr
);
13913 tcg_temp_free_ptr(tcg_rn_ptr
);
13914 tcg_temp_free_ptr(tcg_rm_ptr
);
13915 tcg_temp_free_i32(tcg_imm2
);
13916 tcg_temp_free_i32(tcg_opcode
);
13919 /* C3.6 Data processing - SIMD, inc Crypto
13921 * As the decode gets a little complex we are using a table based
13922 * approach for this part of the decode.
13924 static const AArch64DecodeTable data_proc_simd
[] = {
13925 /* pattern , mask , fn */
13926 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13927 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13928 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13929 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13930 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13931 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13932 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13933 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13934 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13935 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13936 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13937 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13938 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13939 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13940 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13941 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13942 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13943 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13944 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13945 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13946 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13947 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13948 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13949 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13950 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13951 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13952 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13953 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13954 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13955 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13956 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13957 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13958 { 0x00000000, 0x00000000, NULL
}
13961 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13963 /* Note that this is called with all non-FP cases from
13964 * table C3-6 so it must UNDEF for entries not specifically
13965 * allocated to instructions in that table.
13967 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13971 unallocated_encoding(s
);
13975 /* C3.6 Data processing - SIMD and floating point */
13976 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13978 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13979 disas_data_proc_fp(s
, insn
);
13981 /* SIMD, including crypto */
13982 disas_data_proc_simd(s
, insn
);
13988 * @env: The cpu environment
13989 * @s: The DisasContext
13991 * Return true if the page is guarded.
13993 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13995 #ifdef CONFIG_USER_ONLY
13996 return false; /* FIXME */
13998 uint64_t addr
= s
->base
.pc_first
;
13999 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14000 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14001 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14004 * We test this immediately after reading an insn, which means
14005 * that any normal page must be in the TLB. The only exception
14006 * would be for executing from flash or device memory, which
14007 * does not retain the TLB entry.
14009 * FIXME: Assume false for those, for now. We could use
14010 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14011 * table entry even for that case.
14013 return (tlb_hit(entry
->addr_code
, addr
) &&
14014 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14019 * btype_destination_ok:
14020 * @insn: The instruction at the branch destination
14021 * @bt: SCTLR_ELx.BT
14022 * @btype: PSTATE.BTYPE, and is non-zero
14024 * On a guarded page, there are a limited number of insns
14025 * that may be present at the branch target:
14026 * - branch target identifiers,
14027 * - paciasp, pacibsp,
14030 * Anything else causes a Branch Target Exception.
14032 * Return true if the branch is compatible, false to raise BTITRAP.
14034 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14036 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14038 switch (extract32(insn
, 5, 7)) {
14039 case 0b011001: /* PACIASP */
14040 case 0b011011: /* PACIBSP */
14042 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14043 * with btype == 3. Otherwise all btype are ok.
14045 return !bt
|| btype
!= 3;
14046 case 0b100000: /* BTI */
14047 /* Not compatible with any btype. */
14049 case 0b100010: /* BTI c */
14050 /* Not compatible with btype == 3 */
14052 case 0b100100: /* BTI j */
14053 /* Not compatible with btype == 2 */
14055 case 0b100110: /* BTI jc */
14056 /* Compatible with any btype. */
14060 switch (insn
& 0xffe0001fu
) {
14061 case 0xd4200000u
: /* BRK */
14062 case 0xd4400000u
: /* HLT */
14063 /* Give priority to the breakpoint exception. */
14070 /* C3.1 A64 instruction index by encoding */
14071 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14075 s
->pc_curr
= s
->base
.pc_next
;
14076 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14078 s
->base
.pc_next
+= 4;
14080 s
->fp_access_checked
= false;
14082 if (dc_isar_feature(aa64_bti
, s
)) {
14083 if (s
->base
.num_insns
== 1) {
14085 * At the first insn of the TB, compute s->guarded_page.
14086 * We delayed computing this until successfully reading
14087 * the first insn of the TB, above. This (mostly) ensures
14088 * that the softmmu tlb entry has been populated, and the
14089 * page table GP bit is available.
14091 * Note that we need to compute this even if btype == 0,
14092 * because this value is used for BR instructions later
14093 * where ENV is not available.
14095 s
->guarded_page
= is_guarded_page(env
, s
);
14097 /* First insn can have btype set to non-zero. */
14098 tcg_debug_assert(s
->btype
>= 0);
14101 * Note that the Branch Target Exception has fairly high
14102 * priority -- below debugging exceptions but above most
14103 * everything else. This allows us to handle this now
14104 * instead of waiting until the insn is otherwise decoded.
14108 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14109 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14110 syn_btitrap(s
->btype
),
14111 default_exception_el(s
));
14115 /* Not the first insn: btype must be 0. */
14116 tcg_debug_assert(s
->btype
== 0);
14120 switch (extract32(insn
, 25, 4)) {
14121 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14122 unallocated_encoding(s
);
14125 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14126 unallocated_encoding(s
);
14129 case 0x8: case 0x9: /* Data processing - immediate */
14130 disas_data_proc_imm(s
, insn
);
14132 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14133 disas_b_exc_sys(s
, insn
);
14138 case 0xe: /* Loads and stores */
14139 disas_ldst(s
, insn
);
14142 case 0xd: /* Data processing - register */
14143 disas_data_proc_reg(s
, insn
);
14146 case 0xf: /* Data processing - SIMD and floating point */
14147 disas_data_proc_simd_fp(s
, insn
);
14150 assert(FALSE
); /* all 15 cases should be handled above */
14154 /* if we allocated any temporaries, free them here */
14158 * After execution of most insns, btype is reset to 0.
14159 * Note that we set btype == -1 when the insn sets btype.
14161 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14166 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14169 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14170 CPUARMState
*env
= cpu
->env_ptr
;
14171 ARMCPU
*arm_cpu
= env_archcpu(env
);
14172 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14173 int bound
, core_mmu_idx
;
14175 dc
->isar
= &arm_cpu
->isar
;
14179 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14180 * there is no secure EL1, so we route exceptions to EL3.
14182 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14183 !arm_el_is_aa64(env
, 3);
14186 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14187 dc
->condexec_mask
= 0;
14188 dc
->condexec_cond
= 0;
14189 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14190 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14191 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14192 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14193 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14194 #if !defined(CONFIG_USER_ONLY)
14195 dc
->user
= (dc
->current_el
== 0);
14197 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14198 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14199 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14200 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14201 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14202 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14203 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14205 dc
->vec_stride
= 0;
14206 dc
->cp_regs
= arm_cpu
->cp_regs
;
14207 dc
->features
= env
->features
;
14209 /* Single step state. The code-generation logic here is:
14211 * generate code with no special handling for single-stepping (except
14212 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14213 * this happens anyway because those changes are all system register or
14215 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14216 * emit code for one insn
14217 * emit code to clear PSTATE.SS
14218 * emit code to generate software step exception for completed step
14219 * end TB (as usual for having generated an exception)
14220 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14221 * emit code to generate a software step exception
14224 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14225 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14226 dc
->is_ldex
= false;
14227 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14229 /* Bound the number of insns to execute to those left on the page. */
14230 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14232 /* If architectural single step active, limit to 1. */
14233 if (dc
->ss_active
) {
14236 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14238 init_tmp_a64_array(dc
);
14241 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14245 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14247 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14249 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14250 dc
->insn_start
= tcg_last_op();
14253 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14254 const CPUBreakpoint
*bp
)
14256 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14258 if (bp
->flags
& BP_CPU
) {
14259 gen_a64_set_pc_im(dc
->base
.pc_next
);
14260 gen_helper_check_breakpoints(cpu_env
);
14261 /* End the TB early; it likely won't be executed */
14262 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14264 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14265 /* The address covered by the breakpoint must be
14266 included in [tb->pc, tb->pc + tb->size) in order
14267 to for it to be properly cleared -- thus we
14268 increment the PC here so that the logic setting
14269 tb->size below does the right thing. */
14270 dc
->base
.pc_next
+= 4;
14271 dc
->base
.is_jmp
= DISAS_NORETURN
;
14277 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14279 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14280 CPUARMState
*env
= cpu
->env_ptr
;
14282 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14283 /* Singlestep state is Active-pending.
14284 * If we're in this state at the start of a TB then either
14285 * a) we just took an exception to an EL which is being debugged
14286 * and this is the first insn in the exception handler
14287 * b) debug exceptions were masked and we just unmasked them
14288 * without changing EL (eg by clearing PSTATE.D)
14289 * In either case we're going to take a swstep exception in the
14290 * "did not step an insn" case, and so the syndrome ISV and EX
14291 * bits should be zero.
14293 assert(dc
->base
.num_insns
== 1);
14294 gen_swstep_exception(dc
, 0, 0);
14295 dc
->base
.is_jmp
= DISAS_NORETURN
;
14297 disas_a64_insn(env
, dc
);
14300 translator_loop_temp_check(&dc
->base
);
14303 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14305 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14307 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14308 /* Note that this means single stepping WFI doesn't halt the CPU.
14309 * For conditional branch insns this is harmless unreachable code as
14310 * gen_goto_tb() has already handled emitting the debug exception
14311 * (and thus a tb-jump is not possible when singlestepping).
14313 switch (dc
->base
.is_jmp
) {
14315 gen_a64_set_pc_im(dc
->base
.pc_next
);
14319 if (dc
->base
.singlestep_enabled
) {
14320 gen_exception_internal(EXCP_DEBUG
);
14322 gen_step_complete_exception(dc
);
14325 case DISAS_NORETURN
:
14329 switch (dc
->base
.is_jmp
) {
14331 case DISAS_TOO_MANY
:
14332 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14336 gen_a64_set_pc_im(dc
->base
.pc_next
);
14339 tcg_gen_exit_tb(NULL
, 0);
14342 tcg_gen_lookup_and_goto_ptr();
14344 case DISAS_NORETURN
:
14348 gen_a64_set_pc_im(dc
->base
.pc_next
);
14349 gen_helper_wfe(cpu_env
);
14352 gen_a64_set_pc_im(dc
->base
.pc_next
);
14353 gen_helper_yield(cpu_env
);
14357 /* This is a special case because we don't want to just halt the CPU
14358 * if trying to debug across a WFI.
14360 TCGv_i32 tmp
= tcg_const_i32(4);
14362 gen_a64_set_pc_im(dc
->base
.pc_next
);
14363 gen_helper_wfi(cpu_env
, tmp
);
14364 tcg_temp_free_i32(tmp
);
14365 /* The helper doesn't necessarily throw an exception, but we
14366 * must go back to the main loop to check for interrupts anyway.
14368 tcg_gen_exit_tb(NULL
, 0);
14375 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14378 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14380 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14381 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14384 const TranslatorOps aarch64_translator_ops
= {
14385 .init_disas_context
= aarch64_tr_init_disas_context
,
14386 .tb_start
= aarch64_tr_tb_start
,
14387 .insn_start
= aarch64_tr_insn_start
,
14388 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14389 .translate_insn
= aarch64_tr_translate_insn
,
14390 .tb_stop
= aarch64_tr_tb_stop
,
14391 .disas_log
= aarch64_tr_disas_log
,