2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
12 #include "primecell.h"
19 /* Primary interrupt controller. */
21 typedef struct vpb_sic_state
30 static void vpb_sic_update(vpb_sic_state
*s
)
34 flags
= s
->level
& s
->mask
;
35 qemu_set_irq(s
->parent
[s
->irq
], flags
!= 0);
38 static void vpb_sic_update_pic(vpb_sic_state
*s
)
43 for (i
= 21; i
<= 30; i
++) {
45 if (!(s
->pic_enable
& mask
))
47 qemu_set_irq(s
->parent
[i
], (s
->level
& mask
) != 0);
51 static void vpb_sic_set_irq(void *opaque
, int irq
, int level
)
53 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
55 s
->level
|= 1u << irq
;
57 s
->level
&= ~(1u << irq
);
58 if (s
->pic_enable
& (1u << irq
))
59 qemu_set_irq(s
->parent
[irq
], level
);
63 static uint32_t vpb_sic_read(void *opaque
, target_phys_addr_t offset
)
65 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
67 switch (offset
>> 2) {
69 return s
->level
& s
->mask
;
76 case 8: /* PICENABLE */
79 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset
);
84 static void vpb_sic_write(void *opaque
, target_phys_addr_t offset
,
87 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
89 switch (offset
>> 2) {
96 case 4: /* SOFTINTSET */
100 case 5: /* SOFTINTCLR */
104 case 8: /* PICENSET */
105 s
->pic_enable
|= (value
& 0x7fe00000);
106 vpb_sic_update_pic(s
);
108 case 9: /* PICENCLR */
109 s
->pic_enable
&= ~value
;
110 vpb_sic_update_pic(s
);
113 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset
);
119 static CPUReadMemoryFunc
*vpb_sic_readfn
[] = {
125 static CPUWriteMemoryFunc
*vpb_sic_writefn
[] = {
131 static qemu_irq
*vpb_sic_init(uint32_t base
, qemu_irq
*parent
, int irq
)
137 s
= (vpb_sic_state
*)qemu_mallocz(sizeof(vpb_sic_state
));
138 qi
= qemu_allocate_irqs(vpb_sic_set_irq
, s
, 32);
141 iomemtype
= cpu_register_io_memory(0, vpb_sic_readfn
,
143 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
144 /* ??? Save/restore. */
150 /* The AB and PB boards both use the same core, just with different
151 peripherans and expansion busses. For now we emulate a subset of the
152 PB peripherals and just change the board ID. */
154 static struct arm_boot_info versatile_binfo
;
156 static void versatile_init(ram_addr_t ram_size
,
157 const char *boot_device
,
158 const char *kernel_filename
, const char *kernel_cmdline
,
159 const char *initrd_filename
, const char *cpu_model
,
163 ram_addr_t ram_offset
;
174 cpu_model
= "arm926";
175 env
= cpu_init(cpu_model
);
177 fprintf(stderr
, "Unable to find CPU definition\n");
180 ram_offset
= qemu_ram_alloc(ram_size
);
181 /* ??? RAM should repeat to fill physical memory space. */
182 /* SDRAM at address zero. */
183 cpu_register_physical_memory(0, ram_size
, ram_offset
| IO_MEM_RAM
);
185 arm_sysctl_init(0x10000000, 0x41007004);
186 pic
= arm_pic_init_cpu(env
);
187 pic
= pl190_init(0x10140000, pic
[0], pic
[1]);
188 sic
= vpb_sic_init(0x10003000, pic
, 31);
189 pl050_init(0x10006000, sic
[3], 0);
190 pl050_init(0x10007000, sic
[4], 1);
192 pci_bus
= pci_vpb_init(sic
, 27, 0);
193 /* The Versatile PCI bridge does not provide access to PCI IO space,
194 so many of the qemu PCI devices are not useable. */
195 for(n
= 0; n
< nb_nics
; n
++) {
198 if ((!nd
->model
&& !done_smc
) || strcmp(nd
->model
, "smc91c111") == 0) {
199 smc91c111_init(nd
, 0x10010000, sic
[25]);
202 pci_nic_init(pci_bus
, nd
, -1, "rtl8139");
206 usb_ohci_init_pci(pci_bus
, 3, -1);
208 if (drive_get_max_bus(IF_SCSI
) > 0) {
209 fprintf(stderr
, "qemu: too many SCSI bus\n");
212 scsi_hba
= lsi_scsi_init(pci_bus
, -1);
213 for (n
= 0; n
< LSI_MAX_DEVS
; n
++) {
214 index
= drive_get_index(IF_SCSI
, 0, n
);
217 lsi_scsi_attach(scsi_hba
, drives_table
[index
].bdrv
, n
);
220 pl011_init(0x101f1000, pic
[12], serial_hds
[0], PL011_ARM
);
221 pl011_init(0x101f2000, pic
[13], serial_hds
[1], PL011_ARM
);
222 pl011_init(0x101f3000, pic
[14], serial_hds
[2], PL011_ARM
);
223 pl011_init(0x10009000, sic
[6], serial_hds
[3], PL011_ARM
);
225 pl080_init(0x10130000, pic
[17], 8);
226 sp804_init(0x101e2000, pic
[4]);
227 sp804_init(0x101e3000, pic
[5]);
229 /* The versatile/PB actually has a modified Color LCD controller
230 that includes hardware cursor support from the PL111. */
231 pl110_init(0x10120000, pic
[16], 1);
233 index
= drive_get_index(IF_SD
, 0, 0);
235 fprintf(stderr
, "qemu: missing SecureDigital card\n");
239 pl181_init(0x10005000, drives_table
[index
].bdrv
, sic
[22], sic
[1]);
241 /* Disabled because there's no way of specifying a block device. */
242 pl181_init(0x1000b000, NULL
, sic
, 23, 2);
245 /* Add PL031 Real Time Clock. */
246 pl031_init(0x101e8000,pic
[10]);
248 /* Memory map for Versatile/PB: */
249 /* 0x10000000 System registers. */
250 /* 0x10001000 PCI controller config registers. */
251 /* 0x10002000 Serial bus interface. */
252 /* 0x10003000 Secondary interrupt controller. */
253 /* 0x10004000 AACI (audio). */
254 /* 0x10005000 MMCI0. */
255 /* 0x10006000 KMI0 (keyboard). */
256 /* 0x10007000 KMI1 (mouse). */
257 /* 0x10008000 Character LCD Interface. */
258 /* 0x10009000 UART3. */
259 /* 0x1000a000 Smart card 1. */
260 /* 0x1000b000 MMCI1. */
261 /* 0x10010000 Ethernet. */
262 /* 0x10020000 USB. */
263 /* 0x10100000 SSMC. */
264 /* 0x10110000 MPMC. */
265 /* 0x10120000 CLCD Controller. */
266 /* 0x10130000 DMA Controller. */
267 /* 0x10140000 Vectored interrupt controller. */
268 /* 0x101d0000 AHB Monitor Interface. */
269 /* 0x101e0000 System Controller. */
270 /* 0x101e1000 Watchdog Interface. */
271 /* 0x101e2000 Timer 0/1. */
272 /* 0x101e3000 Timer 2/3. */
273 /* 0x101e4000 GPIO port 0. */
274 /* 0x101e5000 GPIO port 1. */
275 /* 0x101e6000 GPIO port 2. */
276 /* 0x101e7000 GPIO port 3. */
277 /* 0x101e8000 RTC. */
278 /* 0x101f0000 Smart card 0. */
279 /* 0x101f1000 UART0. */
280 /* 0x101f2000 UART1. */
281 /* 0x101f3000 UART2. */
282 /* 0x101f4000 SSPI. */
284 versatile_binfo
.ram_size
= ram_size
;
285 versatile_binfo
.kernel_filename
= kernel_filename
;
286 versatile_binfo
.kernel_cmdline
= kernel_cmdline
;
287 versatile_binfo
.initrd_filename
= initrd_filename
;
288 versatile_binfo
.board_id
= board_id
;
289 arm_load_kernel(env
, &versatile_binfo
);
292 static void vpb_init(ram_addr_t ram_size
,
293 const char *boot_device
,
294 const char *kernel_filename
, const char *kernel_cmdline
,
295 const char *initrd_filename
, const char *cpu_model
)
297 versatile_init(ram_size
,
299 kernel_filename
, kernel_cmdline
,
300 initrd_filename
, cpu_model
, 0x183);
303 static void vab_init(ram_addr_t ram_size
,
304 const char *boot_device
,
305 const char *kernel_filename
, const char *kernel_cmdline
,
306 const char *initrd_filename
, const char *cpu_model
)
308 versatile_init(ram_size
,
310 kernel_filename
, kernel_cmdline
,
311 initrd_filename
, cpu_model
, 0x25e);
314 QEMUMachine versatilepb_machine
= {
315 .name
= "versatilepb",
316 .desc
= "ARM Versatile/PB (ARM926EJ-S)",
321 QEMUMachine versatileab_machine
= {
322 .name
= "versatileab",
323 .desc
= "ARM Versatile/AB (ARM926EJ-S)",