4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
132 fprintf_function cpu_fprintf
, int flags
)
134 ARMCPU
*cpu
= ARM_CPU(cs
);
135 CPUARMState
*env
= &cpu
->env
;
136 uint32_t psr
= pstate_read(env
);
138 int el
= arm_current_el(env
);
139 const char *ns_status
;
141 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
142 for (i
= 0; i
< 32; i
++) {
144 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
146 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
147 (i
+ 2) % 3 ? " " : "\n");
151 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
152 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
156 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
158 psr
& PSTATE_N
? 'N' : '-',
159 psr
& PSTATE_Z
? 'Z' : '-',
160 psr
& PSTATE_C
? 'C' : '-',
161 psr
& PSTATE_V
? 'V' : '-',
164 psr
& PSTATE_SP
? 'h' : 't');
166 if (!(flags
& CPU_DUMP_FPU
)) {
167 cpu_fprintf(f
, "\n");
170 if (fp_exception_el(env
, el
) != 0) {
171 cpu_fprintf(f
, " FPU disabled\n");
174 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
175 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
177 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
178 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
180 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
182 if (i
== FFR_PRED_NUM
) {
183 cpu_fprintf(f
, "FFR=");
184 /* It's last, so end the line. */
187 cpu_fprintf(f
, "P%02d=", i
);
200 /* More than one quadword per predicate. */
205 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
207 if (j
* 4 + 4 <= zcr_len
+ 1) {
210 digits
= (zcr_len
% 4 + 1) * 4;
212 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
213 env
->vfp
.pregs
[i
].p
[j
],
214 j
? ":" : eol
? "\n" : " ");
218 for (i
= 0; i
< 32; i
++) {
220 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
221 i
, env
->vfp
.zregs
[i
].d
[1],
222 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
223 } else if (zcr_len
== 1) {
224 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
225 ":%016" PRIx64
":%016" PRIx64
"\n",
226 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
227 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
229 for (j
= zcr_len
; j
>= 0; j
--) {
230 bool odd
= (zcr_len
- j
) % 2 != 0;
232 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
235 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
237 cpu_fprintf(f
, " [%x]=", j
);
240 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
241 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
242 env
->vfp
.zregs
[i
].d
[j
* 2],
243 odd
|| j
== 0 ? "\n" : ":");
248 for (i
= 0; i
< 32; i
++) {
249 uint64_t *q
= aa64_vfp_qreg(env
, i
);
250 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
251 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
256 void gen_a64_set_pc_im(uint64_t val
)
258 tcg_gen_movi_i64(cpu_pc
, val
);
261 /* Load the PC from a generic TCG variable.
263 * If address tagging is enabled via the TCR TBI bits, then loading
264 * an address into the PC will clear out any tag in the it:
265 * + for EL2 and EL3 there is only one TBI bit, and if it is set
266 * then the address is zero-extended, clearing bits [63:56]
267 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
268 * and TBI1 controls addressses with bit 55 == 1.
269 * If the appropriate TBI bit is set for the address then
270 * the address is sign-extended from bit 55 into bits [63:56]
272 * We can avoid doing this for relative-branches, because the
273 * PC + offset can never overflow into the tag bits (assuming
274 * that virtual addresses are less than 56 bits wide, as they
275 * are currently), but we must handle it for branch-to-register.
277 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
280 if (s
->current_el
<= 1) {
281 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
282 * examine bit 55 of address, can just generate code.
283 * If mixed, then test via generated code
285 if (s
->tbi0
&& s
->tbi1
) {
286 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
287 /* Both bits set, sign extension from bit 55 into [63:56] will
290 tcg_gen_shli_i64(tmp_reg
, src
, 8);
291 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
292 tcg_temp_free_i64(tmp_reg
);
293 } else if (!s
->tbi0
&& !s
->tbi1
) {
294 /* Neither bit set, just load it as-is */
295 tcg_gen_mov_i64(cpu_pc
, src
);
297 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
298 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
299 TCGv_i64 tcg_zero
= tcg_const_i64(0);
301 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
304 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
305 tcg_gen_andi_i64(tcg_tmpval
, src
,
306 0x00FFFFFFFFFFFFFFull
);
307 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
310 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
311 tcg_gen_ori_i64(tcg_tmpval
, src
,
312 0xFF00000000000000ull
);
313 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
316 tcg_temp_free_i64(tcg_zero
);
317 tcg_temp_free_i64(tcg_bit55
);
318 tcg_temp_free_i64(tcg_tmpval
);
320 } else { /* EL > 1 */
322 /* Force tag byte to all zero */
323 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
325 /* Load unmodified address */
326 tcg_gen_mov_i64(cpu_pc
, src
);
331 typedef struct DisasCompare64
{
336 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
340 arm_test_cc(&c32
, cc
);
342 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
343 * properly. The NE/EQ comparisons are also fine with this choice. */
344 c64
->cond
= c32
.cond
;
345 c64
->value
= tcg_temp_new_i64();
346 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
351 static void a64_free_cc(DisasCompare64
*c64
)
353 tcg_temp_free_i64(c64
->value
);
356 static void gen_exception_internal(int excp
)
358 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
360 assert(excp_is_internal(excp
));
361 gen_helper_exception_internal(cpu_env
, tcg_excp
);
362 tcg_temp_free_i32(tcg_excp
);
365 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
367 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
368 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
369 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
371 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
373 tcg_temp_free_i32(tcg_el
);
374 tcg_temp_free_i32(tcg_syn
);
375 tcg_temp_free_i32(tcg_excp
);
378 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
380 gen_a64_set_pc_im(s
->pc
- offset
);
381 gen_exception_internal(excp
);
382 s
->base
.is_jmp
= DISAS_NORETURN
;
385 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
386 uint32_t syndrome
, uint32_t target_el
)
388 gen_a64_set_pc_im(s
->pc
- offset
);
389 gen_exception(excp
, syndrome
, target_el
);
390 s
->base
.is_jmp
= DISAS_NORETURN
;
393 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
398 gen_a64_set_pc_im(s
->pc
- offset
);
399 tcg_syn
= tcg_const_i32(syndrome
);
400 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
401 tcg_temp_free_i32(tcg_syn
);
402 s
->base
.is_jmp
= DISAS_NORETURN
;
405 static void gen_ss_advance(DisasContext
*s
)
407 /* If the singlestep state is Active-not-pending, advance to
412 gen_helper_clear_pstate_ss(cpu_env
);
416 static void gen_step_complete_exception(DisasContext
*s
)
418 /* We just completed step of an insn. Move from Active-not-pending
419 * to Active-pending, and then also take the swstep exception.
420 * This corresponds to making the (IMPDEF) choice to prioritize
421 * swstep exceptions over asynchronous exceptions taken to an exception
422 * level where debug is disabled. This choice has the advantage that
423 * we do not need to maintain internal state corresponding to the
424 * ISV/EX syndrome bits between completion of the step and generation
425 * of the exception, and our syndrome information is always correct.
428 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
429 default_exception_el(s
));
430 s
->base
.is_jmp
= DISAS_NORETURN
;
433 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
435 /* No direct tb linking with singlestep (either QEMU's or the ARM
436 * debug architecture kind) or deterministic io
438 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
439 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
443 #ifndef CONFIG_USER_ONLY
444 /* Only link tbs from inside the same guest page */
445 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
453 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
455 TranslationBlock
*tb
;
458 if (use_goto_tb(s
, n
, dest
)) {
460 gen_a64_set_pc_im(dest
);
461 tcg_gen_exit_tb(tb
, n
);
462 s
->base
.is_jmp
= DISAS_NORETURN
;
464 gen_a64_set_pc_im(dest
);
466 gen_step_complete_exception(s
);
467 } else if (s
->base
.singlestep_enabled
) {
468 gen_exception_internal(EXCP_DEBUG
);
470 tcg_gen_lookup_and_goto_ptr();
471 s
->base
.is_jmp
= DISAS_NORETURN
;
476 void unallocated_encoding(DisasContext
*s
)
478 /* Unallocated and reserved encodings are uncategorized */
479 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
480 default_exception_el(s
));
483 static void init_tmp_a64_array(DisasContext
*s
)
485 #ifdef CONFIG_DEBUG_TCG
486 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
488 s
->tmp_a64_count
= 0;
491 static void free_tmp_a64(DisasContext
*s
)
494 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
495 tcg_temp_free_i64(s
->tmp_a64
[i
]);
497 init_tmp_a64_array(s
);
500 TCGv_i64
new_tmp_a64(DisasContext
*s
)
502 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
503 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
506 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
508 TCGv_i64 t
= new_tmp_a64(s
);
509 tcg_gen_movi_i64(t
, 0);
514 * Register access functions
516 * These functions are used for directly accessing a register in where
517 * changes to the final register value are likely to be made. If you
518 * need to use a register for temporary calculation (e.g. index type
519 * operations) use the read_* form.
521 * B1.2.1 Register mappings
523 * In instruction register encoding 31 can refer to ZR (zero register) or
524 * the SP (stack pointer) depending on context. In QEMU's case we map SP
525 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
526 * This is the point of the _sp forms.
528 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
531 return new_tmp_a64_zero(s
);
537 /* register access for when 31 == SP */
538 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
543 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
544 * representing the register contents. This TCGv is an auto-freed
545 * temporary so it need not be explicitly freed, and may be modified.
547 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
549 TCGv_i64 v
= new_tmp_a64(s
);
552 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
554 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
557 tcg_gen_movi_i64(v
, 0);
562 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
564 TCGv_i64 v
= new_tmp_a64(s
);
566 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
568 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
573 /* Return the offset into CPUARMState of a slice (from
574 * the least significant end) of FP register Qn (ie
576 * (Note that this is not the same mapping as for A32; see cpu.h)
578 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
580 return vec_reg_offset(s
, regno
, 0, size
);
583 /* Offset of the high half of the 128 bit vector Qn */
584 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
586 return vec_reg_offset(s
, regno
, 1, MO_64
);
589 /* Convenience accessors for reading and writing single and double
590 * FP registers. Writing clears the upper parts of the associated
591 * 128 bit vector register, as required by the architecture.
592 * Note that unlike the GP register accessors, the values returned
593 * by the read functions must be manually freed.
595 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
597 TCGv_i64 v
= tcg_temp_new_i64();
599 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
603 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
605 TCGv_i32 v
= tcg_temp_new_i32();
607 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
611 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
613 TCGv_i32 v
= tcg_temp_new_i32();
615 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
619 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
620 * If SVE is not enabled, then there are only 128 bits in the vector.
622 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
624 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
625 unsigned vsz
= vec_full_reg_size(s
);
628 TCGv_i64 tcg_zero
= tcg_const_i64(0);
629 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
630 tcg_temp_free_i64(tcg_zero
);
633 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
637 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
639 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
641 tcg_gen_st_i64(v
, cpu_env
, ofs
);
642 clear_vec_high(s
, false, reg
);
645 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
647 TCGv_i64 tmp
= tcg_temp_new_i64();
649 tcg_gen_extu_i32_i64(tmp
, v
);
650 write_fp_dreg(s
, reg
, tmp
);
651 tcg_temp_free_i64(tmp
);
654 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
656 TCGv_ptr statusptr
= tcg_temp_new_ptr();
659 /* In A64 all instructions (both FP and Neon) use the FPCR; there
660 * is no equivalent of the A32 Neon "standard FPSCR value".
661 * However half-precision operations operate under a different
662 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
665 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
667 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
669 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
673 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
674 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
675 GVecGen2Fn
*gvec_fn
, int vece
)
677 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
678 is_q
? 16 : 8, vec_full_reg_size(s
));
681 /* Expand a 2-operand + immediate AdvSIMD vector operation using
682 * an expander function.
684 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
685 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
687 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
688 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
691 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
692 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
693 GVecGen3Fn
*gvec_fn
, int vece
)
695 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
699 /* Expand a 2-operand + immediate AdvSIMD vector operation using
702 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
703 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
705 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
706 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
709 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
710 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
711 int rn
, int rm
, const GVecGen3
*gvec_op
)
713 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
714 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
715 vec_full_reg_size(s
), gvec_op
);
718 /* Expand a 3-operand operation using an out-of-line helper. */
719 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
720 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
722 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
723 vec_full_reg_offset(s
, rn
),
724 vec_full_reg_offset(s
, rm
),
725 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
728 /* Expand a 3-operand + env pointer operation using
729 * an out-of-line helper.
731 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
732 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
734 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
735 vec_full_reg_offset(s
, rn
),
736 vec_full_reg_offset(s
, rm
), cpu_env
,
737 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
740 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
741 * an out-of-line helper.
743 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
744 int rm
, bool is_fp16
, int data
,
745 gen_helper_gvec_3_ptr
*fn
)
747 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
748 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
749 vec_full_reg_offset(s
, rn
),
750 vec_full_reg_offset(s
, rm
), fpst
,
751 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
752 tcg_temp_free_ptr(fpst
);
755 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
756 * than the 32 bit equivalent.
758 static inline void gen_set_NZ64(TCGv_i64 result
)
760 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
761 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
764 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
765 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
768 gen_set_NZ64(result
);
770 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
771 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
773 tcg_gen_movi_i32(cpu_CF
, 0);
774 tcg_gen_movi_i32(cpu_VF
, 0);
777 /* dest = T0 + T1; compute C, N, V and Z flags */
778 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
781 TCGv_i64 result
, flag
, tmp
;
782 result
= tcg_temp_new_i64();
783 flag
= tcg_temp_new_i64();
784 tmp
= tcg_temp_new_i64();
786 tcg_gen_movi_i64(tmp
, 0);
787 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
789 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
791 gen_set_NZ64(result
);
793 tcg_gen_xor_i64(flag
, result
, t0
);
794 tcg_gen_xor_i64(tmp
, t0
, t1
);
795 tcg_gen_andc_i64(flag
, flag
, tmp
);
796 tcg_temp_free_i64(tmp
);
797 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
799 tcg_gen_mov_i64(dest
, result
);
800 tcg_temp_free_i64(result
);
801 tcg_temp_free_i64(flag
);
803 /* 32 bit arithmetic */
804 TCGv_i32 t0_32
= tcg_temp_new_i32();
805 TCGv_i32 t1_32
= tcg_temp_new_i32();
806 TCGv_i32 tmp
= tcg_temp_new_i32();
808 tcg_gen_movi_i32(tmp
, 0);
809 tcg_gen_extrl_i64_i32(t0_32
, t0
);
810 tcg_gen_extrl_i64_i32(t1_32
, t1
);
811 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
812 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
813 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
814 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
815 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
816 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
818 tcg_temp_free_i32(tmp
);
819 tcg_temp_free_i32(t0_32
);
820 tcg_temp_free_i32(t1_32
);
824 /* dest = T0 - T1; compute C, N, V and Z flags */
825 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
828 /* 64 bit arithmetic */
829 TCGv_i64 result
, flag
, tmp
;
831 result
= tcg_temp_new_i64();
832 flag
= tcg_temp_new_i64();
833 tcg_gen_sub_i64(result
, t0
, t1
);
835 gen_set_NZ64(result
);
837 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
838 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
840 tcg_gen_xor_i64(flag
, result
, t0
);
841 tmp
= tcg_temp_new_i64();
842 tcg_gen_xor_i64(tmp
, t0
, t1
);
843 tcg_gen_and_i64(flag
, flag
, tmp
);
844 tcg_temp_free_i64(tmp
);
845 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
846 tcg_gen_mov_i64(dest
, result
);
847 tcg_temp_free_i64(flag
);
848 tcg_temp_free_i64(result
);
850 /* 32 bit arithmetic */
851 TCGv_i32 t0_32
= tcg_temp_new_i32();
852 TCGv_i32 t1_32
= tcg_temp_new_i32();
855 tcg_gen_extrl_i64_i32(t0_32
, t0
);
856 tcg_gen_extrl_i64_i32(t1_32
, t1
);
857 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
858 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
859 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
860 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
861 tmp
= tcg_temp_new_i32();
862 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
863 tcg_temp_free_i32(t0_32
);
864 tcg_temp_free_i32(t1_32
);
865 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
866 tcg_temp_free_i32(tmp
);
867 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
871 /* dest = T0 + T1 + CF; do not compute flags. */
872 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
874 TCGv_i64 flag
= tcg_temp_new_i64();
875 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
876 tcg_gen_add_i64(dest
, t0
, t1
);
877 tcg_gen_add_i64(dest
, dest
, flag
);
878 tcg_temp_free_i64(flag
);
881 tcg_gen_ext32u_i64(dest
, dest
);
885 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
886 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
889 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
890 result
= tcg_temp_new_i64();
891 cf_64
= tcg_temp_new_i64();
892 vf_64
= tcg_temp_new_i64();
893 tmp
= tcg_const_i64(0);
895 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
896 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
897 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
898 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
899 gen_set_NZ64(result
);
901 tcg_gen_xor_i64(vf_64
, result
, t0
);
902 tcg_gen_xor_i64(tmp
, t0
, t1
);
903 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
904 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
906 tcg_gen_mov_i64(dest
, result
);
908 tcg_temp_free_i64(tmp
);
909 tcg_temp_free_i64(vf_64
);
910 tcg_temp_free_i64(cf_64
);
911 tcg_temp_free_i64(result
);
913 TCGv_i32 t0_32
, t1_32
, tmp
;
914 t0_32
= tcg_temp_new_i32();
915 t1_32
= tcg_temp_new_i32();
916 tmp
= tcg_const_i32(0);
918 tcg_gen_extrl_i64_i32(t0_32
, t0
);
919 tcg_gen_extrl_i64_i32(t1_32
, t1
);
920 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
921 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
923 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
924 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
925 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
926 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
927 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
929 tcg_temp_free_i32(tmp
);
930 tcg_temp_free_i32(t1_32
);
931 tcg_temp_free_i32(t0_32
);
936 * Load/Store generators
940 * Store from GPR register to memory.
942 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
943 TCGv_i64 tcg_addr
, int size
, int memidx
,
945 unsigned int iss_srt
,
946 bool iss_sf
, bool iss_ar
)
949 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
954 syn
= syn_data_abort_with_iss(0,
960 0, 0, 0, 0, 0, false);
961 disas_set_insn_syndrome(s
, syn
);
965 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
966 TCGv_i64 tcg_addr
, int size
,
968 unsigned int iss_srt
,
969 bool iss_sf
, bool iss_ar
)
971 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
972 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
976 * Load from memory to GPR register
978 static void do_gpr_ld_memidx(DisasContext
*s
,
979 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
980 int size
, bool is_signed
,
981 bool extend
, int memidx
,
982 bool iss_valid
, unsigned int iss_srt
,
983 bool iss_sf
, bool iss_ar
)
985 TCGMemOp memop
= s
->be_data
+ size
;
993 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
995 if (extend
&& is_signed
) {
997 tcg_gen_ext32u_i64(dest
, dest
);
1003 syn
= syn_data_abort_with_iss(0,
1009 0, 0, 0, 0, 0, false);
1010 disas_set_insn_syndrome(s
, syn
);
1014 static void do_gpr_ld(DisasContext
*s
,
1015 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1016 int size
, bool is_signed
, bool extend
,
1017 bool iss_valid
, unsigned int iss_srt
,
1018 bool iss_sf
, bool iss_ar
)
1020 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1022 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1026 * Store from FP register to memory
1028 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1030 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1031 TCGv_i64 tmp
= tcg_temp_new_i64();
1032 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1034 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1037 bool be
= s
->be_data
== MO_BE
;
1038 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1040 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1041 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1043 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1044 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1046 tcg_temp_free_i64(tcg_hiaddr
);
1049 tcg_temp_free_i64(tmp
);
1053 * Load from memory to FP register
1055 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1057 /* This always zero-extends and writes to a full 128 bit wide vector */
1058 TCGv_i64 tmplo
= tcg_temp_new_i64();
1062 TCGMemOp memop
= s
->be_data
+ size
;
1063 tmphi
= tcg_const_i64(0);
1064 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1066 bool be
= s
->be_data
== MO_BE
;
1067 TCGv_i64 tcg_hiaddr
;
1069 tmphi
= tcg_temp_new_i64();
1070 tcg_hiaddr
= tcg_temp_new_i64();
1072 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1073 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1075 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1077 tcg_temp_free_i64(tcg_hiaddr
);
1080 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1081 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1083 tcg_temp_free_i64(tmplo
);
1084 tcg_temp_free_i64(tmphi
);
1086 clear_vec_high(s
, true, destidx
);
1090 * Vector load/store helpers.
1092 * The principal difference between this and a FP load is that we don't
1093 * zero extend as we are filling a partial chunk of the vector register.
1094 * These functions don't support 128 bit loads/stores, which would be
1095 * normal load/store operations.
1097 * The _i32 versions are useful when operating on 32 bit quantities
1098 * (eg for floating point single or using Neon helper functions).
1101 /* Get value of an element within a vector register */
1102 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1103 int element
, TCGMemOp memop
)
1105 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1108 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1114 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1117 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1120 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1123 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1127 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1130 g_assert_not_reached();
1134 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1135 int element
, TCGMemOp memop
)
1137 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1140 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1143 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1149 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1153 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1156 g_assert_not_reached();
1160 /* Set value of an element within a vector register */
1161 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1162 int element
, TCGMemOp memop
)
1164 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1167 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1170 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1173 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1176 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1179 g_assert_not_reached();
1183 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1184 int destidx
, int element
, TCGMemOp memop
)
1186 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1189 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1195 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1198 g_assert_not_reached();
1202 /* Store from vector register to memory */
1203 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1204 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1206 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1208 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1209 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1211 tcg_temp_free_i64(tcg_tmp
);
1214 /* Load from memory to vector register */
1215 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1216 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1218 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1220 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1221 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1223 tcg_temp_free_i64(tcg_tmp
);
1226 /* Check that FP/Neon access is enabled. If it is, return
1227 * true. If not, emit code to generate an appropriate exception,
1228 * and return false; the caller should not emit any code for
1229 * the instruction. Note that this check must happen after all
1230 * unallocated-encoding checks (otherwise the syndrome information
1231 * for the resulting exception will be incorrect).
1233 static inline bool fp_access_check(DisasContext
*s
)
1235 assert(!s
->fp_access_checked
);
1236 s
->fp_access_checked
= true;
1238 if (!s
->fp_excp_el
) {
1242 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1247 /* Check that SVE access is enabled. If it is, return true.
1248 * If not, emit code to generate an appropriate exception and return false.
1250 bool sve_access_check(DisasContext
*s
)
1252 if (s
->sve_excp_el
) {
1253 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1257 return fp_access_check(s
);
1261 * This utility function is for doing register extension with an
1262 * optional shift. You will likely want to pass a temporary for the
1263 * destination register. See DecodeRegExtend() in the ARM ARM.
1265 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1266 int option
, unsigned int shift
)
1268 int extsize
= extract32(option
, 0, 2);
1269 bool is_signed
= extract32(option
, 2, 1);
1274 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1277 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1280 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1283 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1289 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1292 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1295 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1298 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1304 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1308 static inline void gen_check_sp_alignment(DisasContext
*s
)
1310 /* The AArch64 architecture mandates that (if enabled via PSTATE
1311 * or SCTLR bits) there is a check that SP is 16-aligned on every
1312 * SP-relative load or store (with an exception generated if it is not).
1313 * In line with general QEMU practice regarding misaligned accesses,
1314 * we omit these checks for the sake of guest program performance.
1315 * This function is provided as a hook so we can more easily add these
1316 * checks in future (possibly as a "favour catching guest program bugs
1317 * over speed" user selectable option).
1322 * This provides a simple table based table lookup decoder. It is
1323 * intended to be used when the relevant bits for decode are too
1324 * awkwardly placed and switch/if based logic would be confusing and
1325 * deeply nested. Since it's a linear search through the table, tables
1326 * should be kept small.
1328 * It returns the first handler where insn & mask == pattern, or
1329 * NULL if there is no match.
1330 * The table is terminated by an empty mask (i.e. 0)
1332 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1335 const AArch64DecodeTable
*tptr
= table
;
1337 while (tptr
->mask
) {
1338 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1339 return tptr
->disas_fn
;
1347 * The instruction disassembly implemented here matches
1348 * the instruction encoding classifications in chapter C4
1349 * of the ARM Architecture Reference Manual (DDI0487B_a);
1350 * classification names and decode diagrams here should generally
1351 * match up with those in the manual.
1354 /* Unconditional branch (immediate)
1356 * +----+-----------+-------------------------------------+
1357 * | op | 0 0 1 0 1 | imm26 |
1358 * +----+-----------+-------------------------------------+
1360 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1362 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1364 if (insn
& (1U << 31)) {
1365 /* BL Branch with link */
1366 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1369 /* B Branch / BL Branch with link */
1370 gen_goto_tb(s
, 0, addr
);
1373 /* Compare and branch (immediate)
1374 * 31 30 25 24 23 5 4 0
1375 * +----+-------------+----+---------------------+--------+
1376 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1377 * +----+-------------+----+---------------------+--------+
1379 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1381 unsigned int sf
, op
, rt
;
1383 TCGLabel
*label_match
;
1386 sf
= extract32(insn
, 31, 1);
1387 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1388 rt
= extract32(insn
, 0, 5);
1389 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1391 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1392 label_match
= gen_new_label();
1394 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1395 tcg_cmp
, 0, label_match
);
1397 gen_goto_tb(s
, 0, s
->pc
);
1398 gen_set_label(label_match
);
1399 gen_goto_tb(s
, 1, addr
);
1402 /* Test and branch (immediate)
1403 * 31 30 25 24 23 19 18 5 4 0
1404 * +----+-------------+----+-------+-------------+------+
1405 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1406 * +----+-------------+----+-------+-------------+------+
1408 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1410 unsigned int bit_pos
, op
, rt
;
1412 TCGLabel
*label_match
;
1415 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1416 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1417 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1418 rt
= extract32(insn
, 0, 5);
1420 tcg_cmp
= tcg_temp_new_i64();
1421 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1422 label_match
= gen_new_label();
1423 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1424 tcg_cmp
, 0, label_match
);
1425 tcg_temp_free_i64(tcg_cmp
);
1426 gen_goto_tb(s
, 0, s
->pc
);
1427 gen_set_label(label_match
);
1428 gen_goto_tb(s
, 1, addr
);
1431 /* Conditional branch (immediate)
1432 * 31 25 24 23 5 4 3 0
1433 * +---------------+----+---------------------+----+------+
1434 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1435 * +---------------+----+---------------------+----+------+
1437 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1442 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1443 unallocated_encoding(s
);
1446 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1447 cond
= extract32(insn
, 0, 4);
1450 /* genuinely conditional branches */
1451 TCGLabel
*label_match
= gen_new_label();
1452 arm_gen_test_cc(cond
, label_match
);
1453 gen_goto_tb(s
, 0, s
->pc
);
1454 gen_set_label(label_match
);
1455 gen_goto_tb(s
, 1, addr
);
1457 /* 0xe and 0xf are both "always" conditions */
1458 gen_goto_tb(s
, 0, addr
);
1462 /* HINT instruction group, including various allocated HINTs */
1463 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1464 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1466 unsigned int selector
= crm
<< 3 | op2
;
1469 unallocated_encoding(s
);
1477 s
->base
.is_jmp
= DISAS_WFI
;
1479 /* When running in MTTCG we don't generate jumps to the yield and
1480 * WFE helpers as it won't affect the scheduling of other vCPUs.
1481 * If we wanted to more completely model WFE/SEV so we don't busy
1482 * spin unnecessarily we would need to do something more involved.
1485 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1486 s
->base
.is_jmp
= DISAS_YIELD
;
1490 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1491 s
->base
.is_jmp
= DISAS_WFE
;
1496 /* we treat all as NOP at least for now */
1499 /* default specified as NOP equivalent */
1504 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1506 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1509 /* CLREX, DSB, DMB, ISB */
1510 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1511 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1516 unallocated_encoding(s
);
1527 case 1: /* MBReqTypes_Reads */
1528 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1530 case 2: /* MBReqTypes_Writes */
1531 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1533 default: /* MBReqTypes_All */
1534 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1540 /* We need to break the TB after this insn to execute
1541 * a self-modified code correctly and also to take
1542 * any pending interrupts immediately.
1544 gen_goto_tb(s
, 0, s
->pc
);
1547 unallocated_encoding(s
);
1552 /* MSR (immediate) - move immediate to processor state field */
1553 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1554 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1556 int op
= op1
<< 3 | op2
;
1558 case 0x05: /* SPSel */
1559 if (s
->current_el
== 0) {
1560 unallocated_encoding(s
);
1564 case 0x1e: /* DAIFSet */
1565 case 0x1f: /* DAIFClear */
1567 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1568 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1569 gen_a64_set_pc_im(s
->pc
- 4);
1570 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1571 tcg_temp_free_i32(tcg_imm
);
1572 tcg_temp_free_i32(tcg_op
);
1573 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1574 gen_a64_set_pc_im(s
->pc
);
1575 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1579 unallocated_encoding(s
);
1584 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1586 TCGv_i32 tmp
= tcg_temp_new_i32();
1587 TCGv_i32 nzcv
= tcg_temp_new_i32();
1589 /* build bit 31, N */
1590 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1591 /* build bit 30, Z */
1592 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1593 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1594 /* build bit 29, C */
1595 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1596 /* build bit 28, V */
1597 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1598 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1599 /* generate result */
1600 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1602 tcg_temp_free_i32(nzcv
);
1603 tcg_temp_free_i32(tmp
);
1606 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1609 TCGv_i32 nzcv
= tcg_temp_new_i32();
1611 /* take NZCV from R[t] */
1612 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1615 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1617 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1618 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1620 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1621 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1623 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1624 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1625 tcg_temp_free_i32(nzcv
);
1628 /* MRS - move from system register
1629 * MSR (register) - move to system register
1632 * These are all essentially the same insn in 'read' and 'write'
1633 * versions, with varying op0 fields.
1635 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1636 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1637 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1639 const ARMCPRegInfo
*ri
;
1642 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1643 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1644 crn
, crm
, op0
, op1
, op2
));
1647 /* Unknown register; this might be a guest error or a QEMU
1648 * unimplemented feature.
1650 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1651 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1652 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1653 unallocated_encoding(s
);
1657 /* Check access permissions */
1658 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1659 unallocated_encoding(s
);
1664 /* Emit code to perform further access permissions checks at
1665 * runtime; this may result in an exception.
1668 TCGv_i32 tcg_syn
, tcg_isread
;
1671 gen_a64_set_pc_im(s
->pc
- 4);
1672 tmpptr
= tcg_const_ptr(ri
);
1673 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1674 tcg_syn
= tcg_const_i32(syndrome
);
1675 tcg_isread
= tcg_const_i32(isread
);
1676 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1677 tcg_temp_free_ptr(tmpptr
);
1678 tcg_temp_free_i32(tcg_syn
);
1679 tcg_temp_free_i32(tcg_isread
);
1682 /* Handle special cases first */
1683 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1687 tcg_rt
= cpu_reg(s
, rt
);
1689 gen_get_nzcv(tcg_rt
);
1691 gen_set_nzcv(tcg_rt
);
1694 case ARM_CP_CURRENTEL
:
1695 /* Reads as current EL value from pstate, which is
1696 * guaranteed to be constant by the tb flags.
1698 tcg_rt
= cpu_reg(s
, rt
);
1699 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1702 /* Writes clear the aligned block of memory which rt points into. */
1703 tcg_rt
= cpu_reg(s
, rt
);
1704 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1709 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1711 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1715 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1719 tcg_rt
= cpu_reg(s
, rt
);
1722 if (ri
->type
& ARM_CP_CONST
) {
1723 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1724 } else if (ri
->readfn
) {
1726 tmpptr
= tcg_const_ptr(ri
);
1727 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1728 tcg_temp_free_ptr(tmpptr
);
1730 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1733 if (ri
->type
& ARM_CP_CONST
) {
1734 /* If not forbidden by access permissions, treat as WI */
1736 } else if (ri
->writefn
) {
1738 tmpptr
= tcg_const_ptr(ri
);
1739 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1740 tcg_temp_free_ptr(tmpptr
);
1742 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1746 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1747 /* I/O operations must end the TB here (whether read or write) */
1749 s
->base
.is_jmp
= DISAS_UPDATE
;
1750 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1751 /* We default to ending the TB on a coprocessor register write,
1752 * but allow this to be suppressed by the register definition
1753 * (usually only necessary to work around guest bugs).
1755 s
->base
.is_jmp
= DISAS_UPDATE
;
1760 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1761 * +---------------------+---+-----+-----+-------+-------+-----+------+
1762 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1763 * +---------------------+---+-----+-----+-------+-------+-----+------+
1765 static void disas_system(DisasContext
*s
, uint32_t insn
)
1767 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1768 l
= extract32(insn
, 21, 1);
1769 op0
= extract32(insn
, 19, 2);
1770 op1
= extract32(insn
, 16, 3);
1771 crn
= extract32(insn
, 12, 4);
1772 crm
= extract32(insn
, 8, 4);
1773 op2
= extract32(insn
, 5, 3);
1774 rt
= extract32(insn
, 0, 5);
1777 if (l
|| rt
!= 31) {
1778 unallocated_encoding(s
);
1782 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1783 handle_hint(s
, insn
, op1
, op2
, crm
);
1785 case 3: /* CLREX, DSB, DMB, ISB */
1786 handle_sync(s
, insn
, op1
, op2
, crm
);
1788 case 4: /* MSR (immediate) */
1789 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1792 unallocated_encoding(s
);
1797 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1800 /* Exception generation
1802 * 31 24 23 21 20 5 4 2 1 0
1803 * +-----------------+-----+------------------------+-----+----+
1804 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1805 * +-----------------------+------------------------+----------+
1807 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1809 int opc
= extract32(insn
, 21, 3);
1810 int op2_ll
= extract32(insn
, 0, 5);
1811 int imm16
= extract32(insn
, 5, 16);
1816 /* For SVC, HVC and SMC we advance the single-step state
1817 * machine before taking the exception. This is architecturally
1818 * mandated, to ensure that single-stepping a system call
1819 * instruction works properly.
1824 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1825 default_exception_el(s
));
1828 if (s
->current_el
== 0) {
1829 unallocated_encoding(s
);
1832 /* The pre HVC helper handles cases when HVC gets trapped
1833 * as an undefined insn by runtime configuration.
1835 gen_a64_set_pc_im(s
->pc
- 4);
1836 gen_helper_pre_hvc(cpu_env
);
1838 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1841 if (s
->current_el
== 0) {
1842 unallocated_encoding(s
);
1845 gen_a64_set_pc_im(s
->pc
- 4);
1846 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1847 gen_helper_pre_smc(cpu_env
, tmp
);
1848 tcg_temp_free_i32(tmp
);
1850 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1853 unallocated_encoding(s
);
1859 unallocated_encoding(s
);
1863 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1867 unallocated_encoding(s
);
1870 /* HLT. This has two purposes.
1871 * Architecturally, it is an external halting debug instruction.
1872 * Since QEMU doesn't implement external debug, we treat this as
1873 * it is required for halting debug disabled: it will UNDEF.
1874 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1876 if (semihosting_enabled() && imm16
== 0xf000) {
1877 #ifndef CONFIG_USER_ONLY
1878 /* In system mode, don't allow userspace access to semihosting,
1879 * to provide some semblance of security (and for consistency
1880 * with our 32-bit semihosting).
1882 if (s
->current_el
== 0) {
1883 unsupported_encoding(s
, insn
);
1887 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1889 unsupported_encoding(s
, insn
);
1893 if (op2_ll
< 1 || op2_ll
> 3) {
1894 unallocated_encoding(s
);
1897 /* DCPS1, DCPS2, DCPS3 */
1898 unsupported_encoding(s
, insn
);
1901 unallocated_encoding(s
);
1906 /* Unconditional branch (register)
1907 * 31 25 24 21 20 16 15 10 9 5 4 0
1908 * +---------------+-------+-------+-------+------+-------+
1909 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1910 * +---------------+-------+-------+-------+------+-------+
1912 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1914 unsigned int opc
, op2
, op3
, rn
, op4
;
1916 opc
= extract32(insn
, 21, 4);
1917 op2
= extract32(insn
, 16, 5);
1918 op3
= extract32(insn
, 10, 6);
1919 rn
= extract32(insn
, 5, 5);
1920 op4
= extract32(insn
, 0, 5);
1922 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1923 unallocated_encoding(s
);
1931 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1932 /* BLR also needs to load return address */
1934 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1938 if (s
->current_el
== 0) {
1939 unallocated_encoding(s
);
1942 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1945 gen_helper_exception_return(cpu_env
);
1946 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1949 /* Must exit loop to check un-masked IRQs */
1950 s
->base
.is_jmp
= DISAS_EXIT
;
1954 unallocated_encoding(s
);
1956 unsupported_encoding(s
, insn
);
1960 unallocated_encoding(s
);
1964 s
->base
.is_jmp
= DISAS_JUMP
;
1967 /* Branches, exception generating and system instructions */
1968 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1970 switch (extract32(insn
, 25, 7)) {
1971 case 0x0a: case 0x0b:
1972 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1973 disas_uncond_b_imm(s
, insn
);
1975 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1976 disas_comp_b_imm(s
, insn
);
1978 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1979 disas_test_b_imm(s
, insn
);
1981 case 0x2a: /* Conditional branch (immediate) */
1982 disas_cond_b_imm(s
, insn
);
1984 case 0x6a: /* Exception generation / System */
1985 if (insn
& (1 << 24)) {
1986 disas_system(s
, insn
);
1991 case 0x6b: /* Unconditional branch (register) */
1992 disas_uncond_b_reg(s
, insn
);
1995 unallocated_encoding(s
);
2001 * Load/Store exclusive instructions are implemented by remembering
2002 * the value/address loaded, and seeing if these are the same
2003 * when the store is performed. This is not actually the architecturally
2004 * mandated semantics, but it works for typical guest code sequences
2005 * and avoids having to monitor regular stores.
2007 * The store exclusive uses the atomic cmpxchg primitives to avoid
2008 * races in multi-threaded linux-user and when MTTCG softmmu is
2011 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2012 TCGv_i64 addr
, int size
, bool is_pair
)
2014 int idx
= get_mem_index(s
);
2015 TCGMemOp memop
= s
->be_data
;
2017 g_assert(size
<= 3);
2019 g_assert(size
>= 2);
2021 /* The pair must be single-copy atomic for the doubleword. */
2022 memop
|= MO_64
| MO_ALIGN
;
2023 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2024 if (s
->be_data
== MO_LE
) {
2025 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2026 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2028 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2029 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2032 /* The pair must be single-copy atomic for *each* doubleword, not
2033 the entire quadword, however it must be quadword aligned. */
2035 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2036 memop
| MO_ALIGN_16
);
2038 TCGv_i64 addr2
= tcg_temp_new_i64();
2039 tcg_gen_addi_i64(addr2
, addr
, 8);
2040 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2041 tcg_temp_free_i64(addr2
);
2043 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2044 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2047 memop
|= size
| MO_ALIGN
;
2048 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2049 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2051 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2054 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2055 TCGv_i64 addr
, int size
, int is_pair
)
2057 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2058 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2061 * [addr + datasize] = {Rt2};
2067 * env->exclusive_addr = -1;
2069 TCGLabel
*fail_label
= gen_new_label();
2070 TCGLabel
*done_label
= gen_new_label();
2073 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2075 tmp
= tcg_temp_new_i64();
2078 if (s
->be_data
== MO_LE
) {
2079 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2081 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2083 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2084 cpu_exclusive_val
, tmp
,
2086 MO_64
| MO_ALIGN
| s
->be_data
);
2087 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2088 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2089 if (!HAVE_CMPXCHG128
) {
2090 gen_helper_exit_atomic(cpu_env
);
2091 s
->base
.is_jmp
= DISAS_NORETURN
;
2092 } else if (s
->be_data
== MO_LE
) {
2093 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2098 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2103 } else if (s
->be_data
== MO_LE
) {
2104 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2105 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2107 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2108 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2111 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2112 cpu_reg(s
, rt
), get_mem_index(s
),
2113 size
| MO_ALIGN
| s
->be_data
);
2114 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2116 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2117 tcg_temp_free_i64(tmp
);
2118 tcg_gen_br(done_label
);
2120 gen_set_label(fail_label
);
2121 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2122 gen_set_label(done_label
);
2123 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2126 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2129 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2130 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2131 int memidx
= get_mem_index(s
);
2132 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2135 gen_check_sp_alignment(s
);
2137 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2138 size
| MO_ALIGN
| s
->be_data
);
2141 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2144 TCGv_i64 s1
= cpu_reg(s
, rs
);
2145 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2146 TCGv_i64 t1
= cpu_reg(s
, rt
);
2147 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2148 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2149 int memidx
= get_mem_index(s
);
2152 gen_check_sp_alignment(s
);
2156 TCGv_i64 cmp
= tcg_temp_new_i64();
2157 TCGv_i64 val
= tcg_temp_new_i64();
2159 if (s
->be_data
== MO_LE
) {
2160 tcg_gen_concat32_i64(val
, t1
, t2
);
2161 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2163 tcg_gen_concat32_i64(val
, t2
, t1
);
2164 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2167 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2168 MO_64
| MO_ALIGN
| s
->be_data
);
2169 tcg_temp_free_i64(val
);
2171 if (s
->be_data
== MO_LE
) {
2172 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2174 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2176 tcg_temp_free_i64(cmp
);
2177 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2178 if (HAVE_CMPXCHG128
) {
2179 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2180 if (s
->be_data
== MO_LE
) {
2181 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2183 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2185 tcg_temp_free_i32(tcg_rs
);
2187 gen_helper_exit_atomic(cpu_env
);
2188 s
->base
.is_jmp
= DISAS_NORETURN
;
2191 TCGv_i64 d1
= tcg_temp_new_i64();
2192 TCGv_i64 d2
= tcg_temp_new_i64();
2193 TCGv_i64 a2
= tcg_temp_new_i64();
2194 TCGv_i64 c1
= tcg_temp_new_i64();
2195 TCGv_i64 c2
= tcg_temp_new_i64();
2196 TCGv_i64 zero
= tcg_const_i64(0);
2198 /* Load the two words, in memory order. */
2199 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2200 MO_64
| MO_ALIGN_16
| s
->be_data
);
2201 tcg_gen_addi_i64(a2
, addr
, 8);
2202 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2204 /* Compare the two words, also in memory order. */
2205 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2206 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2207 tcg_gen_and_i64(c2
, c2
, c1
);
2209 /* If compare equal, write back new data, else write back old data. */
2210 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2211 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2212 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2213 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2214 tcg_temp_free_i64(a2
);
2215 tcg_temp_free_i64(c1
);
2216 tcg_temp_free_i64(c2
);
2217 tcg_temp_free_i64(zero
);
2219 /* Write back the data from memory to Rs. */
2220 tcg_gen_mov_i64(s1
, d1
);
2221 tcg_gen_mov_i64(s2
, d2
);
2222 tcg_temp_free_i64(d1
);
2223 tcg_temp_free_i64(d2
);
2227 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2228 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2230 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2232 int opc0
= extract32(opc
, 0, 1);
2236 regsize
= opc0
? 32 : 64;
2238 regsize
= size
== 3 ? 64 : 32;
2240 return regsize
== 64;
2243 /* Load/store exclusive
2245 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2246 * +-----+-------------+----+---+----+------+----+-------+------+------+
2247 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2248 * +-----+-------------+----+---+----+------+----+-------+------+------+
2250 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2251 * L: 0 -> store, 1 -> load
2252 * o2: 0 -> exclusive, 1 -> not
2253 * o1: 0 -> single register, 1 -> register pair
2254 * o0: 1 -> load-acquire/store-release, 0 -> not
2256 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2258 int rt
= extract32(insn
, 0, 5);
2259 int rn
= extract32(insn
, 5, 5);
2260 int rt2
= extract32(insn
, 10, 5);
2261 int rs
= extract32(insn
, 16, 5);
2262 int is_lasr
= extract32(insn
, 15, 1);
2263 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2264 int size
= extract32(insn
, 30, 2);
2267 switch (o2_L_o1_o0
) {
2268 case 0x0: /* STXR */
2269 case 0x1: /* STLXR */
2271 gen_check_sp_alignment(s
);
2274 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2276 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2277 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2280 case 0x4: /* LDXR */
2281 case 0x5: /* LDAXR */
2283 gen_check_sp_alignment(s
);
2285 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2287 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2289 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2293 case 0x9: /* STLR */
2294 /* Generate ISS for non-exclusive accesses including LASR. */
2296 gen_check_sp_alignment(s
);
2298 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2299 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2300 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2301 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2304 case 0xd: /* LDAR */
2305 /* Generate ISS for non-exclusive accesses including LASR. */
2307 gen_check_sp_alignment(s
);
2309 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2310 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2311 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2312 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2315 case 0x2: case 0x3: /* CASP / STXP */
2316 if (size
& 2) { /* STXP / STLXP */
2318 gen_check_sp_alignment(s
);
2321 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2323 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2324 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2328 && ((rt
| rs
) & 1) == 0
2329 && dc_isar_feature(aa64_atomics
, s
)) {
2331 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2336 case 0x6: case 0x7: /* CASPA / LDXP */
2337 if (size
& 2) { /* LDXP / LDAXP */
2339 gen_check_sp_alignment(s
);
2341 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2343 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2345 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2350 && ((rt
| rs
) & 1) == 0
2351 && dc_isar_feature(aa64_atomics
, s
)) {
2352 /* CASPA / CASPAL */
2353 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2359 case 0xb: /* CASL */
2360 case 0xe: /* CASA */
2361 case 0xf: /* CASAL */
2362 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2363 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2368 unallocated_encoding(s
);
2372 * Load register (literal)
2374 * 31 30 29 27 26 25 24 23 5 4 0
2375 * +-----+-------+---+-----+-------------------+-------+
2376 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2377 * +-----+-------+---+-----+-------------------+-------+
2379 * V: 1 -> vector (simd/fp)
2380 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2381 * 10-> 32 bit signed, 11 -> prefetch
2382 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2384 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2386 int rt
= extract32(insn
, 0, 5);
2387 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2388 bool is_vector
= extract32(insn
, 26, 1);
2389 int opc
= extract32(insn
, 30, 2);
2390 bool is_signed
= false;
2392 TCGv_i64 tcg_rt
, tcg_addr
;
2396 unallocated_encoding(s
);
2400 if (!fp_access_check(s
)) {
2405 /* PRFM (literal) : prefetch */
2408 size
= 2 + extract32(opc
, 0, 1);
2409 is_signed
= extract32(opc
, 1, 1);
2412 tcg_rt
= cpu_reg(s
, rt
);
2414 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2416 do_fp_ld(s
, rt
, tcg_addr
, size
);
2418 /* Only unsigned 32bit loads target 32bit registers. */
2419 bool iss_sf
= opc
!= 0;
2421 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2422 true, rt
, iss_sf
, false);
2424 tcg_temp_free_i64(tcg_addr
);
2428 * LDNP (Load Pair - non-temporal hint)
2429 * LDP (Load Pair - non vector)
2430 * LDPSW (Load Pair Signed Word - non vector)
2431 * STNP (Store Pair - non-temporal hint)
2432 * STP (Store Pair - non vector)
2433 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2434 * LDP (Load Pair of SIMD&FP)
2435 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2436 * STP (Store Pair of SIMD&FP)
2438 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2439 * +-----+-------+---+---+-------+---+-----------------------------+
2440 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2441 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2443 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2445 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2446 * V: 0 -> GPR, 1 -> Vector
2447 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2448 * 10 -> signed offset, 11 -> pre-index
2449 * L: 0 -> Store 1 -> Load
2451 * Rt, Rt2 = GPR or SIMD registers to be stored
2452 * Rn = general purpose register containing address
2453 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2455 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2457 int rt
= extract32(insn
, 0, 5);
2458 int rn
= extract32(insn
, 5, 5);
2459 int rt2
= extract32(insn
, 10, 5);
2460 uint64_t offset
= sextract64(insn
, 15, 7);
2461 int index
= extract32(insn
, 23, 2);
2462 bool is_vector
= extract32(insn
, 26, 1);
2463 bool is_load
= extract32(insn
, 22, 1);
2464 int opc
= extract32(insn
, 30, 2);
2466 bool is_signed
= false;
2467 bool postindex
= false;
2470 TCGv_i64 tcg_addr
; /* calculated address */
2474 unallocated_encoding(s
);
2481 size
= 2 + extract32(opc
, 1, 1);
2482 is_signed
= extract32(opc
, 0, 1);
2483 if (!is_load
&& is_signed
) {
2484 unallocated_encoding(s
);
2490 case 1: /* post-index */
2495 /* signed offset with "non-temporal" hint. Since we don't emulate
2496 * caches we don't care about hints to the cache system about
2497 * data access patterns, and handle this identically to plain
2501 /* There is no non-temporal-hint version of LDPSW */
2502 unallocated_encoding(s
);
2507 case 2: /* signed offset, rn not updated */
2510 case 3: /* pre-index */
2516 if (is_vector
&& !fp_access_check(s
)) {
2523 gen_check_sp_alignment(s
);
2526 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2529 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2534 do_fp_ld(s
, rt
, tcg_addr
, size
);
2536 do_fp_st(s
, rt
, tcg_addr
, size
);
2538 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2540 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2542 do_fp_st(s
, rt2
, tcg_addr
, size
);
2545 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2546 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2549 TCGv_i64 tmp
= tcg_temp_new_i64();
2551 /* Do not modify tcg_rt before recognizing any exception
2552 * from the second load.
2554 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2555 false, 0, false, false);
2556 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2557 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2558 false, 0, false, false);
2560 tcg_gen_mov_i64(tcg_rt
, tmp
);
2561 tcg_temp_free_i64(tmp
);
2563 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2564 false, 0, false, false);
2565 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2566 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2567 false, 0, false, false);
2573 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2575 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2577 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2582 * Load/store (immediate post-indexed)
2583 * Load/store (immediate pre-indexed)
2584 * Load/store (unscaled immediate)
2586 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2587 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2588 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2589 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2591 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2593 * V = 0 -> non-vector
2594 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2595 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2597 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2603 int rn
= extract32(insn
, 5, 5);
2604 int imm9
= sextract32(insn
, 12, 9);
2605 int idx
= extract32(insn
, 10, 2);
2606 bool is_signed
= false;
2607 bool is_store
= false;
2608 bool is_extended
= false;
2609 bool is_unpriv
= (idx
== 2);
2610 bool iss_valid
= !is_vector
;
2617 size
|= (opc
& 2) << 1;
2618 if (size
> 4 || is_unpriv
) {
2619 unallocated_encoding(s
);
2622 is_store
= ((opc
& 1) == 0);
2623 if (!fp_access_check(s
)) {
2627 if (size
== 3 && opc
== 2) {
2628 /* PRFM - prefetch */
2630 unallocated_encoding(s
);
2635 if (opc
== 3 && size
> 1) {
2636 unallocated_encoding(s
);
2639 is_store
= (opc
== 0);
2640 is_signed
= extract32(opc
, 1, 1);
2641 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2659 g_assert_not_reached();
2663 gen_check_sp_alignment(s
);
2665 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2668 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2673 do_fp_st(s
, rt
, tcg_addr
, size
);
2675 do_fp_ld(s
, rt
, tcg_addr
, size
);
2678 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2679 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2680 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2683 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2684 iss_valid
, rt
, iss_sf
, false);
2686 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2687 is_signed
, is_extended
, memidx
,
2688 iss_valid
, rt
, iss_sf
, false);
2693 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2695 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2697 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2702 * Load/store (register offset)
2704 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2705 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2706 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2707 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2710 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2711 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2713 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2714 * opc<0>: 0 -> store, 1 -> load
2715 * V: 1 -> vector/simd
2716 * opt: extend encoding (see DecodeRegExtend)
2717 * S: if S=1 then scale (essentially index by sizeof(size))
2718 * Rt: register to transfer into/out of
2719 * Rn: address register or SP for base
2720 * Rm: offset register or ZR for offset
2722 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2728 int rn
= extract32(insn
, 5, 5);
2729 int shift
= extract32(insn
, 12, 1);
2730 int rm
= extract32(insn
, 16, 5);
2731 int opt
= extract32(insn
, 13, 3);
2732 bool is_signed
= false;
2733 bool is_store
= false;
2734 bool is_extended
= false;
2739 if (extract32(opt
, 1, 1) == 0) {
2740 unallocated_encoding(s
);
2745 size
|= (opc
& 2) << 1;
2747 unallocated_encoding(s
);
2750 is_store
= !extract32(opc
, 0, 1);
2751 if (!fp_access_check(s
)) {
2755 if (size
== 3 && opc
== 2) {
2756 /* PRFM - prefetch */
2759 if (opc
== 3 && size
> 1) {
2760 unallocated_encoding(s
);
2763 is_store
= (opc
== 0);
2764 is_signed
= extract32(opc
, 1, 1);
2765 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2769 gen_check_sp_alignment(s
);
2771 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2773 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2774 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2776 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2780 do_fp_st(s
, rt
, tcg_addr
, size
);
2782 do_fp_ld(s
, rt
, tcg_addr
, size
);
2785 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2786 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2788 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2789 true, rt
, iss_sf
, false);
2791 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2792 is_signed
, is_extended
,
2793 true, rt
, iss_sf
, false);
2799 * Load/store (unsigned immediate)
2801 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2802 * +----+-------+---+-----+-----+------------+-------+------+
2803 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2804 * +----+-------+---+-----+-----+------------+-------+------+
2807 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2808 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2810 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2811 * opc<0>: 0 -> store, 1 -> load
2812 * Rn: base address register (inc SP)
2813 * Rt: target register
2815 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2821 int rn
= extract32(insn
, 5, 5);
2822 unsigned int imm12
= extract32(insn
, 10, 12);
2823 unsigned int offset
;
2828 bool is_signed
= false;
2829 bool is_extended
= false;
2832 size
|= (opc
& 2) << 1;
2834 unallocated_encoding(s
);
2837 is_store
= !extract32(opc
, 0, 1);
2838 if (!fp_access_check(s
)) {
2842 if (size
== 3 && opc
== 2) {
2843 /* PRFM - prefetch */
2846 if (opc
== 3 && size
> 1) {
2847 unallocated_encoding(s
);
2850 is_store
= (opc
== 0);
2851 is_signed
= extract32(opc
, 1, 1);
2852 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2856 gen_check_sp_alignment(s
);
2858 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2859 offset
= imm12
<< size
;
2860 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2864 do_fp_st(s
, rt
, tcg_addr
, size
);
2866 do_fp_ld(s
, rt
, tcg_addr
, size
);
2869 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2870 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2872 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2873 true, rt
, iss_sf
, false);
2875 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2876 true, rt
, iss_sf
, false);
2881 /* Atomic memory operations
2883 * 31 30 27 26 24 22 21 16 15 12 10 5 0
2884 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
2885 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
2886 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
2888 * Rt: the result register
2889 * Rn: base address or SP
2890 * Rs: the source register for the operation
2891 * V: vector flag (always 0 as of v8.3)
2895 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
2896 int size
, int rt
, bool is_vector
)
2898 int rs
= extract32(insn
, 16, 5);
2899 int rn
= extract32(insn
, 5, 5);
2900 int o3_opc
= extract32(insn
, 12, 4);
2901 TCGv_i64 tcg_rn
, tcg_rs
;
2902 AtomicThreeOpFn
*fn
;
2904 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
2905 unallocated_encoding(s
);
2909 case 000: /* LDADD */
2910 fn
= tcg_gen_atomic_fetch_add_i64
;
2912 case 001: /* LDCLR */
2913 fn
= tcg_gen_atomic_fetch_and_i64
;
2915 case 002: /* LDEOR */
2916 fn
= tcg_gen_atomic_fetch_xor_i64
;
2918 case 003: /* LDSET */
2919 fn
= tcg_gen_atomic_fetch_or_i64
;
2921 case 004: /* LDSMAX */
2922 fn
= tcg_gen_atomic_fetch_smax_i64
;
2924 case 005: /* LDSMIN */
2925 fn
= tcg_gen_atomic_fetch_smin_i64
;
2927 case 006: /* LDUMAX */
2928 fn
= tcg_gen_atomic_fetch_umax_i64
;
2930 case 007: /* LDUMIN */
2931 fn
= tcg_gen_atomic_fetch_umin_i64
;
2934 fn
= tcg_gen_atomic_xchg_i64
;
2937 unallocated_encoding(s
);
2942 gen_check_sp_alignment(s
);
2944 tcg_rn
= cpu_reg_sp(s
, rn
);
2945 tcg_rs
= read_cpu_reg(s
, rs
, true);
2947 if (o3_opc
== 1) { /* LDCLR */
2948 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
2951 /* The tcg atomic primitives are all full barriers. Therefore we
2952 * can ignore the Acquire and Release bits of this instruction.
2954 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
2955 s
->be_data
| size
| MO_ALIGN
);
2958 /* Load/store register (all forms) */
2959 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2961 int rt
= extract32(insn
, 0, 5);
2962 int opc
= extract32(insn
, 22, 2);
2963 bool is_vector
= extract32(insn
, 26, 1);
2964 int size
= extract32(insn
, 30, 2);
2966 switch (extract32(insn
, 24, 2)) {
2968 if (extract32(insn
, 21, 1) == 0) {
2969 /* Load/store register (unscaled immediate)
2970 * Load/store immediate pre/post-indexed
2971 * Load/store register unprivileged
2973 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2976 switch (extract32(insn
, 10, 2)) {
2978 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
2981 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2986 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2989 unallocated_encoding(s
);
2992 /* AdvSIMD load/store multiple structures
2994 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2995 * +---+---+---------------+---+-------------+--------+------+------+------+
2996 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2997 * +---+---+---------------+---+-------------+--------+------+------+------+
2999 * AdvSIMD load/store multiple structures (post-indexed)
3001 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3002 * +---+---+---------------+---+---+---------+--------+------+------+------+
3003 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3004 * +---+---+---------------+---+---+---------+--------+------+------+------+
3006 * Rt: first (or only) SIMD&FP register to be transferred
3007 * Rn: base address or SP
3008 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3010 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3012 int rt
= extract32(insn
, 0, 5);
3013 int rn
= extract32(insn
, 5, 5);
3014 int size
= extract32(insn
, 10, 2);
3015 int opcode
= extract32(insn
, 12, 4);
3016 bool is_store
= !extract32(insn
, 22, 1);
3017 bool is_postidx
= extract32(insn
, 23, 1);
3018 bool is_q
= extract32(insn
, 30, 1);
3019 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3020 TCGMemOp endian
= s
->be_data
;
3022 int ebytes
; /* bytes per element */
3023 int elements
; /* elements per vector */
3024 int rpt
; /* num iterations */
3025 int selem
; /* structure elements */
3028 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3029 unallocated_encoding(s
);
3033 /* From the shared decode logic */
3064 unallocated_encoding(s
);
3068 if (size
== 3 && !is_q
&& selem
!= 1) {
3070 unallocated_encoding(s
);
3074 if (!fp_access_check(s
)) {
3079 gen_check_sp_alignment(s
);
3082 /* For our purposes, bytes are always little-endian. */
3087 /* Consecutive little-endian elements from a single register
3088 * can be promoted to a larger little-endian operation.
3090 if (selem
== 1 && endian
== MO_LE
) {
3094 elements
= (is_q
? 16 : 8) / ebytes
;
3096 tcg_rn
= cpu_reg_sp(s
, rn
);
3097 tcg_addr
= tcg_temp_new_i64();
3098 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3099 tcg_ebytes
= tcg_const_i64(ebytes
);
3101 for (r
= 0; r
< rpt
; r
++) {
3103 for (e
= 0; e
< elements
; e
++) {
3105 for (xs
= 0; xs
< selem
; xs
++) {
3106 int tt
= (rt
+ r
+ xs
) % 32;
3108 do_vec_st(s
, tt
, e
, tcg_addr
, size
, endian
);
3110 do_vec_ld(s
, tt
, e
, tcg_addr
, size
, endian
);
3112 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3118 /* For non-quad operations, setting a slice of the low
3119 * 64 bits of the register clears the high 64 bits (in
3120 * the ARM ARM pseudocode this is implicit in the fact
3121 * that 'rval' is a 64 bit wide variable).
3122 * For quad operations, we might still need to zero the
3125 for (r
= 0; r
< rpt
* selem
; r
++) {
3126 int tt
= (rt
+ r
) % 32;
3127 clear_vec_high(s
, is_q
, tt
);
3132 int rm
= extract32(insn
, 16, 5);
3134 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3136 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3139 tcg_temp_free_i64(tcg_ebytes
);
3140 tcg_temp_free_i64(tcg_addr
);
3143 /* AdvSIMD load/store single structure
3145 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3146 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3147 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3148 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3150 * AdvSIMD load/store single structure (post-indexed)
3152 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3153 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3154 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3155 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3157 * Rt: first (or only) SIMD&FP register to be transferred
3158 * Rn: base address or SP
3159 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3160 * index = encoded in Q:S:size dependent on size
3162 * lane_size = encoded in R, opc
3163 * transfer width = encoded in opc, S, size
3165 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3167 int rt
= extract32(insn
, 0, 5);
3168 int rn
= extract32(insn
, 5, 5);
3169 int size
= extract32(insn
, 10, 2);
3170 int S
= extract32(insn
, 12, 1);
3171 int opc
= extract32(insn
, 13, 3);
3172 int R
= extract32(insn
, 21, 1);
3173 int is_load
= extract32(insn
, 22, 1);
3174 int is_postidx
= extract32(insn
, 23, 1);
3175 int is_q
= extract32(insn
, 30, 1);
3177 int scale
= extract32(opc
, 1, 2);
3178 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3179 bool replicate
= false;
3180 int index
= is_q
<< 3 | S
<< 2 | size
;
3182 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3186 if (!is_load
|| S
) {
3187 unallocated_encoding(s
);
3196 if (extract32(size
, 0, 1)) {
3197 unallocated_encoding(s
);
3203 if (extract32(size
, 1, 1)) {
3204 unallocated_encoding(s
);
3207 if (!extract32(size
, 0, 1)) {
3211 unallocated_encoding(s
);
3219 g_assert_not_reached();
3222 if (!fp_access_check(s
)) {
3226 ebytes
= 1 << scale
;
3229 gen_check_sp_alignment(s
);
3232 tcg_rn
= cpu_reg_sp(s
, rn
);
3233 tcg_addr
= tcg_temp_new_i64();
3234 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3235 tcg_ebytes
= tcg_const_i64(ebytes
);
3237 for (xs
= 0; xs
< selem
; xs
++) {
3239 /* Load and replicate to all elements */
3240 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3242 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3243 get_mem_index(s
), s
->be_data
+ scale
);
3244 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3245 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3247 tcg_temp_free_i64(tcg_tmp
);
3249 /* Load/store one element per register */
3251 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3253 do_vec_st(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3256 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3261 int rm
= extract32(insn
, 16, 5);
3263 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3265 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3268 tcg_temp_free_i64(tcg_ebytes
);
3269 tcg_temp_free_i64(tcg_addr
);
3272 /* Loads and stores */
3273 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3275 switch (extract32(insn
, 24, 6)) {
3276 case 0x08: /* Load/store exclusive */
3277 disas_ldst_excl(s
, insn
);
3279 case 0x18: case 0x1c: /* Load register (literal) */
3280 disas_ld_lit(s
, insn
);
3282 case 0x28: case 0x29:
3283 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3284 disas_ldst_pair(s
, insn
);
3286 case 0x38: case 0x39:
3287 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3288 disas_ldst_reg(s
, insn
);
3290 case 0x0c: /* AdvSIMD load/store multiple structures */
3291 disas_ldst_multiple_struct(s
, insn
);
3293 case 0x0d: /* AdvSIMD load/store single structure */
3294 disas_ldst_single_struct(s
, insn
);
3297 unallocated_encoding(s
);
3302 /* PC-rel. addressing
3303 * 31 30 29 28 24 23 5 4 0
3304 * +----+-------+-----------+-------------------+------+
3305 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3306 * +----+-------+-----------+-------------------+------+
3308 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3310 unsigned int page
, rd
;
3314 page
= extract32(insn
, 31, 1);
3315 /* SignExtend(immhi:immlo) -> offset */
3316 offset
= sextract64(insn
, 5, 19);
3317 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3318 rd
= extract32(insn
, 0, 5);
3322 /* ADRP (page based) */
3327 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3331 * Add/subtract (immediate)
3333 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3334 * +--+--+--+-----------+-----+-------------+-----+-----+
3335 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3336 * +--+--+--+-----------+-----+-------------+-----+-----+
3338 * sf: 0 -> 32bit, 1 -> 64bit
3339 * op: 0 -> add , 1 -> sub
3341 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3343 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3345 int rd
= extract32(insn
, 0, 5);
3346 int rn
= extract32(insn
, 5, 5);
3347 uint64_t imm
= extract32(insn
, 10, 12);
3348 int shift
= extract32(insn
, 22, 2);
3349 bool setflags
= extract32(insn
, 29, 1);
3350 bool sub_op
= extract32(insn
, 30, 1);
3351 bool is_64bit
= extract32(insn
, 31, 1);
3353 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3354 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3355 TCGv_i64 tcg_result
;
3364 unallocated_encoding(s
);
3368 tcg_result
= tcg_temp_new_i64();
3371 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3373 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3376 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3378 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3380 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3382 tcg_temp_free_i64(tcg_imm
);
3386 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3388 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3391 tcg_temp_free_i64(tcg_result
);
3394 /* The input should be a value in the bottom e bits (with higher
3395 * bits zero); returns that value replicated into every element
3396 * of size e in a 64 bit integer.
3398 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3408 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3409 static inline uint64_t bitmask64(unsigned int length
)
3411 assert(length
> 0 && length
<= 64);
3412 return ~0ULL >> (64 - length
);
3415 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3416 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3417 * value (ie should cause a guest UNDEF exception), and true if they are
3418 * valid, in which case the decoded bit pattern is written to result.
3420 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3421 unsigned int imms
, unsigned int immr
)
3424 unsigned e
, levels
, s
, r
;
3427 assert(immn
< 2 && imms
< 64 && immr
< 64);
3429 /* The bit patterns we create here are 64 bit patterns which
3430 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3431 * 64 bits each. Each element contains the same value: a run
3432 * of between 1 and e-1 non-zero bits, rotated within the
3433 * element by between 0 and e-1 bits.
3435 * The element size and run length are encoded into immn (1 bit)
3436 * and imms (6 bits) as follows:
3437 * 64 bit elements: immn = 1, imms = <length of run - 1>
3438 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3439 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3440 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3441 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3442 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3443 * Notice that immn = 0, imms = 11111x is the only combination
3444 * not covered by one of the above options; this is reserved.
3445 * Further, <length of run - 1> all-ones is a reserved pattern.
3447 * In all cases the rotation is by immr % e (and immr is 6 bits).
3450 /* First determine the element size */
3451 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3453 /* This is the immn == 0, imms == 0x11111x case */
3463 /* <length of run - 1> mustn't be all-ones. */
3467 /* Create the value of one element: s+1 set bits rotated
3468 * by r within the element (which is e bits wide)...
3470 mask
= bitmask64(s
+ 1);
3472 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3473 mask
&= bitmask64(e
);
3475 /* ...then replicate the element over the whole 64 bit value */
3476 mask
= bitfield_replicate(mask
, e
);
3481 /* Logical (immediate)
3482 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3483 * +----+-----+-------------+---+------+------+------+------+
3484 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3485 * +----+-----+-------------+---+------+------+------+------+
3487 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3489 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3490 TCGv_i64 tcg_rd
, tcg_rn
;
3492 bool is_and
= false;
3494 sf
= extract32(insn
, 31, 1);
3495 opc
= extract32(insn
, 29, 2);
3496 is_n
= extract32(insn
, 22, 1);
3497 immr
= extract32(insn
, 16, 6);
3498 imms
= extract32(insn
, 10, 6);
3499 rn
= extract32(insn
, 5, 5);
3500 rd
= extract32(insn
, 0, 5);
3503 unallocated_encoding(s
);
3507 if (opc
== 0x3) { /* ANDS */
3508 tcg_rd
= cpu_reg(s
, rd
);
3510 tcg_rd
= cpu_reg_sp(s
, rd
);
3512 tcg_rn
= cpu_reg(s
, rn
);
3514 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3515 /* some immediate field values are reserved */
3516 unallocated_encoding(s
);
3521 wmask
&= 0xffffffff;
3525 case 0x3: /* ANDS */
3527 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3531 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3534 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3537 assert(FALSE
); /* must handle all above */
3541 if (!sf
&& !is_and
) {
3542 /* zero extend final result; we know we can skip this for AND
3543 * since the immediate had the high 32 bits clear.
3545 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3548 if (opc
== 3) { /* ANDS */
3549 gen_logic_CC(sf
, tcg_rd
);
3554 * Move wide (immediate)
3556 * 31 30 29 28 23 22 21 20 5 4 0
3557 * +--+-----+-------------+-----+----------------+------+
3558 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3559 * +--+-----+-------------+-----+----------------+------+
3561 * sf: 0 -> 32 bit, 1 -> 64 bit
3562 * opc: 00 -> N, 10 -> Z, 11 -> K
3563 * hw: shift/16 (0,16, and sf only 32, 48)
3565 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3567 int rd
= extract32(insn
, 0, 5);
3568 uint64_t imm
= extract32(insn
, 5, 16);
3569 int sf
= extract32(insn
, 31, 1);
3570 int opc
= extract32(insn
, 29, 2);
3571 int pos
= extract32(insn
, 21, 2) << 4;
3572 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3575 if (!sf
&& (pos
>= 32)) {
3576 unallocated_encoding(s
);
3590 tcg_gen_movi_i64(tcg_rd
, imm
);
3593 tcg_imm
= tcg_const_i64(imm
);
3594 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3595 tcg_temp_free_i64(tcg_imm
);
3597 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3601 unallocated_encoding(s
);
3607 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3608 * +----+-----+-------------+---+------+------+------+------+
3609 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3610 * +----+-----+-------------+---+------+------+------+------+
3612 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3614 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3615 TCGv_i64 tcg_rd
, tcg_tmp
;
3617 sf
= extract32(insn
, 31, 1);
3618 opc
= extract32(insn
, 29, 2);
3619 n
= extract32(insn
, 22, 1);
3620 ri
= extract32(insn
, 16, 6);
3621 si
= extract32(insn
, 10, 6);
3622 rn
= extract32(insn
, 5, 5);
3623 rd
= extract32(insn
, 0, 5);
3624 bitsize
= sf
? 64 : 32;
3626 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3627 unallocated_encoding(s
);
3631 tcg_rd
= cpu_reg(s
, rd
);
3633 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3634 to be smaller than bitsize, we'll never reference data outside the
3635 low 32-bits anyway. */
3636 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3638 /* Recognize simple(r) extractions. */
3640 /* Wd<s-r:0> = Wn<s:r> */
3641 len
= (si
- ri
) + 1;
3642 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3643 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3645 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3646 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3649 /* opc == 1, BXFIL fall through to deposit */
3650 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3653 /* Handle the ri > si case with a deposit
3654 * Wd<32+s-r,32-r> = Wn<s:0>
3657 pos
= (bitsize
- ri
) & (bitsize
- 1);
3660 if (opc
== 0 && len
< ri
) {
3661 /* SBFM: sign extend the destination field from len to fill
3662 the balance of the word. Let the deposit below insert all
3663 of those sign bits. */
3664 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3668 if (opc
== 1) { /* BFM, BXFIL */
3669 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3671 /* SBFM or UBFM: We start with zero, and we haven't modified
3672 any bits outside bitsize, therefore the zero-extension
3673 below is unneeded. */
3674 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3679 if (!sf
) { /* zero extend final result */
3680 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3685 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3686 * +----+------+-------------+---+----+------+--------+------+------+
3687 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3688 * +----+------+-------------+---+----+------+--------+------+------+
3690 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3692 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3694 sf
= extract32(insn
, 31, 1);
3695 n
= extract32(insn
, 22, 1);
3696 rm
= extract32(insn
, 16, 5);
3697 imm
= extract32(insn
, 10, 6);
3698 rn
= extract32(insn
, 5, 5);
3699 rd
= extract32(insn
, 0, 5);
3700 op21
= extract32(insn
, 29, 2);
3701 op0
= extract32(insn
, 21, 1);
3702 bitsize
= sf
? 64 : 32;
3704 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3705 unallocated_encoding(s
);
3707 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3709 tcg_rd
= cpu_reg(s
, rd
);
3711 if (unlikely(imm
== 0)) {
3712 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3713 * so an extract from bit 0 is a special case.
3716 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3718 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3720 } else if (rm
== rn
) { /* ROR */
3721 tcg_rm
= cpu_reg(s
, rm
);
3723 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3725 TCGv_i32 tmp
= tcg_temp_new_i32();
3726 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3727 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3728 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3729 tcg_temp_free_i32(tmp
);
3732 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3733 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3734 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3735 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3736 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3738 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3744 /* Data processing - immediate */
3745 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3747 switch (extract32(insn
, 23, 6)) {
3748 case 0x20: case 0x21: /* PC-rel. addressing */
3749 disas_pc_rel_adr(s
, insn
);
3751 case 0x22: case 0x23: /* Add/subtract (immediate) */
3752 disas_add_sub_imm(s
, insn
);
3754 case 0x24: /* Logical (immediate) */
3755 disas_logic_imm(s
, insn
);
3757 case 0x25: /* Move wide (immediate) */
3758 disas_movw_imm(s
, insn
);
3760 case 0x26: /* Bitfield */
3761 disas_bitfield(s
, insn
);
3763 case 0x27: /* Extract */
3764 disas_extract(s
, insn
);
3767 unallocated_encoding(s
);
3772 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3773 * Note that it is the caller's responsibility to ensure that the
3774 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3775 * mandated semantics for out of range shifts.
3777 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3778 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3780 switch (shift_type
) {
3781 case A64_SHIFT_TYPE_LSL
:
3782 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3784 case A64_SHIFT_TYPE_LSR
:
3785 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3787 case A64_SHIFT_TYPE_ASR
:
3789 tcg_gen_ext32s_i64(dst
, src
);
3791 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3793 case A64_SHIFT_TYPE_ROR
:
3795 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3798 t0
= tcg_temp_new_i32();
3799 t1
= tcg_temp_new_i32();
3800 tcg_gen_extrl_i64_i32(t0
, src
);
3801 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3802 tcg_gen_rotr_i32(t0
, t0
, t1
);
3803 tcg_gen_extu_i32_i64(dst
, t0
);
3804 tcg_temp_free_i32(t0
);
3805 tcg_temp_free_i32(t1
);
3809 assert(FALSE
); /* all shift types should be handled */
3813 if (!sf
) { /* zero extend final result */
3814 tcg_gen_ext32u_i64(dst
, dst
);
3818 /* Shift a TCGv src by immediate, put result in dst.
3819 * The shift amount must be in range (this should always be true as the
3820 * relevant instructions will UNDEF on bad shift immediates).
3822 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3823 enum a64_shift_type shift_type
, unsigned int shift_i
)
3825 assert(shift_i
< (sf
? 64 : 32));
3828 tcg_gen_mov_i64(dst
, src
);
3830 TCGv_i64 shift_const
;
3832 shift_const
= tcg_const_i64(shift_i
);
3833 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3834 tcg_temp_free_i64(shift_const
);
3838 /* Logical (shifted register)
3839 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3840 * +----+-----+-----------+-------+---+------+--------+------+------+
3841 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3842 * +----+-----+-----------+-------+---+------+--------+------+------+
3844 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3846 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3847 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3849 sf
= extract32(insn
, 31, 1);
3850 opc
= extract32(insn
, 29, 2);
3851 shift_type
= extract32(insn
, 22, 2);
3852 invert
= extract32(insn
, 21, 1);
3853 rm
= extract32(insn
, 16, 5);
3854 shift_amount
= extract32(insn
, 10, 6);
3855 rn
= extract32(insn
, 5, 5);
3856 rd
= extract32(insn
, 0, 5);
3858 if (!sf
&& (shift_amount
& (1 << 5))) {
3859 unallocated_encoding(s
);
3863 tcg_rd
= cpu_reg(s
, rd
);
3865 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3866 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3867 * register-register MOV and MVN, so it is worth special casing.
3869 tcg_rm
= cpu_reg(s
, rm
);
3871 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3873 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3877 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3879 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3885 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3888 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3891 tcg_rn
= cpu_reg(s
, rn
);
3893 switch (opc
| (invert
<< 2)) {
3896 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3899 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3902 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3906 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3909 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3912 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3920 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3924 gen_logic_CC(sf
, tcg_rd
);
3929 * Add/subtract (extended register)
3931 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3932 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3933 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3934 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3936 * sf: 0 -> 32bit, 1 -> 64bit
3937 * op: 0 -> add , 1 -> sub
3940 * option: extension type (see DecodeRegExtend)
3941 * imm3: optional shift to Rm
3943 * Rd = Rn + LSL(extend(Rm), amount)
3945 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3947 int rd
= extract32(insn
, 0, 5);
3948 int rn
= extract32(insn
, 5, 5);
3949 int imm3
= extract32(insn
, 10, 3);
3950 int option
= extract32(insn
, 13, 3);
3951 int rm
= extract32(insn
, 16, 5);
3952 bool setflags
= extract32(insn
, 29, 1);
3953 bool sub_op
= extract32(insn
, 30, 1);
3954 bool sf
= extract32(insn
, 31, 1);
3956 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3958 TCGv_i64 tcg_result
;
3961 unallocated_encoding(s
);
3965 /* non-flag setting ops may use SP */
3967 tcg_rd
= cpu_reg_sp(s
, rd
);
3969 tcg_rd
= cpu_reg(s
, rd
);
3971 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3973 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3974 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3976 tcg_result
= tcg_temp_new_i64();
3980 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3982 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3986 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3988 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3993 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3995 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3998 tcg_temp_free_i64(tcg_result
);
4002 * Add/subtract (shifted register)
4004 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4005 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4006 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4007 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4009 * sf: 0 -> 32bit, 1 -> 64bit
4010 * op: 0 -> add , 1 -> sub
4012 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4013 * imm6: Shift amount to apply to Rm before the add/sub
4015 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4017 int rd
= extract32(insn
, 0, 5);
4018 int rn
= extract32(insn
, 5, 5);
4019 int imm6
= extract32(insn
, 10, 6);
4020 int rm
= extract32(insn
, 16, 5);
4021 int shift_type
= extract32(insn
, 22, 2);
4022 bool setflags
= extract32(insn
, 29, 1);
4023 bool sub_op
= extract32(insn
, 30, 1);
4024 bool sf
= extract32(insn
, 31, 1);
4026 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4027 TCGv_i64 tcg_rn
, tcg_rm
;
4028 TCGv_i64 tcg_result
;
4030 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4031 unallocated_encoding(s
);
4035 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4036 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4038 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4040 tcg_result
= tcg_temp_new_i64();
4044 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4046 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4050 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4052 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4057 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4059 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4062 tcg_temp_free_i64(tcg_result
);
4065 /* Data-processing (3 source)
4067 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4068 * +--+------+-----------+------+------+----+------+------+------+
4069 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4070 * +--+------+-----------+------+------+----+------+------+------+
4072 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4074 int rd
= extract32(insn
, 0, 5);
4075 int rn
= extract32(insn
, 5, 5);
4076 int ra
= extract32(insn
, 10, 5);
4077 int rm
= extract32(insn
, 16, 5);
4078 int op_id
= (extract32(insn
, 29, 3) << 4) |
4079 (extract32(insn
, 21, 3) << 1) |
4080 extract32(insn
, 15, 1);
4081 bool sf
= extract32(insn
, 31, 1);
4082 bool is_sub
= extract32(op_id
, 0, 1);
4083 bool is_high
= extract32(op_id
, 2, 1);
4084 bool is_signed
= false;
4089 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4091 case 0x42: /* SMADDL */
4092 case 0x43: /* SMSUBL */
4093 case 0x44: /* SMULH */
4096 case 0x0: /* MADD (32bit) */
4097 case 0x1: /* MSUB (32bit) */
4098 case 0x40: /* MADD (64bit) */
4099 case 0x41: /* MSUB (64bit) */
4100 case 0x4a: /* UMADDL */
4101 case 0x4b: /* UMSUBL */
4102 case 0x4c: /* UMULH */
4105 unallocated_encoding(s
);
4110 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4111 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4112 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4113 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4116 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4118 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4121 tcg_temp_free_i64(low_bits
);
4125 tcg_op1
= tcg_temp_new_i64();
4126 tcg_op2
= tcg_temp_new_i64();
4127 tcg_tmp
= tcg_temp_new_i64();
4130 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4131 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4134 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4135 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4137 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4138 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4142 if (ra
== 31 && !is_sub
) {
4143 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4144 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4146 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4148 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4150 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4155 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4158 tcg_temp_free_i64(tcg_op1
);
4159 tcg_temp_free_i64(tcg_op2
);
4160 tcg_temp_free_i64(tcg_tmp
);
4163 /* Add/subtract (with carry)
4164 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4165 * +--+--+--+------------------------+------+---------+------+-----+
4166 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4167 * +--+--+--+------------------------+------+---------+------+-----+
4171 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4173 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4174 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4176 if (extract32(insn
, 10, 6) != 0) {
4177 unallocated_encoding(s
);
4181 sf
= extract32(insn
, 31, 1);
4182 op
= extract32(insn
, 30, 1);
4183 setflags
= extract32(insn
, 29, 1);
4184 rm
= extract32(insn
, 16, 5);
4185 rn
= extract32(insn
, 5, 5);
4186 rd
= extract32(insn
, 0, 5);
4188 tcg_rd
= cpu_reg(s
, rd
);
4189 tcg_rn
= cpu_reg(s
, rn
);
4192 tcg_y
= new_tmp_a64(s
);
4193 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4195 tcg_y
= cpu_reg(s
, rm
);
4199 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4201 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4205 /* Conditional compare (immediate / register)
4206 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4207 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4208 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4209 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4212 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4214 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4215 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4216 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4219 if (!extract32(insn
, 29, 1)) {
4220 unallocated_encoding(s
);
4223 if (insn
& (1 << 10 | 1 << 4)) {
4224 unallocated_encoding(s
);
4227 sf
= extract32(insn
, 31, 1);
4228 op
= extract32(insn
, 30, 1);
4229 is_imm
= extract32(insn
, 11, 1);
4230 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4231 cond
= extract32(insn
, 12, 4);
4232 rn
= extract32(insn
, 5, 5);
4233 nzcv
= extract32(insn
, 0, 4);
4235 /* Set T0 = !COND. */
4236 tcg_t0
= tcg_temp_new_i32();
4237 arm_test_cc(&c
, cond
);
4238 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4241 /* Load the arguments for the new comparison. */
4243 tcg_y
= new_tmp_a64(s
);
4244 tcg_gen_movi_i64(tcg_y
, y
);
4246 tcg_y
= cpu_reg(s
, y
);
4248 tcg_rn
= cpu_reg(s
, rn
);
4250 /* Set the flags for the new comparison. */
4251 tcg_tmp
= tcg_temp_new_i64();
4253 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4255 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4257 tcg_temp_free_i64(tcg_tmp
);
4259 /* If COND was false, force the flags to #nzcv. Compute two masks
4260 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4261 * For tcg hosts that support ANDC, we can make do with just T1.
4262 * In either case, allow the tcg optimizer to delete any unused mask.
4264 tcg_t1
= tcg_temp_new_i32();
4265 tcg_t2
= tcg_temp_new_i32();
4266 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4267 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4269 if (nzcv
& 8) { /* N */
4270 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4272 if (TCG_TARGET_HAS_andc_i32
) {
4273 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4275 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4278 if (nzcv
& 4) { /* Z */
4279 if (TCG_TARGET_HAS_andc_i32
) {
4280 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4282 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4285 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4287 if (nzcv
& 2) { /* C */
4288 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4290 if (TCG_TARGET_HAS_andc_i32
) {
4291 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4293 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4296 if (nzcv
& 1) { /* V */
4297 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4299 if (TCG_TARGET_HAS_andc_i32
) {
4300 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4302 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4305 tcg_temp_free_i32(tcg_t0
);
4306 tcg_temp_free_i32(tcg_t1
);
4307 tcg_temp_free_i32(tcg_t2
);
4310 /* Conditional select
4311 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4312 * +----+----+---+-----------------+------+------+-----+------+------+
4313 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4314 * +----+----+---+-----------------+------+------+-----+------+------+
4316 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4318 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4319 TCGv_i64 tcg_rd
, zero
;
4322 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4323 /* S == 1 or op2<1> == 1 */
4324 unallocated_encoding(s
);
4327 sf
= extract32(insn
, 31, 1);
4328 else_inv
= extract32(insn
, 30, 1);
4329 rm
= extract32(insn
, 16, 5);
4330 cond
= extract32(insn
, 12, 4);
4331 else_inc
= extract32(insn
, 10, 1);
4332 rn
= extract32(insn
, 5, 5);
4333 rd
= extract32(insn
, 0, 5);
4335 tcg_rd
= cpu_reg(s
, rd
);
4337 a64_test_cc(&c
, cond
);
4338 zero
= tcg_const_i64(0);
4340 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4342 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4344 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4347 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4348 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4349 if (else_inv
&& else_inc
) {
4350 tcg_gen_neg_i64(t_false
, t_false
);
4351 } else if (else_inv
) {
4352 tcg_gen_not_i64(t_false
, t_false
);
4353 } else if (else_inc
) {
4354 tcg_gen_addi_i64(t_false
, t_false
, 1);
4356 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4359 tcg_temp_free_i64(zero
);
4363 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4367 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4368 unsigned int rn
, unsigned int rd
)
4370 TCGv_i64 tcg_rd
, tcg_rn
;
4371 tcg_rd
= cpu_reg(s
, rd
);
4372 tcg_rn
= cpu_reg(s
, rn
);
4375 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4377 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4378 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4379 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4380 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4381 tcg_temp_free_i32(tcg_tmp32
);
4385 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4386 unsigned int rn
, unsigned int rd
)
4388 TCGv_i64 tcg_rd
, tcg_rn
;
4389 tcg_rd
= cpu_reg(s
, rd
);
4390 tcg_rn
= cpu_reg(s
, rn
);
4393 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4395 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4396 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4397 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4398 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4399 tcg_temp_free_i32(tcg_tmp32
);
4403 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4404 unsigned int rn
, unsigned int rd
)
4406 TCGv_i64 tcg_rd
, tcg_rn
;
4407 tcg_rd
= cpu_reg(s
, rd
);
4408 tcg_rn
= cpu_reg(s
, rn
);
4411 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4413 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4414 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4415 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4416 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4417 tcg_temp_free_i32(tcg_tmp32
);
4421 /* REV with sf==1, opcode==3 ("REV64") */
4422 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4423 unsigned int rn
, unsigned int rd
)
4426 unallocated_encoding(s
);
4429 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4432 /* REV with sf==0, opcode==2
4433 * REV32 (sf==1, opcode==2)
4435 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4436 unsigned int rn
, unsigned int rd
)
4438 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4441 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4442 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4444 /* bswap32_i64 requires zero high word */
4445 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4446 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4447 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4448 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4449 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4451 tcg_temp_free_i64(tcg_tmp
);
4453 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4454 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4458 /* REV16 (opcode==1) */
4459 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4460 unsigned int rn
, unsigned int rd
)
4462 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4463 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4464 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4465 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4467 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4468 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4469 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4470 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4471 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4473 tcg_temp_free_i64(mask
);
4474 tcg_temp_free_i64(tcg_tmp
);
4477 /* Data-processing (1 source)
4478 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4479 * +----+---+---+-----------------+---------+--------+------+------+
4480 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4481 * +----+---+---+-----------------+---------+--------+------+------+
4483 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4485 unsigned int sf
, opcode
, rn
, rd
;
4487 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4488 unallocated_encoding(s
);
4492 sf
= extract32(insn
, 31, 1);
4493 opcode
= extract32(insn
, 10, 6);
4494 rn
= extract32(insn
, 5, 5);
4495 rd
= extract32(insn
, 0, 5);
4499 handle_rbit(s
, sf
, rn
, rd
);
4502 handle_rev16(s
, sf
, rn
, rd
);
4505 handle_rev32(s
, sf
, rn
, rd
);
4508 handle_rev64(s
, sf
, rn
, rd
);
4511 handle_clz(s
, sf
, rn
, rd
);
4514 handle_cls(s
, sf
, rn
, rd
);
4519 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4520 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4522 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4523 tcg_rd
= cpu_reg(s
, rd
);
4525 if (!sf
&& is_signed
) {
4526 tcg_n
= new_tmp_a64(s
);
4527 tcg_m
= new_tmp_a64(s
);
4528 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4529 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4531 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4532 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4536 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4538 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4541 if (!sf
) { /* zero extend final result */
4542 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4546 /* LSLV, LSRV, ASRV, RORV */
4547 static void handle_shift_reg(DisasContext
*s
,
4548 enum a64_shift_type shift_type
, unsigned int sf
,
4549 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4551 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4552 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4553 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4555 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4556 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4557 tcg_temp_free_i64(tcg_shift
);
4560 /* CRC32[BHWX], CRC32C[BHWX] */
4561 static void handle_crc32(DisasContext
*s
,
4562 unsigned int sf
, unsigned int sz
, bool crc32c
,
4563 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4565 TCGv_i64 tcg_acc
, tcg_val
;
4568 if (!dc_isar_feature(aa64_crc32
, s
)
4569 || (sf
== 1 && sz
!= 3)
4570 || (sf
== 0 && sz
== 3)) {
4571 unallocated_encoding(s
);
4576 tcg_val
= cpu_reg(s
, rm
);
4590 g_assert_not_reached();
4592 tcg_val
= new_tmp_a64(s
);
4593 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4596 tcg_acc
= cpu_reg(s
, rn
);
4597 tcg_bytes
= tcg_const_i32(1 << sz
);
4600 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4602 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4605 tcg_temp_free_i32(tcg_bytes
);
4608 /* Data-processing (2 source)
4609 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4610 * +----+---+---+-----------------+------+--------+------+------+
4611 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4612 * +----+---+---+-----------------+------+--------+------+------+
4614 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4616 unsigned int sf
, rm
, opcode
, rn
, rd
;
4617 sf
= extract32(insn
, 31, 1);
4618 rm
= extract32(insn
, 16, 5);
4619 opcode
= extract32(insn
, 10, 6);
4620 rn
= extract32(insn
, 5, 5);
4621 rd
= extract32(insn
, 0, 5);
4623 if (extract32(insn
, 29, 1)) {
4624 unallocated_encoding(s
);
4630 handle_div(s
, false, sf
, rm
, rn
, rd
);
4633 handle_div(s
, true, sf
, rm
, rn
, rd
);
4636 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4639 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4642 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4645 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4654 case 23: /* CRC32 */
4656 int sz
= extract32(opcode
, 0, 2);
4657 bool crc32c
= extract32(opcode
, 2, 1);
4658 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4662 unallocated_encoding(s
);
4667 /* Data processing - register */
4668 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4670 switch (extract32(insn
, 24, 5)) {
4671 case 0x0a: /* Logical (shifted register) */
4672 disas_logic_reg(s
, insn
);
4674 case 0x0b: /* Add/subtract */
4675 if (insn
& (1 << 21)) { /* (extended register) */
4676 disas_add_sub_ext_reg(s
, insn
);
4678 disas_add_sub_reg(s
, insn
);
4681 case 0x1b: /* Data-processing (3 source) */
4682 disas_data_proc_3src(s
, insn
);
4685 switch (extract32(insn
, 21, 3)) {
4686 case 0x0: /* Add/subtract (with carry) */
4687 disas_adc_sbc(s
, insn
);
4689 case 0x2: /* Conditional compare */
4690 disas_cc(s
, insn
); /* both imm and reg forms */
4692 case 0x4: /* Conditional select */
4693 disas_cond_select(s
, insn
);
4695 case 0x6: /* Data-processing */
4696 if (insn
& (1 << 30)) { /* (1 source) */
4697 disas_data_proc_1src(s
, insn
);
4698 } else { /* (2 source) */
4699 disas_data_proc_2src(s
, insn
);
4703 unallocated_encoding(s
);
4708 unallocated_encoding(s
);
4713 static void handle_fp_compare(DisasContext
*s
, int size
,
4714 unsigned int rn
, unsigned int rm
,
4715 bool cmp_with_zero
, bool signal_all_nans
)
4717 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4718 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
4720 if (size
== MO_64
) {
4721 TCGv_i64 tcg_vn
, tcg_vm
;
4723 tcg_vn
= read_fp_dreg(s
, rn
);
4724 if (cmp_with_zero
) {
4725 tcg_vm
= tcg_const_i64(0);
4727 tcg_vm
= read_fp_dreg(s
, rm
);
4729 if (signal_all_nans
) {
4730 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4732 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4734 tcg_temp_free_i64(tcg_vn
);
4735 tcg_temp_free_i64(tcg_vm
);
4737 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
4738 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
4740 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
4741 if (cmp_with_zero
) {
4742 tcg_gen_movi_i32(tcg_vm
, 0);
4744 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
4749 if (signal_all_nans
) {
4750 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4752 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4756 if (signal_all_nans
) {
4757 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4759 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4763 g_assert_not_reached();
4766 tcg_temp_free_i32(tcg_vn
);
4767 tcg_temp_free_i32(tcg_vm
);
4770 tcg_temp_free_ptr(fpst
);
4772 gen_set_nzcv(tcg_flags
);
4774 tcg_temp_free_i64(tcg_flags
);
4777 /* Floating point compare
4778 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4779 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4780 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4781 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4783 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4785 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4788 mos
= extract32(insn
, 29, 3);
4789 type
= extract32(insn
, 22, 2);
4790 rm
= extract32(insn
, 16, 5);
4791 op
= extract32(insn
, 14, 2);
4792 rn
= extract32(insn
, 5, 5);
4793 opc
= extract32(insn
, 3, 2);
4794 op2r
= extract32(insn
, 0, 3);
4796 if (mos
|| op
|| op2r
) {
4797 unallocated_encoding(s
);
4810 if (dc_isar_feature(aa64_fp16
, s
)) {
4815 unallocated_encoding(s
);
4819 if (!fp_access_check(s
)) {
4823 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
4826 /* Floating point conditional compare
4827 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4828 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4829 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4830 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4832 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4834 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4836 TCGLabel
*label_continue
= NULL
;
4839 mos
= extract32(insn
, 29, 3);
4840 type
= extract32(insn
, 22, 2);
4841 rm
= extract32(insn
, 16, 5);
4842 cond
= extract32(insn
, 12, 4);
4843 rn
= extract32(insn
, 5, 5);
4844 op
= extract32(insn
, 4, 1);
4845 nzcv
= extract32(insn
, 0, 4);
4848 unallocated_encoding(s
);
4861 if (dc_isar_feature(aa64_fp16
, s
)) {
4866 unallocated_encoding(s
);
4870 if (!fp_access_check(s
)) {
4874 if (cond
< 0x0e) { /* not always */
4875 TCGLabel
*label_match
= gen_new_label();
4876 label_continue
= gen_new_label();
4877 arm_gen_test_cc(cond
, label_match
);
4879 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4880 gen_set_nzcv(tcg_flags
);
4881 tcg_temp_free_i64(tcg_flags
);
4882 tcg_gen_br(label_continue
);
4883 gen_set_label(label_match
);
4886 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
4889 gen_set_label(label_continue
);
4893 /* Floating point conditional select
4894 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4895 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4896 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4897 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4899 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4901 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4902 TCGv_i64 t_true
, t_false
, t_zero
;
4906 mos
= extract32(insn
, 29, 3);
4907 type
= extract32(insn
, 22, 2);
4908 rm
= extract32(insn
, 16, 5);
4909 cond
= extract32(insn
, 12, 4);
4910 rn
= extract32(insn
, 5, 5);
4911 rd
= extract32(insn
, 0, 5);
4914 unallocated_encoding(s
);
4927 if (dc_isar_feature(aa64_fp16
, s
)) {
4932 unallocated_encoding(s
);
4936 if (!fp_access_check(s
)) {
4940 /* Zero extend sreg & hreg inputs to 64 bits now. */
4941 t_true
= tcg_temp_new_i64();
4942 t_false
= tcg_temp_new_i64();
4943 read_vec_element(s
, t_true
, rn
, 0, sz
);
4944 read_vec_element(s
, t_false
, rm
, 0, sz
);
4946 a64_test_cc(&c
, cond
);
4947 t_zero
= tcg_const_i64(0);
4948 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4949 tcg_temp_free_i64(t_zero
);
4950 tcg_temp_free_i64(t_false
);
4953 /* Note that sregs & hregs write back zeros to the high bits,
4954 and we've already done the zero-extension. */
4955 write_fp_dreg(s
, rd
, t_true
);
4956 tcg_temp_free_i64(t_true
);
4959 /* Floating-point data-processing (1 source) - half precision */
4960 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
4962 TCGv_ptr fpst
= NULL
;
4963 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
4964 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4967 case 0x0: /* FMOV */
4968 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4970 case 0x1: /* FABS */
4971 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
4973 case 0x2: /* FNEG */
4974 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
4976 case 0x3: /* FSQRT */
4977 fpst
= get_fpstatus_ptr(true);
4978 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
4980 case 0x8: /* FRINTN */
4981 case 0x9: /* FRINTP */
4982 case 0xa: /* FRINTM */
4983 case 0xb: /* FRINTZ */
4984 case 0xc: /* FRINTA */
4986 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4987 fpst
= get_fpstatus_ptr(true);
4989 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4990 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
4992 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4993 tcg_temp_free_i32(tcg_rmode
);
4996 case 0xe: /* FRINTX */
4997 fpst
= get_fpstatus_ptr(true);
4998 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5000 case 0xf: /* FRINTI */
5001 fpst
= get_fpstatus_ptr(true);
5002 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5008 write_fp_sreg(s
, rd
, tcg_res
);
5011 tcg_temp_free_ptr(fpst
);
5013 tcg_temp_free_i32(tcg_op
);
5014 tcg_temp_free_i32(tcg_res
);
5017 /* Floating-point data-processing (1 source) - single precision */
5018 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5024 fpst
= get_fpstatus_ptr(false);
5025 tcg_op
= read_fp_sreg(s
, rn
);
5026 tcg_res
= tcg_temp_new_i32();
5029 case 0x0: /* FMOV */
5030 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5032 case 0x1: /* FABS */
5033 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5035 case 0x2: /* FNEG */
5036 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5038 case 0x3: /* FSQRT */
5039 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5041 case 0x8: /* FRINTN */
5042 case 0x9: /* FRINTP */
5043 case 0xa: /* FRINTM */
5044 case 0xb: /* FRINTZ */
5045 case 0xc: /* FRINTA */
5047 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5049 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5050 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5052 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5053 tcg_temp_free_i32(tcg_rmode
);
5056 case 0xe: /* FRINTX */
5057 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5059 case 0xf: /* FRINTI */
5060 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5066 write_fp_sreg(s
, rd
, tcg_res
);
5068 tcg_temp_free_ptr(fpst
);
5069 tcg_temp_free_i32(tcg_op
);
5070 tcg_temp_free_i32(tcg_res
);
5073 /* Floating-point data-processing (1 source) - double precision */
5074 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5081 case 0x0: /* FMOV */
5082 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5086 fpst
= get_fpstatus_ptr(false);
5087 tcg_op
= read_fp_dreg(s
, rn
);
5088 tcg_res
= tcg_temp_new_i64();
5091 case 0x1: /* FABS */
5092 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5094 case 0x2: /* FNEG */
5095 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5097 case 0x3: /* FSQRT */
5098 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5100 case 0x8: /* FRINTN */
5101 case 0x9: /* FRINTP */
5102 case 0xa: /* FRINTM */
5103 case 0xb: /* FRINTZ */
5104 case 0xc: /* FRINTA */
5106 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5108 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5109 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5111 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5112 tcg_temp_free_i32(tcg_rmode
);
5115 case 0xe: /* FRINTX */
5116 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5118 case 0xf: /* FRINTI */
5119 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5125 write_fp_dreg(s
, rd
, tcg_res
);
5127 tcg_temp_free_ptr(fpst
);
5128 tcg_temp_free_i64(tcg_op
);
5129 tcg_temp_free_i64(tcg_res
);
5132 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5133 int rd
, int rn
, int dtype
, int ntype
)
5138 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5140 /* Single to double */
5141 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5142 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5143 write_fp_dreg(s
, rd
, tcg_rd
);
5144 tcg_temp_free_i64(tcg_rd
);
5146 /* Single to half */
5147 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5148 TCGv_i32 ahp
= get_ahp_flag();
5149 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5151 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5152 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5153 write_fp_sreg(s
, rd
, tcg_rd
);
5154 tcg_temp_free_i32(tcg_rd
);
5155 tcg_temp_free_i32(ahp
);
5156 tcg_temp_free_ptr(fpst
);
5158 tcg_temp_free_i32(tcg_rn
);
5163 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5164 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5166 /* Double to single */
5167 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5169 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5170 TCGv_i32 ahp
= get_ahp_flag();
5171 /* Double to half */
5172 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5173 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5174 tcg_temp_free_ptr(fpst
);
5175 tcg_temp_free_i32(ahp
);
5177 write_fp_sreg(s
, rd
, tcg_rd
);
5178 tcg_temp_free_i32(tcg_rd
);
5179 tcg_temp_free_i64(tcg_rn
);
5184 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5185 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5186 TCGv_i32 tcg_ahp
= get_ahp_flag();
5187 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5189 /* Half to single */
5190 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5191 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5192 write_fp_sreg(s
, rd
, tcg_rd
);
5193 tcg_temp_free_ptr(tcg_fpst
);
5194 tcg_temp_free_i32(tcg_ahp
);
5195 tcg_temp_free_i32(tcg_rd
);
5197 /* Half to double */
5198 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5199 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5200 write_fp_dreg(s
, rd
, tcg_rd
);
5201 tcg_temp_free_i64(tcg_rd
);
5203 tcg_temp_free_i32(tcg_rn
);
5211 /* Floating point data-processing (1 source)
5212 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5213 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5214 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5215 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5217 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5219 int type
= extract32(insn
, 22, 2);
5220 int opcode
= extract32(insn
, 15, 6);
5221 int rn
= extract32(insn
, 5, 5);
5222 int rd
= extract32(insn
, 0, 5);
5225 case 0x4: case 0x5: case 0x7:
5227 /* FCVT between half, single and double precision */
5228 int dtype
= extract32(opcode
, 0, 2);
5229 if (type
== 2 || dtype
== type
) {
5230 unallocated_encoding(s
);
5233 if (!fp_access_check(s
)) {
5237 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5243 /* 32-to-32 and 64-to-64 ops */
5246 if (!fp_access_check(s
)) {
5250 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5253 if (!fp_access_check(s
)) {
5257 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5260 if (!dc_isar_feature(aa64_fp16
, s
)) {
5261 unallocated_encoding(s
);
5265 if (!fp_access_check(s
)) {
5269 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5272 unallocated_encoding(s
);
5276 unallocated_encoding(s
);
5281 /* Floating-point data-processing (2 source) - single precision */
5282 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5283 int rd
, int rn
, int rm
)
5290 tcg_res
= tcg_temp_new_i32();
5291 fpst
= get_fpstatus_ptr(false);
5292 tcg_op1
= read_fp_sreg(s
, rn
);
5293 tcg_op2
= read_fp_sreg(s
, rm
);
5296 case 0x0: /* FMUL */
5297 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5299 case 0x1: /* FDIV */
5300 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5302 case 0x2: /* FADD */
5303 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5305 case 0x3: /* FSUB */
5306 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5308 case 0x4: /* FMAX */
5309 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5311 case 0x5: /* FMIN */
5312 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5314 case 0x6: /* FMAXNM */
5315 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5317 case 0x7: /* FMINNM */
5318 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5320 case 0x8: /* FNMUL */
5321 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5322 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5326 write_fp_sreg(s
, rd
, tcg_res
);
5328 tcg_temp_free_ptr(fpst
);
5329 tcg_temp_free_i32(tcg_op1
);
5330 tcg_temp_free_i32(tcg_op2
);
5331 tcg_temp_free_i32(tcg_res
);
5334 /* Floating-point data-processing (2 source) - double precision */
5335 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5336 int rd
, int rn
, int rm
)
5343 tcg_res
= tcg_temp_new_i64();
5344 fpst
= get_fpstatus_ptr(false);
5345 tcg_op1
= read_fp_dreg(s
, rn
);
5346 tcg_op2
= read_fp_dreg(s
, rm
);
5349 case 0x0: /* FMUL */
5350 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5352 case 0x1: /* FDIV */
5353 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5355 case 0x2: /* FADD */
5356 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5358 case 0x3: /* FSUB */
5359 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5361 case 0x4: /* FMAX */
5362 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5364 case 0x5: /* FMIN */
5365 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5367 case 0x6: /* FMAXNM */
5368 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5370 case 0x7: /* FMINNM */
5371 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5373 case 0x8: /* FNMUL */
5374 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5375 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5379 write_fp_dreg(s
, rd
, tcg_res
);
5381 tcg_temp_free_ptr(fpst
);
5382 tcg_temp_free_i64(tcg_op1
);
5383 tcg_temp_free_i64(tcg_op2
);
5384 tcg_temp_free_i64(tcg_res
);
5387 /* Floating-point data-processing (2 source) - half precision */
5388 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5389 int rd
, int rn
, int rm
)
5396 tcg_res
= tcg_temp_new_i32();
5397 fpst
= get_fpstatus_ptr(true);
5398 tcg_op1
= read_fp_hreg(s
, rn
);
5399 tcg_op2
= read_fp_hreg(s
, rm
);
5402 case 0x0: /* FMUL */
5403 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5405 case 0x1: /* FDIV */
5406 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5408 case 0x2: /* FADD */
5409 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5411 case 0x3: /* FSUB */
5412 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5414 case 0x4: /* FMAX */
5415 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5417 case 0x5: /* FMIN */
5418 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5420 case 0x6: /* FMAXNM */
5421 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5423 case 0x7: /* FMINNM */
5424 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5426 case 0x8: /* FNMUL */
5427 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5428 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5431 g_assert_not_reached();
5434 write_fp_sreg(s
, rd
, tcg_res
);
5436 tcg_temp_free_ptr(fpst
);
5437 tcg_temp_free_i32(tcg_op1
);
5438 tcg_temp_free_i32(tcg_op2
);
5439 tcg_temp_free_i32(tcg_res
);
5442 /* Floating point data-processing (2 source)
5443 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5444 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5445 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5446 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5448 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5450 int type
= extract32(insn
, 22, 2);
5451 int rd
= extract32(insn
, 0, 5);
5452 int rn
= extract32(insn
, 5, 5);
5453 int rm
= extract32(insn
, 16, 5);
5454 int opcode
= extract32(insn
, 12, 4);
5457 unallocated_encoding(s
);
5463 if (!fp_access_check(s
)) {
5466 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5469 if (!fp_access_check(s
)) {
5472 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5475 if (!dc_isar_feature(aa64_fp16
, s
)) {
5476 unallocated_encoding(s
);
5479 if (!fp_access_check(s
)) {
5482 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5485 unallocated_encoding(s
);
5489 /* Floating-point data-processing (3 source) - single precision */
5490 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5491 int rd
, int rn
, int rm
, int ra
)
5493 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5494 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5495 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5497 tcg_op1
= read_fp_sreg(s
, rn
);
5498 tcg_op2
= read_fp_sreg(s
, rm
);
5499 tcg_op3
= read_fp_sreg(s
, ra
);
5501 /* These are fused multiply-add, and must be done as one
5502 * floating point operation with no rounding between the
5503 * multiplication and addition steps.
5504 * NB that doing the negations here as separate steps is
5505 * correct : an input NaN should come out with its sign bit
5506 * flipped if it is a negated-input.
5509 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5513 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5516 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5518 write_fp_sreg(s
, rd
, tcg_res
);
5520 tcg_temp_free_ptr(fpst
);
5521 tcg_temp_free_i32(tcg_op1
);
5522 tcg_temp_free_i32(tcg_op2
);
5523 tcg_temp_free_i32(tcg_op3
);
5524 tcg_temp_free_i32(tcg_res
);
5527 /* Floating-point data-processing (3 source) - double precision */
5528 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
5529 int rd
, int rn
, int rm
, int ra
)
5531 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
5532 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5533 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5535 tcg_op1
= read_fp_dreg(s
, rn
);
5536 tcg_op2
= read_fp_dreg(s
, rm
);
5537 tcg_op3
= read_fp_dreg(s
, ra
);
5539 /* These are fused multiply-add, and must be done as one
5540 * floating point operation with no rounding between the
5541 * multiplication and addition steps.
5542 * NB that doing the negations here as separate steps is
5543 * correct : an input NaN should come out with its sign bit
5544 * flipped if it is a negated-input.
5547 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
5551 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
5554 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5556 write_fp_dreg(s
, rd
, tcg_res
);
5558 tcg_temp_free_ptr(fpst
);
5559 tcg_temp_free_i64(tcg_op1
);
5560 tcg_temp_free_i64(tcg_op2
);
5561 tcg_temp_free_i64(tcg_op3
);
5562 tcg_temp_free_i64(tcg_res
);
5565 /* Floating-point data-processing (3 source) - half precision */
5566 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
5567 int rd
, int rn
, int rm
, int ra
)
5569 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5570 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5571 TCGv_ptr fpst
= get_fpstatus_ptr(true);
5573 tcg_op1
= read_fp_hreg(s
, rn
);
5574 tcg_op2
= read_fp_hreg(s
, rm
);
5575 tcg_op3
= read_fp_hreg(s
, ra
);
5577 /* These are fused multiply-add, and must be done as one
5578 * floating point operation with no rounding between the
5579 * multiplication and addition steps.
5580 * NB that doing the negations here as separate steps is
5581 * correct : an input NaN should come out with its sign bit
5582 * flipped if it is a negated-input.
5585 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
5589 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
5592 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5594 write_fp_sreg(s
, rd
, tcg_res
);
5596 tcg_temp_free_ptr(fpst
);
5597 tcg_temp_free_i32(tcg_op1
);
5598 tcg_temp_free_i32(tcg_op2
);
5599 tcg_temp_free_i32(tcg_op3
);
5600 tcg_temp_free_i32(tcg_res
);
5603 /* Floating point data-processing (3 source)
5604 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
5605 * +---+---+---+-----------+------+----+------+----+------+------+------+
5606 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
5607 * +---+---+---+-----------+------+----+------+----+------+------+------+
5609 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
5611 int type
= extract32(insn
, 22, 2);
5612 int rd
= extract32(insn
, 0, 5);
5613 int rn
= extract32(insn
, 5, 5);
5614 int ra
= extract32(insn
, 10, 5);
5615 int rm
= extract32(insn
, 16, 5);
5616 bool o0
= extract32(insn
, 15, 1);
5617 bool o1
= extract32(insn
, 21, 1);
5621 if (!fp_access_check(s
)) {
5624 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5627 if (!fp_access_check(s
)) {
5630 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5633 if (!dc_isar_feature(aa64_fp16
, s
)) {
5634 unallocated_encoding(s
);
5637 if (!fp_access_check(s
)) {
5640 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5643 unallocated_encoding(s
);
5647 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5648 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5649 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5651 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
5657 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5658 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5659 extract32(imm8
, 0, 6);
5663 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5664 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5665 (extract32(imm8
, 0, 6) << 3);
5669 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5670 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5671 (extract32(imm8
, 0, 6) << 6);
5674 g_assert_not_reached();
5679 /* Floating point immediate
5680 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5681 * +---+---+---+-----------+------+---+------------+-------+------+------+
5682 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5683 * +---+---+---+-----------+------+---+------------+-------+------+------+
5685 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5687 int rd
= extract32(insn
, 0, 5);
5688 int imm8
= extract32(insn
, 13, 8);
5689 int type
= extract32(insn
, 22, 2);
5703 if (dc_isar_feature(aa64_fp16
, s
)) {
5708 unallocated_encoding(s
);
5712 if (!fp_access_check(s
)) {
5716 imm
= vfp_expand_imm(sz
, imm8
);
5718 tcg_res
= tcg_const_i64(imm
);
5719 write_fp_dreg(s
, rd
, tcg_res
);
5720 tcg_temp_free_i64(tcg_res
);
5723 /* Handle floating point <=> fixed point conversions. Note that we can
5724 * also deal with fp <=> integer conversions as a special case (scale == 64)
5725 * OPTME: consider handling that special case specially or at least skipping
5726 * the call to scalbn in the helpers for zero shifts.
5728 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5729 bool itof
, int rmode
, int scale
, int sf
, int type
)
5731 bool is_signed
= !(opcode
& 1);
5732 TCGv_ptr tcg_fpstatus
;
5733 TCGv_i32 tcg_shift
, tcg_single
;
5734 TCGv_i64 tcg_double
;
5736 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
5738 tcg_shift
= tcg_const_i32(64 - scale
);
5741 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5743 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5746 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5748 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5751 tcg_int
= tcg_extend
;
5755 case 1: /* float64 */
5756 tcg_double
= tcg_temp_new_i64();
5758 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5759 tcg_shift
, tcg_fpstatus
);
5761 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5762 tcg_shift
, tcg_fpstatus
);
5764 write_fp_dreg(s
, rd
, tcg_double
);
5765 tcg_temp_free_i64(tcg_double
);
5768 case 0: /* float32 */
5769 tcg_single
= tcg_temp_new_i32();
5771 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5772 tcg_shift
, tcg_fpstatus
);
5774 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5775 tcg_shift
, tcg_fpstatus
);
5777 write_fp_sreg(s
, rd
, tcg_single
);
5778 tcg_temp_free_i32(tcg_single
);
5781 case 3: /* float16 */
5782 tcg_single
= tcg_temp_new_i32();
5784 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
5785 tcg_shift
, tcg_fpstatus
);
5787 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
5788 tcg_shift
, tcg_fpstatus
);
5790 write_fp_sreg(s
, rd
, tcg_single
);
5791 tcg_temp_free_i32(tcg_single
);
5795 g_assert_not_reached();
5798 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5801 if (extract32(opcode
, 2, 1)) {
5802 /* There are too many rounding modes to all fit into rmode,
5803 * so FCVTA[US] is a special case.
5805 rmode
= FPROUNDING_TIEAWAY
;
5808 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5810 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5813 case 1: /* float64 */
5814 tcg_double
= read_fp_dreg(s
, rn
);
5817 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5818 tcg_shift
, tcg_fpstatus
);
5820 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5821 tcg_shift
, tcg_fpstatus
);
5825 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5826 tcg_shift
, tcg_fpstatus
);
5828 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5829 tcg_shift
, tcg_fpstatus
);
5833 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5835 tcg_temp_free_i64(tcg_double
);
5838 case 0: /* float32 */
5839 tcg_single
= read_fp_sreg(s
, rn
);
5842 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5843 tcg_shift
, tcg_fpstatus
);
5845 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5846 tcg_shift
, tcg_fpstatus
);
5849 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5851 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5852 tcg_shift
, tcg_fpstatus
);
5854 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5855 tcg_shift
, tcg_fpstatus
);
5857 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5858 tcg_temp_free_i32(tcg_dest
);
5860 tcg_temp_free_i32(tcg_single
);
5863 case 3: /* float16 */
5864 tcg_single
= read_fp_sreg(s
, rn
);
5867 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
5868 tcg_shift
, tcg_fpstatus
);
5870 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
5871 tcg_shift
, tcg_fpstatus
);
5874 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5876 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
5877 tcg_shift
, tcg_fpstatus
);
5879 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
5880 tcg_shift
, tcg_fpstatus
);
5882 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5883 tcg_temp_free_i32(tcg_dest
);
5885 tcg_temp_free_i32(tcg_single
);
5889 g_assert_not_reached();
5892 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5893 tcg_temp_free_i32(tcg_rmode
);
5896 tcg_temp_free_ptr(tcg_fpstatus
);
5897 tcg_temp_free_i32(tcg_shift
);
5900 /* Floating point <-> fixed point conversions
5901 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5902 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5903 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5904 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5906 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5908 int rd
= extract32(insn
, 0, 5);
5909 int rn
= extract32(insn
, 5, 5);
5910 int scale
= extract32(insn
, 10, 6);
5911 int opcode
= extract32(insn
, 16, 3);
5912 int rmode
= extract32(insn
, 19, 2);
5913 int type
= extract32(insn
, 22, 2);
5914 bool sbit
= extract32(insn
, 29, 1);
5915 bool sf
= extract32(insn
, 31, 1);
5918 if (sbit
|| (!sf
&& scale
< 32)) {
5919 unallocated_encoding(s
);
5924 case 0: /* float32 */
5925 case 1: /* float64 */
5927 case 3: /* float16 */
5928 if (dc_isar_feature(aa64_fp16
, s
)) {
5933 unallocated_encoding(s
);
5937 switch ((rmode
<< 3) | opcode
) {
5938 case 0x2: /* SCVTF */
5939 case 0x3: /* UCVTF */
5942 case 0x18: /* FCVTZS */
5943 case 0x19: /* FCVTZU */
5947 unallocated_encoding(s
);
5951 if (!fp_access_check(s
)) {
5955 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5958 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5960 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5961 * without conversion.
5965 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5971 tmp
= tcg_temp_new_i64();
5972 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5973 write_fp_dreg(s
, rd
, tmp
);
5974 tcg_temp_free_i64(tmp
);
5978 write_fp_dreg(s
, rd
, tcg_rn
);
5981 /* 64 bit to top half. */
5982 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5983 clear_vec_high(s
, true, rd
);
5987 tmp
= tcg_temp_new_i64();
5988 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
5989 write_fp_dreg(s
, rd
, tmp
);
5990 tcg_temp_free_i64(tmp
);
5993 g_assert_not_reached();
5996 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6001 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6005 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6008 /* 64 bits from top half */
6009 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6013 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6016 g_assert_not_reached();
6021 /* Floating point <-> integer conversions
6022 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6023 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6024 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6025 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6027 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6029 int rd
= extract32(insn
, 0, 5);
6030 int rn
= extract32(insn
, 5, 5);
6031 int opcode
= extract32(insn
, 16, 3);
6032 int rmode
= extract32(insn
, 19, 2);
6033 int type
= extract32(insn
, 22, 2);
6034 bool sbit
= extract32(insn
, 29, 1);
6035 bool sf
= extract32(insn
, 31, 1);
6038 unallocated_encoding(s
);
6044 bool itof
= opcode
& 1;
6047 unallocated_encoding(s
);
6051 switch (sf
<< 3 | type
<< 1 | rmode
) {
6052 case 0x0: /* 32 bit */
6053 case 0xa: /* 64 bit */
6054 case 0xd: /* 64 bit to top half of quad */
6056 case 0x6: /* 16-bit float, 32-bit int */
6057 case 0xe: /* 16-bit float, 64-bit int */
6058 if (dc_isar_feature(aa64_fp16
, s
)) {
6063 /* all other sf/type/rmode combinations are invalid */
6064 unallocated_encoding(s
);
6068 if (!fp_access_check(s
)) {
6071 handle_fmov(s
, rd
, rn
, type
, itof
);
6073 /* actual FP conversions */
6074 bool itof
= extract32(opcode
, 1, 1);
6076 if (rmode
!= 0 && opcode
> 1) {
6077 unallocated_encoding(s
);
6081 case 0: /* float32 */
6082 case 1: /* float64 */
6084 case 3: /* float16 */
6085 if (dc_isar_feature(aa64_fp16
, s
)) {
6090 unallocated_encoding(s
);
6094 if (!fp_access_check(s
)) {
6097 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6101 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6102 * 31 30 29 28 25 24 0
6103 * +---+---+---+---------+-----------------------------+
6104 * | | 0 | | 1 1 1 1 | |
6105 * +---+---+---+---------+-----------------------------+
6107 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6109 if (extract32(insn
, 24, 1)) {
6110 /* Floating point data-processing (3 source) */
6111 disas_fp_3src(s
, insn
);
6112 } else if (extract32(insn
, 21, 1) == 0) {
6113 /* Floating point to fixed point conversions */
6114 disas_fp_fixed_conv(s
, insn
);
6116 switch (extract32(insn
, 10, 2)) {
6118 /* Floating point conditional compare */
6119 disas_fp_ccomp(s
, insn
);
6122 /* Floating point data-processing (2 source) */
6123 disas_fp_2src(s
, insn
);
6126 /* Floating point conditional select */
6127 disas_fp_csel(s
, insn
);
6130 switch (ctz32(extract32(insn
, 12, 4))) {
6131 case 0: /* [15:12] == xxx1 */
6132 /* Floating point immediate */
6133 disas_fp_imm(s
, insn
);
6135 case 1: /* [15:12] == xx10 */
6136 /* Floating point compare */
6137 disas_fp_compare(s
, insn
);
6139 case 2: /* [15:12] == x100 */
6140 /* Floating point data-processing (1 source) */
6141 disas_fp_1src(s
, insn
);
6143 case 3: /* [15:12] == 1000 */
6144 unallocated_encoding(s
);
6146 default: /* [15:12] == 0000 */
6147 /* Floating point <-> integer conversions */
6148 disas_fp_int_conv(s
, insn
);
6156 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6159 /* Extract 64 bits from the middle of two concatenated 64 bit
6160 * vector register slices left:right. The extracted bits start
6161 * at 'pos' bits into the right (least significant) side.
6162 * We return the result in tcg_right, and guarantee not to
6165 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6166 assert(pos
> 0 && pos
< 64);
6168 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6169 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6170 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6172 tcg_temp_free_i64(tcg_tmp
);
6176 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6177 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6178 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6179 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6181 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6183 int is_q
= extract32(insn
, 30, 1);
6184 int op2
= extract32(insn
, 22, 2);
6185 int imm4
= extract32(insn
, 11, 4);
6186 int rm
= extract32(insn
, 16, 5);
6187 int rn
= extract32(insn
, 5, 5);
6188 int rd
= extract32(insn
, 0, 5);
6189 int pos
= imm4
<< 3;
6190 TCGv_i64 tcg_resl
, tcg_resh
;
6192 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6193 unallocated_encoding(s
);
6197 if (!fp_access_check(s
)) {
6201 tcg_resh
= tcg_temp_new_i64();
6202 tcg_resl
= tcg_temp_new_i64();
6204 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6205 * either extracting 128 bits from a 128:128 concatenation, or
6206 * extracting 64 bits from a 64:64 concatenation.
6209 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6211 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6212 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6214 tcg_gen_movi_i64(tcg_resh
, 0);
6221 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6222 EltPosns
*elt
= eltposns
;
6229 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6231 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6234 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6235 tcg_hh
= tcg_temp_new_i64();
6236 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6237 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6238 tcg_temp_free_i64(tcg_hh
);
6242 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6243 tcg_temp_free_i64(tcg_resl
);
6244 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6245 tcg_temp_free_i64(tcg_resh
);
6249 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6250 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6251 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6252 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6254 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6256 int op2
= extract32(insn
, 22, 2);
6257 int is_q
= extract32(insn
, 30, 1);
6258 int rm
= extract32(insn
, 16, 5);
6259 int rn
= extract32(insn
, 5, 5);
6260 int rd
= extract32(insn
, 0, 5);
6261 int is_tblx
= extract32(insn
, 12, 1);
6262 int len
= extract32(insn
, 13, 2);
6263 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6264 TCGv_i32 tcg_regno
, tcg_numregs
;
6267 unallocated_encoding(s
);
6271 if (!fp_access_check(s
)) {
6275 /* This does a table lookup: for every byte element in the input
6276 * we index into a table formed from up to four vector registers,
6277 * and then the output is the result of the lookups. Our helper
6278 * function does the lookup operation for a single 64 bit part of
6281 tcg_resl
= tcg_temp_new_i64();
6282 tcg_resh
= tcg_temp_new_i64();
6285 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6287 tcg_gen_movi_i64(tcg_resl
, 0);
6289 if (is_tblx
&& is_q
) {
6290 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6292 tcg_gen_movi_i64(tcg_resh
, 0);
6295 tcg_idx
= tcg_temp_new_i64();
6296 tcg_regno
= tcg_const_i32(rn
);
6297 tcg_numregs
= tcg_const_i32(len
+ 1);
6298 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6299 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6300 tcg_regno
, tcg_numregs
);
6302 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6303 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6304 tcg_regno
, tcg_numregs
);
6306 tcg_temp_free_i64(tcg_idx
);
6307 tcg_temp_free_i32(tcg_regno
);
6308 tcg_temp_free_i32(tcg_numregs
);
6310 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6311 tcg_temp_free_i64(tcg_resl
);
6312 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6313 tcg_temp_free_i64(tcg_resh
);
6317 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6318 * +---+---+-------------+------+---+------+---+------------------+------+
6319 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6320 * +---+---+-------------+------+---+------+---+------------------+------+
6322 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6324 int rd
= extract32(insn
, 0, 5);
6325 int rn
= extract32(insn
, 5, 5);
6326 int rm
= extract32(insn
, 16, 5);
6327 int size
= extract32(insn
, 22, 2);
6328 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6329 * bit 2 indicates 1 vs 2 variant of the insn.
6331 int opcode
= extract32(insn
, 12, 2);
6332 bool part
= extract32(insn
, 14, 1);
6333 bool is_q
= extract32(insn
, 30, 1);
6334 int esize
= 8 << size
;
6336 int datasize
= is_q
? 128 : 64;
6337 int elements
= datasize
/ esize
;
6338 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6340 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6341 unallocated_encoding(s
);
6345 if (!fp_access_check(s
)) {
6349 tcg_resl
= tcg_const_i64(0);
6350 tcg_resh
= tcg_const_i64(0);
6351 tcg_res
= tcg_temp_new_i64();
6353 for (i
= 0; i
< elements
; i
++) {
6355 case 1: /* UZP1/2 */
6357 int midpoint
= elements
/ 2;
6359 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6361 read_vec_element(s
, tcg_res
, rm
,
6362 2 * (i
- midpoint
) + part
, size
);
6366 case 2: /* TRN1/2 */
6368 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6370 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6373 case 3: /* ZIP1/2 */
6375 int base
= part
* elements
/ 2;
6377 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6379 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6384 g_assert_not_reached();
6389 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6390 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6392 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6393 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6397 tcg_temp_free_i64(tcg_res
);
6399 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6400 tcg_temp_free_i64(tcg_resl
);
6401 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6402 tcg_temp_free_i64(tcg_resh
);
6406 * do_reduction_op helper
6408 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6409 * important for correct NaN propagation that we do these
6410 * operations in exactly the order specified by the pseudocode.
6412 * This is a recursive function, TCG temps should be freed by the
6413 * calling function once it is done with the values.
6415 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6416 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6418 if (esize
== size
) {
6420 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6423 /* We should have one register left here */
6424 assert(ctpop8(vmap
) == 1);
6425 element
= ctz32(vmap
);
6426 assert(element
< 8);
6428 tcg_elem
= tcg_temp_new_i32();
6429 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6432 int bits
= size
/ 2;
6433 int shift
= ctpop8(vmap
) / 2;
6434 int vmap_lo
= (vmap
>> shift
) & vmap
;
6435 int vmap_hi
= (vmap
& ~vmap_lo
);
6436 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6438 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6439 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6440 tcg_res
= tcg_temp_new_i32();
6443 case 0x0c: /* fmaxnmv half-precision */
6444 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6446 case 0x0f: /* fmaxv half-precision */
6447 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6449 case 0x1c: /* fminnmv half-precision */
6450 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6452 case 0x1f: /* fminv half-precision */
6453 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6455 case 0x2c: /* fmaxnmv */
6456 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6458 case 0x2f: /* fmaxv */
6459 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6461 case 0x3c: /* fminnmv */
6462 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6464 case 0x3f: /* fminv */
6465 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6468 g_assert_not_reached();
6471 tcg_temp_free_i32(tcg_hi
);
6472 tcg_temp_free_i32(tcg_lo
);
6477 /* AdvSIMD across lanes
6478 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6479 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6480 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6481 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6483 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6485 int rd
= extract32(insn
, 0, 5);
6486 int rn
= extract32(insn
, 5, 5);
6487 int size
= extract32(insn
, 22, 2);
6488 int opcode
= extract32(insn
, 12, 5);
6489 bool is_q
= extract32(insn
, 30, 1);
6490 bool is_u
= extract32(insn
, 29, 1);
6492 bool is_min
= false;
6496 TCGv_i64 tcg_res
, tcg_elt
;
6499 case 0x1b: /* ADDV */
6501 unallocated_encoding(s
);
6505 case 0x3: /* SADDLV, UADDLV */
6506 case 0xa: /* SMAXV, UMAXV */
6507 case 0x1a: /* SMINV, UMINV */
6508 if (size
== 3 || (size
== 2 && !is_q
)) {
6509 unallocated_encoding(s
);
6513 case 0xc: /* FMAXNMV, FMINNMV */
6514 case 0xf: /* FMAXV, FMINV */
6515 /* Bit 1 of size field encodes min vs max and the actual size
6516 * depends on the encoding of the U bit. If not set (and FP16
6517 * enabled) then we do half-precision float instead of single
6520 is_min
= extract32(size
, 1, 1);
6522 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
6524 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
6525 unallocated_encoding(s
);
6532 unallocated_encoding(s
);
6536 if (!fp_access_check(s
)) {
6541 elements
= (is_q
? 128 : 64) / esize
;
6543 tcg_res
= tcg_temp_new_i64();
6544 tcg_elt
= tcg_temp_new_i64();
6546 /* These instructions operate across all lanes of a vector
6547 * to produce a single result. We can guarantee that a 64
6548 * bit intermediate is sufficient:
6549 * + for [US]ADDLV the maximum element size is 32 bits, and
6550 * the result type is 64 bits
6551 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6552 * same as the element size, which is 32 bits at most
6553 * For the integer operations we can choose to work at 64
6554 * or 32 bits and truncate at the end; for simplicity
6555 * we use 64 bits always. The floating point
6556 * ops do require 32 bit intermediates, though.
6559 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
6561 for (i
= 1; i
< elements
; i
++) {
6562 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
6565 case 0x03: /* SADDLV / UADDLV */
6566 case 0x1b: /* ADDV */
6567 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
6569 case 0x0a: /* SMAXV / UMAXV */
6571 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
6573 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
6576 case 0x1a: /* SMINV / UMINV */
6578 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
6580 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
6584 g_assert_not_reached();
6589 /* Floating point vector reduction ops which work across 32
6590 * bit (single) or 16 bit (half-precision) intermediates.
6591 * Note that correct NaN propagation requires that we do these
6592 * operations in exactly the order specified by the pseudocode.
6594 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
6595 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
6596 int vmap
= (1 << elements
) - 1;
6597 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
6598 (is_q
? 128 : 64), vmap
, fpst
);
6599 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
6600 tcg_temp_free_i32(tcg_res32
);
6601 tcg_temp_free_ptr(fpst
);
6604 tcg_temp_free_i64(tcg_elt
);
6606 /* Now truncate the result to the width required for the final output */
6607 if (opcode
== 0x03) {
6608 /* SADDLV, UADDLV: result is 2*esize */
6614 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
6617 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
6620 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6625 g_assert_not_reached();
6628 write_fp_dreg(s
, rd
, tcg_res
);
6629 tcg_temp_free_i64(tcg_res
);
6632 /* DUP (Element, Vector)
6634 * 31 30 29 21 20 16 15 10 9 5 4 0
6635 * +---+---+-------------------+--------+-------------+------+------+
6636 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6637 * +---+---+-------------------+--------+-------------+------+------+
6639 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6641 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
6644 int size
= ctz32(imm5
);
6645 int index
= imm5
>> (size
+ 1);
6647 if (size
> 3 || (size
== 3 && !is_q
)) {
6648 unallocated_encoding(s
);
6652 if (!fp_access_check(s
)) {
6656 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
6657 vec_reg_offset(s
, rn
, index
, size
),
6658 is_q
? 16 : 8, vec_full_reg_size(s
));
6661 /* DUP (element, scalar)
6662 * 31 21 20 16 15 10 9 5 4 0
6663 * +-----------------------+--------+-------------+------+------+
6664 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6665 * +-----------------------+--------+-------------+------+------+
6667 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
6670 int size
= ctz32(imm5
);
6675 unallocated_encoding(s
);
6679 if (!fp_access_check(s
)) {
6683 index
= imm5
>> (size
+ 1);
6685 /* This instruction just extracts the specified element and
6686 * zero-extends it into the bottom of the destination register.
6688 tmp
= tcg_temp_new_i64();
6689 read_vec_element(s
, tmp
, rn
, index
, size
);
6690 write_fp_dreg(s
, rd
, tmp
);
6691 tcg_temp_free_i64(tmp
);
6696 * 31 30 29 21 20 16 15 10 9 5 4 0
6697 * +---+---+-------------------+--------+-------------+------+------+
6698 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
6699 * +---+---+-------------------+--------+-------------+------+------+
6701 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6703 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
6706 int size
= ctz32(imm5
);
6707 uint32_t dofs
, oprsz
, maxsz
;
6709 if (size
> 3 || ((size
== 3) && !is_q
)) {
6710 unallocated_encoding(s
);
6714 if (!fp_access_check(s
)) {
6718 dofs
= vec_full_reg_offset(s
, rd
);
6719 oprsz
= is_q
? 16 : 8;
6720 maxsz
= vec_full_reg_size(s
);
6722 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
6727 * 31 21 20 16 15 14 11 10 9 5 4 0
6728 * +-----------------------+--------+------------+---+------+------+
6729 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6730 * +-----------------------+--------+------------+---+------+------+
6732 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6733 * index: encoded in imm5<4:size+1>
6735 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
6738 int size
= ctz32(imm5
);
6739 int src_index
, dst_index
;
6743 unallocated_encoding(s
);
6747 if (!fp_access_check(s
)) {
6751 dst_index
= extract32(imm5
, 1+size
, 5);
6752 src_index
= extract32(imm4
, size
, 4);
6754 tmp
= tcg_temp_new_i64();
6756 read_vec_element(s
, tmp
, rn
, src_index
, size
);
6757 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
6759 tcg_temp_free_i64(tmp
);
6765 * 31 21 20 16 15 10 9 5 4 0
6766 * +-----------------------+--------+-------------+------+------+
6767 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6768 * +-----------------------+--------+-------------+------+------+
6770 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6771 * index: encoded in imm5<4:size+1>
6773 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
6775 int size
= ctz32(imm5
);
6779 unallocated_encoding(s
);
6783 if (!fp_access_check(s
)) {
6787 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6788 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6795 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6796 * +---+---+-------------------+--------+-------------+------+------+
6797 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6798 * +---+---+-------------------+--------+-------------+------+------+
6800 * U: unsigned when set
6801 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6803 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6804 int rn
, int rd
, int imm5
)
6806 int size
= ctz32(imm5
);
6810 /* Check for UnallocatedEncodings */
6812 if (size
> 2 || (size
== 2 && !is_q
)) {
6813 unallocated_encoding(s
);
6818 || (size
< 3 && is_q
)
6819 || (size
== 3 && !is_q
)) {
6820 unallocated_encoding(s
);
6825 if (!fp_access_check(s
)) {
6829 element
= extract32(imm5
, 1+size
, 4);
6831 tcg_rd
= cpu_reg(s
, rd
);
6832 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6833 if (is_signed
&& !is_q
) {
6834 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6839 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6840 * +---+---+----+-----------------+------+---+------+---+------+------+
6841 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6842 * +---+---+----+-----------------+------+---+------+---+------+------+
6844 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6846 int rd
= extract32(insn
, 0, 5);
6847 int rn
= extract32(insn
, 5, 5);
6848 int imm4
= extract32(insn
, 11, 4);
6849 int op
= extract32(insn
, 29, 1);
6850 int is_q
= extract32(insn
, 30, 1);
6851 int imm5
= extract32(insn
, 16, 5);
6856 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6858 unallocated_encoding(s
);
6863 /* DUP (element - vector) */
6864 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6868 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6873 handle_simd_insg(s
, rd
, rn
, imm5
);
6875 unallocated_encoding(s
);
6880 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6881 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6884 unallocated_encoding(s
);
6890 /* AdvSIMD modified immediate
6891 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6892 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6893 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6894 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6896 * There are a number of operations that can be carried out here:
6897 * MOVI - move (shifted) imm into register
6898 * MVNI - move inverted (shifted) imm into register
6899 * ORR - bitwise OR of (shifted) imm with register
6900 * BIC - bitwise clear of (shifted) imm with register
6901 * With ARMv8.2 we also have:
6902 * FMOV half-precision
6904 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6906 int rd
= extract32(insn
, 0, 5);
6907 int cmode
= extract32(insn
, 12, 4);
6908 int cmode_3_1
= extract32(cmode
, 1, 3);
6909 int cmode_0
= extract32(cmode
, 0, 1);
6910 int o2
= extract32(insn
, 11, 1);
6911 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6912 bool is_neg
= extract32(insn
, 29, 1);
6913 bool is_q
= extract32(insn
, 30, 1);
6916 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6917 /* Check for FMOV (vector, immediate) - half-precision */
6918 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
6919 unallocated_encoding(s
);
6924 if (!fp_access_check(s
)) {
6928 /* See AdvSIMDExpandImm() in ARM ARM */
6929 switch (cmode_3_1
) {
6930 case 0: /* Replicate(Zeros(24):imm8, 2) */
6931 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6932 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6933 case 3: /* Replicate(imm8:Zeros(24), 2) */
6935 int shift
= cmode_3_1
* 8;
6936 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6939 case 4: /* Replicate(Zeros(8):imm8, 4) */
6940 case 5: /* Replicate(imm8:Zeros(8), 4) */
6942 int shift
= (cmode_3_1
& 0x1) * 8;
6943 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6948 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6949 imm
= (abcdefgh
<< 16) | 0xffff;
6951 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6952 imm
= (abcdefgh
<< 8) | 0xff;
6954 imm
= bitfield_replicate(imm
, 32);
6957 if (!cmode_0
&& !is_neg
) {
6958 imm
= bitfield_replicate(abcdefgh
, 8);
6959 } else if (!cmode_0
&& is_neg
) {
6962 for (i
= 0; i
< 8; i
++) {
6963 if ((abcdefgh
) & (1 << i
)) {
6964 imm
|= 0xffULL
<< (i
* 8);
6967 } else if (cmode_0
) {
6969 imm
= (abcdefgh
& 0x3f) << 48;
6970 if (abcdefgh
& 0x80) {
6971 imm
|= 0x8000000000000000ULL
;
6973 if (abcdefgh
& 0x40) {
6974 imm
|= 0x3fc0000000000000ULL
;
6976 imm
|= 0x4000000000000000ULL
;
6980 /* FMOV (vector, immediate) - half-precision */
6981 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
6982 /* now duplicate across the lanes */
6983 imm
= bitfield_replicate(imm
, 16);
6985 imm
= (abcdefgh
& 0x3f) << 19;
6986 if (abcdefgh
& 0x80) {
6989 if (abcdefgh
& 0x40) {
7000 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7001 g_assert_not_reached();
7004 if (cmode_3_1
!= 7 && is_neg
) {
7008 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7009 /* MOVI or MVNI, with MVNI negation handled above. */
7010 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7011 vec_full_reg_size(s
), imm
);
7013 /* ORR or BIC, with BIC negation to AND handled above. */
7015 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7017 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7022 /* AdvSIMD scalar copy
7023 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7024 * +-----+----+-----------------+------+---+------+---+------+------+
7025 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7026 * +-----+----+-----------------+------+---+------+---+------+------+
7028 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7030 int rd
= extract32(insn
, 0, 5);
7031 int rn
= extract32(insn
, 5, 5);
7032 int imm4
= extract32(insn
, 11, 4);
7033 int imm5
= extract32(insn
, 16, 5);
7034 int op
= extract32(insn
, 29, 1);
7036 if (op
!= 0 || imm4
!= 0) {
7037 unallocated_encoding(s
);
7041 /* DUP (element, scalar) */
7042 handle_simd_dupes(s
, rd
, rn
, imm5
);
7045 /* AdvSIMD scalar pairwise
7046 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7047 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7048 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7049 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7051 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7053 int u
= extract32(insn
, 29, 1);
7054 int size
= extract32(insn
, 22, 2);
7055 int opcode
= extract32(insn
, 12, 5);
7056 int rn
= extract32(insn
, 5, 5);
7057 int rd
= extract32(insn
, 0, 5);
7060 /* For some ops (the FP ones), size[1] is part of the encoding.
7061 * For ADDP strictly it is not but size[1] is always 1 for valid
7064 opcode
|= (extract32(size
, 1, 1) << 5);
7067 case 0x3b: /* ADDP */
7068 if (u
|| size
!= 3) {
7069 unallocated_encoding(s
);
7072 if (!fp_access_check(s
)) {
7078 case 0xc: /* FMAXNMP */
7079 case 0xd: /* FADDP */
7080 case 0xf: /* FMAXP */
7081 case 0x2c: /* FMINNMP */
7082 case 0x2f: /* FMINP */
7083 /* FP op, size[0] is 32 or 64 bit*/
7085 if (!dc_isar_feature(aa64_fp16
, s
)) {
7086 unallocated_encoding(s
);
7092 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7095 if (!fp_access_check(s
)) {
7099 fpst
= get_fpstatus_ptr(size
== MO_16
);
7102 unallocated_encoding(s
);
7106 if (size
== MO_64
) {
7107 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7108 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7109 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7111 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7112 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7115 case 0x3b: /* ADDP */
7116 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7118 case 0xc: /* FMAXNMP */
7119 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7121 case 0xd: /* FADDP */
7122 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7124 case 0xf: /* FMAXP */
7125 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7127 case 0x2c: /* FMINNMP */
7128 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7130 case 0x2f: /* FMINP */
7131 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7134 g_assert_not_reached();
7137 write_fp_dreg(s
, rd
, tcg_res
);
7139 tcg_temp_free_i64(tcg_op1
);
7140 tcg_temp_free_i64(tcg_op2
);
7141 tcg_temp_free_i64(tcg_res
);
7143 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7144 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7145 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7147 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7148 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7150 if (size
== MO_16
) {
7152 case 0xc: /* FMAXNMP */
7153 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7155 case 0xd: /* FADDP */
7156 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7158 case 0xf: /* FMAXP */
7159 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7161 case 0x2c: /* FMINNMP */
7162 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7164 case 0x2f: /* FMINP */
7165 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7168 g_assert_not_reached();
7172 case 0xc: /* FMAXNMP */
7173 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7175 case 0xd: /* FADDP */
7176 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7178 case 0xf: /* FMAXP */
7179 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7181 case 0x2c: /* FMINNMP */
7182 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7184 case 0x2f: /* FMINP */
7185 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7188 g_assert_not_reached();
7192 write_fp_sreg(s
, rd
, tcg_res
);
7194 tcg_temp_free_i32(tcg_op1
);
7195 tcg_temp_free_i32(tcg_op2
);
7196 tcg_temp_free_i32(tcg_res
);
7200 tcg_temp_free_ptr(fpst
);
7205 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7207 * This code is handles the common shifting code and is used by both
7208 * the vector and scalar code.
7210 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7211 TCGv_i64 tcg_rnd
, bool accumulate
,
7212 bool is_u
, int size
, int shift
)
7214 bool extended_result
= false;
7215 bool round
= tcg_rnd
!= NULL
;
7217 TCGv_i64 tcg_src_hi
;
7219 if (round
&& size
== 3) {
7220 extended_result
= true;
7221 ext_lshift
= 64 - shift
;
7222 tcg_src_hi
= tcg_temp_new_i64();
7223 } else if (shift
== 64) {
7224 if (!accumulate
&& is_u
) {
7225 /* result is zero */
7226 tcg_gen_movi_i64(tcg_res
, 0);
7231 /* Deal with the rounding step */
7233 if (extended_result
) {
7234 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7236 /* take care of sign extending tcg_res */
7237 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7238 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7239 tcg_src
, tcg_src_hi
,
7242 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7246 tcg_temp_free_i64(tcg_zero
);
7248 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7252 /* Now do the shift right */
7253 if (round
&& extended_result
) {
7254 /* extended case, >64 bit precision required */
7255 if (ext_lshift
== 0) {
7256 /* special case, only high bits matter */
7257 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7259 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7260 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7261 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7266 /* essentially shifting in 64 zeros */
7267 tcg_gen_movi_i64(tcg_src
, 0);
7269 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7273 /* effectively extending the sign-bit */
7274 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7276 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7282 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7284 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7287 if (extended_result
) {
7288 tcg_temp_free_i64(tcg_src_hi
);
7292 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7293 static void handle_scalar_simd_shri(DisasContext
*s
,
7294 bool is_u
, int immh
, int immb
,
7295 int opcode
, int rn
, int rd
)
7298 int immhb
= immh
<< 3 | immb
;
7299 int shift
= 2 * (8 << size
) - immhb
;
7300 bool accumulate
= false;
7302 bool insert
= false;
7307 if (!extract32(immh
, 3, 1)) {
7308 unallocated_encoding(s
);
7312 if (!fp_access_check(s
)) {
7317 case 0x02: /* SSRA / USRA (accumulate) */
7320 case 0x04: /* SRSHR / URSHR (rounding) */
7323 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7324 accumulate
= round
= true;
7326 case 0x08: /* SRI */
7332 uint64_t round_const
= 1ULL << (shift
- 1);
7333 tcg_round
= tcg_const_i64(round_const
);
7338 tcg_rn
= read_fp_dreg(s
, rn
);
7339 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7342 /* shift count same as element size is valid but does nothing;
7343 * special case to avoid potential shift by 64.
7345 int esize
= 8 << size
;
7346 if (shift
!= esize
) {
7347 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7348 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7351 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7352 accumulate
, is_u
, size
, shift
);
7355 write_fp_dreg(s
, rd
, tcg_rd
);
7357 tcg_temp_free_i64(tcg_rn
);
7358 tcg_temp_free_i64(tcg_rd
);
7360 tcg_temp_free_i64(tcg_round
);
7364 /* SHL/SLI - Scalar shift left */
7365 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7366 int immh
, int immb
, int opcode
,
7369 int size
= 32 - clz32(immh
) - 1;
7370 int immhb
= immh
<< 3 | immb
;
7371 int shift
= immhb
- (8 << size
);
7372 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7373 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7375 if (!extract32(immh
, 3, 1)) {
7376 unallocated_encoding(s
);
7380 if (!fp_access_check(s
)) {
7384 tcg_rn
= read_fp_dreg(s
, rn
);
7385 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7388 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7390 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7393 write_fp_dreg(s
, rd
, tcg_rd
);
7395 tcg_temp_free_i64(tcg_rn
);
7396 tcg_temp_free_i64(tcg_rd
);
7399 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7400 * (signed/unsigned) narrowing */
7401 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7402 bool is_u_shift
, bool is_u_narrow
,
7403 int immh
, int immb
, int opcode
,
7406 int immhb
= immh
<< 3 | immb
;
7407 int size
= 32 - clz32(immh
) - 1;
7408 int esize
= 8 << size
;
7409 int shift
= (2 * esize
) - immhb
;
7410 int elements
= is_scalar
? 1 : (64 / esize
);
7411 bool round
= extract32(opcode
, 0, 1);
7412 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7413 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7414 TCGv_i32 tcg_rd_narrowed
;
7417 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7418 { gen_helper_neon_narrow_sat_s8
,
7419 gen_helper_neon_unarrow_sat8
},
7420 { gen_helper_neon_narrow_sat_s16
,
7421 gen_helper_neon_unarrow_sat16
},
7422 { gen_helper_neon_narrow_sat_s32
,
7423 gen_helper_neon_unarrow_sat32
},
7426 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7427 gen_helper_neon_narrow_sat_u8
,
7428 gen_helper_neon_narrow_sat_u16
,
7429 gen_helper_neon_narrow_sat_u32
,
7432 NeonGenNarrowEnvFn
*narrowfn
;
7438 if (extract32(immh
, 3, 1)) {
7439 unallocated_encoding(s
);
7443 if (!fp_access_check(s
)) {
7448 narrowfn
= unsigned_narrow_fns
[size
];
7450 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7453 tcg_rn
= tcg_temp_new_i64();
7454 tcg_rd
= tcg_temp_new_i64();
7455 tcg_rd_narrowed
= tcg_temp_new_i32();
7456 tcg_final
= tcg_const_i64(0);
7459 uint64_t round_const
= 1ULL << (shift
- 1);
7460 tcg_round
= tcg_const_i64(round_const
);
7465 for (i
= 0; i
< elements
; i
++) {
7466 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7467 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7468 false, is_u_shift
, size
+1, shift
);
7469 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7470 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7471 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7475 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7477 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7481 tcg_temp_free_i64(tcg_round
);
7483 tcg_temp_free_i64(tcg_rn
);
7484 tcg_temp_free_i64(tcg_rd
);
7485 tcg_temp_free_i32(tcg_rd_narrowed
);
7486 tcg_temp_free_i64(tcg_final
);
7488 clear_vec_high(s
, is_q
, rd
);
7491 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7492 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7493 bool src_unsigned
, bool dst_unsigned
,
7494 int immh
, int immb
, int rn
, int rd
)
7496 int immhb
= immh
<< 3 | immb
;
7497 int size
= 32 - clz32(immh
) - 1;
7498 int shift
= immhb
- (8 << size
);
7502 assert(!(scalar
&& is_q
));
7505 if (!is_q
&& extract32(immh
, 3, 1)) {
7506 unallocated_encoding(s
);
7510 /* Since we use the variable-shift helpers we must
7511 * replicate the shift count into each element of
7512 * the tcg_shift value.
7516 shift
|= shift
<< 8;
7519 shift
|= shift
<< 16;
7525 g_assert_not_reached();
7529 if (!fp_access_check(s
)) {
7534 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
7535 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
7536 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
7537 { NULL
, gen_helper_neon_qshl_u64
},
7539 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
7540 int maxpass
= is_q
? 2 : 1;
7542 for (pass
= 0; pass
< maxpass
; pass
++) {
7543 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7545 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7546 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7547 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7549 tcg_temp_free_i64(tcg_op
);
7551 tcg_temp_free_i64(tcg_shift
);
7552 clear_vec_high(s
, is_q
, rd
);
7554 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
7555 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
7557 { gen_helper_neon_qshl_s8
,
7558 gen_helper_neon_qshl_s16
,
7559 gen_helper_neon_qshl_s32
},
7560 { gen_helper_neon_qshlu_s8
,
7561 gen_helper_neon_qshlu_s16
,
7562 gen_helper_neon_qshlu_s32
}
7564 { NULL
, NULL
, NULL
},
7565 { gen_helper_neon_qshl_u8
,
7566 gen_helper_neon_qshl_u16
,
7567 gen_helper_neon_qshl_u32
}
7570 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
7571 TCGMemOp memop
= scalar
? size
: MO_32
;
7572 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
7574 for (pass
= 0; pass
< maxpass
; pass
++) {
7575 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7577 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
7578 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7582 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
7585 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
7590 g_assert_not_reached();
7592 write_fp_sreg(s
, rd
, tcg_op
);
7594 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7597 tcg_temp_free_i32(tcg_op
);
7599 tcg_temp_free_i32(tcg_shift
);
7602 clear_vec_high(s
, is_q
, rd
);
7607 /* Common vector code for handling integer to FP conversion */
7608 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
7609 int elements
, int is_signed
,
7610 int fracbits
, int size
)
7612 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
7613 TCGv_i32 tcg_shift
= NULL
;
7615 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
7618 if (fracbits
|| size
== MO_64
) {
7619 tcg_shift
= tcg_const_i32(fracbits
);
7622 if (size
== MO_64
) {
7623 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
7624 TCGv_i64 tcg_double
= tcg_temp_new_i64();
7626 for (pass
= 0; pass
< elements
; pass
++) {
7627 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
7630 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
7631 tcg_shift
, tcg_fpst
);
7633 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
7634 tcg_shift
, tcg_fpst
);
7636 if (elements
== 1) {
7637 write_fp_dreg(s
, rd
, tcg_double
);
7639 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
7643 tcg_temp_free_i64(tcg_int64
);
7644 tcg_temp_free_i64(tcg_double
);
7647 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
7648 TCGv_i32 tcg_float
= tcg_temp_new_i32();
7650 for (pass
= 0; pass
< elements
; pass
++) {
7651 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
7657 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
7658 tcg_shift
, tcg_fpst
);
7660 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
7661 tcg_shift
, tcg_fpst
);
7665 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
7667 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
7674 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
7675 tcg_shift
, tcg_fpst
);
7677 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
7678 tcg_shift
, tcg_fpst
);
7682 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7684 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7689 g_assert_not_reached();
7692 if (elements
== 1) {
7693 write_fp_sreg(s
, rd
, tcg_float
);
7695 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
7699 tcg_temp_free_i32(tcg_int32
);
7700 tcg_temp_free_i32(tcg_float
);
7703 tcg_temp_free_ptr(tcg_fpst
);
7705 tcg_temp_free_i32(tcg_shift
);
7708 clear_vec_high(s
, elements
<< size
== 16, rd
);
7711 /* UCVTF/SCVTF - Integer to FP conversion */
7712 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
7713 bool is_q
, bool is_u
,
7714 int immh
, int immb
, int opcode
,
7717 int size
, elements
, fracbits
;
7718 int immhb
= immh
<< 3 | immb
;
7722 if (!is_scalar
&& !is_q
) {
7723 unallocated_encoding(s
);
7726 } else if (immh
& 4) {
7728 } else if (immh
& 2) {
7730 if (!dc_isar_feature(aa64_fp16
, s
)) {
7731 unallocated_encoding(s
);
7735 /* immh == 0 would be a failure of the decode logic */
7736 g_assert(immh
== 1);
7737 unallocated_encoding(s
);
7744 elements
= (8 << is_q
) >> size
;
7746 fracbits
= (16 << size
) - immhb
;
7748 if (!fp_access_check(s
)) {
7752 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
7755 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
7756 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
7757 bool is_q
, bool is_u
,
7758 int immh
, int immb
, int rn
, int rd
)
7760 int immhb
= immh
<< 3 | immb
;
7761 int pass
, size
, fracbits
;
7762 TCGv_ptr tcg_fpstatus
;
7763 TCGv_i32 tcg_rmode
, tcg_shift
;
7767 if (!is_scalar
&& !is_q
) {
7768 unallocated_encoding(s
);
7771 } else if (immh
& 0x4) {
7773 } else if (immh
& 0x2) {
7775 if (!dc_isar_feature(aa64_fp16
, s
)) {
7776 unallocated_encoding(s
);
7780 /* Should have split out AdvSIMD modified immediate earlier. */
7782 unallocated_encoding(s
);
7786 if (!fp_access_check(s
)) {
7790 assert(!(is_scalar
&& is_q
));
7792 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
7793 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
7794 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7795 fracbits
= (16 << size
) - immhb
;
7796 tcg_shift
= tcg_const_i32(fracbits
);
7798 if (size
== MO_64
) {
7799 int maxpass
= is_scalar
? 1 : 2;
7801 for (pass
= 0; pass
< maxpass
; pass
++) {
7802 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7804 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7806 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7808 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7810 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7811 tcg_temp_free_i64(tcg_op
);
7813 clear_vec_high(s
, is_q
, rd
);
7815 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
7816 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
7821 fn
= gen_helper_vfp_touhh
;
7823 fn
= gen_helper_vfp_toshh
;
7828 fn
= gen_helper_vfp_touls
;
7830 fn
= gen_helper_vfp_tosls
;
7834 g_assert_not_reached();
7837 for (pass
= 0; pass
< maxpass
; pass
++) {
7838 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7840 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
7841 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7843 write_fp_sreg(s
, rd
, tcg_op
);
7845 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
7847 tcg_temp_free_i32(tcg_op
);
7850 clear_vec_high(s
, is_q
, rd
);
7854 tcg_temp_free_ptr(tcg_fpstatus
);
7855 tcg_temp_free_i32(tcg_shift
);
7856 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7857 tcg_temp_free_i32(tcg_rmode
);
7860 /* AdvSIMD scalar shift by immediate
7861 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7862 * +-----+---+-------------+------+------+--------+---+------+------+
7863 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7864 * +-----+---+-------------+------+------+--------+---+------+------+
7866 * This is the scalar version so it works on a fixed sized registers
7868 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
7870 int rd
= extract32(insn
, 0, 5);
7871 int rn
= extract32(insn
, 5, 5);
7872 int opcode
= extract32(insn
, 11, 5);
7873 int immb
= extract32(insn
, 16, 3);
7874 int immh
= extract32(insn
, 19, 4);
7875 bool is_u
= extract32(insn
, 29, 1);
7878 unallocated_encoding(s
);
7883 case 0x08: /* SRI */
7885 unallocated_encoding(s
);
7889 case 0x00: /* SSHR / USHR */
7890 case 0x02: /* SSRA / USRA */
7891 case 0x04: /* SRSHR / URSHR */
7892 case 0x06: /* SRSRA / URSRA */
7893 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7895 case 0x0a: /* SHL / SLI */
7896 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7898 case 0x1c: /* SCVTF, UCVTF */
7899 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7902 case 0x10: /* SQSHRUN, SQSHRUN2 */
7903 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7905 unallocated_encoding(s
);
7908 handle_vec_simd_sqshrn(s
, true, false, false, true,
7909 immh
, immb
, opcode
, rn
, rd
);
7911 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7912 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7913 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7914 immh
, immb
, opcode
, rn
, rd
);
7916 case 0xc: /* SQSHLU */
7918 unallocated_encoding(s
);
7921 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7923 case 0xe: /* SQSHL, UQSHL */
7924 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7926 case 0x1f: /* FCVTZS, FCVTZU */
7927 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7930 unallocated_encoding(s
);
7935 /* AdvSIMD scalar three different
7936 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7937 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7938 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7939 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7941 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7943 bool is_u
= extract32(insn
, 29, 1);
7944 int size
= extract32(insn
, 22, 2);
7945 int opcode
= extract32(insn
, 12, 4);
7946 int rm
= extract32(insn
, 16, 5);
7947 int rn
= extract32(insn
, 5, 5);
7948 int rd
= extract32(insn
, 0, 5);
7951 unallocated_encoding(s
);
7956 case 0x9: /* SQDMLAL, SQDMLAL2 */
7957 case 0xb: /* SQDMLSL, SQDMLSL2 */
7958 case 0xd: /* SQDMULL, SQDMULL2 */
7959 if (size
== 0 || size
== 3) {
7960 unallocated_encoding(s
);
7965 unallocated_encoding(s
);
7969 if (!fp_access_check(s
)) {
7974 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7975 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7976 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7978 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7979 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7981 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7982 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7985 case 0xd: /* SQDMULL, SQDMULL2 */
7987 case 0xb: /* SQDMLSL, SQDMLSL2 */
7988 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7990 case 0x9: /* SQDMLAL, SQDMLAL2 */
7991 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7992 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7996 g_assert_not_reached();
7999 write_fp_dreg(s
, rd
, tcg_res
);
8001 tcg_temp_free_i64(tcg_op1
);
8002 tcg_temp_free_i64(tcg_op2
);
8003 tcg_temp_free_i64(tcg_res
);
8005 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8006 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8007 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8009 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8010 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8013 case 0xd: /* SQDMULL, SQDMULL2 */
8015 case 0xb: /* SQDMLSL, SQDMLSL2 */
8016 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8018 case 0x9: /* SQDMLAL, SQDMLAL2 */
8020 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8021 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8022 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8024 tcg_temp_free_i64(tcg_op3
);
8028 g_assert_not_reached();
8031 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8032 write_fp_dreg(s
, rd
, tcg_res
);
8034 tcg_temp_free_i32(tcg_op1
);
8035 tcg_temp_free_i32(tcg_op2
);
8036 tcg_temp_free_i64(tcg_res
);
8040 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8041 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8043 /* Handle 64x64->64 opcodes which are shared between the scalar
8044 * and vector 3-same groups. We cover every opcode where size == 3
8045 * is valid in either the three-reg-same (integer, not pairwise)
8046 * or scalar-three-reg-same groups.
8051 case 0x1: /* SQADD */
8053 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8055 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8058 case 0x5: /* SQSUB */
8060 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8062 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8065 case 0x6: /* CMGT, CMHI */
8066 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8067 * We implement this using setcond (test) and then negating.
8069 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8071 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8072 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8074 case 0x7: /* CMGE, CMHS */
8075 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8077 case 0x11: /* CMTST, CMEQ */
8082 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8084 case 0x8: /* SSHL, USHL */
8086 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8088 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8091 case 0x9: /* SQSHL, UQSHL */
8093 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8095 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8098 case 0xa: /* SRSHL, URSHL */
8100 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8102 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8105 case 0xb: /* SQRSHL, UQRSHL */
8107 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8109 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8112 case 0x10: /* ADD, SUB */
8114 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8116 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8120 g_assert_not_reached();
8124 /* Handle the 3-same-operands float operations; shared by the scalar
8125 * and vector encodings. The caller must filter out any encodings
8126 * not allocated for the encoding it is dealing with.
8128 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8129 int fpopcode
, int rd
, int rn
, int rm
)
8132 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8134 for (pass
= 0; pass
< elements
; pass
++) {
8137 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8138 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8139 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8141 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8142 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8145 case 0x39: /* FMLS */
8146 /* As usual for ARM, separate negation for fused multiply-add */
8147 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8149 case 0x19: /* FMLA */
8150 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8151 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8154 case 0x18: /* FMAXNM */
8155 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8157 case 0x1a: /* FADD */
8158 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8160 case 0x1b: /* FMULX */
8161 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8163 case 0x1c: /* FCMEQ */
8164 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8166 case 0x1e: /* FMAX */
8167 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8169 case 0x1f: /* FRECPS */
8170 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8172 case 0x38: /* FMINNM */
8173 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8175 case 0x3a: /* FSUB */
8176 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8178 case 0x3e: /* FMIN */
8179 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8181 case 0x3f: /* FRSQRTS */
8182 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8184 case 0x5b: /* FMUL */
8185 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8187 case 0x5c: /* FCMGE */
8188 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8190 case 0x5d: /* FACGE */
8191 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8193 case 0x5f: /* FDIV */
8194 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8196 case 0x7a: /* FABD */
8197 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8198 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8200 case 0x7c: /* FCMGT */
8201 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8203 case 0x7d: /* FACGT */
8204 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8207 g_assert_not_reached();
8210 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8212 tcg_temp_free_i64(tcg_res
);
8213 tcg_temp_free_i64(tcg_op1
);
8214 tcg_temp_free_i64(tcg_op2
);
8217 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8218 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8219 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8221 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8222 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8225 case 0x39: /* FMLS */
8226 /* As usual for ARM, separate negation for fused multiply-add */
8227 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8229 case 0x19: /* FMLA */
8230 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8231 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8234 case 0x1a: /* FADD */
8235 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8237 case 0x1b: /* FMULX */
8238 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8240 case 0x1c: /* FCMEQ */
8241 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8243 case 0x1e: /* FMAX */
8244 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8246 case 0x1f: /* FRECPS */
8247 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8249 case 0x18: /* FMAXNM */
8250 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8252 case 0x38: /* FMINNM */
8253 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8255 case 0x3a: /* FSUB */
8256 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8258 case 0x3e: /* FMIN */
8259 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8261 case 0x3f: /* FRSQRTS */
8262 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8264 case 0x5b: /* FMUL */
8265 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8267 case 0x5c: /* FCMGE */
8268 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8270 case 0x5d: /* FACGE */
8271 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8273 case 0x5f: /* FDIV */
8274 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8276 case 0x7a: /* FABD */
8277 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8278 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8280 case 0x7c: /* FCMGT */
8281 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8283 case 0x7d: /* FACGT */
8284 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8287 g_assert_not_reached();
8290 if (elements
== 1) {
8291 /* scalar single so clear high part */
8292 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8294 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8295 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8296 tcg_temp_free_i64(tcg_tmp
);
8298 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8301 tcg_temp_free_i32(tcg_res
);
8302 tcg_temp_free_i32(tcg_op1
);
8303 tcg_temp_free_i32(tcg_op2
);
8307 tcg_temp_free_ptr(fpst
);
8309 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8312 /* AdvSIMD scalar three same
8313 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8314 * +-----+---+-----------+------+---+------+--------+---+------+------+
8315 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8316 * +-----+---+-----------+------+---+------+--------+---+------+------+
8318 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8320 int rd
= extract32(insn
, 0, 5);
8321 int rn
= extract32(insn
, 5, 5);
8322 int opcode
= extract32(insn
, 11, 5);
8323 int rm
= extract32(insn
, 16, 5);
8324 int size
= extract32(insn
, 22, 2);
8325 bool u
= extract32(insn
, 29, 1);
8328 if (opcode
>= 0x18) {
8329 /* Floating point: U, size[1] and opcode indicate operation */
8330 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8332 case 0x1b: /* FMULX */
8333 case 0x1f: /* FRECPS */
8334 case 0x3f: /* FRSQRTS */
8335 case 0x5d: /* FACGE */
8336 case 0x7d: /* FACGT */
8337 case 0x1c: /* FCMEQ */
8338 case 0x5c: /* FCMGE */
8339 case 0x7c: /* FCMGT */
8340 case 0x7a: /* FABD */
8343 unallocated_encoding(s
);
8347 if (!fp_access_check(s
)) {
8351 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8356 case 0x1: /* SQADD, UQADD */
8357 case 0x5: /* SQSUB, UQSUB */
8358 case 0x9: /* SQSHL, UQSHL */
8359 case 0xb: /* SQRSHL, UQRSHL */
8361 case 0x8: /* SSHL, USHL */
8362 case 0xa: /* SRSHL, URSHL */
8363 case 0x6: /* CMGT, CMHI */
8364 case 0x7: /* CMGE, CMHS */
8365 case 0x11: /* CMTST, CMEQ */
8366 case 0x10: /* ADD, SUB (vector) */
8368 unallocated_encoding(s
);
8372 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8373 if (size
!= 1 && size
!= 2) {
8374 unallocated_encoding(s
);
8379 unallocated_encoding(s
);
8383 if (!fp_access_check(s
)) {
8387 tcg_rd
= tcg_temp_new_i64();
8390 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8391 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8393 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8394 tcg_temp_free_i64(tcg_rn
);
8395 tcg_temp_free_i64(tcg_rm
);
8397 /* Do a single operation on the lowest element in the vector.
8398 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8399 * no side effects for all these operations.
8400 * OPTME: special-purpose helpers would avoid doing some
8401 * unnecessary work in the helper for the 8 and 16 bit cases.
8403 NeonGenTwoOpEnvFn
*genenvfn
;
8404 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8405 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8406 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8408 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8409 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8412 case 0x1: /* SQADD, UQADD */
8414 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8415 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8416 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8417 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8419 genenvfn
= fns
[size
][u
];
8422 case 0x5: /* SQSUB, UQSUB */
8424 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8425 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8426 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8427 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8429 genenvfn
= fns
[size
][u
];
8432 case 0x9: /* SQSHL, UQSHL */
8434 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8435 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8436 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8437 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8439 genenvfn
= fns
[size
][u
];
8442 case 0xb: /* SQRSHL, UQRSHL */
8444 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8445 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8446 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8447 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8449 genenvfn
= fns
[size
][u
];
8452 case 0x16: /* SQDMULH, SQRDMULH */
8454 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8455 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8456 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8458 assert(size
== 1 || size
== 2);
8459 genenvfn
= fns
[size
- 1][u
];
8463 g_assert_not_reached();
8466 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8467 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8468 tcg_temp_free_i32(tcg_rd32
);
8469 tcg_temp_free_i32(tcg_rn
);
8470 tcg_temp_free_i32(tcg_rm
);
8473 write_fp_dreg(s
, rd
, tcg_rd
);
8475 tcg_temp_free_i64(tcg_rd
);
8478 /* AdvSIMD scalar three same FP16
8479 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8480 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8481 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8482 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8483 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8484 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8486 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8489 int rd
= extract32(insn
, 0, 5);
8490 int rn
= extract32(insn
, 5, 5);
8491 int opcode
= extract32(insn
, 11, 3);
8492 int rm
= extract32(insn
, 16, 5);
8493 bool u
= extract32(insn
, 29, 1);
8494 bool a
= extract32(insn
, 23, 1);
8495 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8502 case 0x03: /* FMULX */
8503 case 0x04: /* FCMEQ (reg) */
8504 case 0x07: /* FRECPS */
8505 case 0x0f: /* FRSQRTS */
8506 case 0x14: /* FCMGE (reg) */
8507 case 0x15: /* FACGE */
8508 case 0x1a: /* FABD */
8509 case 0x1c: /* FCMGT (reg) */
8510 case 0x1d: /* FACGT */
8513 unallocated_encoding(s
);
8517 if (!dc_isar_feature(aa64_fp16
, s
)) {
8518 unallocated_encoding(s
);
8521 if (!fp_access_check(s
)) {
8525 fpst
= get_fpstatus_ptr(true);
8527 tcg_op1
= read_fp_hreg(s
, rn
);
8528 tcg_op2
= read_fp_hreg(s
, rm
);
8529 tcg_res
= tcg_temp_new_i32();
8532 case 0x03: /* FMULX */
8533 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8535 case 0x04: /* FCMEQ (reg) */
8536 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8538 case 0x07: /* FRECPS */
8539 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8541 case 0x0f: /* FRSQRTS */
8542 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8544 case 0x14: /* FCMGE (reg) */
8545 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8547 case 0x15: /* FACGE */
8548 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8550 case 0x1a: /* FABD */
8551 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8552 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
8554 case 0x1c: /* FCMGT (reg) */
8555 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8557 case 0x1d: /* FACGT */
8558 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8561 g_assert_not_reached();
8564 write_fp_sreg(s
, rd
, tcg_res
);
8567 tcg_temp_free_i32(tcg_res
);
8568 tcg_temp_free_i32(tcg_op1
);
8569 tcg_temp_free_i32(tcg_op2
);
8570 tcg_temp_free_ptr(fpst
);
8573 /* AdvSIMD scalar three same extra
8574 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8575 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8576 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8577 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8579 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
8582 int rd
= extract32(insn
, 0, 5);
8583 int rn
= extract32(insn
, 5, 5);
8584 int opcode
= extract32(insn
, 11, 4);
8585 int rm
= extract32(insn
, 16, 5);
8586 int size
= extract32(insn
, 22, 2);
8587 bool u
= extract32(insn
, 29, 1);
8588 TCGv_i32 ele1
, ele2
, ele3
;
8592 switch (u
* 16 + opcode
) {
8593 case 0x10: /* SQRDMLAH (vector) */
8594 case 0x11: /* SQRDMLSH (vector) */
8595 if (size
!= 1 && size
!= 2) {
8596 unallocated_encoding(s
);
8599 feature
= dc_isar_feature(aa64_rdm
, s
);
8602 unallocated_encoding(s
);
8606 unallocated_encoding(s
);
8609 if (!fp_access_check(s
)) {
8613 /* Do a single operation on the lowest element in the vector.
8614 * We use the standard Neon helpers and rely on 0 OP 0 == 0
8615 * with no side effects for all these operations.
8616 * OPTME: special-purpose helpers would avoid doing some
8617 * unnecessary work in the helper for the 16 bit cases.
8619 ele1
= tcg_temp_new_i32();
8620 ele2
= tcg_temp_new_i32();
8621 ele3
= tcg_temp_new_i32();
8623 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
8624 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
8625 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
8628 case 0x0: /* SQRDMLAH */
8630 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8632 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8635 case 0x1: /* SQRDMLSH */
8637 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8639 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8643 g_assert_not_reached();
8645 tcg_temp_free_i32(ele1
);
8646 tcg_temp_free_i32(ele2
);
8648 res
= tcg_temp_new_i64();
8649 tcg_gen_extu_i32_i64(res
, ele3
);
8650 tcg_temp_free_i32(ele3
);
8652 write_fp_dreg(s
, rd
, res
);
8653 tcg_temp_free_i64(res
);
8656 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
8657 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
8658 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
8660 /* Handle 64->64 opcodes which are shared between the scalar and
8661 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
8662 * is valid in either group and also the double-precision fp ops.
8663 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
8669 case 0x4: /* CLS, CLZ */
8671 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
8673 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
8677 /* This opcode is shared with CNT and RBIT but we have earlier
8678 * enforced that size == 3 if and only if this is the NOT insn.
8680 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
8682 case 0x7: /* SQABS, SQNEG */
8684 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
8686 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
8689 case 0xa: /* CMLT */
8690 /* 64 bit integer comparison against zero, result is
8691 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
8696 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
8697 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8699 case 0x8: /* CMGT, CMGE */
8700 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
8702 case 0x9: /* CMEQ, CMLE */
8703 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
8705 case 0xb: /* ABS, NEG */
8707 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8709 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8710 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8711 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
8713 tcg_temp_free_i64(tcg_zero
);
8716 case 0x2f: /* FABS */
8717 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
8719 case 0x6f: /* FNEG */
8720 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
8722 case 0x7f: /* FSQRT */
8723 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
8725 case 0x1a: /* FCVTNS */
8726 case 0x1b: /* FCVTMS */
8727 case 0x1c: /* FCVTAS */
8728 case 0x3a: /* FCVTPS */
8729 case 0x3b: /* FCVTZS */
8731 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8732 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8733 tcg_temp_free_i32(tcg_shift
);
8736 case 0x5a: /* FCVTNU */
8737 case 0x5b: /* FCVTMU */
8738 case 0x5c: /* FCVTAU */
8739 case 0x7a: /* FCVTPU */
8740 case 0x7b: /* FCVTZU */
8742 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8743 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8744 tcg_temp_free_i32(tcg_shift
);
8747 case 0x18: /* FRINTN */
8748 case 0x19: /* FRINTM */
8749 case 0x38: /* FRINTP */
8750 case 0x39: /* FRINTZ */
8751 case 0x58: /* FRINTA */
8752 case 0x79: /* FRINTI */
8753 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8755 case 0x59: /* FRINTX */
8756 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8759 g_assert_not_reached();
8763 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
8764 bool is_scalar
, bool is_u
, bool is_q
,
8765 int size
, int rn
, int rd
)
8767 bool is_double
= (size
== MO_64
);
8770 if (!fp_access_check(s
)) {
8774 fpst
= get_fpstatus_ptr(size
== MO_16
);
8777 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8778 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8779 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8780 NeonGenTwoDoubleOPFn
*genfn
;
8785 case 0x2e: /* FCMLT (zero) */
8788 case 0x2c: /* FCMGT (zero) */
8789 genfn
= gen_helper_neon_cgt_f64
;
8791 case 0x2d: /* FCMEQ (zero) */
8792 genfn
= gen_helper_neon_ceq_f64
;
8794 case 0x6d: /* FCMLE (zero) */
8797 case 0x6c: /* FCMGE (zero) */
8798 genfn
= gen_helper_neon_cge_f64
;
8801 g_assert_not_reached();
8804 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8805 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8807 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8809 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8811 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8813 tcg_temp_free_i64(tcg_res
);
8814 tcg_temp_free_i64(tcg_zero
);
8815 tcg_temp_free_i64(tcg_op
);
8817 clear_vec_high(s
, !is_scalar
, rd
);
8819 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8820 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8821 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8822 NeonGenTwoSingleOPFn
*genfn
;
8824 int pass
, maxpasses
;
8826 if (size
== MO_16
) {
8828 case 0x2e: /* FCMLT (zero) */
8831 case 0x2c: /* FCMGT (zero) */
8832 genfn
= gen_helper_advsimd_cgt_f16
;
8834 case 0x2d: /* FCMEQ (zero) */
8835 genfn
= gen_helper_advsimd_ceq_f16
;
8837 case 0x6d: /* FCMLE (zero) */
8840 case 0x6c: /* FCMGE (zero) */
8841 genfn
= gen_helper_advsimd_cge_f16
;
8844 g_assert_not_reached();
8848 case 0x2e: /* FCMLT (zero) */
8851 case 0x2c: /* FCMGT (zero) */
8852 genfn
= gen_helper_neon_cgt_f32
;
8854 case 0x2d: /* FCMEQ (zero) */
8855 genfn
= gen_helper_neon_ceq_f32
;
8857 case 0x6d: /* FCMLE (zero) */
8860 case 0x6c: /* FCMGE (zero) */
8861 genfn
= gen_helper_neon_cge_f32
;
8864 g_assert_not_reached();
8871 int vector_size
= 8 << is_q
;
8872 maxpasses
= vector_size
>> size
;
8875 for (pass
= 0; pass
< maxpasses
; pass
++) {
8876 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8878 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8880 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8883 write_fp_sreg(s
, rd
, tcg_res
);
8885 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
8888 tcg_temp_free_i32(tcg_res
);
8889 tcg_temp_free_i32(tcg_zero
);
8890 tcg_temp_free_i32(tcg_op
);
8892 clear_vec_high(s
, is_q
, rd
);
8896 tcg_temp_free_ptr(fpst
);
8899 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
8900 bool is_scalar
, bool is_u
, bool is_q
,
8901 int size
, int rn
, int rd
)
8903 bool is_double
= (size
== 3);
8904 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8907 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8908 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8911 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8912 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8914 case 0x3d: /* FRECPE */
8915 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
8917 case 0x3f: /* FRECPX */
8918 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
8920 case 0x7d: /* FRSQRTE */
8921 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
8924 g_assert_not_reached();
8926 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8928 tcg_temp_free_i64(tcg_res
);
8929 tcg_temp_free_i64(tcg_op
);
8930 clear_vec_high(s
, !is_scalar
, rd
);
8932 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8933 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8934 int pass
, maxpasses
;
8939 maxpasses
= is_q
? 4 : 2;
8942 for (pass
= 0; pass
< maxpasses
; pass
++) {
8943 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
8946 case 0x3c: /* URECPE */
8947 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
8949 case 0x3d: /* FRECPE */
8950 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
8952 case 0x3f: /* FRECPX */
8953 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
8955 case 0x7d: /* FRSQRTE */
8956 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
8959 g_assert_not_reached();
8963 write_fp_sreg(s
, rd
, tcg_res
);
8965 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8968 tcg_temp_free_i32(tcg_res
);
8969 tcg_temp_free_i32(tcg_op
);
8971 clear_vec_high(s
, is_q
, rd
);
8974 tcg_temp_free_ptr(fpst
);
8977 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
8978 int opcode
, bool u
, bool is_q
,
8979 int size
, int rn
, int rd
)
8981 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8982 * in the source becomes a size element in the destination).
8985 TCGv_i32 tcg_res
[2];
8986 int destelt
= is_q
? 2 : 0;
8987 int passes
= scalar
? 1 : 2;
8990 tcg_res
[1] = tcg_const_i32(0);
8993 for (pass
= 0; pass
< passes
; pass
++) {
8994 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8995 NeonGenNarrowFn
*genfn
= NULL
;
8996 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
8999 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9001 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9003 tcg_res
[pass
] = tcg_temp_new_i32();
9006 case 0x12: /* XTN, SQXTUN */
9008 static NeonGenNarrowFn
* const xtnfns
[3] = {
9009 gen_helper_neon_narrow_u8
,
9010 gen_helper_neon_narrow_u16
,
9011 tcg_gen_extrl_i64_i32
,
9013 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9014 gen_helper_neon_unarrow_sat8
,
9015 gen_helper_neon_unarrow_sat16
,
9016 gen_helper_neon_unarrow_sat32
,
9019 genenvfn
= sqxtunfns
[size
];
9021 genfn
= xtnfns
[size
];
9025 case 0x14: /* SQXTN, UQXTN */
9027 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9028 { gen_helper_neon_narrow_sat_s8
,
9029 gen_helper_neon_narrow_sat_u8
},
9030 { gen_helper_neon_narrow_sat_s16
,
9031 gen_helper_neon_narrow_sat_u16
},
9032 { gen_helper_neon_narrow_sat_s32
,
9033 gen_helper_neon_narrow_sat_u32
},
9035 genenvfn
= fns
[size
][u
];
9038 case 0x16: /* FCVTN, FCVTN2 */
9039 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9041 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9043 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9044 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9045 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9046 TCGv_i32 ahp
= get_ahp_flag();
9048 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9049 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9050 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9051 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9052 tcg_temp_free_i32(tcg_lo
);
9053 tcg_temp_free_i32(tcg_hi
);
9054 tcg_temp_free_ptr(fpst
);
9055 tcg_temp_free_i32(ahp
);
9058 case 0x56: /* FCVTXN, FCVTXN2 */
9059 /* 64 bit to 32 bit float conversion
9060 * with von Neumann rounding (round to odd)
9063 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9066 g_assert_not_reached();
9070 genfn(tcg_res
[pass
], tcg_op
);
9071 } else if (genenvfn
) {
9072 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9075 tcg_temp_free_i64(tcg_op
);
9078 for (pass
= 0; pass
< 2; pass
++) {
9079 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9080 tcg_temp_free_i32(tcg_res
[pass
]);
9082 clear_vec_high(s
, is_q
, rd
);
9085 /* Remaining saturating accumulating ops */
9086 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9087 bool is_q
, int size
, int rn
, int rd
)
9089 bool is_double
= (size
== 3);
9092 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9093 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9096 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9097 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9098 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9100 if (is_u
) { /* USQADD */
9101 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9102 } else { /* SUQADD */
9103 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9105 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9107 tcg_temp_free_i64(tcg_rd
);
9108 tcg_temp_free_i64(tcg_rn
);
9109 clear_vec_high(s
, !is_scalar
, rd
);
9111 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9112 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9113 int pass
, maxpasses
;
9118 maxpasses
= is_q
? 4 : 2;
9121 for (pass
= 0; pass
< maxpasses
; pass
++) {
9123 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9124 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9126 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9127 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9130 if (is_u
) { /* USQADD */
9133 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9136 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9139 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9142 g_assert_not_reached();
9144 } else { /* SUQADD */
9147 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9150 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9153 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9156 g_assert_not_reached();
9161 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9162 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9163 tcg_temp_free_i64(tcg_zero
);
9165 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9167 tcg_temp_free_i32(tcg_rd
);
9168 tcg_temp_free_i32(tcg_rn
);
9169 clear_vec_high(s
, is_q
, rd
);
9173 /* AdvSIMD scalar two reg misc
9174 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9175 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9176 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9177 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9179 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9181 int rd
= extract32(insn
, 0, 5);
9182 int rn
= extract32(insn
, 5, 5);
9183 int opcode
= extract32(insn
, 12, 5);
9184 int size
= extract32(insn
, 22, 2);
9185 bool u
= extract32(insn
, 29, 1);
9186 bool is_fcvt
= false;
9189 TCGv_ptr tcg_fpstatus
;
9192 case 0x3: /* USQADD / SUQADD*/
9193 if (!fp_access_check(s
)) {
9196 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9198 case 0x7: /* SQABS / SQNEG */
9200 case 0xa: /* CMLT */
9202 unallocated_encoding(s
);
9206 case 0x8: /* CMGT, CMGE */
9207 case 0x9: /* CMEQ, CMLE */
9208 case 0xb: /* ABS, NEG */
9210 unallocated_encoding(s
);
9214 case 0x12: /* SQXTUN */
9216 unallocated_encoding(s
);
9220 case 0x14: /* SQXTN, UQXTN */
9222 unallocated_encoding(s
);
9225 if (!fp_access_check(s
)) {
9228 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9233 /* Floating point: U, size[1] and opcode indicate operation;
9234 * size[0] indicates single or double precision.
9236 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9237 size
= extract32(size
, 0, 1) ? 3 : 2;
9239 case 0x2c: /* FCMGT (zero) */
9240 case 0x2d: /* FCMEQ (zero) */
9241 case 0x2e: /* FCMLT (zero) */
9242 case 0x6c: /* FCMGE (zero) */
9243 case 0x6d: /* FCMLE (zero) */
9244 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9246 case 0x1d: /* SCVTF */
9247 case 0x5d: /* UCVTF */
9249 bool is_signed
= (opcode
== 0x1d);
9250 if (!fp_access_check(s
)) {
9253 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9256 case 0x3d: /* FRECPE */
9257 case 0x3f: /* FRECPX */
9258 case 0x7d: /* FRSQRTE */
9259 if (!fp_access_check(s
)) {
9262 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9264 case 0x1a: /* FCVTNS */
9265 case 0x1b: /* FCVTMS */
9266 case 0x3a: /* FCVTPS */
9267 case 0x3b: /* FCVTZS */
9268 case 0x5a: /* FCVTNU */
9269 case 0x5b: /* FCVTMU */
9270 case 0x7a: /* FCVTPU */
9271 case 0x7b: /* FCVTZU */
9273 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9275 case 0x1c: /* FCVTAS */
9276 case 0x5c: /* FCVTAU */
9277 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9279 rmode
= FPROUNDING_TIEAWAY
;
9281 case 0x56: /* FCVTXN, FCVTXN2 */
9283 unallocated_encoding(s
);
9286 if (!fp_access_check(s
)) {
9289 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9292 unallocated_encoding(s
);
9297 unallocated_encoding(s
);
9301 if (!fp_access_check(s
)) {
9306 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9307 tcg_fpstatus
= get_fpstatus_ptr(false);
9308 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9311 tcg_fpstatus
= NULL
;
9315 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9316 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9318 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9319 write_fp_dreg(s
, rd
, tcg_rd
);
9320 tcg_temp_free_i64(tcg_rd
);
9321 tcg_temp_free_i64(tcg_rn
);
9323 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9324 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9326 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9329 case 0x7: /* SQABS, SQNEG */
9331 NeonGenOneOpEnvFn
*genfn
;
9332 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9333 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9334 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9335 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9337 genfn
= fns
[size
][u
];
9338 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9341 case 0x1a: /* FCVTNS */
9342 case 0x1b: /* FCVTMS */
9343 case 0x1c: /* FCVTAS */
9344 case 0x3a: /* FCVTPS */
9345 case 0x3b: /* FCVTZS */
9347 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9348 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9349 tcg_temp_free_i32(tcg_shift
);
9352 case 0x5a: /* FCVTNU */
9353 case 0x5b: /* FCVTMU */
9354 case 0x5c: /* FCVTAU */
9355 case 0x7a: /* FCVTPU */
9356 case 0x7b: /* FCVTZU */
9358 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9359 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9360 tcg_temp_free_i32(tcg_shift
);
9364 g_assert_not_reached();
9367 write_fp_sreg(s
, rd
, tcg_rd
);
9368 tcg_temp_free_i32(tcg_rd
);
9369 tcg_temp_free_i32(tcg_rn
);
9373 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9374 tcg_temp_free_i32(tcg_rmode
);
9375 tcg_temp_free_ptr(tcg_fpstatus
);
9379 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9380 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9381 int immh
, int immb
, int opcode
, int rn
, int rd
)
9383 int size
= 32 - clz32(immh
) - 1;
9384 int immhb
= immh
<< 3 | immb
;
9385 int shift
= 2 * (8 << size
) - immhb
;
9386 bool accumulate
= false;
9387 int dsize
= is_q
? 128 : 64;
9388 int esize
= 8 << size
;
9389 int elements
= dsize
/esize
;
9390 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9391 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9392 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9394 uint64_t round_const
;
9397 if (extract32(immh
, 3, 1) && !is_q
) {
9398 unallocated_encoding(s
);
9401 tcg_debug_assert(size
<= 3);
9403 if (!fp_access_check(s
)) {
9408 case 0x02: /* SSRA / USRA (accumulate) */
9410 /* Shift count same as element size produces zero to add. */
9411 if (shift
== 8 << size
) {
9414 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9416 /* Shift count same as element size produces all sign to add. */
9417 if (shift
== 8 << size
) {
9420 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9423 case 0x08: /* SRI */
9424 /* Shift count same as element size is valid but does nothing. */
9425 if (shift
== 8 << size
) {
9428 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9431 case 0x00: /* SSHR / USHR */
9433 if (shift
== 8 << size
) {
9434 /* Shift count the same size as element size produces zero. */
9435 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9436 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9438 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9441 /* Shift count the same size as element size produces all sign. */
9442 if (shift
== 8 << size
) {
9445 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9449 case 0x04: /* SRSHR / URSHR (rounding) */
9451 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9455 g_assert_not_reached();
9458 round_const
= 1ULL << (shift
- 1);
9459 tcg_round
= tcg_const_i64(round_const
);
9461 for (i
= 0; i
< elements
; i
++) {
9462 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9464 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9467 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9468 accumulate
, is_u
, size
, shift
);
9470 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9472 tcg_temp_free_i64(tcg_round
);
9475 clear_vec_high(s
, is_q
, rd
);
9478 /* SHL/SLI - Vector shift left */
9479 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9480 int immh
, int immb
, int opcode
, int rn
, int rd
)
9482 int size
= 32 - clz32(immh
) - 1;
9483 int immhb
= immh
<< 3 | immb
;
9484 int shift
= immhb
- (8 << size
);
9486 if (extract32(immh
, 3, 1) && !is_q
) {
9487 unallocated_encoding(s
);
9491 if (size
> 3 && !is_q
) {
9492 unallocated_encoding(s
);
9496 if (!fp_access_check(s
)) {
9501 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
9503 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9507 /* USHLL/SHLL - Vector shift left with widening */
9508 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
9509 int immh
, int immb
, int opcode
, int rn
, int rd
)
9511 int size
= 32 - clz32(immh
) - 1;
9512 int immhb
= immh
<< 3 | immb
;
9513 int shift
= immhb
- (8 << size
);
9515 int esize
= 8 << size
;
9516 int elements
= dsize
/esize
;
9517 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9518 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9522 unallocated_encoding(s
);
9526 if (!fp_access_check(s
)) {
9530 /* For the LL variants the store is larger than the load,
9531 * so if rd == rn we would overwrite parts of our input.
9532 * So load everything right now and use shifts in the main loop.
9534 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
9536 for (i
= 0; i
< elements
; i
++) {
9537 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
9538 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
9539 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
9540 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
9544 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9545 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
9546 int immh
, int immb
, int opcode
, int rn
, int rd
)
9548 int immhb
= immh
<< 3 | immb
;
9549 int size
= 32 - clz32(immh
) - 1;
9551 int esize
= 8 << size
;
9552 int elements
= dsize
/esize
;
9553 int shift
= (2 * esize
) - immhb
;
9554 bool round
= extract32(opcode
, 0, 1);
9555 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
9559 if (extract32(immh
, 3, 1)) {
9560 unallocated_encoding(s
);
9564 if (!fp_access_check(s
)) {
9568 tcg_rn
= tcg_temp_new_i64();
9569 tcg_rd
= tcg_temp_new_i64();
9570 tcg_final
= tcg_temp_new_i64();
9571 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
9574 uint64_t round_const
= 1ULL << (shift
- 1);
9575 tcg_round
= tcg_const_i64(round_const
);
9580 for (i
= 0; i
< elements
; i
++) {
9581 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
9582 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9583 false, true, size
+1, shift
);
9585 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
9589 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
9591 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
9594 tcg_temp_free_i64(tcg_round
);
9596 tcg_temp_free_i64(tcg_rn
);
9597 tcg_temp_free_i64(tcg_rd
);
9598 tcg_temp_free_i64(tcg_final
);
9600 clear_vec_high(s
, is_q
, rd
);
9604 /* AdvSIMD shift by immediate
9605 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9606 * +---+---+---+-------------+------+------+--------+---+------+------+
9607 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9608 * +---+---+---+-------------+------+------+--------+---+------+------+
9610 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
9612 int rd
= extract32(insn
, 0, 5);
9613 int rn
= extract32(insn
, 5, 5);
9614 int opcode
= extract32(insn
, 11, 5);
9615 int immb
= extract32(insn
, 16, 3);
9616 int immh
= extract32(insn
, 19, 4);
9617 bool is_u
= extract32(insn
, 29, 1);
9618 bool is_q
= extract32(insn
, 30, 1);
9621 case 0x08: /* SRI */
9623 unallocated_encoding(s
);
9627 case 0x00: /* SSHR / USHR */
9628 case 0x02: /* SSRA / USRA (accumulate) */
9629 case 0x04: /* SRSHR / URSHR (rounding) */
9630 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9631 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9633 case 0x0a: /* SHL / SLI */
9634 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9636 case 0x10: /* SHRN */
9637 case 0x11: /* RSHRN / SQRSHRUN */
9639 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
9642 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
9645 case 0x12: /* SQSHRN / UQSHRN */
9646 case 0x13: /* SQRSHRN / UQRSHRN */
9647 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
9650 case 0x14: /* SSHLL / USHLL */
9651 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9653 case 0x1c: /* SCVTF / UCVTF */
9654 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
9657 case 0xc: /* SQSHLU */
9659 unallocated_encoding(s
);
9662 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
9664 case 0xe: /* SQSHL, UQSHL */
9665 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
9667 case 0x1f: /* FCVTZS/ FCVTZU */
9668 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
9671 unallocated_encoding(s
);
9676 /* Generate code to do a "long" addition or subtraction, ie one done in
9677 * TCGv_i64 on vector lanes twice the width specified by size.
9679 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
9680 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
9682 static NeonGenTwo64OpFn
* const fns
[3][2] = {
9683 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
9684 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
9685 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
9687 NeonGenTwo64OpFn
*genfn
;
9690 genfn
= fns
[size
][is_sub
];
9691 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9694 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
9695 int opcode
, int rd
, int rn
, int rm
)
9697 /* 3-reg-different widening insns: 64 x 64 -> 128 */
9698 TCGv_i64 tcg_res
[2];
9701 tcg_res
[0] = tcg_temp_new_i64();
9702 tcg_res
[1] = tcg_temp_new_i64();
9704 /* Does this op do an adding accumulate, a subtracting accumulate,
9705 * or no accumulate at all?
9723 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9724 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9727 /* size == 2 means two 32x32->64 operations; this is worth special
9728 * casing because we can generally handle it inline.
9731 for (pass
= 0; pass
< 2; pass
++) {
9732 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9733 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9734 TCGv_i64 tcg_passres
;
9735 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
9737 int elt
= pass
+ is_q
* 2;
9739 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
9740 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
9743 tcg_passres
= tcg_res
[pass
];
9745 tcg_passres
= tcg_temp_new_i64();
9749 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9750 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9752 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9753 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9755 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9756 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9758 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
9759 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
9761 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
9762 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
9763 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
9765 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
9766 tcg_temp_free_i64(tcg_tmp1
);
9767 tcg_temp_free_i64(tcg_tmp2
);
9770 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9771 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9772 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
9773 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9775 case 9: /* SQDMLAL, SQDMLAL2 */
9776 case 11: /* SQDMLSL, SQDMLSL2 */
9777 case 13: /* SQDMULL, SQDMULL2 */
9778 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9779 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
9780 tcg_passres
, tcg_passres
);
9783 g_assert_not_reached();
9786 if (opcode
== 9 || opcode
== 11) {
9787 /* saturating accumulate ops */
9789 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
9791 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
9792 tcg_res
[pass
], tcg_passres
);
9793 } else if (accop
> 0) {
9794 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9795 } else if (accop
< 0) {
9796 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9800 tcg_temp_free_i64(tcg_passres
);
9803 tcg_temp_free_i64(tcg_op1
);
9804 tcg_temp_free_i64(tcg_op2
);
9807 /* size 0 or 1, generally helper functions */
9808 for (pass
= 0; pass
< 2; pass
++) {
9809 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9810 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9811 TCGv_i64 tcg_passres
;
9812 int elt
= pass
+ is_q
* 2;
9814 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
9815 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
9818 tcg_passres
= tcg_res
[pass
];
9820 tcg_passres
= tcg_temp_new_i64();
9824 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9825 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9827 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
9828 static NeonGenWidenFn
* const widenfns
[2][2] = {
9829 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
9830 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
9832 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
9834 widenfn(tcg_op2_64
, tcg_op2
);
9835 widenfn(tcg_passres
, tcg_op1
);
9836 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
9837 tcg_passres
, tcg_op2_64
);
9838 tcg_temp_free_i64(tcg_op2_64
);
9841 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9842 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9845 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
9847 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
9851 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
9853 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
9857 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9858 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9859 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
9862 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
9864 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
9868 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
9870 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
9874 case 9: /* SQDMLAL, SQDMLAL2 */
9875 case 11: /* SQDMLSL, SQDMLSL2 */
9876 case 13: /* SQDMULL, SQDMULL2 */
9878 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
9879 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
9880 tcg_passres
, tcg_passres
);
9882 case 14: /* PMULL */
9884 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
9887 g_assert_not_reached();
9889 tcg_temp_free_i32(tcg_op1
);
9890 tcg_temp_free_i32(tcg_op2
);
9893 if (opcode
== 9 || opcode
== 11) {
9894 /* saturating accumulate ops */
9896 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
9898 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
9902 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
9903 tcg_res
[pass
], tcg_passres
);
9905 tcg_temp_free_i64(tcg_passres
);
9910 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9911 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9912 tcg_temp_free_i64(tcg_res
[0]);
9913 tcg_temp_free_i64(tcg_res
[1]);
9916 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
9917 int opcode
, int rd
, int rn
, int rm
)
9919 TCGv_i64 tcg_res
[2];
9920 int part
= is_q
? 2 : 0;
9923 for (pass
= 0; pass
< 2; pass
++) {
9924 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9925 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9926 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
9927 static NeonGenWidenFn
* const widenfns
[3][2] = {
9928 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
9929 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
9930 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
9932 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
9934 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9935 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
9936 widenfn(tcg_op2_wide
, tcg_op2
);
9937 tcg_temp_free_i32(tcg_op2
);
9938 tcg_res
[pass
] = tcg_temp_new_i64();
9939 gen_neon_addl(size
, (opcode
== 3),
9940 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
9941 tcg_temp_free_i64(tcg_op1
);
9942 tcg_temp_free_i64(tcg_op2_wide
);
9945 for (pass
= 0; pass
< 2; pass
++) {
9946 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9947 tcg_temp_free_i64(tcg_res
[pass
]);
9951 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
9953 tcg_gen_addi_i64(in
, in
, 1U << 31);
9954 tcg_gen_extrh_i64_i32(res
, in
);
9957 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
9958 int opcode
, int rd
, int rn
, int rm
)
9960 TCGv_i32 tcg_res
[2];
9961 int part
= is_q
? 2 : 0;
9964 for (pass
= 0; pass
< 2; pass
++) {
9965 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9966 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9967 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
9968 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
9969 { gen_helper_neon_narrow_high_u8
,
9970 gen_helper_neon_narrow_round_high_u8
},
9971 { gen_helper_neon_narrow_high_u16
,
9972 gen_helper_neon_narrow_round_high_u16
},
9973 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
9975 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
9977 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9978 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9980 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
9982 tcg_temp_free_i64(tcg_op1
);
9983 tcg_temp_free_i64(tcg_op2
);
9985 tcg_res
[pass
] = tcg_temp_new_i32();
9986 gennarrow(tcg_res
[pass
], tcg_wideres
);
9987 tcg_temp_free_i64(tcg_wideres
);
9990 for (pass
= 0; pass
< 2; pass
++) {
9991 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
9992 tcg_temp_free_i32(tcg_res
[pass
]);
9994 clear_vec_high(s
, is_q
, rd
);
9997 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
9999 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10000 * is the only three-reg-diff instruction which produces a
10001 * 128-bit wide result from a single operation. However since
10002 * it's possible to calculate the two halves more or less
10003 * separately we just use two helper calls.
10005 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10006 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10007 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10009 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10010 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10011 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10012 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10013 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10014 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10016 tcg_temp_free_i64(tcg_op1
);
10017 tcg_temp_free_i64(tcg_op2
);
10018 tcg_temp_free_i64(tcg_res
);
10021 /* AdvSIMD three different
10022 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10023 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10024 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10025 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10027 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10029 /* Instructions in this group fall into three basic classes
10030 * (in each case with the operation working on each element in
10031 * the input vectors):
10032 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10034 * (2) wide 64 x 128 -> 128
10035 * (3) narrowing 128 x 128 -> 64
10036 * Here we do initial decode, catch unallocated cases and
10037 * dispatch to separate functions for each class.
10039 int is_q
= extract32(insn
, 30, 1);
10040 int is_u
= extract32(insn
, 29, 1);
10041 int size
= extract32(insn
, 22, 2);
10042 int opcode
= extract32(insn
, 12, 4);
10043 int rm
= extract32(insn
, 16, 5);
10044 int rn
= extract32(insn
, 5, 5);
10045 int rd
= extract32(insn
, 0, 5);
10048 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10049 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10050 /* 64 x 128 -> 128 */
10052 unallocated_encoding(s
);
10055 if (!fp_access_check(s
)) {
10058 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10060 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10061 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10062 /* 128 x 128 -> 64 */
10064 unallocated_encoding(s
);
10067 if (!fp_access_check(s
)) {
10070 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10072 case 14: /* PMULL, PMULL2 */
10073 if (is_u
|| size
== 1 || size
== 2) {
10074 unallocated_encoding(s
);
10078 if (!dc_isar_feature(aa64_pmull
, s
)) {
10079 unallocated_encoding(s
);
10082 if (!fp_access_check(s
)) {
10085 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10089 case 9: /* SQDMLAL, SQDMLAL2 */
10090 case 11: /* SQDMLSL, SQDMLSL2 */
10091 case 13: /* SQDMULL, SQDMULL2 */
10092 if (is_u
|| size
== 0) {
10093 unallocated_encoding(s
);
10097 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10098 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10099 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10100 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10101 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10102 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10103 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10104 /* 64 x 64 -> 128 */
10106 unallocated_encoding(s
);
10110 if (!fp_access_check(s
)) {
10114 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10117 /* opcode 15 not allocated */
10118 unallocated_encoding(s
);
10123 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10124 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10126 int rd
= extract32(insn
, 0, 5);
10127 int rn
= extract32(insn
, 5, 5);
10128 int rm
= extract32(insn
, 16, 5);
10129 int size
= extract32(insn
, 22, 2);
10130 bool is_u
= extract32(insn
, 29, 1);
10131 bool is_q
= extract32(insn
, 30, 1);
10133 if (!fp_access_check(s
)) {
10137 switch (size
+ 4 * is_u
) {
10139 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10142 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10145 if (rn
== rm
) { /* MOV */
10146 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10148 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10152 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10155 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10158 case 5: /* BSL bitwise select */
10159 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10161 case 6: /* BIT, bitwise insert if true */
10162 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10164 case 7: /* BIF, bitwise insert if false */
10165 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10169 g_assert_not_reached();
10173 /* Pairwise op subgroup of C3.6.16.
10175 * This is called directly or via the handle_3same_float for float pairwise
10176 * operations where the opcode and size are calculated differently.
10178 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10179 int size
, int rn
, int rm
, int rd
)
10184 /* Floating point operations need fpst */
10185 if (opcode
>= 0x58) {
10186 fpst
= get_fpstatus_ptr(false);
10191 if (!fp_access_check(s
)) {
10195 /* These operations work on the concatenated rm:rn, with each pair of
10196 * adjacent elements being operated on to produce an element in the result.
10199 TCGv_i64 tcg_res
[2];
10201 for (pass
= 0; pass
< 2; pass
++) {
10202 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10203 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10204 int passreg
= (pass
== 0) ? rn
: rm
;
10206 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10207 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10208 tcg_res
[pass
] = tcg_temp_new_i64();
10211 case 0x17: /* ADDP */
10212 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10214 case 0x58: /* FMAXNMP */
10215 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10217 case 0x5a: /* FADDP */
10218 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10220 case 0x5e: /* FMAXP */
10221 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10223 case 0x78: /* FMINNMP */
10224 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10226 case 0x7e: /* FMINP */
10227 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10230 g_assert_not_reached();
10233 tcg_temp_free_i64(tcg_op1
);
10234 tcg_temp_free_i64(tcg_op2
);
10237 for (pass
= 0; pass
< 2; pass
++) {
10238 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10239 tcg_temp_free_i64(tcg_res
[pass
]);
10242 int maxpass
= is_q
? 4 : 2;
10243 TCGv_i32 tcg_res
[4];
10245 for (pass
= 0; pass
< maxpass
; pass
++) {
10246 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10247 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10248 NeonGenTwoOpFn
*genfn
= NULL
;
10249 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10250 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10252 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10253 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10254 tcg_res
[pass
] = tcg_temp_new_i32();
10257 case 0x17: /* ADDP */
10259 static NeonGenTwoOpFn
* const fns
[3] = {
10260 gen_helper_neon_padd_u8
,
10261 gen_helper_neon_padd_u16
,
10267 case 0x14: /* SMAXP, UMAXP */
10269 static NeonGenTwoOpFn
* const fns
[3][2] = {
10270 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10271 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10272 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10274 genfn
= fns
[size
][u
];
10277 case 0x15: /* SMINP, UMINP */
10279 static NeonGenTwoOpFn
* const fns
[3][2] = {
10280 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10281 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10282 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10284 genfn
= fns
[size
][u
];
10287 /* The FP operations are all on single floats (32 bit) */
10288 case 0x58: /* FMAXNMP */
10289 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10291 case 0x5a: /* FADDP */
10292 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10294 case 0x5e: /* FMAXP */
10295 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10297 case 0x78: /* FMINNMP */
10298 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10300 case 0x7e: /* FMINP */
10301 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10304 g_assert_not_reached();
10307 /* FP ops called directly, otherwise call now */
10309 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10312 tcg_temp_free_i32(tcg_op1
);
10313 tcg_temp_free_i32(tcg_op2
);
10316 for (pass
= 0; pass
< maxpass
; pass
++) {
10317 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10318 tcg_temp_free_i32(tcg_res
[pass
]);
10320 clear_vec_high(s
, is_q
, rd
);
10324 tcg_temp_free_ptr(fpst
);
10328 /* Floating point op subgroup of C3.6.16. */
10329 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10331 /* For floating point ops, the U, size[1] and opcode bits
10332 * together indicate the operation. size[0] indicates single
10335 int fpopcode
= extract32(insn
, 11, 5)
10336 | (extract32(insn
, 23, 1) << 5)
10337 | (extract32(insn
, 29, 1) << 6);
10338 int is_q
= extract32(insn
, 30, 1);
10339 int size
= extract32(insn
, 22, 1);
10340 int rm
= extract32(insn
, 16, 5);
10341 int rn
= extract32(insn
, 5, 5);
10342 int rd
= extract32(insn
, 0, 5);
10344 int datasize
= is_q
? 128 : 64;
10345 int esize
= 32 << size
;
10346 int elements
= datasize
/ esize
;
10348 if (size
== 1 && !is_q
) {
10349 unallocated_encoding(s
);
10353 switch (fpopcode
) {
10354 case 0x58: /* FMAXNMP */
10355 case 0x5a: /* FADDP */
10356 case 0x5e: /* FMAXP */
10357 case 0x78: /* FMINNMP */
10358 case 0x7e: /* FMINP */
10359 if (size
&& !is_q
) {
10360 unallocated_encoding(s
);
10363 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10366 case 0x1b: /* FMULX */
10367 case 0x1f: /* FRECPS */
10368 case 0x3f: /* FRSQRTS */
10369 case 0x5d: /* FACGE */
10370 case 0x7d: /* FACGT */
10371 case 0x19: /* FMLA */
10372 case 0x39: /* FMLS */
10373 case 0x18: /* FMAXNM */
10374 case 0x1a: /* FADD */
10375 case 0x1c: /* FCMEQ */
10376 case 0x1e: /* FMAX */
10377 case 0x38: /* FMINNM */
10378 case 0x3a: /* FSUB */
10379 case 0x3e: /* FMIN */
10380 case 0x5b: /* FMUL */
10381 case 0x5c: /* FCMGE */
10382 case 0x5f: /* FDIV */
10383 case 0x7a: /* FABD */
10384 case 0x7c: /* FCMGT */
10385 if (!fp_access_check(s
)) {
10389 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10392 unallocated_encoding(s
);
10397 /* Integer op subgroup of C3.6.16. */
10398 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10400 int is_q
= extract32(insn
, 30, 1);
10401 int u
= extract32(insn
, 29, 1);
10402 int size
= extract32(insn
, 22, 2);
10403 int opcode
= extract32(insn
, 11, 5);
10404 int rm
= extract32(insn
, 16, 5);
10405 int rn
= extract32(insn
, 5, 5);
10406 int rd
= extract32(insn
, 0, 5);
10411 case 0x13: /* MUL, PMUL */
10412 if (u
&& size
!= 0) {
10413 unallocated_encoding(s
);
10417 case 0x0: /* SHADD, UHADD */
10418 case 0x2: /* SRHADD, URHADD */
10419 case 0x4: /* SHSUB, UHSUB */
10420 case 0xc: /* SMAX, UMAX */
10421 case 0xd: /* SMIN, UMIN */
10422 case 0xe: /* SABD, UABD */
10423 case 0xf: /* SABA, UABA */
10424 case 0x12: /* MLA, MLS */
10426 unallocated_encoding(s
);
10430 case 0x16: /* SQDMULH, SQRDMULH */
10431 if (size
== 0 || size
== 3) {
10432 unallocated_encoding(s
);
10437 if (size
== 3 && !is_q
) {
10438 unallocated_encoding(s
);
10444 if (!fp_access_check(s
)) {
10449 case 0x10: /* ADD, SUB */
10451 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10453 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10456 case 0x13: /* MUL, PMUL */
10457 if (!u
) { /* MUL */
10458 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10462 case 0x12: /* MLA, MLS */
10464 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10466 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10470 if (!u
) { /* CMTST */
10471 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10475 cond
= TCG_COND_EQ
;
10477 case 0x06: /* CMGT, CMHI */
10478 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10480 case 0x07: /* CMGE, CMHS */
10481 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10483 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10484 vec_full_reg_offset(s
, rn
),
10485 vec_full_reg_offset(s
, rm
),
10486 is_q
? 16 : 8, vec_full_reg_size(s
));
10492 for (pass
= 0; pass
< 2; pass
++) {
10493 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10494 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10495 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10497 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10498 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10500 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10502 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10504 tcg_temp_free_i64(tcg_res
);
10505 tcg_temp_free_i64(tcg_op1
);
10506 tcg_temp_free_i64(tcg_op2
);
10509 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10510 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10511 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10512 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10513 NeonGenTwoOpFn
*genfn
= NULL
;
10514 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
10516 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
10517 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
10520 case 0x0: /* SHADD, UHADD */
10522 static NeonGenTwoOpFn
* const fns
[3][2] = {
10523 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
10524 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
10525 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
10527 genfn
= fns
[size
][u
];
10530 case 0x1: /* SQADD, UQADD */
10532 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10533 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
10534 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
10535 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
10537 genenvfn
= fns
[size
][u
];
10540 case 0x2: /* SRHADD, URHADD */
10542 static NeonGenTwoOpFn
* const fns
[3][2] = {
10543 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
10544 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
10545 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
10547 genfn
= fns
[size
][u
];
10550 case 0x4: /* SHSUB, UHSUB */
10552 static NeonGenTwoOpFn
* const fns
[3][2] = {
10553 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
10554 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
10555 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
10557 genfn
= fns
[size
][u
];
10560 case 0x5: /* SQSUB, UQSUB */
10562 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10563 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
10564 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
10565 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
10567 genenvfn
= fns
[size
][u
];
10570 case 0x8: /* SSHL, USHL */
10572 static NeonGenTwoOpFn
* const fns
[3][2] = {
10573 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
10574 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
10575 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
10577 genfn
= fns
[size
][u
];
10580 case 0x9: /* SQSHL, UQSHL */
10582 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10583 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
10584 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
10585 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
10587 genenvfn
= fns
[size
][u
];
10590 case 0xa: /* SRSHL, URSHL */
10592 static NeonGenTwoOpFn
* const fns
[3][2] = {
10593 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
10594 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
10595 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
10597 genfn
= fns
[size
][u
];
10600 case 0xb: /* SQRSHL, UQRSHL */
10602 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10603 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
10604 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
10605 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
10607 genenvfn
= fns
[size
][u
];
10610 case 0xc: /* SMAX, UMAX */
10612 static NeonGenTwoOpFn
* const fns
[3][2] = {
10613 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
10614 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
10615 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10617 genfn
= fns
[size
][u
];
10621 case 0xd: /* SMIN, UMIN */
10623 static NeonGenTwoOpFn
* const fns
[3][2] = {
10624 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
10625 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
10626 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10628 genfn
= fns
[size
][u
];
10631 case 0xe: /* SABD, UABD */
10632 case 0xf: /* SABA, UABA */
10634 static NeonGenTwoOpFn
* const fns
[3][2] = {
10635 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
10636 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
10637 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
10639 genfn
= fns
[size
][u
];
10642 case 0x13: /* MUL, PMUL */
10643 assert(u
); /* PMUL */
10645 genfn
= gen_helper_neon_mul_p8
;
10647 case 0x16: /* SQDMULH, SQRDMULH */
10649 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
10650 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
10651 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
10653 assert(size
== 1 || size
== 2);
10654 genenvfn
= fns
[size
- 1][u
];
10658 g_assert_not_reached();
10662 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
10664 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10667 if (opcode
== 0xf) {
10668 /* SABA, UABA: accumulating ops */
10669 static NeonGenTwoOpFn
* const fns
[3] = {
10670 gen_helper_neon_add_u8
,
10671 gen_helper_neon_add_u16
,
10675 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
10676 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
10679 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10681 tcg_temp_free_i32(tcg_res
);
10682 tcg_temp_free_i32(tcg_op1
);
10683 tcg_temp_free_i32(tcg_op2
);
10686 clear_vec_high(s
, is_q
, rd
);
10689 /* AdvSIMD three same
10690 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
10691 * +---+---+---+-----------+------+---+------+--------+---+------+------+
10692 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
10693 * +---+---+---+-----------+------+---+------+--------+---+------+------+
10695 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
10697 int opcode
= extract32(insn
, 11, 5);
10700 case 0x3: /* logic ops */
10701 disas_simd_3same_logic(s
, insn
);
10703 case 0x17: /* ADDP */
10704 case 0x14: /* SMAXP, UMAXP */
10705 case 0x15: /* SMINP, UMINP */
10707 /* Pairwise operations */
10708 int is_q
= extract32(insn
, 30, 1);
10709 int u
= extract32(insn
, 29, 1);
10710 int size
= extract32(insn
, 22, 2);
10711 int rm
= extract32(insn
, 16, 5);
10712 int rn
= extract32(insn
, 5, 5);
10713 int rd
= extract32(insn
, 0, 5);
10714 if (opcode
== 0x17) {
10715 if (u
|| (size
== 3 && !is_q
)) {
10716 unallocated_encoding(s
);
10721 unallocated_encoding(s
);
10725 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
10728 case 0x18 ... 0x31:
10729 /* floating point ops, sz[1] and U are part of opcode */
10730 disas_simd_3same_float(s
, insn
);
10733 disas_simd_3same_int(s
, insn
);
10739 * Advanced SIMD three same (ARMv8.2 FP16 variants)
10741 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
10742 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
10743 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
10744 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
10746 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
10747 * (register), FACGE, FABD, FCMGT (register) and FACGT.
10750 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
10752 int opcode
, fpopcode
;
10753 int is_q
, u
, a
, rm
, rn
, rd
;
10754 int datasize
, elements
;
10757 bool pairwise
= false;
10759 if (!dc_isar_feature(aa64_fp16
, s
)) {
10760 unallocated_encoding(s
);
10764 if (!fp_access_check(s
)) {
10768 /* For these floating point ops, the U, a and opcode bits
10769 * together indicate the operation.
10771 opcode
= extract32(insn
, 11, 3);
10772 u
= extract32(insn
, 29, 1);
10773 a
= extract32(insn
, 23, 1);
10774 is_q
= extract32(insn
, 30, 1);
10775 rm
= extract32(insn
, 16, 5);
10776 rn
= extract32(insn
, 5, 5);
10777 rd
= extract32(insn
, 0, 5);
10779 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
10780 datasize
= is_q
? 128 : 64;
10781 elements
= datasize
/ 16;
10783 switch (fpopcode
) {
10784 case 0x10: /* FMAXNMP */
10785 case 0x12: /* FADDP */
10786 case 0x16: /* FMAXP */
10787 case 0x18: /* FMINNMP */
10788 case 0x1e: /* FMINP */
10793 fpst
= get_fpstatus_ptr(true);
10796 int maxpass
= is_q
? 8 : 4;
10797 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10798 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10799 TCGv_i32 tcg_res
[8];
10801 for (pass
= 0; pass
< maxpass
; pass
++) {
10802 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10803 int passelt
= (pass
<< 1) & (maxpass
- 1);
10805 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
10806 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
10807 tcg_res
[pass
] = tcg_temp_new_i32();
10809 switch (fpopcode
) {
10810 case 0x10: /* FMAXNMP */
10811 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
10814 case 0x12: /* FADDP */
10815 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10817 case 0x16: /* FMAXP */
10818 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10820 case 0x18: /* FMINNMP */
10821 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
10824 case 0x1e: /* FMINP */
10825 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10828 g_assert_not_reached();
10832 for (pass
= 0; pass
< maxpass
; pass
++) {
10833 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
10834 tcg_temp_free_i32(tcg_res
[pass
]);
10837 tcg_temp_free_i32(tcg_op1
);
10838 tcg_temp_free_i32(tcg_op2
);
10841 for (pass
= 0; pass
< elements
; pass
++) {
10842 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10843 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10844 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10846 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
10847 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
10849 switch (fpopcode
) {
10850 case 0x0: /* FMAXNM */
10851 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10853 case 0x1: /* FMLA */
10854 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
10855 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
10858 case 0x2: /* FADD */
10859 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10861 case 0x3: /* FMULX */
10862 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10864 case 0x4: /* FCMEQ */
10865 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10867 case 0x6: /* FMAX */
10868 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10870 case 0x7: /* FRECPS */
10871 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10873 case 0x8: /* FMINNM */
10874 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10876 case 0x9: /* FMLS */
10877 /* As usual for ARM, separate negation for fused multiply-add */
10878 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
10879 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
10880 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
10883 case 0xa: /* FSUB */
10884 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10886 case 0xe: /* FMIN */
10887 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10889 case 0xf: /* FRSQRTS */
10890 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10892 case 0x13: /* FMUL */
10893 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10895 case 0x14: /* FCMGE */
10896 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10898 case 0x15: /* FACGE */
10899 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10901 case 0x17: /* FDIV */
10902 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10904 case 0x1a: /* FABD */
10905 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10906 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
10908 case 0x1c: /* FCMGT */
10909 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10911 case 0x1d: /* FACGT */
10912 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10915 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
10916 __func__
, insn
, fpopcode
, s
->pc
);
10917 g_assert_not_reached();
10920 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
10921 tcg_temp_free_i32(tcg_res
);
10922 tcg_temp_free_i32(tcg_op1
);
10923 tcg_temp_free_i32(tcg_op2
);
10927 tcg_temp_free_ptr(fpst
);
10929 clear_vec_high(s
, is_q
, rd
);
10932 /* AdvSIMD three same extra
10933 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
10934 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
10935 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
10936 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
10938 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
10940 int rd
= extract32(insn
, 0, 5);
10941 int rn
= extract32(insn
, 5, 5);
10942 int opcode
= extract32(insn
, 11, 4);
10943 int rm
= extract32(insn
, 16, 5);
10944 int size
= extract32(insn
, 22, 2);
10945 bool u
= extract32(insn
, 29, 1);
10946 bool is_q
= extract32(insn
, 30, 1);
10950 switch (u
* 16 + opcode
) {
10951 case 0x10: /* SQRDMLAH (vector) */
10952 case 0x11: /* SQRDMLSH (vector) */
10953 if (size
!= 1 && size
!= 2) {
10954 unallocated_encoding(s
);
10957 feature
= dc_isar_feature(aa64_rdm
, s
);
10959 case 0x02: /* SDOT (vector) */
10960 case 0x12: /* UDOT (vector) */
10961 if (size
!= MO_32
) {
10962 unallocated_encoding(s
);
10965 feature
= dc_isar_feature(aa64_dp
, s
);
10967 case 0x18: /* FCMLA, #0 */
10968 case 0x19: /* FCMLA, #90 */
10969 case 0x1a: /* FCMLA, #180 */
10970 case 0x1b: /* FCMLA, #270 */
10971 case 0x1c: /* FCADD, #90 */
10972 case 0x1e: /* FCADD, #270 */
10974 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
10975 || (size
== 3 && !is_q
)) {
10976 unallocated_encoding(s
);
10979 feature
= dc_isar_feature(aa64_fcma
, s
);
10982 unallocated_encoding(s
);
10986 unallocated_encoding(s
);
10989 if (!fp_access_check(s
)) {
10994 case 0x0: /* SQRDMLAH (vector) */
10997 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11000 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11003 g_assert_not_reached();
11007 case 0x1: /* SQRDMLSH (vector) */
11010 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11013 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11016 g_assert_not_reached();
11020 case 0x2: /* SDOT / UDOT */
11021 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11022 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11025 case 0x8: /* FCMLA, #0 */
11026 case 0x9: /* FCMLA, #90 */
11027 case 0xa: /* FCMLA, #180 */
11028 case 0xb: /* FCMLA, #270 */
11029 rot
= extract32(opcode
, 0, 2);
11032 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11033 gen_helper_gvec_fcmlah
);
11036 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11037 gen_helper_gvec_fcmlas
);
11040 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11041 gen_helper_gvec_fcmlad
);
11044 g_assert_not_reached();
11048 case 0xc: /* FCADD, #90 */
11049 case 0xe: /* FCADD, #270 */
11050 rot
= extract32(opcode
, 1, 1);
11053 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11054 gen_helper_gvec_fcaddh
);
11057 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11058 gen_helper_gvec_fcadds
);
11061 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11062 gen_helper_gvec_fcaddd
);
11065 g_assert_not_reached();
11070 g_assert_not_reached();
11074 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11075 int size
, int rn
, int rd
)
11077 /* Handle 2-reg-misc ops which are widening (so each size element
11078 * in the source becomes a 2*size element in the destination.
11079 * The only instruction like this is FCVTL.
11084 /* 32 -> 64 bit fp conversion */
11085 TCGv_i64 tcg_res
[2];
11086 int srcelt
= is_q
? 2 : 0;
11088 for (pass
= 0; pass
< 2; pass
++) {
11089 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11090 tcg_res
[pass
] = tcg_temp_new_i64();
11092 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11093 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11094 tcg_temp_free_i32(tcg_op
);
11096 for (pass
= 0; pass
< 2; pass
++) {
11097 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11098 tcg_temp_free_i64(tcg_res
[pass
]);
11101 /* 16 -> 32 bit fp conversion */
11102 int srcelt
= is_q
? 4 : 0;
11103 TCGv_i32 tcg_res
[4];
11104 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11105 TCGv_i32 ahp
= get_ahp_flag();
11107 for (pass
= 0; pass
< 4; pass
++) {
11108 tcg_res
[pass
] = tcg_temp_new_i32();
11110 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11111 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11114 for (pass
= 0; pass
< 4; pass
++) {
11115 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11116 tcg_temp_free_i32(tcg_res
[pass
]);
11119 tcg_temp_free_ptr(fpst
);
11120 tcg_temp_free_i32(ahp
);
11124 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11125 bool is_q
, int size
, int rn
, int rd
)
11127 int op
= (opcode
<< 1) | u
;
11128 int opsz
= op
+ size
;
11129 int grp_size
= 3 - opsz
;
11130 int dsize
= is_q
? 128 : 64;
11134 unallocated_encoding(s
);
11138 if (!fp_access_check(s
)) {
11143 /* Special case bytes, use bswap op on each group of elements */
11144 int groups
= dsize
/ (8 << grp_size
);
11146 for (i
= 0; i
< groups
; i
++) {
11147 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11149 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11150 switch (grp_size
) {
11152 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11155 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11158 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11161 g_assert_not_reached();
11163 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11164 tcg_temp_free_i64(tcg_tmp
);
11166 clear_vec_high(s
, is_q
, rd
);
11168 int revmask
= (1 << grp_size
) - 1;
11169 int esize
= 8 << size
;
11170 int elements
= dsize
/ esize
;
11171 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11172 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11173 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11175 for (i
= 0; i
< elements
; i
++) {
11176 int e_rev
= (i
& 0xf) ^ revmask
;
11177 int off
= e_rev
* esize
;
11178 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11180 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11181 tcg_rn
, off
- 64, esize
);
11183 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11186 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11187 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11189 tcg_temp_free_i64(tcg_rd_hi
);
11190 tcg_temp_free_i64(tcg_rd
);
11191 tcg_temp_free_i64(tcg_rn
);
11195 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11196 bool is_q
, int size
, int rn
, int rd
)
11198 /* Implement the pairwise operations from 2-misc:
11199 * SADDLP, UADDLP, SADALP, UADALP.
11200 * These all add pairs of elements in the input to produce a
11201 * double-width result element in the output (possibly accumulating).
11203 bool accum
= (opcode
== 0x6);
11204 int maxpass
= is_q
? 2 : 1;
11206 TCGv_i64 tcg_res
[2];
11209 /* 32 + 32 -> 64 op */
11210 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11212 for (pass
= 0; pass
< maxpass
; pass
++) {
11213 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11214 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11216 tcg_res
[pass
] = tcg_temp_new_i64();
11218 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11219 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11220 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11222 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11223 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11226 tcg_temp_free_i64(tcg_op1
);
11227 tcg_temp_free_i64(tcg_op2
);
11230 for (pass
= 0; pass
< maxpass
; pass
++) {
11231 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11232 NeonGenOneOpFn
*genfn
;
11233 static NeonGenOneOpFn
* const fns
[2][2] = {
11234 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11235 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11238 genfn
= fns
[size
][u
];
11240 tcg_res
[pass
] = tcg_temp_new_i64();
11242 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11243 genfn(tcg_res
[pass
], tcg_op
);
11246 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11248 gen_helper_neon_addl_u16(tcg_res
[pass
],
11249 tcg_res
[pass
], tcg_op
);
11251 gen_helper_neon_addl_u32(tcg_res
[pass
],
11252 tcg_res
[pass
], tcg_op
);
11255 tcg_temp_free_i64(tcg_op
);
11259 tcg_res
[1] = tcg_const_i64(0);
11261 for (pass
= 0; pass
< 2; pass
++) {
11262 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11263 tcg_temp_free_i64(tcg_res
[pass
]);
11267 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11269 /* Implement SHLL and SHLL2 */
11271 int part
= is_q
? 2 : 0;
11272 TCGv_i64 tcg_res
[2];
11274 for (pass
= 0; pass
< 2; pass
++) {
11275 static NeonGenWidenFn
* const widenfns
[3] = {
11276 gen_helper_neon_widen_u8
,
11277 gen_helper_neon_widen_u16
,
11278 tcg_gen_extu_i32_i64
,
11280 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11281 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11283 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11284 tcg_res
[pass
] = tcg_temp_new_i64();
11285 widenfn(tcg_res
[pass
], tcg_op
);
11286 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11288 tcg_temp_free_i32(tcg_op
);
11291 for (pass
= 0; pass
< 2; pass
++) {
11292 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11293 tcg_temp_free_i64(tcg_res
[pass
]);
11297 /* AdvSIMD two reg misc
11298 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11299 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11300 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11301 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11303 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11305 int size
= extract32(insn
, 22, 2);
11306 int opcode
= extract32(insn
, 12, 5);
11307 bool u
= extract32(insn
, 29, 1);
11308 bool is_q
= extract32(insn
, 30, 1);
11309 int rn
= extract32(insn
, 5, 5);
11310 int rd
= extract32(insn
, 0, 5);
11311 bool need_fpstatus
= false;
11312 bool need_rmode
= false;
11314 TCGv_i32 tcg_rmode
;
11315 TCGv_ptr tcg_fpstatus
;
11318 case 0x0: /* REV64, REV32 */
11319 case 0x1: /* REV16 */
11320 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11322 case 0x5: /* CNT, NOT, RBIT */
11323 if (u
&& size
== 0) {
11326 } else if (u
&& size
== 1) {
11329 } else if (!u
&& size
== 0) {
11333 unallocated_encoding(s
);
11335 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11336 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11338 unallocated_encoding(s
);
11341 if (!fp_access_check(s
)) {
11345 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11347 case 0x4: /* CLS, CLZ */
11349 unallocated_encoding(s
);
11353 case 0x2: /* SADDLP, UADDLP */
11354 case 0x6: /* SADALP, UADALP */
11356 unallocated_encoding(s
);
11359 if (!fp_access_check(s
)) {
11362 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11364 case 0x13: /* SHLL, SHLL2 */
11365 if (u
== 0 || size
== 3) {
11366 unallocated_encoding(s
);
11369 if (!fp_access_check(s
)) {
11372 handle_shll(s
, is_q
, size
, rn
, rd
);
11374 case 0xa: /* CMLT */
11376 unallocated_encoding(s
);
11380 case 0x8: /* CMGT, CMGE */
11381 case 0x9: /* CMEQ, CMLE */
11382 case 0xb: /* ABS, NEG */
11383 if (size
== 3 && !is_q
) {
11384 unallocated_encoding(s
);
11388 case 0x3: /* SUQADD, USQADD */
11389 if (size
== 3 && !is_q
) {
11390 unallocated_encoding(s
);
11393 if (!fp_access_check(s
)) {
11396 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11398 case 0x7: /* SQABS, SQNEG */
11399 if (size
== 3 && !is_q
) {
11400 unallocated_encoding(s
);
11405 case 0x16 ... 0x1d:
11408 /* Floating point: U, size[1] and opcode indicate operation;
11409 * size[0] indicates single or double precision.
11411 int is_double
= extract32(size
, 0, 1);
11412 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11413 size
= is_double
? 3 : 2;
11415 case 0x2f: /* FABS */
11416 case 0x6f: /* FNEG */
11417 if (size
== 3 && !is_q
) {
11418 unallocated_encoding(s
);
11422 case 0x1d: /* SCVTF */
11423 case 0x5d: /* UCVTF */
11425 bool is_signed
= (opcode
== 0x1d) ? true : false;
11426 int elements
= is_double
? 2 : is_q
? 4 : 2;
11427 if (is_double
&& !is_q
) {
11428 unallocated_encoding(s
);
11431 if (!fp_access_check(s
)) {
11434 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11437 case 0x2c: /* FCMGT (zero) */
11438 case 0x2d: /* FCMEQ (zero) */
11439 case 0x2e: /* FCMLT (zero) */
11440 case 0x6c: /* FCMGE (zero) */
11441 case 0x6d: /* FCMLE (zero) */
11442 if (size
== 3 && !is_q
) {
11443 unallocated_encoding(s
);
11446 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11448 case 0x7f: /* FSQRT */
11449 if (size
== 3 && !is_q
) {
11450 unallocated_encoding(s
);
11454 case 0x1a: /* FCVTNS */
11455 case 0x1b: /* FCVTMS */
11456 case 0x3a: /* FCVTPS */
11457 case 0x3b: /* FCVTZS */
11458 case 0x5a: /* FCVTNU */
11459 case 0x5b: /* FCVTMU */
11460 case 0x7a: /* FCVTPU */
11461 case 0x7b: /* FCVTZU */
11462 need_fpstatus
= true;
11464 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11465 if (size
== 3 && !is_q
) {
11466 unallocated_encoding(s
);
11470 case 0x5c: /* FCVTAU */
11471 case 0x1c: /* FCVTAS */
11472 need_fpstatus
= true;
11474 rmode
= FPROUNDING_TIEAWAY
;
11475 if (size
== 3 && !is_q
) {
11476 unallocated_encoding(s
);
11480 case 0x3c: /* URECPE */
11482 unallocated_encoding(s
);
11486 case 0x3d: /* FRECPE */
11487 case 0x7d: /* FRSQRTE */
11488 if (size
== 3 && !is_q
) {
11489 unallocated_encoding(s
);
11492 if (!fp_access_check(s
)) {
11495 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11497 case 0x56: /* FCVTXN, FCVTXN2 */
11499 unallocated_encoding(s
);
11503 case 0x16: /* FCVTN, FCVTN2 */
11504 /* handle_2misc_narrow does a 2*size -> size operation, but these
11505 * instructions encode the source size rather than dest size.
11507 if (!fp_access_check(s
)) {
11510 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
11512 case 0x17: /* FCVTL, FCVTL2 */
11513 if (!fp_access_check(s
)) {
11516 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
11518 case 0x18: /* FRINTN */
11519 case 0x19: /* FRINTM */
11520 case 0x38: /* FRINTP */
11521 case 0x39: /* FRINTZ */
11523 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11525 case 0x59: /* FRINTX */
11526 case 0x79: /* FRINTI */
11527 need_fpstatus
= true;
11528 if (size
== 3 && !is_q
) {
11529 unallocated_encoding(s
);
11533 case 0x58: /* FRINTA */
11535 rmode
= FPROUNDING_TIEAWAY
;
11536 need_fpstatus
= true;
11537 if (size
== 3 && !is_q
) {
11538 unallocated_encoding(s
);
11542 case 0x7c: /* URSQRTE */
11544 unallocated_encoding(s
);
11547 need_fpstatus
= true;
11550 unallocated_encoding(s
);
11556 unallocated_encoding(s
);
11560 if (!fp_access_check(s
)) {
11564 if (need_fpstatus
|| need_rmode
) {
11565 tcg_fpstatus
= get_fpstatus_ptr(false);
11567 tcg_fpstatus
= NULL
;
11570 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
11571 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
11578 if (u
&& size
== 0) { /* NOT */
11579 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
11585 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
11592 /* All 64-bit element operations can be shared with scalar 2misc */
11595 /* Coverity claims (size == 3 && !is_q) has been eliminated
11596 * from all paths leading to here.
11598 tcg_debug_assert(is_q
);
11599 for (pass
= 0; pass
< 2; pass
++) {
11600 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11601 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11603 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11605 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
11606 tcg_rmode
, tcg_fpstatus
);
11608 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11610 tcg_temp_free_i64(tcg_res
);
11611 tcg_temp_free_i64(tcg_op
);
11616 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11617 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11618 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11621 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
11624 /* Special cases for 32 bit elements */
11626 case 0xa: /* CMLT */
11627 /* 32 bit integer comparison against zero, result is
11628 * test ? (2^32 - 1) : 0. We implement via setcond(test)
11631 cond
= TCG_COND_LT
;
11633 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
11634 tcg_gen_neg_i32(tcg_res
, tcg_res
);
11636 case 0x8: /* CMGT, CMGE */
11637 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
11639 case 0x9: /* CMEQ, CMLE */
11640 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
11642 case 0x4: /* CLS */
11644 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
11646 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
11649 case 0x7: /* SQABS, SQNEG */
11651 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
11653 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
11656 case 0xb: /* ABS, NEG */
11658 tcg_gen_neg_i32(tcg_res
, tcg_op
);
11660 TCGv_i32 tcg_zero
= tcg_const_i32(0);
11661 tcg_gen_neg_i32(tcg_res
, tcg_op
);
11662 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
11663 tcg_zero
, tcg_op
, tcg_res
);
11664 tcg_temp_free_i32(tcg_zero
);
11667 case 0x2f: /* FABS */
11668 gen_helper_vfp_abss(tcg_res
, tcg_op
);
11670 case 0x6f: /* FNEG */
11671 gen_helper_vfp_negs(tcg_res
, tcg_op
);
11673 case 0x7f: /* FSQRT */
11674 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
11676 case 0x1a: /* FCVTNS */
11677 case 0x1b: /* FCVTMS */
11678 case 0x1c: /* FCVTAS */
11679 case 0x3a: /* FCVTPS */
11680 case 0x3b: /* FCVTZS */
11682 TCGv_i32 tcg_shift
= tcg_const_i32(0);
11683 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
11684 tcg_shift
, tcg_fpstatus
);
11685 tcg_temp_free_i32(tcg_shift
);
11688 case 0x5a: /* FCVTNU */
11689 case 0x5b: /* FCVTMU */
11690 case 0x5c: /* FCVTAU */
11691 case 0x7a: /* FCVTPU */
11692 case 0x7b: /* FCVTZU */
11694 TCGv_i32 tcg_shift
= tcg_const_i32(0);
11695 gen_helper_vfp_touls(tcg_res
, tcg_op
,
11696 tcg_shift
, tcg_fpstatus
);
11697 tcg_temp_free_i32(tcg_shift
);
11700 case 0x18: /* FRINTN */
11701 case 0x19: /* FRINTM */
11702 case 0x38: /* FRINTP */
11703 case 0x39: /* FRINTZ */
11704 case 0x58: /* FRINTA */
11705 case 0x79: /* FRINTI */
11706 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
11708 case 0x59: /* FRINTX */
11709 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
11711 case 0x7c: /* URSQRTE */
11712 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
11715 g_assert_not_reached();
11718 /* Use helpers for 8 and 16 bit elements */
11720 case 0x5: /* CNT, RBIT */
11721 /* For these two insns size is part of the opcode specifier
11722 * (handled earlier); they always operate on byte elements.
11725 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
11727 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
11730 case 0x7: /* SQABS, SQNEG */
11732 NeonGenOneOpEnvFn
*genfn
;
11733 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
11734 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
11735 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
11737 genfn
= fns
[size
][u
];
11738 genfn(tcg_res
, cpu_env
, tcg_op
);
11741 case 0x8: /* CMGT, CMGE */
11742 case 0x9: /* CMEQ, CMLE */
11743 case 0xa: /* CMLT */
11745 static NeonGenTwoOpFn
* const fns
[3][2] = {
11746 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
11747 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
11748 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
11750 NeonGenTwoOpFn
*genfn
;
11753 TCGv_i32 tcg_zero
= tcg_const_i32(0);
11755 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
11756 comp
= (opcode
- 0x8) * 2 + u
;
11757 /* ...but LE, LT are implemented as reverse GE, GT */
11758 reverse
= (comp
> 2);
11762 genfn
= fns
[comp
][size
];
11764 genfn(tcg_res
, tcg_zero
, tcg_op
);
11766 genfn(tcg_res
, tcg_op
, tcg_zero
);
11768 tcg_temp_free_i32(tcg_zero
);
11771 case 0xb: /* ABS, NEG */
11773 TCGv_i32 tcg_zero
= tcg_const_i32(0);
11775 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
11777 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
11779 tcg_temp_free_i32(tcg_zero
);
11782 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
11784 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
11788 case 0x4: /* CLS, CLZ */
11791 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
11793 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
11797 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
11799 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
11804 g_assert_not_reached();
11808 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11810 tcg_temp_free_i32(tcg_res
);
11811 tcg_temp_free_i32(tcg_op
);
11814 clear_vec_high(s
, is_q
, rd
);
11817 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
11818 tcg_temp_free_i32(tcg_rmode
);
11820 if (need_fpstatus
) {
11821 tcg_temp_free_ptr(tcg_fpstatus
);
11825 /* AdvSIMD [scalar] two register miscellaneous (FP16)
11827 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
11828 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
11829 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
11830 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
11831 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
11832 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
11834 * This actually covers two groups where scalar access is governed by
11835 * bit 28. A bunch of the instructions (float to integral) only exist
11836 * in the vector form and are un-allocated for the scalar decode. Also
11837 * in the scalar decode Q is always 1.
11839 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
11841 int fpop
, opcode
, a
, u
;
11845 bool only_in_vector
= false;
11848 TCGv_i32 tcg_rmode
= NULL
;
11849 TCGv_ptr tcg_fpstatus
= NULL
;
11850 bool need_rmode
= false;
11851 bool need_fpst
= true;
11854 if (!dc_isar_feature(aa64_fp16
, s
)) {
11855 unallocated_encoding(s
);
11859 rd
= extract32(insn
, 0, 5);
11860 rn
= extract32(insn
, 5, 5);
11862 a
= extract32(insn
, 23, 1);
11863 u
= extract32(insn
, 29, 1);
11864 is_scalar
= extract32(insn
, 28, 1);
11865 is_q
= extract32(insn
, 30, 1);
11867 opcode
= extract32(insn
, 12, 5);
11868 fpop
= deposit32(opcode
, 5, 1, a
);
11869 fpop
= deposit32(fpop
, 6, 1, u
);
11871 rd
= extract32(insn
, 0, 5);
11872 rn
= extract32(insn
, 5, 5);
11875 case 0x1d: /* SCVTF */
11876 case 0x5d: /* UCVTF */
11883 elements
= (is_q
? 8 : 4);
11886 if (!fp_access_check(s
)) {
11889 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
11893 case 0x2c: /* FCMGT (zero) */
11894 case 0x2d: /* FCMEQ (zero) */
11895 case 0x2e: /* FCMLT (zero) */
11896 case 0x6c: /* FCMGE (zero) */
11897 case 0x6d: /* FCMLE (zero) */
11898 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
11900 case 0x3d: /* FRECPE */
11901 case 0x3f: /* FRECPX */
11903 case 0x18: /* FRINTN */
11905 only_in_vector
= true;
11906 rmode
= FPROUNDING_TIEEVEN
;
11908 case 0x19: /* FRINTM */
11910 only_in_vector
= true;
11911 rmode
= FPROUNDING_NEGINF
;
11913 case 0x38: /* FRINTP */
11915 only_in_vector
= true;
11916 rmode
= FPROUNDING_POSINF
;
11918 case 0x39: /* FRINTZ */
11920 only_in_vector
= true;
11921 rmode
= FPROUNDING_ZERO
;
11923 case 0x58: /* FRINTA */
11925 only_in_vector
= true;
11926 rmode
= FPROUNDING_TIEAWAY
;
11928 case 0x59: /* FRINTX */
11929 case 0x79: /* FRINTI */
11930 only_in_vector
= true;
11931 /* current rounding mode */
11933 case 0x1a: /* FCVTNS */
11935 rmode
= FPROUNDING_TIEEVEN
;
11937 case 0x1b: /* FCVTMS */
11939 rmode
= FPROUNDING_NEGINF
;
11941 case 0x1c: /* FCVTAS */
11943 rmode
= FPROUNDING_TIEAWAY
;
11945 case 0x3a: /* FCVTPS */
11947 rmode
= FPROUNDING_POSINF
;
11949 case 0x3b: /* FCVTZS */
11951 rmode
= FPROUNDING_ZERO
;
11953 case 0x5a: /* FCVTNU */
11955 rmode
= FPROUNDING_TIEEVEN
;
11957 case 0x5b: /* FCVTMU */
11959 rmode
= FPROUNDING_NEGINF
;
11961 case 0x5c: /* FCVTAU */
11963 rmode
= FPROUNDING_TIEAWAY
;
11965 case 0x7a: /* FCVTPU */
11967 rmode
= FPROUNDING_POSINF
;
11969 case 0x7b: /* FCVTZU */
11971 rmode
= FPROUNDING_ZERO
;
11973 case 0x2f: /* FABS */
11974 case 0x6f: /* FNEG */
11977 case 0x7d: /* FRSQRTE */
11978 case 0x7f: /* FSQRT (vector) */
11981 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
11982 g_assert_not_reached();
11986 /* Check additional constraints for the scalar encoding */
11989 unallocated_encoding(s
);
11992 /* FRINTxx is only in the vector form */
11993 if (only_in_vector
) {
11994 unallocated_encoding(s
);
11999 if (!fp_access_check(s
)) {
12003 if (need_rmode
|| need_fpst
) {
12004 tcg_fpstatus
= get_fpstatus_ptr(true);
12008 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12009 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12013 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12014 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12017 case 0x1a: /* FCVTNS */
12018 case 0x1b: /* FCVTMS */
12019 case 0x1c: /* FCVTAS */
12020 case 0x3a: /* FCVTPS */
12021 case 0x3b: /* FCVTZS */
12022 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12024 case 0x3d: /* FRECPE */
12025 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12027 case 0x3f: /* FRECPX */
12028 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12030 case 0x5a: /* FCVTNU */
12031 case 0x5b: /* FCVTMU */
12032 case 0x5c: /* FCVTAU */
12033 case 0x7a: /* FCVTPU */
12034 case 0x7b: /* FCVTZU */
12035 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12037 case 0x6f: /* FNEG */
12038 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12040 case 0x7d: /* FRSQRTE */
12041 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12044 g_assert_not_reached();
12047 /* limit any sign extension going on */
12048 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12049 write_fp_sreg(s
, rd
, tcg_res
);
12051 tcg_temp_free_i32(tcg_res
);
12052 tcg_temp_free_i32(tcg_op
);
12054 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12055 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12056 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12058 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12061 case 0x1a: /* FCVTNS */
12062 case 0x1b: /* FCVTMS */
12063 case 0x1c: /* FCVTAS */
12064 case 0x3a: /* FCVTPS */
12065 case 0x3b: /* FCVTZS */
12066 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12068 case 0x3d: /* FRECPE */
12069 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12071 case 0x5a: /* FCVTNU */
12072 case 0x5b: /* FCVTMU */
12073 case 0x5c: /* FCVTAU */
12074 case 0x7a: /* FCVTPU */
12075 case 0x7b: /* FCVTZU */
12076 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12078 case 0x18: /* FRINTN */
12079 case 0x19: /* FRINTM */
12080 case 0x38: /* FRINTP */
12081 case 0x39: /* FRINTZ */
12082 case 0x58: /* FRINTA */
12083 case 0x79: /* FRINTI */
12084 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12086 case 0x59: /* FRINTX */
12087 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12089 case 0x2f: /* FABS */
12090 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12092 case 0x6f: /* FNEG */
12093 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12095 case 0x7d: /* FRSQRTE */
12096 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12098 case 0x7f: /* FSQRT */
12099 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12102 g_assert_not_reached();
12105 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12107 tcg_temp_free_i32(tcg_res
);
12108 tcg_temp_free_i32(tcg_op
);
12111 clear_vec_high(s
, is_q
, rd
);
12115 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12116 tcg_temp_free_i32(tcg_rmode
);
12119 if (tcg_fpstatus
) {
12120 tcg_temp_free_ptr(tcg_fpstatus
);
12124 /* AdvSIMD scalar x indexed element
12125 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12126 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12127 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12128 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12129 * AdvSIMD vector x indexed element
12130 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12131 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12132 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12133 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12135 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12137 /* This encoding has two kinds of instruction:
12138 * normal, where we perform elt x idxelt => elt for each
12139 * element in the vector
12140 * long, where we perform elt x idxelt and generate a result of
12141 * double the width of the input element
12142 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12144 bool is_scalar
= extract32(insn
, 28, 1);
12145 bool is_q
= extract32(insn
, 30, 1);
12146 bool u
= extract32(insn
, 29, 1);
12147 int size
= extract32(insn
, 22, 2);
12148 int l
= extract32(insn
, 21, 1);
12149 int m
= extract32(insn
, 20, 1);
12150 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12151 int rm
= extract32(insn
, 16, 4);
12152 int opcode
= extract32(insn
, 12, 4);
12153 int h
= extract32(insn
, 11, 1);
12154 int rn
= extract32(insn
, 5, 5);
12155 int rd
= extract32(insn
, 0, 5);
12156 bool is_long
= false;
12158 bool is_fp16
= false;
12162 switch (16 * u
+ opcode
) {
12163 case 0x08: /* MUL */
12164 case 0x10: /* MLA */
12165 case 0x14: /* MLS */
12167 unallocated_encoding(s
);
12171 case 0x02: /* SMLAL, SMLAL2 */
12172 case 0x12: /* UMLAL, UMLAL2 */
12173 case 0x06: /* SMLSL, SMLSL2 */
12174 case 0x16: /* UMLSL, UMLSL2 */
12175 case 0x0a: /* SMULL, SMULL2 */
12176 case 0x1a: /* UMULL, UMULL2 */
12178 unallocated_encoding(s
);
12183 case 0x03: /* SQDMLAL, SQDMLAL2 */
12184 case 0x07: /* SQDMLSL, SQDMLSL2 */
12185 case 0x0b: /* SQDMULL, SQDMULL2 */
12188 case 0x0c: /* SQDMULH */
12189 case 0x0d: /* SQRDMULH */
12191 case 0x01: /* FMLA */
12192 case 0x05: /* FMLS */
12193 case 0x09: /* FMUL */
12194 case 0x19: /* FMULX */
12197 case 0x1d: /* SQRDMLAH */
12198 case 0x1f: /* SQRDMLSH */
12199 if (!dc_isar_feature(aa64_rdm
, s
)) {
12200 unallocated_encoding(s
);
12204 case 0x0e: /* SDOT */
12205 case 0x1e: /* UDOT */
12206 if (size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12207 unallocated_encoding(s
);
12211 case 0x11: /* FCMLA #0 */
12212 case 0x13: /* FCMLA #90 */
12213 case 0x15: /* FCMLA #180 */
12214 case 0x17: /* FCMLA #270 */
12215 if (!dc_isar_feature(aa64_fcma
, s
)) {
12216 unallocated_encoding(s
);
12222 unallocated_encoding(s
);
12227 case 1: /* normal fp */
12228 /* convert insn encoded size to TCGMemOp size */
12230 case 0: /* half-precision */
12234 case MO_32
: /* single precision */
12235 case MO_64
: /* double precision */
12238 unallocated_encoding(s
);
12243 case 2: /* complex fp */
12244 /* Each indexable element is a complex pair. */
12249 unallocated_encoding(s
);
12257 unallocated_encoding(s
);
12262 default: /* integer */
12266 unallocated_encoding(s
);
12271 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12272 unallocated_encoding(s
);
12276 /* Given TCGMemOp size, adjust register and indexing. */
12279 index
= h
<< 2 | l
<< 1 | m
;
12282 index
= h
<< 1 | l
;
12287 unallocated_encoding(s
);
12294 g_assert_not_reached();
12297 if (!fp_access_check(s
)) {
12302 fpst
= get_fpstatus_ptr(is_fp16
);
12307 switch (16 * u
+ opcode
) {
12308 case 0x0e: /* SDOT */
12309 case 0x1e: /* UDOT */
12310 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12311 u
? gen_helper_gvec_udot_idx_b
12312 : gen_helper_gvec_sdot_idx_b
);
12314 case 0x11: /* FCMLA #0 */
12315 case 0x13: /* FCMLA #90 */
12316 case 0x15: /* FCMLA #180 */
12317 case 0x17: /* FCMLA #270 */
12319 int rot
= extract32(insn
, 13, 2);
12320 int data
= (index
<< 2) | rot
;
12321 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12322 vec_full_reg_offset(s
, rn
),
12323 vec_full_reg_offset(s
, rm
), fpst
,
12324 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12326 ? gen_helper_gvec_fcmlas_idx
12327 : gen_helper_gvec_fcmlah_idx
);
12328 tcg_temp_free_ptr(fpst
);
12334 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12337 assert(is_fp
&& is_q
&& !is_long
);
12339 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12341 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12342 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12343 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12345 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12347 switch (16 * u
+ opcode
) {
12348 case 0x05: /* FMLS */
12349 /* As usual for ARM, separate negation for fused multiply-add */
12350 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12352 case 0x01: /* FMLA */
12353 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12354 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12356 case 0x09: /* FMUL */
12357 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12359 case 0x19: /* FMULX */
12360 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12363 g_assert_not_reached();
12366 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12367 tcg_temp_free_i64(tcg_op
);
12368 tcg_temp_free_i64(tcg_res
);
12371 tcg_temp_free_i64(tcg_idx
);
12372 clear_vec_high(s
, !is_scalar
, rd
);
12373 } else if (!is_long
) {
12374 /* 32 bit floating point, or 16 or 32 bit integer.
12375 * For the 16 bit scalar case we use the usual Neon helpers and
12376 * rely on the fact that 0 op 0 == 0 with no side effects.
12378 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12379 int pass
, maxpasses
;
12384 maxpasses
= is_q
? 4 : 2;
12387 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12389 if (size
== 1 && !is_scalar
) {
12390 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12391 * the index into both halves of the 32 bit tcg_idx and then use
12392 * the usual Neon helpers.
12394 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12397 for (pass
= 0; pass
< maxpasses
; pass
++) {
12398 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12399 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12401 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12403 switch (16 * u
+ opcode
) {
12404 case 0x08: /* MUL */
12405 case 0x10: /* MLA */
12406 case 0x14: /* MLS */
12408 static NeonGenTwoOpFn
* const fns
[2][2] = {
12409 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12410 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12412 NeonGenTwoOpFn
*genfn
;
12413 bool is_sub
= opcode
== 0x4;
12416 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12418 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12420 if (opcode
== 0x8) {
12423 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12424 genfn
= fns
[size
- 1][is_sub
];
12425 genfn(tcg_res
, tcg_op
, tcg_res
);
12428 case 0x05: /* FMLS */
12429 case 0x01: /* FMLA */
12430 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12431 is_scalar
? size
: MO_32
);
12434 if (opcode
== 0x5) {
12435 /* As usual for ARM, separate negation for fused
12437 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12440 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12443 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12448 if (opcode
== 0x5) {
12449 /* As usual for ARM, separate negation for
12450 * fused multiply-add */
12451 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12453 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12457 g_assert_not_reached();
12460 case 0x09: /* FMUL */
12464 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12467 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12472 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12475 g_assert_not_reached();
12478 case 0x19: /* FMULX */
12482 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12485 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12490 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12493 g_assert_not_reached();
12496 case 0x0c: /* SQDMULH */
12498 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12501 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12505 case 0x0d: /* SQRDMULH */
12507 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
12510 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
12514 case 0x1d: /* SQRDMLAH */
12515 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12516 is_scalar
? size
: MO_32
);
12518 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
12519 tcg_op
, tcg_idx
, tcg_res
);
12521 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
12522 tcg_op
, tcg_idx
, tcg_res
);
12525 case 0x1f: /* SQRDMLSH */
12526 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12527 is_scalar
? size
: MO_32
);
12529 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
12530 tcg_op
, tcg_idx
, tcg_res
);
12532 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
12533 tcg_op
, tcg_idx
, tcg_res
);
12537 g_assert_not_reached();
12541 write_fp_sreg(s
, rd
, tcg_res
);
12543 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12546 tcg_temp_free_i32(tcg_op
);
12547 tcg_temp_free_i32(tcg_res
);
12550 tcg_temp_free_i32(tcg_idx
);
12551 clear_vec_high(s
, is_q
, rd
);
12553 /* long ops: 16x16->32 or 32x32->64 */
12554 TCGv_i64 tcg_res
[2];
12556 bool satop
= extract32(opcode
, 0, 1);
12557 TCGMemOp memop
= MO_32
;
12564 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12566 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
12568 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12569 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12570 TCGv_i64 tcg_passres
;
12576 passelt
= pass
+ (is_q
* 2);
12579 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
12581 tcg_res
[pass
] = tcg_temp_new_i64();
12583 if (opcode
== 0xa || opcode
== 0xb) {
12584 /* Non-accumulating ops */
12585 tcg_passres
= tcg_res
[pass
];
12587 tcg_passres
= tcg_temp_new_i64();
12590 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
12591 tcg_temp_free_i64(tcg_op
);
12594 /* saturating, doubling */
12595 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
12596 tcg_passres
, tcg_passres
);
12599 if (opcode
== 0xa || opcode
== 0xb) {
12603 /* Accumulating op: handle accumulate step */
12604 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12607 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
12608 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
12610 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
12611 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
12613 case 0x7: /* SQDMLSL, SQDMLSL2 */
12614 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
12616 case 0x3: /* SQDMLAL, SQDMLAL2 */
12617 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
12622 g_assert_not_reached();
12624 tcg_temp_free_i64(tcg_passres
);
12626 tcg_temp_free_i64(tcg_idx
);
12628 clear_vec_high(s
, !is_scalar
, rd
);
12630 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12633 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12636 /* The simplest way to handle the 16x16 indexed ops is to
12637 * duplicate the index into both halves of the 32 bit tcg_idx
12638 * and then use the usual Neon helpers.
12640 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12643 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12644 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12645 TCGv_i64 tcg_passres
;
12648 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
12650 read_vec_element_i32(s
, tcg_op
, rn
,
12651 pass
+ (is_q
* 2), MO_32
);
12654 tcg_res
[pass
] = tcg_temp_new_i64();
12656 if (opcode
== 0xa || opcode
== 0xb) {
12657 /* Non-accumulating ops */
12658 tcg_passres
= tcg_res
[pass
];
12660 tcg_passres
= tcg_temp_new_i64();
12663 if (memop
& MO_SIGN
) {
12664 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
12666 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
12669 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
12670 tcg_passres
, tcg_passres
);
12672 tcg_temp_free_i32(tcg_op
);
12674 if (opcode
== 0xa || opcode
== 0xb) {
12678 /* Accumulating op: handle accumulate step */
12679 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12682 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
12683 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
12686 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
12687 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
12690 case 0x7: /* SQDMLSL, SQDMLSL2 */
12691 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
12693 case 0x3: /* SQDMLAL, SQDMLAL2 */
12694 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
12699 g_assert_not_reached();
12701 tcg_temp_free_i64(tcg_passres
);
12703 tcg_temp_free_i32(tcg_idx
);
12706 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
12711 tcg_res
[1] = tcg_const_i64(0);
12714 for (pass
= 0; pass
< 2; pass
++) {
12715 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12716 tcg_temp_free_i64(tcg_res
[pass
]);
12721 tcg_temp_free_ptr(fpst
);
12726 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
12727 * +-----------------+------+-----------+--------+-----+------+------+
12728 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
12729 * +-----------------+------+-----------+--------+-----+------+------+
12731 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
12733 int size
= extract32(insn
, 22, 2);
12734 int opcode
= extract32(insn
, 12, 5);
12735 int rn
= extract32(insn
, 5, 5);
12736 int rd
= extract32(insn
, 0, 5);
12738 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
12739 TCGv_i32 tcg_decrypt
;
12740 CryptoThreeOpIntFn
*genfn
;
12742 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
12743 unallocated_encoding(s
);
12748 case 0x4: /* AESE */
12750 genfn
= gen_helper_crypto_aese
;
12752 case 0x6: /* AESMC */
12754 genfn
= gen_helper_crypto_aesmc
;
12756 case 0x5: /* AESD */
12758 genfn
= gen_helper_crypto_aese
;
12760 case 0x7: /* AESIMC */
12762 genfn
= gen_helper_crypto_aesmc
;
12765 unallocated_encoding(s
);
12769 if (!fp_access_check(s
)) {
12773 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12774 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12775 tcg_decrypt
= tcg_const_i32(decrypt
);
12777 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
12779 tcg_temp_free_ptr(tcg_rd_ptr
);
12780 tcg_temp_free_ptr(tcg_rn_ptr
);
12781 tcg_temp_free_i32(tcg_decrypt
);
12784 /* Crypto three-reg SHA
12785 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
12786 * +-----------------+------+---+------+---+--------+-----+------+------+
12787 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
12788 * +-----------------+------+---+------+---+--------+-----+------+------+
12790 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
12792 int size
= extract32(insn
, 22, 2);
12793 int opcode
= extract32(insn
, 12, 3);
12794 int rm
= extract32(insn
, 16, 5);
12795 int rn
= extract32(insn
, 5, 5);
12796 int rd
= extract32(insn
, 0, 5);
12797 CryptoThreeOpFn
*genfn
;
12798 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
12802 unallocated_encoding(s
);
12807 case 0: /* SHA1C */
12808 case 1: /* SHA1P */
12809 case 2: /* SHA1M */
12810 case 3: /* SHA1SU0 */
12812 feature
= dc_isar_feature(aa64_sha1
, s
);
12814 case 4: /* SHA256H */
12815 genfn
= gen_helper_crypto_sha256h
;
12816 feature
= dc_isar_feature(aa64_sha256
, s
);
12818 case 5: /* SHA256H2 */
12819 genfn
= gen_helper_crypto_sha256h2
;
12820 feature
= dc_isar_feature(aa64_sha256
, s
);
12822 case 6: /* SHA256SU1 */
12823 genfn
= gen_helper_crypto_sha256su1
;
12824 feature
= dc_isar_feature(aa64_sha256
, s
);
12827 unallocated_encoding(s
);
12832 unallocated_encoding(s
);
12836 if (!fp_access_check(s
)) {
12840 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12841 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12842 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
12845 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
12847 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
12849 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
12850 tcg_rm_ptr
, tcg_opcode
);
12851 tcg_temp_free_i32(tcg_opcode
);
12854 tcg_temp_free_ptr(tcg_rd_ptr
);
12855 tcg_temp_free_ptr(tcg_rn_ptr
);
12856 tcg_temp_free_ptr(tcg_rm_ptr
);
12859 /* Crypto two-reg SHA
12860 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
12861 * +-----------------+------+-----------+--------+-----+------+------+
12862 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
12863 * +-----------------+------+-----------+--------+-----+------+------+
12865 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
12867 int size
= extract32(insn
, 22, 2);
12868 int opcode
= extract32(insn
, 12, 5);
12869 int rn
= extract32(insn
, 5, 5);
12870 int rd
= extract32(insn
, 0, 5);
12871 CryptoTwoOpFn
*genfn
;
12873 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
12876 unallocated_encoding(s
);
12881 case 0: /* SHA1H */
12882 feature
= dc_isar_feature(aa64_sha1
, s
);
12883 genfn
= gen_helper_crypto_sha1h
;
12885 case 1: /* SHA1SU1 */
12886 feature
= dc_isar_feature(aa64_sha1
, s
);
12887 genfn
= gen_helper_crypto_sha1su1
;
12889 case 2: /* SHA256SU0 */
12890 feature
= dc_isar_feature(aa64_sha256
, s
);
12891 genfn
= gen_helper_crypto_sha256su0
;
12894 unallocated_encoding(s
);
12899 unallocated_encoding(s
);
12903 if (!fp_access_check(s
)) {
12907 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12908 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12910 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
12912 tcg_temp_free_ptr(tcg_rd_ptr
);
12913 tcg_temp_free_ptr(tcg_rn_ptr
);
12916 /* Crypto three-reg SHA512
12917 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
12918 * +-----------------------+------+---+---+-----+--------+------+------+
12919 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
12920 * +-----------------------+------+---+---+-----+--------+------+------+
12922 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
12924 int opcode
= extract32(insn
, 10, 2);
12925 int o
= extract32(insn
, 14, 1);
12926 int rm
= extract32(insn
, 16, 5);
12927 int rn
= extract32(insn
, 5, 5);
12928 int rd
= extract32(insn
, 0, 5);
12930 CryptoThreeOpFn
*genfn
;
12934 case 0: /* SHA512H */
12935 feature
= dc_isar_feature(aa64_sha512
, s
);
12936 genfn
= gen_helper_crypto_sha512h
;
12938 case 1: /* SHA512H2 */
12939 feature
= dc_isar_feature(aa64_sha512
, s
);
12940 genfn
= gen_helper_crypto_sha512h2
;
12942 case 2: /* SHA512SU1 */
12943 feature
= dc_isar_feature(aa64_sha512
, s
);
12944 genfn
= gen_helper_crypto_sha512su1
;
12947 feature
= dc_isar_feature(aa64_sha3
, s
);
12953 case 0: /* SM3PARTW1 */
12954 feature
= dc_isar_feature(aa64_sm3
, s
);
12955 genfn
= gen_helper_crypto_sm3partw1
;
12957 case 1: /* SM3PARTW2 */
12958 feature
= dc_isar_feature(aa64_sm3
, s
);
12959 genfn
= gen_helper_crypto_sm3partw2
;
12961 case 2: /* SM4EKEY */
12962 feature
= dc_isar_feature(aa64_sm4
, s
);
12963 genfn
= gen_helper_crypto_sm4ekey
;
12966 unallocated_encoding(s
);
12972 unallocated_encoding(s
);
12976 if (!fp_access_check(s
)) {
12981 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
12983 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12984 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12985 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
12987 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
12989 tcg_temp_free_ptr(tcg_rd_ptr
);
12990 tcg_temp_free_ptr(tcg_rn_ptr
);
12991 tcg_temp_free_ptr(tcg_rm_ptr
);
12993 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
12996 tcg_op1
= tcg_temp_new_i64();
12997 tcg_op2
= tcg_temp_new_i64();
12998 tcg_res
[0] = tcg_temp_new_i64();
12999 tcg_res
[1] = tcg_temp_new_i64();
13001 for (pass
= 0; pass
< 2; pass
++) {
13002 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13003 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13005 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13006 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13008 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13009 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13011 tcg_temp_free_i64(tcg_op1
);
13012 tcg_temp_free_i64(tcg_op2
);
13013 tcg_temp_free_i64(tcg_res
[0]);
13014 tcg_temp_free_i64(tcg_res
[1]);
13018 /* Crypto two-reg SHA512
13019 * 31 12 11 10 9 5 4 0
13020 * +-----------------------------------------+--------+------+------+
13021 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13022 * +-----------------------------------------+--------+------+------+
13024 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13026 int opcode
= extract32(insn
, 10, 2);
13027 int rn
= extract32(insn
, 5, 5);
13028 int rd
= extract32(insn
, 0, 5);
13029 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13031 CryptoTwoOpFn
*genfn
;
13034 case 0: /* SHA512SU0 */
13035 feature
= dc_isar_feature(aa64_sha512
, s
);
13036 genfn
= gen_helper_crypto_sha512su0
;
13039 feature
= dc_isar_feature(aa64_sm4
, s
);
13040 genfn
= gen_helper_crypto_sm4e
;
13043 unallocated_encoding(s
);
13048 unallocated_encoding(s
);
13052 if (!fp_access_check(s
)) {
13056 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13057 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13059 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13061 tcg_temp_free_ptr(tcg_rd_ptr
);
13062 tcg_temp_free_ptr(tcg_rn_ptr
);
13065 /* Crypto four-register
13066 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13067 * +-------------------+-----+------+---+------+------+------+
13068 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13069 * +-------------------+-----+------+---+------+------+------+
13071 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13073 int op0
= extract32(insn
, 21, 2);
13074 int rm
= extract32(insn
, 16, 5);
13075 int ra
= extract32(insn
, 10, 5);
13076 int rn
= extract32(insn
, 5, 5);
13077 int rd
= extract32(insn
, 0, 5);
13083 feature
= dc_isar_feature(aa64_sha3
, s
);
13085 case 2: /* SM3SS1 */
13086 feature
= dc_isar_feature(aa64_sm3
, s
);
13089 unallocated_encoding(s
);
13094 unallocated_encoding(s
);
13098 if (!fp_access_check(s
)) {
13103 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13106 tcg_op1
= tcg_temp_new_i64();
13107 tcg_op2
= tcg_temp_new_i64();
13108 tcg_op3
= tcg_temp_new_i64();
13109 tcg_res
[0] = tcg_temp_new_i64();
13110 tcg_res
[1] = tcg_temp_new_i64();
13112 for (pass
= 0; pass
< 2; pass
++) {
13113 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13114 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13115 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13119 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13122 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13124 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13126 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13127 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13129 tcg_temp_free_i64(tcg_op1
);
13130 tcg_temp_free_i64(tcg_op2
);
13131 tcg_temp_free_i64(tcg_op3
);
13132 tcg_temp_free_i64(tcg_res
[0]);
13133 tcg_temp_free_i64(tcg_res
[1]);
13135 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13137 tcg_op1
= tcg_temp_new_i32();
13138 tcg_op2
= tcg_temp_new_i32();
13139 tcg_op3
= tcg_temp_new_i32();
13140 tcg_res
= tcg_temp_new_i32();
13141 tcg_zero
= tcg_const_i32(0);
13143 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13144 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13145 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13147 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13148 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13149 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13150 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13152 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13153 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13154 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13155 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13157 tcg_temp_free_i32(tcg_op1
);
13158 tcg_temp_free_i32(tcg_op2
);
13159 tcg_temp_free_i32(tcg_op3
);
13160 tcg_temp_free_i32(tcg_res
);
13161 tcg_temp_free_i32(tcg_zero
);
13166 * 31 21 20 16 15 10 9 5 4 0
13167 * +-----------------------+------+--------+------+------+
13168 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13169 * +-----------------------+------+--------+------+------+
13171 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13173 int rm
= extract32(insn
, 16, 5);
13174 int imm6
= extract32(insn
, 10, 6);
13175 int rn
= extract32(insn
, 5, 5);
13176 int rd
= extract32(insn
, 0, 5);
13177 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13180 if (!dc_isar_feature(aa64_sha3
, s
)) {
13181 unallocated_encoding(s
);
13185 if (!fp_access_check(s
)) {
13189 tcg_op1
= tcg_temp_new_i64();
13190 tcg_op2
= tcg_temp_new_i64();
13191 tcg_res
[0] = tcg_temp_new_i64();
13192 tcg_res
[1] = tcg_temp_new_i64();
13194 for (pass
= 0; pass
< 2; pass
++) {
13195 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13196 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13198 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13199 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13201 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13202 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13204 tcg_temp_free_i64(tcg_op1
);
13205 tcg_temp_free_i64(tcg_op2
);
13206 tcg_temp_free_i64(tcg_res
[0]);
13207 tcg_temp_free_i64(tcg_res
[1]);
13210 /* Crypto three-reg imm2
13211 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13212 * +-----------------------+------+-----+------+--------+------+------+
13213 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13214 * +-----------------------+------+-----+------+--------+------+------+
13216 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13218 int opcode
= extract32(insn
, 10, 2);
13219 int imm2
= extract32(insn
, 12, 2);
13220 int rm
= extract32(insn
, 16, 5);
13221 int rn
= extract32(insn
, 5, 5);
13222 int rd
= extract32(insn
, 0, 5);
13223 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13224 TCGv_i32 tcg_imm2
, tcg_opcode
;
13226 if (!dc_isar_feature(aa64_sm3
, s
)) {
13227 unallocated_encoding(s
);
13231 if (!fp_access_check(s
)) {
13235 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13236 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13237 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13238 tcg_imm2
= tcg_const_i32(imm2
);
13239 tcg_opcode
= tcg_const_i32(opcode
);
13241 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13244 tcg_temp_free_ptr(tcg_rd_ptr
);
13245 tcg_temp_free_ptr(tcg_rn_ptr
);
13246 tcg_temp_free_ptr(tcg_rm_ptr
);
13247 tcg_temp_free_i32(tcg_imm2
);
13248 tcg_temp_free_i32(tcg_opcode
);
13251 /* C3.6 Data processing - SIMD, inc Crypto
13253 * As the decode gets a little complex we are using a table based
13254 * approach for this part of the decode.
13256 static const AArch64DecodeTable data_proc_simd
[] = {
13257 /* pattern , mask , fn */
13258 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13259 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13260 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13261 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13262 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13263 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13264 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13265 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13266 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13267 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13268 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13269 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13270 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13271 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13272 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13273 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13274 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13275 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13276 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13277 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13278 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13279 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13280 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13281 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13282 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13283 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13284 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13285 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13286 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13287 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13288 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13289 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13290 { 0x00000000, 0x00000000, NULL
}
13293 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13295 /* Note that this is called with all non-FP cases from
13296 * table C3-6 so it must UNDEF for entries not specifically
13297 * allocated to instructions in that table.
13299 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13303 unallocated_encoding(s
);
13307 /* C3.6 Data processing - SIMD and floating point */
13308 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13310 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13311 disas_data_proc_fp(s
, insn
);
13313 /* SIMD, including crypto */
13314 disas_data_proc_simd(s
, insn
);
13318 /* C3.1 A64 instruction index by encoding */
13319 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13323 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13327 s
->fp_access_checked
= false;
13329 switch (extract32(insn
, 25, 4)) {
13330 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13331 unallocated_encoding(s
);
13334 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
13335 unallocated_encoding(s
);
13338 case 0x8: case 0x9: /* Data processing - immediate */
13339 disas_data_proc_imm(s
, insn
);
13341 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13342 disas_b_exc_sys(s
, insn
);
13347 case 0xe: /* Loads and stores */
13348 disas_ldst(s
, insn
);
13351 case 0xd: /* Data processing - register */
13352 disas_data_proc_reg(s
, insn
);
13355 case 0xf: /* Data processing - SIMD and floating point */
13356 disas_data_proc_simd_fp(s
, insn
);
13359 assert(FALSE
); /* all 15 cases should be handled above */
13363 /* if we allocated any temporaries, free them here */
13367 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13370 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13371 CPUARMState
*env
= cpu
->env_ptr
;
13372 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13375 dc
->isar
= &arm_cpu
->isar
;
13376 dc
->pc
= dc
->base
.pc_first
;
13380 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13381 * there is no secure EL1, so we route exceptions to EL3.
13383 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13384 !arm_el_is_aa64(env
, 3);
13387 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
13388 dc
->condexec_mask
= 0;
13389 dc
->condexec_cond
= 0;
13390 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
13391 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
13392 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
13393 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13394 #if !defined(CONFIG_USER_ONLY)
13395 dc
->user
= (dc
->current_el
== 0);
13397 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
13398 dc
->sve_excp_el
= ARM_TBFLAG_SVEEXC_EL(dc
->base
.tb
->flags
);
13399 dc
->sve_len
= (ARM_TBFLAG_ZCR_LEN(dc
->base
.tb
->flags
) + 1) * 16;
13401 dc
->vec_stride
= 0;
13402 dc
->cp_regs
= arm_cpu
->cp_regs
;
13403 dc
->features
= env
->features
;
13405 /* Single step state. The code-generation logic here is:
13407 * generate code with no special handling for single-stepping (except
13408 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13409 * this happens anyway because those changes are all system register or
13411 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13412 * emit code for one insn
13413 * emit code to clear PSTATE.SS
13414 * emit code to generate software step exception for completed step
13415 * end TB (as usual for having generated an exception)
13416 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13417 * emit code to generate a software step exception
13420 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
13421 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
13422 dc
->is_ldex
= false;
13423 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
13425 /* Bound the number of insns to execute to those left on the page. */
13426 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13428 /* If architectural single step active, limit to 1. */
13429 if (dc
->ss_active
) {
13432 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13434 init_tmp_a64_array(dc
);
13437 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
13441 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13443 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13445 tcg_gen_insn_start(dc
->pc
, 0, 0);
13446 dc
->insn_start
= tcg_last_op();
13449 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13450 const CPUBreakpoint
*bp
)
13452 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13454 if (bp
->flags
& BP_CPU
) {
13455 gen_a64_set_pc_im(dc
->pc
);
13456 gen_helper_check_breakpoints(cpu_env
);
13457 /* End the TB early; it likely won't be executed */
13458 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13460 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13461 /* The address covered by the breakpoint must be
13462 included in [tb->pc, tb->pc + tb->size) in order
13463 to for it to be properly cleared -- thus we
13464 increment the PC here so that the logic setting
13465 tb->size below does the right thing. */
13467 dc
->base
.is_jmp
= DISAS_NORETURN
;
13473 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13475 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13476 CPUARMState
*env
= cpu
->env_ptr
;
13478 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13479 /* Singlestep state is Active-pending.
13480 * If we're in this state at the start of a TB then either
13481 * a) we just took an exception to an EL which is being debugged
13482 * and this is the first insn in the exception handler
13483 * b) debug exceptions were masked and we just unmasked them
13484 * without changing EL (eg by clearing PSTATE.D)
13485 * In either case we're going to take a swstep exception in the
13486 * "did not step an insn" case, and so the syndrome ISV and EX
13487 * bits should be zero.
13489 assert(dc
->base
.num_insns
== 1);
13490 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13491 default_exception_el(dc
));
13492 dc
->base
.is_jmp
= DISAS_NORETURN
;
13494 disas_a64_insn(env
, dc
);
13497 dc
->base
.pc_next
= dc
->pc
;
13498 translator_loop_temp_check(&dc
->base
);
13501 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13503 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13505 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
13506 /* Note that this means single stepping WFI doesn't halt the CPU.
13507 * For conditional branch insns this is harmless unreachable code as
13508 * gen_goto_tb() has already handled emitting the debug exception
13509 * (and thus a tb-jump is not possible when singlestepping).
13511 switch (dc
->base
.is_jmp
) {
13513 gen_a64_set_pc_im(dc
->pc
);
13517 if (dc
->base
.singlestep_enabled
) {
13518 gen_exception_internal(EXCP_DEBUG
);
13520 gen_step_complete_exception(dc
);
13523 case DISAS_NORETURN
:
13527 switch (dc
->base
.is_jmp
) {
13529 case DISAS_TOO_MANY
:
13530 gen_goto_tb(dc
, 1, dc
->pc
);
13534 gen_a64_set_pc_im(dc
->pc
);
13537 tcg_gen_exit_tb(NULL
, 0);
13540 tcg_gen_lookup_and_goto_ptr();
13542 case DISAS_NORETURN
:
13546 gen_a64_set_pc_im(dc
->pc
);
13547 gen_helper_wfe(cpu_env
);
13550 gen_a64_set_pc_im(dc
->pc
);
13551 gen_helper_yield(cpu_env
);
13555 /* This is a special case because we don't want to just halt the CPU
13556 * if trying to debug across a WFI.
13558 TCGv_i32 tmp
= tcg_const_i32(4);
13560 gen_a64_set_pc_im(dc
->pc
);
13561 gen_helper_wfi(cpu_env
, tmp
);
13562 tcg_temp_free_i32(tmp
);
13563 /* The helper doesn't necessarily throw an exception, but we
13564 * must go back to the main loop to check for interrupts anyway.
13566 tcg_gen_exit_tb(NULL
, 0);
13572 /* Functions above can change dc->pc, so re-align db->pc_next */
13573 dc
->base
.pc_next
= dc
->pc
;
13576 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
13579 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13581 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
13582 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
13585 const TranslatorOps aarch64_translator_ops
= {
13586 .init_disas_context
= aarch64_tr_init_disas_context
,
13587 .tb_start
= aarch64_tr_tb_start
,
13588 .insn_start
= aarch64_tr_insn_start
,
13589 .breakpoint_check
= aarch64_tr_breakpoint_check
,
13590 .translate_insn
= aarch64_tr_translate_insn
,
13591 .tb_stop
= aarch64_tr_tb_stop
,
13592 .disas_log
= aarch64_tr_disas_log
,