hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/loader.h"
  32 #include "sysemu/arch_init.h"
  33 #include "hw/i2c/smbus.h"
  34 #include "hw/boards.h"
  35 #include "hw/timer/mc146818rtc.h"
  36 #include "hw/xen/xen.h"
  37 #include "sysemu/kvm.h"
  38 #include "hw/kvm/clock.h"
  39 #include "hw/pci-host/q35.h"
  40 #include "exec/address-spaces.h"
  41 #include "hw/i386/ich9.h"
  42 #include "hw/smbios/smbios.h"
  43 #include "hw/ide/pci.h"
  44 #include "hw/ide/ahci.h"
  45 #include "hw/usb.h"
  46 #include "hw/cpu/icc_bus.h"
  47 #include "qemu/error-report.h"
  48 #include "migration/migration.h"
  49
  50 /* ICH9 AHCI has 6 ports */
  51 #define MAX_SATA_PORTS     6
  52
  53 static bool has_acpi_build = true;
  54 static bool rsdp_in_ram = true;
  55 static bool smbios_defaults = true;
  56 static bool smbios_legacy_mode;
  57 static bool smbios_uuid_encoded = true;
  58 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
  59  * host addresses aligned at 1Gbyte boundaries.  This way we can use 1GByte
  60  * pages in the host.
  61  */
  62 static bool gigabyte_align = true;
  63 static bool has_reserved_memory = true;
  64
  65 /* PC hardware initialisation */
  66 static void pc_q35_init(MachineState *machine)
  67 {
  68     PCMachineState *pcms = PC_MACHINE(machine);
  69     Q35PCIHost *q35_host;
  70     PCIHostState *phb;
  71     PCIBus *host_bus;
  72     PCIDevice *lpc;
  73     BusState *idebus[MAX_SATA_PORTS];
  74     ISADevice *rtc_state;
  75     MemoryRegion *pci_memory;
  76     MemoryRegion *rom_memory;
  77     MemoryRegion *ram_memory;
  78     GSIState *gsi_state;
  79     ISABus *isa_bus;
  80     int pci_enabled = 1;
  81     qemu_irq *gsi;
  82     qemu_irq *i8259;
  83     int i;
  84     ICH9LPCState *ich9_lpc;
  85     PCIDevice *ahci;
  86     DeviceState *icc_bridge;
  87     PcGuestInfo *guest_info;
  88     ram_addr_t lowmem;
  89     DriveInfo *hd[MAX_SATA_PORTS];
  90     MachineClass *mc = MACHINE_GET_CLASS(machine);
  91
  92     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  93      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  94      * also known as MMCFG).
  95      * If it doesn't, we need to split it in chunks below and above 4G.
  96      * In any case, try to make sure that guest addresses aligned at
  97      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  98      * For old machine types, use whatever split we used historically to avoid
  99      * breaking migration.
 100      */
 101     if (machine->ram_size >= 0xb0000000) {
 102         lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
 103     } else {
 104         lowmem = 0xb0000000;
 105     }
 106
 107     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 108      * min(qemu limit, user limit).
 109      */
 110     if (lowmem > pcms->max_ram_below_4g) {
 111         lowmem = pcms->max_ram_below_4g;
 112         if (machine->ram_size - lowmem > lowmem &&
 113             lowmem & ((1ULL << 30) - 1)) {
 114             error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
 115                          ") not a multiple of 1G; possible bad performance.",
 116                          pcms->max_ram_below_4g);
 117         }
 118     }
 119
 120     if (machine->ram_size >= lowmem) {
 121         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 122         pcms->below_4g_mem_size = lowmem;
 123     } else {
 124         pcms->above_4g_mem_size = 0;
 125         pcms->below_4g_mem_size = machine->ram_size;
 126     }
 127
 128     if (xen_enabled() && xen_hvm_init(pcms, &ram_memory) != 0) {
 129         fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
 130         exit(1);
 131     }
 132
 133     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
 134     object_property_add_child(qdev_get_machine(), "icc-bridge",
 135                               OBJECT(icc_bridge), NULL);
 136
 137     pc_cpus_init(machine->cpu_model, icc_bridge);
 138     pc_acpi_init("q35-acpi-dsdt.aml");
 139
 140     kvmclock_create();
 141
 142     /* pci enabled */
 143     if (pci_enabled) {
 144         pci_memory = g_new(MemoryRegion, 1);
 145         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 146         rom_memory = pci_memory;
 147     } else {
 148         pci_memory = NULL;
 149         rom_memory = get_system_memory();
 150     }
 151
 152     guest_info = pc_guest_info_init(pcms);
 153     guest_info->isapc_ram_fw = false;
 154     guest_info->has_acpi_build = has_acpi_build;
 155     guest_info->has_reserved_memory = has_reserved_memory;
 156     guest_info->rsdp_in_ram = rsdp_in_ram;
 157
 158     /* Migration was not supported in 2.0 for Q35, so do not bother
 159      * with this hack (see hw/i386/acpi-build.c).
 160      */
 161     guest_info->legacy_acpi_table_size = 0;
 162
 163     if (smbios_defaults) {
 164         /* These values are guest ABI, do not change */
 165         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 166                             mc->name, smbios_legacy_mode, smbios_uuid_encoded,
 167                             SMBIOS_ENTRY_POINT_21);
 168     }
 169
 170     /* allocate ram and load rom/bios */
 171     if (!xen_enabled()) {
 172         pc_memory_init(pcms, get_system_memory(),
 173                        rom_memory, &ram_memory, guest_info);
 174     }
 175
 176     /* irq lines */
 177     gsi_state = g_malloc0(sizeof(*gsi_state));
 178     if (kvm_irqchip_in_kernel()) {
 179         kvm_pc_setup_irq_routing(pci_enabled);
 180         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 181                                  GSI_NUM_PINS);
 182     } else {
 183         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 184     }
 185
 186     /* create pci host bus */
 187     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 188
 189     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 190     q35_host->mch.ram_memory = ram_memory;
 191     q35_host->mch.pci_address_space = pci_memory;
 192     q35_host->mch.system_memory = get_system_memory();
 193     q35_host->mch.address_space_io = get_system_io();
 194     q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size;
 195     q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size;
 196     q35_host->mch.guest_info = guest_info;
 197     /* pci */
 198     qdev_init_nofail(DEVICE(q35_host));
 199     phb = PCI_HOST_BRIDGE(q35_host);
 200     host_bus = phb->bus;
 201     /* create ISA bus */
 202     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 203                                           ICH9_LPC_FUNC), true,
 204                                           TYPE_ICH9_LPC_DEVICE);
 205
 206     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 207                              TYPE_HOTPLUG_HANDLER,
 208                              (Object **)&pcms->acpi_dev,
 209                              object_property_allow_set_link,
 210                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 211     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 212                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 213
 214     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 215     ich9_lpc->pic = gsi;
 216     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 217     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 218                  ICH9_LPC_NB_PIRQS);
 219     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 220     isa_bus = ich9_lpc->isa_bus;
 221
 222     /*end early*/
 223     isa_bus_irqs(isa_bus, gsi);
 224
 225     if (kvm_irqchip_in_kernel()) {
 226         i8259 = kvm_i8259_init(isa_bus);
 227     } else if (xen_enabled()) {
 228         i8259 = xen_interrupt_controller_init();
 229     } else {
 230         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 231     }
 232
 233     for (i = 0; i < ISA_NUM_IRQS; i++) {
 234         gsi_state->i8259_irq[i] = i8259[i];
 235     }
 236     if (pci_enabled) {
 237         ioapic_init_gsi(gsi_state, "q35");
 238     }
 239     qdev_init_nofail(icc_bridge);
 240
 241     pc_register_ferr_irq(gsi[13]);
 242
 243     assert(pcms->vmport != ON_OFF_AUTO_MAX);
 244     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 245         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 246     }
 247
 248     /* init basic PC hardware */
 249     pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
 250                          (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104);
 251
 252     /* connect pm stuff to lpc */
 253     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms), !mc->no_tco);
 254
 255     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 256     ahci = pci_create_simple_multifunction(host_bus,
 257                                            PCI_DEVFN(ICH9_SATA1_DEV,
 258                                                      ICH9_SATA1_FUNC),
 259                                            true, "ich9-ahci");
 260     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 261     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 262     g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
 263     ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
 264     ahci_ide_create_devs(ahci, hd);
 265
 266     if (usb_enabled()) {
 267         /* Should we create 6 UHCI according to ich9 spec? */
 268         ehci_create_ich9_with_companions(host_bus, 0x1d);
 269     }
 270
 271     /* TODO: Populate SPD eeprom data.  */
 272     smbus_eeprom_init(ich9_smb_init(host_bus,
 273                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 274                                     0xb100),
 275                       8, NULL, 0);
 276
 277     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 278
 279     /* the rest devices to which pci devfn is automatically assigned */
 280     pc_vga_init(isa_bus, host_bus);
 281     pc_nic_init(isa_bus, host_bus);
 282     if (pci_enabled) {
 283         pc_pci_device_init(host_bus);
 284     }
 285 }
 286
 287 /* Looking for a pc_compat_2_4() function? It doesn't exist.
 288  * pc_compat_*() functions that run on machine-init time and
 289  * change global QEMU state are deprecated. Please don't create
 290  * one, and implement any pc-*-2.4 (and newer) compat code in
 291  * HW_COMPAT_*, PC_COMPAT_*, or * pc_*_machine_options().
 292  */
 293
 294 static void pc_compat_2_3(MachineState *machine)
 295 {
 296     PCMachineState *pcms = PC_MACHINE(machine);
 297     savevm_skip_section_footers();
 298     if (kvm_enabled()) {
 299         pcms->smm = ON_OFF_AUTO_OFF;
 300     }
 301     global_state_set_optional();
 302     savevm_skip_configuration();
 303 }
 304
 305 static void pc_compat_2_2(MachineState *machine)
 306 {
 307     pc_compat_2_3(machine);
 308     rsdp_in_ram = false;
 309     machine->suppress_vmdesc = true;
 310 }
 311
 312 static void pc_compat_2_1(MachineState *machine)
 313 {
 314     PCMachineState *pcms = PC_MACHINE(machine);
 315
 316     pc_compat_2_2(machine);
 317     pcms->enforce_aligned_dimm = false;
 318     smbios_uuid_encoded = false;
 319     x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM);
 320 }
 321
 322 static void pc_compat_2_0(MachineState *machine)
 323 {
 324     pc_compat_2_1(machine);
 325     smbios_legacy_mode = true;
 326     has_reserved_memory = false;
 327     pc_set_legacy_acpi_data_size();
 328 }
 329
 330 static void pc_compat_1_7(MachineState *machine)
 331 {
 332     pc_compat_2_0(machine);
 333     smbios_defaults = false;
 334     gigabyte_align = false;
 335     option_rom_has_mr = true;
 336     x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC);
 337 }
 338
 339 static void pc_compat_1_6(MachineState *machine)
 340 {
 341     pc_compat_1_7(machine);
 342     rom_file_has_mr = false;
 343     has_acpi_build = false;
 344 }
 345
 346 static void pc_compat_1_5(MachineState *machine)
 347 {
 348     pc_compat_1_6(machine);
 349 }
 350
 351 static void pc_compat_1_4(MachineState *machine)
 352 {
 353     pc_compat_1_5(machine);
 354 }
 355
 356 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 357     static void pc_init_##suffix(MachineState *machine) \
 358     { \
 359         void (*compat)(MachineState *m) = (compatfn); \
 360         if (compat) { \
 361             compat(machine); \
 362         } \
 363         pc_q35_init(machine); \
 364     } \
 365     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 366
 367
 368 static void pc_q35_machine_options(MachineClass *m)
 369 {
 370     m->family = "pc_q35";
 371     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 372     m->hot_add_cpu = pc_hot_add_cpu;
 373     m->units_per_default_bus = 1;
 374     m->default_machine_opts = "firmware=bios-256k.bin";
 375     m->default_display = "std";
 376     m->no_floppy = 1;
 377     m->no_tco = 0;
 378 }
 379
 380 static void pc_q35_2_5_machine_options(MachineClass *m)
 381 {
 382     pc_q35_machine_options(m);
 383     m->alias = "q35";
 384 }
 385
 386 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 387                    pc_q35_2_5_machine_options);
 388
 389 static void pc_q35_2_4_machine_options(MachineClass *m)
 390 {
 391     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 392     pc_q35_2_5_machine_options(m);
 393     m->alias = NULL;
 394     pcmc->broken_reserved_end = true;
 395     pcmc->inter_dimm_gap = false;
 396     SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 397 }
 398
 399 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 400                    pc_q35_2_4_machine_options);
 401
 402
 403 static void pc_q35_2_3_machine_options(MachineClass *m)
 404 {
 405     pc_q35_2_4_machine_options(m);
 406     m->no_floppy = 0;
 407     m->no_tco = 1;
 408     m->alias = NULL;
 409     SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
 410 }
 411
 412 DEFINE_Q35_MACHINE(v2_3, "pc-q35-2.3", pc_compat_2_3,
 413                    pc_q35_2_3_machine_options);
 414
 415
 416 static void pc_q35_2_2_machine_options(MachineClass *m)
 417 {
 418     pc_q35_2_3_machine_options(m);
 419     SET_MACHINE_COMPAT(m, PC_COMPAT_2_2);
 420 }
 421
 422 DEFINE_Q35_MACHINE(v2_2, "pc-q35-2.2", pc_compat_2_2,
 423                    pc_q35_2_2_machine_options);
 424
 425
 426 static void pc_q35_2_1_machine_options(MachineClass *m)
 427 {
 428     pc_q35_2_2_machine_options(m);
 429     m->default_display = NULL;
 430     SET_MACHINE_COMPAT(m, PC_COMPAT_2_1);
 431 }
 432
 433 DEFINE_Q35_MACHINE(v2_1, "pc-q35-2.1", pc_compat_2_1,
 434                    pc_q35_2_1_machine_options);
 435
 436
 437 static void pc_q35_2_0_machine_options(MachineClass *m)
 438 {
 439     pc_q35_2_1_machine_options(m);
 440     SET_MACHINE_COMPAT(m, PC_COMPAT_2_0);
 441 }
 442
 443 DEFINE_Q35_MACHINE(v2_0, "pc-q35-2.0", pc_compat_2_0,
 444                    pc_q35_2_0_machine_options);
 445
 446
 447 static void pc_q35_1_7_machine_options(MachineClass *m)
 448 {
 449     pc_q35_2_0_machine_options(m);
 450     m->default_machine_opts = NULL;
 451     SET_MACHINE_COMPAT(m, PC_COMPAT_1_7);
 452 }
 453
 454 DEFINE_Q35_MACHINE(v1_7, "pc-q35-1.7", pc_compat_1_7,
 455                    pc_q35_1_7_machine_options);
 456
 457
 458 static void pc_q35_1_6_machine_options(MachineClass *m)
 459 {
 460     pc_q35_machine_options(m);
 461     SET_MACHINE_COMPAT(m, PC_COMPAT_1_6);
 462 }
 463
 464 DEFINE_Q35_MACHINE(v1_6, "pc-q35-1.6", pc_compat_1_6,
 465                    pc_q35_1_6_machine_options);
 466
 467
 468 static void pc_q35_1_5_machine_options(MachineClass *m)
 469 {
 470     pc_q35_1_6_machine_options(m);
 471     SET_MACHINE_COMPAT(m, PC_COMPAT_1_5);
 472 }
 473
 474 DEFINE_Q35_MACHINE(v1_5, "pc-q35-1.5", pc_compat_1_5,
 475                    pc_q35_1_5_machine_options);
 476
 477
 478 static void pc_q35_1_4_machine_options(MachineClass *m)
 479 {
 480     pc_q35_1_5_machine_options(m);
 481     m->hot_add_cpu = NULL;
 482     SET_MACHINE_COMPAT(m, PC_COMPAT_1_4);
 483 }
 484
 485 DEFINE_Q35_MACHINE(v1_4, "pc-q35-1.4", pc_compat_1_4,
 486                    pc_q35_1_4_machine_options);