target/riscv/machine.c

   1 /*
   2  * RISC-V VMState Description
   3  *
   4  * Copyright (c) 2020 Huawei Technologies Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/error-report.h"
  22 #include "sysemu/kvm.h"
  23 #include "migration/cpu.h"
  24
  25 static bool pmp_needed(void *opaque)
  26 {
  27     RISCVCPU *cpu = opaque;
  28     CPURISCVState *env = &cpu->env;
  29
  30     return riscv_feature(env, RISCV_FEATURE_PMP);
  31 }
  32
  33 static int pmp_post_load(void *opaque, int version_id)
  34 {
  35     RISCVCPU *cpu = opaque;
  36     CPURISCVState *env = &cpu->env;
  37     int i;
  38
  39     for (i = 0; i < MAX_RISCV_PMPS; i++) {
  40         pmp_update_rule_addr(env, i);
  41     }
  42     pmp_update_rule_nums(env);
  43
  44     return 0;
  45 }
  46
  47 static const VMStateDescription vmstate_pmp_entry = {
  48     .name = "cpu/pmp/entry",
  49     .version_id = 1,
  50     .minimum_version_id = 1,
  51     .fields = (VMStateField[]) {
  52         VMSTATE_UINTTL(addr_reg, pmp_entry_t),
  53         VMSTATE_UINT8(cfg_reg, pmp_entry_t),
  54         VMSTATE_END_OF_LIST()
  55     }
  56 };
  57
  58 static const VMStateDescription vmstate_pmp = {
  59     .name = "cpu/pmp",
  60     .version_id = 1,
  61     .minimum_version_id = 1,
  62     .needed = pmp_needed,
  63     .post_load = pmp_post_load,
  64     .fields = (VMStateField[]) {
  65         VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
  66                              0, vmstate_pmp_entry, pmp_entry_t),
  67         VMSTATE_END_OF_LIST()
  68     }
  69 };
  70
  71 static bool hyper_needed(void *opaque)
  72 {
  73     RISCVCPU *cpu = opaque;
  74     CPURISCVState *env = &cpu->env;
  75
  76     return riscv_has_ext(env, RVH);
  77 }
  78
  79 static bool vector_needed(void *opaque)
  80 {
  81     RISCVCPU *cpu = opaque;
  82     CPURISCVState *env = &cpu->env;
  83
  84     return riscv_has_ext(env, RVV);
  85 }
  86
  87 static const VMStateDescription vmstate_vector = {
  88     .name = "cpu/vector",
  89     .version_id = 1,
  90     .minimum_version_id = 1,
  91     .needed = vector_needed,
  92     .fields = (VMStateField[]) {
  93             VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
  94             VMSTATE_UINTTL(env.vxrm, RISCVCPU),
  95             VMSTATE_UINTTL(env.vxsat, RISCVCPU),
  96             VMSTATE_UINTTL(env.vl, RISCVCPU),
  97             VMSTATE_UINTTL(env.vstart, RISCVCPU),
  98             VMSTATE_UINTTL(env.vtype, RISCVCPU),
  99             VMSTATE_END_OF_LIST()
 100         }
 101 };
 102
 103 static const VMStateDescription vmstate_hyper = {
 104     .name = "cpu/hyper",
 105     .version_id = 1,
 106     .minimum_version_id = 1,
 107     .needed = hyper_needed,
 108     .fields = (VMStateField[]) {
 109         VMSTATE_UINTTL(env.hstatus, RISCVCPU),
 110         VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
 111         VMSTATE_UINTTL(env.hideleg, RISCVCPU),
 112         VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
 113         VMSTATE_UINTTL(env.htval, RISCVCPU),
 114         VMSTATE_UINTTL(env.htinst, RISCVCPU),
 115         VMSTATE_UINTTL(env.hgatp, RISCVCPU),
 116         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
 117
 118         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
 119         VMSTATE_UINTTL(env.vstvec, RISCVCPU),
 120         VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
 121         VMSTATE_UINTTL(env.vsepc, RISCVCPU),
 122         VMSTATE_UINTTL(env.vscause, RISCVCPU),
 123         VMSTATE_UINTTL(env.vstval, RISCVCPU),
 124         VMSTATE_UINTTL(env.vsatp, RISCVCPU),
 125
 126         VMSTATE_UINTTL(env.mtval2, RISCVCPU),
 127         VMSTATE_UINTTL(env.mtinst, RISCVCPU),
 128
 129         VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
 130         VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
 131         VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
 132         VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
 133         VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
 134         VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
 135         VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
 136
 137         VMSTATE_END_OF_LIST()
 138     }
 139 };
 140
 141 const VMStateDescription vmstate_riscv_cpu = {
 142     .name = "cpu",
 143     .version_id = 2,
 144     .minimum_version_id = 2,
 145     .fields = (VMStateField[]) {
 146         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
 147         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
 148         VMSTATE_UINTTL(env.pc, RISCVCPU),
 149         VMSTATE_UINTTL(env.load_res, RISCVCPU),
 150         VMSTATE_UINTTL(env.load_val, RISCVCPU),
 151         VMSTATE_UINTTL(env.frm, RISCVCPU),
 152         VMSTATE_UINTTL(env.badaddr, RISCVCPU),
 153         VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
 154         VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
 155         VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
 156         VMSTATE_UINTTL(env.misa, RISCVCPU),
 157         VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
 158         VMSTATE_UINT32(env.features, RISCVCPU),
 159         VMSTATE_UINTTL(env.priv, RISCVCPU),
 160         VMSTATE_UINTTL(env.virt, RISCVCPU),
 161         VMSTATE_UINTTL(env.resetvec, RISCVCPU),
 162         VMSTATE_UINTTL(env.mhartid, RISCVCPU),
 163         VMSTATE_UINT64(env.mstatus, RISCVCPU),
 164         VMSTATE_UINTTL(env.mip, RISCVCPU),
 165         VMSTATE_UINT32(env.miclaim, RISCVCPU),
 166         VMSTATE_UINTTL(env.mie, RISCVCPU),
 167         VMSTATE_UINTTL(env.mideleg, RISCVCPU),
 168         VMSTATE_UINTTL(env.satp, RISCVCPU),
 169         VMSTATE_UINTTL(env.stval, RISCVCPU),
 170         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
 171         VMSTATE_UINTTL(env.stvec, RISCVCPU),
 172         VMSTATE_UINTTL(env.sepc, RISCVCPU),
 173         VMSTATE_UINTTL(env.scause, RISCVCPU),
 174         VMSTATE_UINTTL(env.mtvec, RISCVCPU),
 175         VMSTATE_UINTTL(env.mepc, RISCVCPU),
 176         VMSTATE_UINTTL(env.mcause, RISCVCPU),
 177         VMSTATE_UINTTL(env.mtval, RISCVCPU),
 178         VMSTATE_UINTTL(env.scounteren, RISCVCPU),
 179         VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
 180         VMSTATE_UINTTL(env.sscratch, RISCVCPU),
 181         VMSTATE_UINTTL(env.mscratch, RISCVCPU),
 182         VMSTATE_UINT64(env.mfromhost, RISCVCPU),
 183         VMSTATE_UINT64(env.mtohost, RISCVCPU),
 184         VMSTATE_UINT64(env.timecmp, RISCVCPU),
 185
 186         VMSTATE_END_OF_LIST()
 187     },
 188     .subsections = (const VMStateDescription * []) {
 189         &vmstate_pmp,
 190         &vmstate_hyper,
 191         &vmstate_vector,
 192         NULL
 193     }
 194 };