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crypto: skip testing of unsupported cipher algorithms
[qemu/ar7.git] / target-i386 / kvm.c
blob08d644474138cfd5fd1c719fa242455944f5dc8d
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38
39 #include "exec/ioport.h"
40 #include "standard-headers/asm-x86/hyperv.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/msi.h"
43 #include "migration/migration.h"
44 #include "exec/memattrs.h"
45
46 //#define DEBUG_KVM
47
48 #ifdef DEBUG_KVM
49 #define DPRINTF(fmt, ...) \
50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51 #else
52 #define DPRINTF(fmt, ...) \
53 do { } while (0)
54 #endif
55
56 #define MSR_KVM_WALL_CLOCK 0x11
57 #define MSR_KVM_SYSTEM_TIME 0x12
58
59 #ifndef BUS_MCEERR_AR
60 #define BUS_MCEERR_AR 4
61 #endif
62 #ifndef BUS_MCEERR_AO
63 #define BUS_MCEERR_AO 5
64 #endif
65
66 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71 };
72
73 static bool has_msr_star;
74 static bool has_msr_hsave_pa;
75 static bool has_msr_tsc_aux;
76 static bool has_msr_tsc_adjust;
77 static bool has_msr_tsc_deadline;
78 static bool has_msr_feature_control;
79 static bool has_msr_async_pf_en;
80 static bool has_msr_pv_eoi_en;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static bool has_msr_kvm_steal_time;
85 static int lm_capable_kernel;
86 static bool has_msr_hv_hypercall;
87 static bool has_msr_hv_vapic;
88 static bool has_msr_hv_tsc;
89 static bool has_msr_hv_crash;
90 static bool has_msr_hv_reset;
91 static bool has_msr_hv_vpindex;
92 static bool has_msr_hv_runtime;
93 static bool has_msr_hv_synic;
94 static bool has_msr_hv_stimer;
95 static bool has_msr_mtrr;
96 static bool has_msr_xss;
97
98 static bool has_msr_architectural_pmu;
99 static uint32_t num_architectural_pmu_counters;
100
101 static int has_xsave;
102 static int has_xcrs;
103 static int has_pit_state2;
104
105 int kvm_has_pit_state2(void)
106 {
107 return has_pit_state2;
108 }
109
110 bool kvm_has_smm(void)
111 {
112 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
113 }
114
115 bool kvm_allows_irq0_override(void)
116 {
117 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
118 }
119
120 static int kvm_get_tsc(CPUState *cs)
121 {
122 X86CPU *cpu = X86_CPU(cs);
123 CPUX86State *env = &cpu->env;
124 struct {
125 struct kvm_msrs info;
126 struct kvm_msr_entry entries[1];
127 } msr_data;
128 int ret;
129
130 if (env->tsc_valid) {
131 return 0;
132 }
133
134 msr_data.info.nmsrs = 1;
135 msr_data.entries[0].index = MSR_IA32_TSC;
136 env->tsc_valid = !runstate_is_running();
137
138 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
139 if (ret < 0) {
140 return ret;
141 }
142
143 env->tsc = msr_data.entries[0].data;
144 return 0;
145 }
146
147 static inline void do_kvm_synchronize_tsc(void *arg)
148 {
149 CPUState *cpu = arg;
150
151 kvm_get_tsc(cpu);
152 }
153
154 void kvm_synchronize_all_tsc(void)
155 {
156 CPUState *cpu;
157
158 if (kvm_enabled()) {
159 CPU_FOREACH(cpu) {
160 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
161 }
162 }
163 }
164
165 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
166 {
167 struct kvm_cpuid2 *cpuid;
168 int r, size;
169
170 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
171 cpuid = g_malloc0(size);
172 cpuid->nent = max;
173 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
174 if (r == 0 && cpuid->nent >= max) {
175 r = -E2BIG;
176 }
177 if (r < 0) {
178 if (r == -E2BIG) {
179 g_free(cpuid);
180 return NULL;
181 } else {
182 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
183 strerror(-r));
184 exit(1);
185 }
186 }
187 return cpuid;
188 }
189
190 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
191 * for all entries.
192 */
193 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
194 {
195 struct kvm_cpuid2 *cpuid;
196 int max = 1;
197 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
198 max *= 2;
199 }
200 return cpuid;
201 }
202
203 static const struct kvm_para_features {
204 int cap;
205 int feature;
206 } para_features[] = {
207 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
208 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
209 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
210 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
211 };
212
213 static int get_para_features(KVMState *s)
214 {
215 int i, features = 0;
216
217 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
218 if (kvm_check_extension(s, para_features[i].cap)) {
219 features |= (1 << para_features[i].feature);
220 }
221 }
222
223 return features;
224 }
225
226
227 /* Returns the value for a specific register on the cpuid entry
228 */
229 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
230 {
231 uint32_t ret = 0;
232 switch (reg) {
233 case R_EAX:
234 ret = entry->eax;
235 break;
236 case R_EBX:
237 ret = entry->ebx;
238 break;
239 case R_ECX:
240 ret = entry->ecx;
241 break;
242 case R_EDX:
243 ret = entry->edx;
244 break;
245 }
246 return ret;
247 }
248
249 /* Find matching entry for function/index on kvm_cpuid2 struct
250 */
251 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
252 uint32_t function,
253 uint32_t index)
254 {
255 int i;
256 for (i = 0; i < cpuid->nent; ++i) {
257 if (cpuid->entries[i].function == function &&
258 cpuid->entries[i].index == index) {
259 return &cpuid->entries[i];
260 }
261 }
262 /* not found: */
263 return NULL;
264 }
265
266 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
267 uint32_t index, int reg)
268 {
269 struct kvm_cpuid2 *cpuid;
270 uint32_t ret = 0;
271 uint32_t cpuid_1_edx;
272 bool found = false;
273
274 cpuid = get_supported_cpuid(s);
275
276 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
277 if (entry) {
278 found = true;
279 ret = cpuid_entry_get_reg(entry, reg);
280 }
281
282 /* Fixups for the data returned by KVM, below */
283
284 if (function == 1 && reg == R_EDX) {
285 /* KVM before 2.6.30 misreports the following features */
286 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
287 } else if (function == 1 && reg == R_ECX) {
288 /* We can set the hypervisor flag, even if KVM does not return it on
289 * GET_SUPPORTED_CPUID
290 */
291 ret |= CPUID_EXT_HYPERVISOR;
292 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
293 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
294 * and the irqchip is in the kernel.
295 */
296 if (kvm_irqchip_in_kernel() &&
297 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
298 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
299 }
300
301 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
302 * without the in-kernel irqchip
303 */
304 if (!kvm_irqchip_in_kernel()) {
305 ret &= ~CPUID_EXT_X2APIC;
306 }
307 } else if (function == 6 && reg == R_EAX) {
308 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
309 } else if (function == 0x80000001 && reg == R_EDX) {
310 /* On Intel, kvm returns cpuid according to the Intel spec,
311 * so add missing bits according to the AMD spec:
312 */
313 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
314 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
315 }
316
317 g_free(cpuid);
318
319 /* fallback for older kernels */
320 if ((function == KVM_CPUID_FEATURES) && !found) {
321 ret = get_para_features(s);
322 }
323
324 return ret;
325 }
326
327 typedef struct HWPoisonPage {
328 ram_addr_t ram_addr;
329 QLIST_ENTRY(HWPoisonPage) list;
330 } HWPoisonPage;
331
332 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
333 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
334
335 static void kvm_unpoison_all(void *param)
336 {
337 HWPoisonPage *page, *next_page;
338
339 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
340 QLIST_REMOVE(page, list);
341 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
342 g_free(page);
343 }
344 }
345
346 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
347 {
348 HWPoisonPage *page;
349
350 QLIST_FOREACH(page, &hwpoison_page_list, list) {
351 if (page->ram_addr == ram_addr) {
352 return;
353 }
354 }
355 page = g_new(HWPoisonPage, 1);
356 page->ram_addr = ram_addr;
357 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
358 }
359
360 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
361 int *max_banks)
362 {
363 int r;
364
365 r = kvm_check_extension(s, KVM_CAP_MCE);
366 if (r > 0) {
367 *max_banks = r;
368 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
369 }
370 return -ENOSYS;
371 }
372
373 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
374 {
375 CPUX86State *env = &cpu->env;
376 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
377 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
378 uint64_t mcg_status = MCG_STATUS_MCIP;
379
380 if (code == BUS_MCEERR_AR) {
381 status |= MCI_STATUS_AR | 0x134;
382 mcg_status |= MCG_STATUS_EIPV;
383 } else {
384 status |= 0xc0;
385 mcg_status |= MCG_STATUS_RIPV;
386 }
387 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
388 (MCM_ADDR_PHYS << 6) | 0xc,
389 cpu_x86_support_mca_broadcast(env) ?
390 MCE_INJECT_BROADCAST : 0);
391 }
392
393 static void hardware_memory_error(void)
394 {
395 fprintf(stderr, "Hardware memory error!\n");
396 exit(1);
397 }
398
399 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
400 {
401 X86CPU *cpu = X86_CPU(c);
402 CPUX86State *env = &cpu->env;
403 ram_addr_t ram_addr;
404 hwaddr paddr;
405
406 if ((env->mcg_cap & MCG_SER_P) && addr
407 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
408 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
409 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
410 fprintf(stderr, "Hardware memory error for memory used by "
411 "QEMU itself instead of guest system!\n");
412 /* Hope we are lucky for AO MCE */
413 if (code == BUS_MCEERR_AO) {
414 return 0;
415 } else {
416 hardware_memory_error();
417 }
418 }
419 kvm_hwpoison_page_add(ram_addr);
420 kvm_mce_inject(cpu, paddr, code);
421 } else {
422 if (code == BUS_MCEERR_AO) {
423 return 0;
424 } else if (code == BUS_MCEERR_AR) {
425 hardware_memory_error();
426 } else {
427 return 1;
428 }
429 }
430 return 0;
431 }
432
433 int kvm_arch_on_sigbus(int code, void *addr)
434 {
435 X86CPU *cpu = X86_CPU(first_cpu);
436
437 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
438 ram_addr_t ram_addr;
439 hwaddr paddr;
440
441 /* Hope we are lucky for AO MCE */
442 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
443 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
444 addr, &paddr)) {
445 fprintf(stderr, "Hardware memory error for memory used by "
446 "QEMU itself instead of guest system!: %p\n", addr);
447 return 0;
448 }
449 kvm_hwpoison_page_add(ram_addr);
450 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
451 } else {
452 if (code == BUS_MCEERR_AO) {
453 return 0;
454 } else if (code == BUS_MCEERR_AR) {
455 hardware_memory_error();
456 } else {
457 return 1;
458 }
459 }
460 return 0;
461 }
462
463 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
464 {
465 CPUX86State *env = &cpu->env;
466
467 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
468 unsigned int bank, bank_num = env->mcg_cap & 0xff;
469 struct kvm_x86_mce mce;
470
471 env->exception_injected = -1;
472
473 /*
474 * There must be at least one bank in use if an MCE is pending.
475 * Find it and use its values for the event injection.
476 */
477 for (bank = 0; bank < bank_num; bank++) {
478 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
479 break;
480 }
481 }
482 assert(bank < bank_num);
483
484 mce.bank = bank;
485 mce.status = env->mce_banks[bank * 4 + 1];
486 mce.mcg_status = env->mcg_status;
487 mce.addr = env->mce_banks[bank * 4 + 2];
488 mce.misc = env->mce_banks[bank * 4 + 3];
489
490 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
491 }
492 return 0;
493 }
494
495 static void cpu_update_state(void *opaque, int running, RunState state)
496 {
497 CPUX86State *env = opaque;
498
499 if (running) {
500 env->tsc_valid = false;
501 }
502 }
503
504 unsigned long kvm_arch_vcpu_id(CPUState *cs)
505 {
506 X86CPU *cpu = X86_CPU(cs);
507 return cpu->apic_id;
508 }
509
510 #ifndef KVM_CPUID_SIGNATURE_NEXT
511 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
512 #endif
513
514 static bool hyperv_hypercall_available(X86CPU *cpu)
515 {
516 return cpu->hyperv_vapic ||
517 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
518 }
519
520 static bool hyperv_enabled(X86CPU *cpu)
521 {
522 CPUState *cs = CPU(cpu);
523 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
524 (hyperv_hypercall_available(cpu) ||
525 cpu->hyperv_time ||
526 cpu->hyperv_relaxed_timing ||
527 cpu->hyperv_crash ||
528 cpu->hyperv_reset ||
529 cpu->hyperv_vpindex ||
530 cpu->hyperv_runtime ||
531 cpu->hyperv_synic ||
532 cpu->hyperv_stimer);
533 }
534
535 static int kvm_arch_set_tsc_khz(CPUState *cs)
536 {
537 X86CPU *cpu = X86_CPU(cs);
538 CPUX86State *env = &cpu->env;
539 int r;
540
541 if (!env->tsc_khz) {
542 return 0;
543 }
544
545 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
546 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
547 -ENOTSUP;
548 if (r < 0) {
549 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
550 * TSC frequency doesn't match the one we want.
551 */
552 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
553 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
554 -ENOTSUP;
555 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
556 error_report("warning: TSC frequency mismatch between "
557 "VM and host, and TSC scaling unavailable");
558 return r;
559 }
560 }
561
562 return 0;
563 }
564
565 static Error *invtsc_mig_blocker;
566
567 #define KVM_MAX_CPUID_ENTRIES 100
568
569 int kvm_arch_init_vcpu(CPUState *cs)
570 {
571 struct {
572 struct kvm_cpuid2 cpuid;
573 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
574 } QEMU_PACKED cpuid_data;
575 X86CPU *cpu = X86_CPU(cs);
576 CPUX86State *env = &cpu->env;
577 uint32_t limit, i, j, cpuid_i;
578 uint32_t unused;
579 struct kvm_cpuid_entry2 *c;
580 uint32_t signature[3];
581 int kvm_base = KVM_CPUID_SIGNATURE;
582 int r;
583
584 memset(&cpuid_data, 0, sizeof(cpuid_data));
585
586 cpuid_i = 0;
587
588 /* Paravirtualization CPUIDs */
589 if (hyperv_enabled(cpu)) {
590 c = &cpuid_data.entries[cpuid_i++];
591 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
592 if (!cpu->hyperv_vendor_id) {
593 memcpy(signature, "Microsoft Hv", 12);
594 } else {
595 size_t len = strlen(cpu->hyperv_vendor_id);
596
597 if (len > 12) {
598 error_report("hv-vendor-id truncated to 12 characters");
599 len = 12;
600 }
601 memset(signature, 0, 12);
602 memcpy(signature, cpu->hyperv_vendor_id, len);
603 }
604 c->eax = HYPERV_CPUID_MIN;
605 c->ebx = signature[0];
606 c->ecx = signature[1];
607 c->edx = signature[2];
608
609 c = &cpuid_data.entries[cpuid_i++];
610 c->function = HYPERV_CPUID_INTERFACE;
611 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
612 c->eax = signature[0];
613 c->ebx = 0;
614 c->ecx = 0;
615 c->edx = 0;
616
617 c = &cpuid_data.entries[cpuid_i++];
618 c->function = HYPERV_CPUID_VERSION;
619 c->eax = 0x00001bbc;
620 c->ebx = 0x00060001;
621
622 c = &cpuid_data.entries[cpuid_i++];
623 c->function = HYPERV_CPUID_FEATURES;
624 if (cpu->hyperv_relaxed_timing) {
625 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
626 }
627 if (cpu->hyperv_vapic) {
628 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
629 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
630 has_msr_hv_vapic = true;
631 }
632 if (cpu->hyperv_time &&
633 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
634 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
635 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
636 c->eax |= 0x200;
637 has_msr_hv_tsc = true;
638 }
639 if (cpu->hyperv_crash && has_msr_hv_crash) {
640 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
641 }
642 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
643 if (cpu->hyperv_reset && has_msr_hv_reset) {
644 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
645 }
646 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
647 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
648 }
649 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
650 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
651 }
652 if (cpu->hyperv_synic) {
653 int sint;
654
655 if (!has_msr_hv_synic ||
656 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
657 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
658 return -ENOSYS;
659 }
660
661 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
662 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
663 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
664 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
665 }
666 }
667 if (cpu->hyperv_stimer) {
668 if (!has_msr_hv_stimer) {
669 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
670 return -ENOSYS;
671 }
672 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
673 }
674 c = &cpuid_data.entries[cpuid_i++];
675 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
676 if (cpu->hyperv_relaxed_timing) {
677 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
678 }
679 if (has_msr_hv_vapic) {
680 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
681 }
682 c->ebx = cpu->hyperv_spinlock_attempts;
683
684 c = &cpuid_data.entries[cpuid_i++];
685 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
686 c->eax = 0x40;
687 c->ebx = 0x40;
688
689 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
690 has_msr_hv_hypercall = true;
691 }
692
693 if (cpu->expose_kvm) {
694 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
695 c = &cpuid_data.entries[cpuid_i++];
696 c->function = KVM_CPUID_SIGNATURE | kvm_base;
697 c->eax = KVM_CPUID_FEATURES | kvm_base;
698 c->ebx = signature[0];
699 c->ecx = signature[1];
700 c->edx = signature[2];
701
702 c = &cpuid_data.entries[cpuid_i++];
703 c->function = KVM_CPUID_FEATURES | kvm_base;
704 c->eax = env->features[FEAT_KVM];
705
706 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
707
708 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
709
710 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
711 }
712
713 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
714
715 for (i = 0; i <= limit; i++) {
716 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
717 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
718 abort();
719 }
720 c = &cpuid_data.entries[cpuid_i++];
721
722 switch (i) {
723 case 2: {
724 /* Keep reading function 2 till all the input is received */
725 int times;
726
727 c->function = i;
728 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
729 KVM_CPUID_FLAG_STATE_READ_NEXT;
730 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
731 times = c->eax & 0xff;
732
733 for (j = 1; j < times; ++j) {
734 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
735 fprintf(stderr, "cpuid_data is full, no space for "
736 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
737 abort();
738 }
739 c = &cpuid_data.entries[cpuid_i++];
740 c->function = i;
741 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
742 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
743 }
744 break;
745 }
746 case 4:
747 case 0xb:
748 case 0xd:
749 for (j = 0; ; j++) {
750 if (i == 0xd && j == 64) {
751 break;
752 }
753 c->function = i;
754 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
755 c->index = j;
756 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
757
758 if (i == 4 && c->eax == 0) {
759 break;
760 }
761 if (i == 0xb && !(c->ecx & 0xff00)) {
762 break;
763 }
764 if (i == 0xd && c->eax == 0) {
765 continue;
766 }
767 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
768 fprintf(stderr, "cpuid_data is full, no space for "
769 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
770 abort();
771 }
772 c = &cpuid_data.entries[cpuid_i++];
773 }
774 break;
775 default:
776 c->function = i;
777 c->flags = 0;
778 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
779 break;
780 }
781 }
782
783 if (limit >= 0x0a) {
784 uint32_t ver;
785
786 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
787 if ((ver & 0xff) > 0) {
788 has_msr_architectural_pmu = true;
789 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
790
791 /* Shouldn't be more than 32, since that's the number of bits
792 * available in EBX to tell us _which_ counters are available.
793 * Play it safe.
794 */
795 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
796 num_architectural_pmu_counters = MAX_GP_COUNTERS;
797 }
798 }
799 }
800
801 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
802
803 for (i = 0x80000000; i <= limit; i++) {
804 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
805 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
806 abort();
807 }
808 c = &cpuid_data.entries[cpuid_i++];
809
810 c->function = i;
811 c->flags = 0;
812 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
813 }
814
815 /* Call Centaur's CPUID instructions they are supported. */
816 if (env->cpuid_xlevel2 > 0) {
817 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
818
819 for (i = 0xC0000000; i <= limit; i++) {
820 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
821 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
822 abort();
823 }
824 c = &cpuid_data.entries[cpuid_i++];
825
826 c->function = i;
827 c->flags = 0;
828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
829 }
830 }
831
832 cpuid_data.cpuid.nent = cpuid_i;
833
834 if (((env->cpuid_version >> 8)&0xF) >= 6
835 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
836 (CPUID_MCE | CPUID_MCA)
837 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
838 uint64_t mcg_cap, unsupported_caps;
839 int banks;
840 int ret;
841
842 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
843 if (ret < 0) {
844 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
845 return ret;
846 }
847
848 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
849 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
850 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
851 return -ENOTSUP;
852 }
853
854 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
855 if (unsupported_caps) {
856 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
857 unsupported_caps);
858 }
859
860 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
861 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
862 if (ret < 0) {
863 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
864 return ret;
865 }
866 }
867
868 qemu_add_vm_change_state_handler(cpu_update_state, env);
869
870 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
871 if (c) {
872 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
873 !!(c->ecx & CPUID_EXT_SMX);
874 }
875
876 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
877 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
878 /* for migration */
879 error_setg(&invtsc_mig_blocker,
880 "State blocked by non-migratable CPU device"
881 " (invtsc flag)");
882 migrate_add_blocker(invtsc_mig_blocker);
883 /* for savevm */
884 vmstate_x86_cpu.unmigratable = 1;
885 }
886
887 cpuid_data.cpuid.padding = 0;
888 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
889 if (r) {
890 return r;
891 }
892
893 r = kvm_arch_set_tsc_khz(cs);
894 if (r < 0) {
895 return r;
896 }
897
898 /* vcpu's TSC frequency is either specified by user, or following
899 * the value used by KVM if the former is not present. In the
900 * latter case, we query it from KVM and record in env->tsc_khz,
901 * so that vcpu's TSC frequency can be migrated later via this field.
902 */
903 if (!env->tsc_khz) {
904 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
905 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
906 -ENOTSUP;
907 if (r > 0) {
908 env->tsc_khz = r;
909 }
910 }
911
912 if (has_xsave) {
913 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
914 }
915
916 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
917 has_msr_mtrr = true;
918 }
919
920 return 0;
921 }
922
923 void kvm_arch_reset_vcpu(X86CPU *cpu)
924 {
925 CPUX86State *env = &cpu->env;
926
927 env->exception_injected = -1;
928 env->interrupt_injected = -1;
929 env->xcr0 = 1;
930 if (kvm_irqchip_in_kernel()) {
931 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
932 KVM_MP_STATE_UNINITIALIZED;
933 } else {
934 env->mp_state = KVM_MP_STATE_RUNNABLE;
935 }
936 }
937
938 void kvm_arch_do_init_vcpu(X86CPU *cpu)
939 {
940 CPUX86State *env = &cpu->env;
941
942 /* APs get directly into wait-for-SIPI state. */
943 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
944 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
945 }
946 }
947
948 static int kvm_get_supported_msrs(KVMState *s)
949 {
950 static int kvm_supported_msrs;
951 int ret = 0;
952
953 /* first time */
954 if (kvm_supported_msrs == 0) {
955 struct kvm_msr_list msr_list, *kvm_msr_list;
956
957 kvm_supported_msrs = -1;
958
959 /* Obtain MSR list from KVM. These are the MSRs that we must
960 * save/restore */
961 msr_list.nmsrs = 0;
962 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
963 if (ret < 0 && ret != -E2BIG) {
964 return ret;
965 }
966 /* Old kernel modules had a bug and could write beyond the provided
967 memory. Allocate at least a safe amount of 1K. */
968 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
969 msr_list.nmsrs *
970 sizeof(msr_list.indices[0])));
971
972 kvm_msr_list->nmsrs = msr_list.nmsrs;
973 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
974 if (ret >= 0) {
975 int i;
976
977 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
978 if (kvm_msr_list->indices[i] == MSR_STAR) {
979 has_msr_star = true;
980 continue;
981 }
982 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
983 has_msr_hsave_pa = true;
984 continue;
985 }
986 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
987 has_msr_tsc_aux = true;
988 continue;
989 }
990 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
991 has_msr_tsc_adjust = true;
992 continue;
993 }
994 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
995 has_msr_tsc_deadline = true;
996 continue;
997 }
998 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
999 has_msr_smbase = true;
1000 continue;
1001 }
1002 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1003 has_msr_misc_enable = true;
1004 continue;
1005 }
1006 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1007 has_msr_bndcfgs = true;
1008 continue;
1009 }
1010 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1011 has_msr_xss = true;
1012 continue;
1013 }
1014 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1015 has_msr_hv_crash = true;
1016 continue;
1017 }
1018 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1019 has_msr_hv_reset = true;
1020 continue;
1021 }
1022 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1023 has_msr_hv_vpindex = true;
1024 continue;
1025 }
1026 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1027 has_msr_hv_runtime = true;
1028 continue;
1029 }
1030 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1031 has_msr_hv_synic = true;
1032 continue;
1033 }
1034 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1035 has_msr_hv_stimer = true;
1036 continue;
1037 }
1038 }
1039 }
1040
1041 g_free(kvm_msr_list);
1042 }
1043
1044 return ret;
1045 }
1046
1047 static Notifier smram_machine_done;
1048 static KVMMemoryListener smram_listener;
1049 static AddressSpace smram_address_space;
1050 static MemoryRegion smram_as_root;
1051 static MemoryRegion smram_as_mem;
1052
1053 static void register_smram_listener(Notifier *n, void *unused)
1054 {
1055 MemoryRegion *smram =
1056 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1057
1058 /* Outer container... */
1059 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1060 memory_region_set_enabled(&smram_as_root, true);
1061
1062 /* ... with two regions inside: normal system memory with low
1063 * priority, and...
1064 */
1065 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1066 get_system_memory(), 0, ~0ull);
1067 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1068 memory_region_set_enabled(&smram_as_mem, true);
1069
1070 if (smram) {
1071 /* ... SMRAM with higher priority */
1072 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1073 memory_region_set_enabled(smram, true);
1074 }
1075
1076 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1077 kvm_memory_listener_register(kvm_state, &smram_listener,
1078 &smram_address_space, 1);
1079 }
1080
1081 int kvm_arch_init(MachineState *ms, KVMState *s)
1082 {
1083 uint64_t identity_base = 0xfffbc000;
1084 uint64_t shadow_mem;
1085 int ret;
1086 struct utsname utsname;
1087
1088 #ifdef KVM_CAP_XSAVE
1089 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1090 #endif
1091
1092 #ifdef KVM_CAP_XCRS
1093 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1094 #endif
1095
1096 #ifdef KVM_CAP_PIT_STATE2
1097 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1098 #endif
1099
1100 ret = kvm_get_supported_msrs(s);
1101 if (ret < 0) {
1102 return ret;
1103 }
1104
1105 uname(&utsname);
1106 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1107
1108 /*
1109 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1110 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1111 * Since these must be part of guest physical memory, we need to allocate
1112 * them, both by setting their start addresses in the kernel and by
1113 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1114 *
1115 * Older KVM versions may not support setting the identity map base. In
1116 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1117 * size.
1118 */
1119 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1120 /* Allows up to 16M BIOSes. */
1121 identity_base = 0xfeffc000;
1122
1123 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1124 if (ret < 0) {
1125 return ret;
1126 }
1127 }
1128
1129 /* Set TSS base one page after EPT identity map. */
1130 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1131 if (ret < 0) {
1132 return ret;
1133 }
1134
1135 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1136 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1137 if (ret < 0) {
1138 fprintf(stderr, "e820_add_entry() table is full\n");
1139 return ret;
1140 }
1141 qemu_register_reset(kvm_unpoison_all, NULL);
1142
1143 shadow_mem = machine_kvm_shadow_mem(ms);
1144 if (shadow_mem != -1) {
1145 shadow_mem /= 4096;
1146 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1147 if (ret < 0) {
1148 return ret;
1149 }
1150 }
1151
1152 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1153 smram_machine_done.notify = register_smram_listener;
1154 qemu_add_machine_init_done_notifier(&smram_machine_done);
1155 }
1156 return 0;
1157 }
1158
1159 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1160 {
1161 lhs->selector = rhs->selector;
1162 lhs->base = rhs->base;
1163 lhs->limit = rhs->limit;
1164 lhs->type = 3;
1165 lhs->present = 1;
1166 lhs->dpl = 3;
1167 lhs->db = 0;
1168 lhs->s = 1;
1169 lhs->l = 0;
1170 lhs->g = 0;
1171 lhs->avl = 0;
1172 lhs->unusable = 0;
1173 }
1174
1175 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1176 {
1177 unsigned flags = rhs->flags;
1178 lhs->selector = rhs->selector;
1179 lhs->base = rhs->base;
1180 lhs->limit = rhs->limit;
1181 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1182 lhs->present = (flags & DESC_P_MASK) != 0;
1183 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1184 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1185 lhs->s = (flags & DESC_S_MASK) != 0;
1186 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1187 lhs->g = (flags & DESC_G_MASK) != 0;
1188 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1189 lhs->unusable = !lhs->present;
1190 lhs->padding = 0;
1191 }
1192
1193 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1194 {
1195 lhs->selector = rhs->selector;
1196 lhs->base = rhs->base;
1197 lhs->limit = rhs->limit;
1198 if (rhs->unusable) {
1199 lhs->flags = 0;
1200 } else {
1201 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1202 (rhs->present * DESC_P_MASK) |
1203 (rhs->dpl << DESC_DPL_SHIFT) |
1204 (rhs->db << DESC_B_SHIFT) |
1205 (rhs->s * DESC_S_MASK) |
1206 (rhs->l << DESC_L_SHIFT) |
1207 (rhs->g * DESC_G_MASK) |
1208 (rhs->avl * DESC_AVL_MASK);
1209 }
1210 }
1211
1212 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1213 {
1214 if (set) {
1215 *kvm_reg = *qemu_reg;
1216 } else {
1217 *qemu_reg = *kvm_reg;
1218 }
1219 }
1220
1221 static int kvm_getput_regs(X86CPU *cpu, int set)
1222 {
1223 CPUX86State *env = &cpu->env;
1224 struct kvm_regs regs;
1225 int ret = 0;
1226
1227 if (!set) {
1228 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1229 if (ret < 0) {
1230 return ret;
1231 }
1232 }
1233
1234 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1235 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1236 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1237 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1238 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1239 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1240 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1241 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1242 #ifdef TARGET_X86_64
1243 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1244 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1245 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1246 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1247 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1248 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1249 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1250 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1251 #endif
1252
1253 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1254 kvm_getput_reg(&regs.rip, &env->eip, set);
1255
1256 if (set) {
1257 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1258 }
1259
1260 return ret;
1261 }
1262
1263 static int kvm_put_fpu(X86CPU *cpu)
1264 {
1265 CPUX86State *env = &cpu->env;
1266 struct kvm_fpu fpu;
1267 int i;
1268
1269 memset(&fpu, 0, sizeof fpu);
1270 fpu.fsw = env->fpus & ~(7 << 11);
1271 fpu.fsw |= (env->fpstt & 7) << 11;
1272 fpu.fcw = env->fpuc;
1273 fpu.last_opcode = env->fpop;
1274 fpu.last_ip = env->fpip;
1275 fpu.last_dp = env->fpdp;
1276 for (i = 0; i < 8; ++i) {
1277 fpu.ftwx |= (!env->fptags[i]) << i;
1278 }
1279 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1280 for (i = 0; i < CPU_NB_REGS; i++) {
1281 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1282 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1283 }
1284 fpu.mxcsr = env->mxcsr;
1285
1286 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1287 }
1288
1289 #define XSAVE_FCW_FSW 0
1290 #define XSAVE_FTW_FOP 1
1291 #define XSAVE_CWD_RIP 2
1292 #define XSAVE_CWD_RDP 4
1293 #define XSAVE_MXCSR 6
1294 #define XSAVE_ST_SPACE 8
1295 #define XSAVE_XMM_SPACE 40
1296 #define XSAVE_XSTATE_BV 128
1297 #define XSAVE_YMMH_SPACE 144
1298 #define XSAVE_BNDREGS 240
1299 #define XSAVE_BNDCSR 256
1300 #define XSAVE_OPMASK 272
1301 #define XSAVE_ZMM_Hi256 288
1302 #define XSAVE_Hi16_ZMM 416
1303 #define XSAVE_PKRU 672
1304
1305 static int kvm_put_xsave(X86CPU *cpu)
1306 {
1307 CPUX86State *env = &cpu->env;
1308 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1309 uint16_t cwd, swd, twd;
1310 uint8_t *xmm, *ymmh, *zmmh;
1311 int i, r;
1312
1313 if (!has_xsave) {
1314 return kvm_put_fpu(cpu);
1315 }
1316
1317 memset(xsave, 0, sizeof(struct kvm_xsave));
1318 twd = 0;
1319 swd = env->fpus & ~(7 << 11);
1320 swd |= (env->fpstt & 7) << 11;
1321 cwd = env->fpuc;
1322 for (i = 0; i < 8; ++i) {
1323 twd |= (!env->fptags[i]) << i;
1324 }
1325 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1326 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1327 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1328 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1329 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1330 sizeof env->fpregs);
1331 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1332 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1333 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1334 sizeof env->bnd_regs);
1335 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1336 sizeof(env->bndcs_regs));
1337 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1338 sizeof env->opmask_regs);
1339
1340 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1341 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1342 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1343 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1344 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1345 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1346 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1347 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1348 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1349 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1350 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1351 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1352 }
1353
1354 #ifdef TARGET_X86_64
1355 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1356 16 * sizeof env->xmm_regs[16]);
1357 memcpy(&xsave->region[XSAVE_PKRU], &env->pkru, sizeof env->pkru);
1358 #endif
1359 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1360 return r;
1361 }
1362
1363 static int kvm_put_xcrs(X86CPU *cpu)
1364 {
1365 CPUX86State *env = &cpu->env;
1366 struct kvm_xcrs xcrs = {};
1367
1368 if (!has_xcrs) {
1369 return 0;
1370 }
1371
1372 xcrs.nr_xcrs = 1;
1373 xcrs.flags = 0;
1374 xcrs.xcrs[0].xcr = 0;
1375 xcrs.xcrs[0].value = env->xcr0;
1376 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1377 }
1378
1379 static int kvm_put_sregs(X86CPU *cpu)
1380 {
1381 CPUX86State *env = &cpu->env;
1382 struct kvm_sregs sregs;
1383
1384 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1385 if (env->interrupt_injected >= 0) {
1386 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1387 (uint64_t)1 << (env->interrupt_injected % 64);
1388 }
1389
1390 if ((env->eflags & VM_MASK)) {
1391 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1392 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1393 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1394 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1395 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1396 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1397 } else {
1398 set_seg(&sregs.cs, &env->segs[R_CS]);
1399 set_seg(&sregs.ds, &env->segs[R_DS]);
1400 set_seg(&sregs.es, &env->segs[R_ES]);
1401 set_seg(&sregs.fs, &env->segs[R_FS]);
1402 set_seg(&sregs.gs, &env->segs[R_GS]);
1403 set_seg(&sregs.ss, &env->segs[R_SS]);
1404 }
1405
1406 set_seg(&sregs.tr, &env->tr);
1407 set_seg(&sregs.ldt, &env->ldt);
1408
1409 sregs.idt.limit = env->idt.limit;
1410 sregs.idt.base = env->idt.base;
1411 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1412 sregs.gdt.limit = env->gdt.limit;
1413 sregs.gdt.base = env->gdt.base;
1414 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1415
1416 sregs.cr0 = env->cr[0];
1417 sregs.cr2 = env->cr[2];
1418 sregs.cr3 = env->cr[3];
1419 sregs.cr4 = env->cr[4];
1420
1421 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1422 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1423
1424 sregs.efer = env->efer;
1425
1426 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1427 }
1428
1429 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1430 uint32_t index, uint64_t value)
1431 {
1432 entry->index = index;
1433 entry->reserved = 0;
1434 entry->data = value;
1435 }
1436
1437 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1438 {
1439 CPUX86State *env = &cpu->env;
1440 struct {
1441 struct kvm_msrs info;
1442 struct kvm_msr_entry entries[1];
1443 } msr_data;
1444 struct kvm_msr_entry *msrs = msr_data.entries;
1445
1446 if (!has_msr_tsc_deadline) {
1447 return 0;
1448 }
1449
1450 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1451
1452 msr_data.info = (struct kvm_msrs) {
1453 .nmsrs = 1,
1454 };
1455
1456 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1457 }
1458
1459 /*
1460 * Provide a separate write service for the feature control MSR in order to
1461 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1462 * before writing any other state because forcibly leaving nested mode
1463 * invalidates the VCPU state.
1464 */
1465 static int kvm_put_msr_feature_control(X86CPU *cpu)
1466 {
1467 struct {
1468 struct kvm_msrs info;
1469 struct kvm_msr_entry entry;
1470 } msr_data;
1471
1472 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1473 cpu->env.msr_ia32_feature_control);
1474
1475 msr_data.info = (struct kvm_msrs) {
1476 .nmsrs = 1,
1477 };
1478
1479 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1480 }
1481
1482 static int kvm_put_msrs(X86CPU *cpu, int level)
1483 {
1484 CPUX86State *env = &cpu->env;
1485 struct {
1486 struct kvm_msrs info;
1487 struct kvm_msr_entry entries[150];
1488 } msr_data;
1489 struct kvm_msr_entry *msrs = msr_data.entries;
1490 int n = 0, i;
1491
1492 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1493 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1494 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1495 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1496 if (has_msr_star) {
1497 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1498 }
1499 if (has_msr_hsave_pa) {
1500 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1501 }
1502 if (has_msr_tsc_aux) {
1503 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1504 }
1505 if (has_msr_tsc_adjust) {
1506 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1507 }
1508 if (has_msr_misc_enable) {
1509 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1510 env->msr_ia32_misc_enable);
1511 }
1512 if (has_msr_smbase) {
1513 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1514 }
1515 if (has_msr_bndcfgs) {
1516 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1517 }
1518 if (has_msr_xss) {
1519 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1520 }
1521 #ifdef TARGET_X86_64
1522 if (lm_capable_kernel) {
1523 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1524 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1525 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1526 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1527 }
1528 #endif
1529 /*
1530 * The following MSRs have side effects on the guest or are too heavy
1531 * for normal writeback. Limit them to reset or full state updates.
1532 */
1533 if (level >= KVM_PUT_RESET_STATE) {
1534 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1535 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1536 env->system_time_msr);
1537 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1538 if (has_msr_async_pf_en) {
1539 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1540 env->async_pf_en_msr);
1541 }
1542 if (has_msr_pv_eoi_en) {
1543 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1544 env->pv_eoi_en_msr);
1545 }
1546 if (has_msr_kvm_steal_time) {
1547 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1548 env->steal_time_msr);
1549 }
1550 if (has_msr_architectural_pmu) {
1551 /* Stop the counter. */
1552 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1553 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1554
1555 /* Set the counter values. */
1556 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1557 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1558 env->msr_fixed_counters[i]);
1559 }
1560 for (i = 0; i < num_architectural_pmu_counters; i++) {
1561 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1562 env->msr_gp_counters[i]);
1563 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1564 env->msr_gp_evtsel[i]);
1565 }
1566 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1567 env->msr_global_status);
1568 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1569 env->msr_global_ovf_ctrl);
1570
1571 /* Now start the PMU. */
1572 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1573 env->msr_fixed_ctr_ctrl);
1574 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1575 env->msr_global_ctrl);
1576 }
1577 if (has_msr_hv_hypercall) {
1578 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1579 env->msr_hv_guest_os_id);
1580 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1581 env->msr_hv_hypercall);
1582 }
1583 if (has_msr_hv_vapic) {
1584 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1585 env->msr_hv_vapic);
1586 }
1587 if (has_msr_hv_tsc) {
1588 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1589 env->msr_hv_tsc);
1590 }
1591 if (has_msr_hv_crash) {
1592 int j;
1593
1594 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1595 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1596 env->msr_hv_crash_params[j]);
1597
1598 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1599 HV_X64_MSR_CRASH_CTL_NOTIFY);
1600 }
1601 if (has_msr_hv_runtime) {
1602 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1603 env->msr_hv_runtime);
1604 }
1605 if (cpu->hyperv_synic) {
1606 int j;
1607
1608 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1609 env->msr_hv_synic_control);
1610 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1611 env->msr_hv_synic_version);
1612 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1613 env->msr_hv_synic_evt_page);
1614 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1615 env->msr_hv_synic_msg_page);
1616
1617 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1618 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1619 env->msr_hv_synic_sint[j]);
1620 }
1621 }
1622 if (has_msr_hv_stimer) {
1623 int j;
1624
1625 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1626 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2,
1627 env->msr_hv_stimer_config[j]);
1628 }
1629
1630 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1631 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2,
1632 env->msr_hv_stimer_count[j]);
1633 }
1634 }
1635 if (has_msr_mtrr) {
1636 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1637 kvm_msr_entry_set(&msrs[n++],
1638 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1639 kvm_msr_entry_set(&msrs[n++],
1640 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1641 kvm_msr_entry_set(&msrs[n++],
1642 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1643 kvm_msr_entry_set(&msrs[n++],
1644 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1645 kvm_msr_entry_set(&msrs[n++],
1646 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1647 kvm_msr_entry_set(&msrs[n++],
1648 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1649 kvm_msr_entry_set(&msrs[n++],
1650 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1651 kvm_msr_entry_set(&msrs[n++],
1652 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1653 kvm_msr_entry_set(&msrs[n++],
1654 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1655 kvm_msr_entry_set(&msrs[n++],
1656 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1657 kvm_msr_entry_set(&msrs[n++],
1658 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1659 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1660 kvm_msr_entry_set(&msrs[n++],
1661 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1662 kvm_msr_entry_set(&msrs[n++],
1663 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1664 }
1665 }
1666
1667 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1668 * kvm_put_msr_feature_control. */
1669 }
1670 if (env->mcg_cap) {
1671 int i;
1672
1673 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1674 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1675 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1676 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1677 }
1678 }
1679
1680 msr_data.info = (struct kvm_msrs) {
1681 .nmsrs = n,
1682 };
1683
1684 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1685
1686 }
1687
1688
1689 static int kvm_get_fpu(X86CPU *cpu)
1690 {
1691 CPUX86State *env = &cpu->env;
1692 struct kvm_fpu fpu;
1693 int i, ret;
1694
1695 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1696 if (ret < 0) {
1697 return ret;
1698 }
1699
1700 env->fpstt = (fpu.fsw >> 11) & 7;
1701 env->fpus = fpu.fsw;
1702 env->fpuc = fpu.fcw;
1703 env->fpop = fpu.last_opcode;
1704 env->fpip = fpu.last_ip;
1705 env->fpdp = fpu.last_dp;
1706 for (i = 0; i < 8; ++i) {
1707 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1708 }
1709 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1710 for (i = 0; i < CPU_NB_REGS; i++) {
1711 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1712 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1713 }
1714 env->mxcsr = fpu.mxcsr;
1715
1716 return 0;
1717 }
1718
1719 static int kvm_get_xsave(X86CPU *cpu)
1720 {
1721 CPUX86State *env = &cpu->env;
1722 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1723 int ret, i;
1724 const uint8_t *xmm, *ymmh, *zmmh;
1725 uint16_t cwd, swd, twd;
1726
1727 if (!has_xsave) {
1728 return kvm_get_fpu(cpu);
1729 }
1730
1731 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1732 if (ret < 0) {
1733 return ret;
1734 }
1735
1736 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1737 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1738 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1739 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1740 env->fpstt = (swd >> 11) & 7;
1741 env->fpus = swd;
1742 env->fpuc = cwd;
1743 for (i = 0; i < 8; ++i) {
1744 env->fptags[i] = !((twd >> i) & 1);
1745 }
1746 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1747 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1748 env->mxcsr = xsave->region[XSAVE_MXCSR];
1749 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1750 sizeof env->fpregs);
1751 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1752 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1753 sizeof env->bnd_regs);
1754 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1755 sizeof(env->bndcs_regs));
1756 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1757 sizeof env->opmask_regs);
1758
1759 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1760 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1761 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1762 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1763 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1764 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1765 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1766 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1767 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1768 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1769 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1770 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1771 }
1772
1773 #ifdef TARGET_X86_64
1774 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1775 16 * sizeof env->xmm_regs[16]);
1776 memcpy(&env->pkru, &xsave->region[XSAVE_PKRU], sizeof env->pkru);
1777 #endif
1778 return 0;
1779 }
1780
1781 static int kvm_get_xcrs(X86CPU *cpu)
1782 {
1783 CPUX86State *env = &cpu->env;
1784 int i, ret;
1785 struct kvm_xcrs xcrs;
1786
1787 if (!has_xcrs) {
1788 return 0;
1789 }
1790
1791 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1792 if (ret < 0) {
1793 return ret;
1794 }
1795
1796 for (i = 0; i < xcrs.nr_xcrs; i++) {
1797 /* Only support xcr0 now */
1798 if (xcrs.xcrs[i].xcr == 0) {
1799 env->xcr0 = xcrs.xcrs[i].value;
1800 break;
1801 }
1802 }
1803 return 0;
1804 }
1805
1806 static int kvm_get_sregs(X86CPU *cpu)
1807 {
1808 CPUX86State *env = &cpu->env;
1809 struct kvm_sregs sregs;
1810 uint32_t hflags;
1811 int bit, i, ret;
1812
1813 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1814 if (ret < 0) {
1815 return ret;
1816 }
1817
1818 /* There can only be one pending IRQ set in the bitmap at a time, so try
1819 to find it and save its number instead (-1 for none). */
1820 env->interrupt_injected = -1;
1821 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1822 if (sregs.interrupt_bitmap[i]) {
1823 bit = ctz64(sregs.interrupt_bitmap[i]);
1824 env->interrupt_injected = i * 64 + bit;
1825 break;
1826 }
1827 }
1828
1829 get_seg(&env->segs[R_CS], &sregs.cs);
1830 get_seg(&env->segs[R_DS], &sregs.ds);
1831 get_seg(&env->segs[R_ES], &sregs.es);
1832 get_seg(&env->segs[R_FS], &sregs.fs);
1833 get_seg(&env->segs[R_GS], &sregs.gs);
1834 get_seg(&env->segs[R_SS], &sregs.ss);
1835
1836 get_seg(&env->tr, &sregs.tr);
1837 get_seg(&env->ldt, &sregs.ldt);
1838
1839 env->idt.limit = sregs.idt.limit;
1840 env->idt.base = sregs.idt.base;
1841 env->gdt.limit = sregs.gdt.limit;
1842 env->gdt.base = sregs.gdt.base;
1843
1844 env->cr[0] = sregs.cr0;
1845 env->cr[2] = sregs.cr2;
1846 env->cr[3] = sregs.cr3;
1847 env->cr[4] = sregs.cr4;
1848
1849 env->efer = sregs.efer;
1850
1851 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1852
1853 #define HFLAG_COPY_MASK \
1854 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1855 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1856 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1857 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1858
1859 hflags = env->hflags & HFLAG_COPY_MASK;
1860 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1861 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1862 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1863 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1864 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1865
1866 if (env->cr[4] & CR4_OSFXSR_MASK) {
1867 hflags |= HF_OSFXSR_MASK;
1868 }
1869
1870 if (env->efer & MSR_EFER_LMA) {
1871 hflags |= HF_LMA_MASK;
1872 }
1873
1874 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1875 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1876 } else {
1877 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1878 (DESC_B_SHIFT - HF_CS32_SHIFT);
1879 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1880 (DESC_B_SHIFT - HF_SS32_SHIFT);
1881 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1882 !(hflags & HF_CS32_MASK)) {
1883 hflags |= HF_ADDSEG_MASK;
1884 } else {
1885 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1886 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1887 }
1888 }
1889 env->hflags = hflags;
1890
1891 return 0;
1892 }
1893
1894 static int kvm_get_msrs(X86CPU *cpu)
1895 {
1896 CPUX86State *env = &cpu->env;
1897 struct {
1898 struct kvm_msrs info;
1899 struct kvm_msr_entry entries[150];
1900 } msr_data;
1901 struct kvm_msr_entry *msrs = msr_data.entries;
1902 int ret, i, n;
1903
1904 n = 0;
1905 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1906 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1907 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1908 msrs[n++].index = MSR_PAT;
1909 if (has_msr_star) {
1910 msrs[n++].index = MSR_STAR;
1911 }
1912 if (has_msr_hsave_pa) {
1913 msrs[n++].index = MSR_VM_HSAVE_PA;
1914 }
1915 if (has_msr_tsc_aux) {
1916 msrs[n++].index = MSR_TSC_AUX;
1917 }
1918 if (has_msr_tsc_adjust) {
1919 msrs[n++].index = MSR_TSC_ADJUST;
1920 }
1921 if (has_msr_tsc_deadline) {
1922 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1923 }
1924 if (has_msr_misc_enable) {
1925 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1926 }
1927 if (has_msr_smbase) {
1928 msrs[n++].index = MSR_IA32_SMBASE;
1929 }
1930 if (has_msr_feature_control) {
1931 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1932 }
1933 if (has_msr_bndcfgs) {
1934 msrs[n++].index = MSR_IA32_BNDCFGS;
1935 }
1936 if (has_msr_xss) {
1937 msrs[n++].index = MSR_IA32_XSS;
1938 }
1939
1940
1941 if (!env->tsc_valid) {
1942 msrs[n++].index = MSR_IA32_TSC;
1943 env->tsc_valid = !runstate_is_running();
1944 }
1945
1946 #ifdef TARGET_X86_64
1947 if (lm_capable_kernel) {
1948 msrs[n++].index = MSR_CSTAR;
1949 msrs[n++].index = MSR_KERNELGSBASE;
1950 msrs[n++].index = MSR_FMASK;
1951 msrs[n++].index = MSR_LSTAR;
1952 }
1953 #endif
1954 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1955 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1956 if (has_msr_async_pf_en) {
1957 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1958 }
1959 if (has_msr_pv_eoi_en) {
1960 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1961 }
1962 if (has_msr_kvm_steal_time) {
1963 msrs[n++].index = MSR_KVM_STEAL_TIME;
1964 }
1965 if (has_msr_architectural_pmu) {
1966 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1967 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1968 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1969 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1970 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1971 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1972 }
1973 for (i = 0; i < num_architectural_pmu_counters; i++) {
1974 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1975 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1976 }
1977 }
1978
1979 if (env->mcg_cap) {
1980 msrs[n++].index = MSR_MCG_STATUS;
1981 msrs[n++].index = MSR_MCG_CTL;
1982 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1983 msrs[n++].index = MSR_MC0_CTL + i;
1984 }
1985 }
1986
1987 if (has_msr_hv_hypercall) {
1988 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1989 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1990 }
1991 if (has_msr_hv_vapic) {
1992 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1993 }
1994 if (has_msr_hv_tsc) {
1995 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1996 }
1997 if (has_msr_hv_crash) {
1998 int j;
1999
2000 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2001 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
2002 }
2003 }
2004 if (has_msr_hv_runtime) {
2005 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
2006 }
2007 if (cpu->hyperv_synic) {
2008 uint32_t msr;
2009
2010 msrs[n++].index = HV_X64_MSR_SCONTROL;
2011 msrs[n++].index = HV_X64_MSR_SVERSION;
2012 msrs[n++].index = HV_X64_MSR_SIEFP;
2013 msrs[n++].index = HV_X64_MSR_SIMP;
2014 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2015 msrs[n++].index = msr;
2016 }
2017 }
2018 if (has_msr_hv_stimer) {
2019 uint32_t msr;
2020
2021 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2022 msr++) {
2023 msrs[n++].index = msr;
2024 }
2025 }
2026 if (has_msr_mtrr) {
2027 msrs[n++].index = MSR_MTRRdefType;
2028 msrs[n++].index = MSR_MTRRfix64K_00000;
2029 msrs[n++].index = MSR_MTRRfix16K_80000;
2030 msrs[n++].index = MSR_MTRRfix16K_A0000;
2031 msrs[n++].index = MSR_MTRRfix4K_C0000;
2032 msrs[n++].index = MSR_MTRRfix4K_C8000;
2033 msrs[n++].index = MSR_MTRRfix4K_D0000;
2034 msrs[n++].index = MSR_MTRRfix4K_D8000;
2035 msrs[n++].index = MSR_MTRRfix4K_E0000;
2036 msrs[n++].index = MSR_MTRRfix4K_E8000;
2037 msrs[n++].index = MSR_MTRRfix4K_F0000;
2038 msrs[n++].index = MSR_MTRRfix4K_F8000;
2039 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2040 msrs[n++].index = MSR_MTRRphysBase(i);
2041 msrs[n++].index = MSR_MTRRphysMask(i);
2042 }
2043 }
2044
2045 msr_data.info = (struct kvm_msrs) {
2046 .nmsrs = n,
2047 };
2048
2049 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
2050 if (ret < 0) {
2051 return ret;
2052 }
2053
2054 for (i = 0; i < ret; i++) {
2055 uint32_t index = msrs[i].index;
2056 switch (index) {
2057 case MSR_IA32_SYSENTER_CS:
2058 env->sysenter_cs = msrs[i].data;
2059 break;
2060 case MSR_IA32_SYSENTER_ESP:
2061 env->sysenter_esp = msrs[i].data;
2062 break;
2063 case MSR_IA32_SYSENTER_EIP:
2064 env->sysenter_eip = msrs[i].data;
2065 break;
2066 case MSR_PAT:
2067 env->pat = msrs[i].data;
2068 break;
2069 case MSR_STAR:
2070 env->star = msrs[i].data;
2071 break;
2072 #ifdef TARGET_X86_64
2073 case MSR_CSTAR:
2074 env->cstar = msrs[i].data;
2075 break;
2076 case MSR_KERNELGSBASE:
2077 env->kernelgsbase = msrs[i].data;
2078 break;
2079 case MSR_FMASK:
2080 env->fmask = msrs[i].data;
2081 break;
2082 case MSR_LSTAR:
2083 env->lstar = msrs[i].data;
2084 break;
2085 #endif
2086 case MSR_IA32_TSC:
2087 env->tsc = msrs[i].data;
2088 break;
2089 case MSR_TSC_AUX:
2090 env->tsc_aux = msrs[i].data;
2091 break;
2092 case MSR_TSC_ADJUST:
2093 env->tsc_adjust = msrs[i].data;
2094 break;
2095 case MSR_IA32_TSCDEADLINE:
2096 env->tsc_deadline = msrs[i].data;
2097 break;
2098 case MSR_VM_HSAVE_PA:
2099 env->vm_hsave = msrs[i].data;
2100 break;
2101 case MSR_KVM_SYSTEM_TIME:
2102 env->system_time_msr = msrs[i].data;
2103 break;
2104 case MSR_KVM_WALL_CLOCK:
2105 env->wall_clock_msr = msrs[i].data;
2106 break;
2107 case MSR_MCG_STATUS:
2108 env->mcg_status = msrs[i].data;
2109 break;
2110 case MSR_MCG_CTL:
2111 env->mcg_ctl = msrs[i].data;
2112 break;
2113 case MSR_IA32_MISC_ENABLE:
2114 env->msr_ia32_misc_enable = msrs[i].data;
2115 break;
2116 case MSR_IA32_SMBASE:
2117 env->smbase = msrs[i].data;
2118 break;
2119 case MSR_IA32_FEATURE_CONTROL:
2120 env->msr_ia32_feature_control = msrs[i].data;
2121 break;
2122 case MSR_IA32_BNDCFGS:
2123 env->msr_bndcfgs = msrs[i].data;
2124 break;
2125 case MSR_IA32_XSS:
2126 env->xss = msrs[i].data;
2127 break;
2128 default:
2129 if (msrs[i].index >= MSR_MC0_CTL &&
2130 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2131 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2132 }
2133 break;
2134 case MSR_KVM_ASYNC_PF_EN:
2135 env->async_pf_en_msr = msrs[i].data;
2136 break;
2137 case MSR_KVM_PV_EOI_EN:
2138 env->pv_eoi_en_msr = msrs[i].data;
2139 break;
2140 case MSR_KVM_STEAL_TIME:
2141 env->steal_time_msr = msrs[i].data;
2142 break;
2143 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2144 env->msr_fixed_ctr_ctrl = msrs[i].data;
2145 break;
2146 case MSR_CORE_PERF_GLOBAL_CTRL:
2147 env->msr_global_ctrl = msrs[i].data;
2148 break;
2149 case MSR_CORE_PERF_GLOBAL_STATUS:
2150 env->msr_global_status = msrs[i].data;
2151 break;
2152 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2153 env->msr_global_ovf_ctrl = msrs[i].data;
2154 break;
2155 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2156 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2157 break;
2158 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2159 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2160 break;
2161 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2162 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2163 break;
2164 case HV_X64_MSR_HYPERCALL:
2165 env->msr_hv_hypercall = msrs[i].data;
2166 break;
2167 case HV_X64_MSR_GUEST_OS_ID:
2168 env->msr_hv_guest_os_id = msrs[i].data;
2169 break;
2170 case HV_X64_MSR_APIC_ASSIST_PAGE:
2171 env->msr_hv_vapic = msrs[i].data;
2172 break;
2173 case HV_X64_MSR_REFERENCE_TSC:
2174 env->msr_hv_tsc = msrs[i].data;
2175 break;
2176 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2177 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2178 break;
2179 case HV_X64_MSR_VP_RUNTIME:
2180 env->msr_hv_runtime = msrs[i].data;
2181 break;
2182 case HV_X64_MSR_SCONTROL:
2183 env->msr_hv_synic_control = msrs[i].data;
2184 break;
2185 case HV_X64_MSR_SVERSION:
2186 env->msr_hv_synic_version = msrs[i].data;
2187 break;
2188 case HV_X64_MSR_SIEFP:
2189 env->msr_hv_synic_evt_page = msrs[i].data;
2190 break;
2191 case HV_X64_MSR_SIMP:
2192 env->msr_hv_synic_msg_page = msrs[i].data;
2193 break;
2194 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2195 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2196 break;
2197 case HV_X64_MSR_STIMER0_CONFIG:
2198 case HV_X64_MSR_STIMER1_CONFIG:
2199 case HV_X64_MSR_STIMER2_CONFIG:
2200 case HV_X64_MSR_STIMER3_CONFIG:
2201 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2202 msrs[i].data;
2203 break;
2204 case HV_X64_MSR_STIMER0_COUNT:
2205 case HV_X64_MSR_STIMER1_COUNT:
2206 case HV_X64_MSR_STIMER2_COUNT:
2207 case HV_X64_MSR_STIMER3_COUNT:
2208 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2209 msrs[i].data;
2210 break;
2211 case MSR_MTRRdefType:
2212 env->mtrr_deftype = msrs[i].data;
2213 break;
2214 case MSR_MTRRfix64K_00000:
2215 env->mtrr_fixed[0] = msrs[i].data;
2216 break;
2217 case MSR_MTRRfix16K_80000:
2218 env->mtrr_fixed[1] = msrs[i].data;
2219 break;
2220 case MSR_MTRRfix16K_A0000:
2221 env->mtrr_fixed[2] = msrs[i].data;
2222 break;
2223 case MSR_MTRRfix4K_C0000:
2224 env->mtrr_fixed[3] = msrs[i].data;
2225 break;
2226 case MSR_MTRRfix4K_C8000:
2227 env->mtrr_fixed[4] = msrs[i].data;
2228 break;
2229 case MSR_MTRRfix4K_D0000:
2230 env->mtrr_fixed[5] = msrs[i].data;
2231 break;
2232 case MSR_MTRRfix4K_D8000:
2233 env->mtrr_fixed[6] = msrs[i].data;
2234 break;
2235 case MSR_MTRRfix4K_E0000:
2236 env->mtrr_fixed[7] = msrs[i].data;
2237 break;
2238 case MSR_MTRRfix4K_E8000:
2239 env->mtrr_fixed[8] = msrs[i].data;
2240 break;
2241 case MSR_MTRRfix4K_F0000:
2242 env->mtrr_fixed[9] = msrs[i].data;
2243 break;
2244 case MSR_MTRRfix4K_F8000:
2245 env->mtrr_fixed[10] = msrs[i].data;
2246 break;
2247 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2248 if (index & 1) {
2249 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2250 } else {
2251 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2252 }
2253 break;
2254 }
2255 }
2256
2257 return 0;
2258 }
2259
2260 static int kvm_put_mp_state(X86CPU *cpu)
2261 {
2262 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2263
2264 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2265 }
2266
2267 static int kvm_get_mp_state(X86CPU *cpu)
2268 {
2269 CPUState *cs = CPU(cpu);
2270 CPUX86State *env = &cpu->env;
2271 struct kvm_mp_state mp_state;
2272 int ret;
2273
2274 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2275 if (ret < 0) {
2276 return ret;
2277 }
2278 env->mp_state = mp_state.mp_state;
2279 if (kvm_irqchip_in_kernel()) {
2280 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2281 }
2282 return 0;
2283 }
2284
2285 static int kvm_get_apic(X86CPU *cpu)
2286 {
2287 DeviceState *apic = cpu->apic_state;
2288 struct kvm_lapic_state kapic;
2289 int ret;
2290
2291 if (apic && kvm_irqchip_in_kernel()) {
2292 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2293 if (ret < 0) {
2294 return ret;
2295 }
2296
2297 kvm_get_apic_state(apic, &kapic);
2298 }
2299 return 0;
2300 }
2301
2302 static int kvm_put_apic(X86CPU *cpu)
2303 {
2304 DeviceState *apic = cpu->apic_state;
2305 struct kvm_lapic_state kapic;
2306
2307 if (apic && kvm_irqchip_in_kernel()) {
2308 kvm_put_apic_state(apic, &kapic);
2309
2310 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2311 }
2312 return 0;
2313 }
2314
2315 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2316 {
2317 CPUState *cs = CPU(cpu);
2318 CPUX86State *env = &cpu->env;
2319 struct kvm_vcpu_events events = {};
2320
2321 if (!kvm_has_vcpu_events()) {
2322 return 0;
2323 }
2324
2325 events.exception.injected = (env->exception_injected >= 0);
2326 events.exception.nr = env->exception_injected;
2327 events.exception.has_error_code = env->has_error_code;
2328 events.exception.error_code = env->error_code;
2329 events.exception.pad = 0;
2330
2331 events.interrupt.injected = (env->interrupt_injected >= 0);
2332 events.interrupt.nr = env->interrupt_injected;
2333 events.interrupt.soft = env->soft_interrupt;
2334
2335 events.nmi.injected = env->nmi_injected;
2336 events.nmi.pending = env->nmi_pending;
2337 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2338 events.nmi.pad = 0;
2339
2340 events.sipi_vector = env->sipi_vector;
2341
2342 if (has_msr_smbase) {
2343 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2344 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2345 if (kvm_irqchip_in_kernel()) {
2346 /* As soon as these are moved to the kernel, remove them
2347 * from cs->interrupt_request.
2348 */
2349 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2350 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2351 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2352 } else {
2353 /* Keep these in cs->interrupt_request. */
2354 events.smi.pending = 0;
2355 events.smi.latched_init = 0;
2356 }
2357 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2358 }
2359
2360 events.flags = 0;
2361 if (level >= KVM_PUT_RESET_STATE) {
2362 events.flags |=
2363 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2364 }
2365
2366 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2367 }
2368
2369 static int kvm_get_vcpu_events(X86CPU *cpu)
2370 {
2371 CPUX86State *env = &cpu->env;
2372 struct kvm_vcpu_events events;
2373 int ret;
2374
2375 if (!kvm_has_vcpu_events()) {
2376 return 0;
2377 }
2378
2379 memset(&events, 0, sizeof(events));
2380 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2381 if (ret < 0) {
2382 return ret;
2383 }
2384 env->exception_injected =
2385 events.exception.injected ? events.exception.nr : -1;
2386 env->has_error_code = events.exception.has_error_code;
2387 env->error_code = events.exception.error_code;
2388
2389 env->interrupt_injected =
2390 events.interrupt.injected ? events.interrupt.nr : -1;
2391 env->soft_interrupt = events.interrupt.soft;
2392
2393 env->nmi_injected = events.nmi.injected;
2394 env->nmi_pending = events.nmi.pending;
2395 if (events.nmi.masked) {
2396 env->hflags2 |= HF2_NMI_MASK;
2397 } else {
2398 env->hflags2 &= ~HF2_NMI_MASK;
2399 }
2400
2401 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2402 if (events.smi.smm) {
2403 env->hflags |= HF_SMM_MASK;
2404 } else {
2405 env->hflags &= ~HF_SMM_MASK;
2406 }
2407 if (events.smi.pending) {
2408 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2409 } else {
2410 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2411 }
2412 if (events.smi.smm_inside_nmi) {
2413 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2414 } else {
2415 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2416 }
2417 if (events.smi.latched_init) {
2418 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2419 } else {
2420 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2421 }
2422 }
2423
2424 env->sipi_vector = events.sipi_vector;
2425
2426 return 0;
2427 }
2428
2429 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2430 {
2431 CPUState *cs = CPU(cpu);
2432 CPUX86State *env = &cpu->env;
2433 int ret = 0;
2434 unsigned long reinject_trap = 0;
2435
2436 if (!kvm_has_vcpu_events()) {
2437 if (env->exception_injected == 1) {
2438 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2439 } else if (env->exception_injected == 3) {
2440 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2441 }
2442 env->exception_injected = -1;
2443 }
2444
2445 /*
2446 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2447 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2448 * by updating the debug state once again if single-stepping is on.
2449 * Another reason to call kvm_update_guest_debug here is a pending debug
2450 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2451 * reinject them via SET_GUEST_DEBUG.
2452 */
2453 if (reinject_trap ||
2454 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2455 ret = kvm_update_guest_debug(cs, reinject_trap);
2456 }
2457 return ret;
2458 }
2459
2460 static int kvm_put_debugregs(X86CPU *cpu)
2461 {
2462 CPUX86State *env = &cpu->env;
2463 struct kvm_debugregs dbgregs;
2464 int i;
2465
2466 if (!kvm_has_debugregs()) {
2467 return 0;
2468 }
2469
2470 for (i = 0; i < 4; i++) {
2471 dbgregs.db[i] = env->dr[i];
2472 }
2473 dbgregs.dr6 = env->dr[6];
2474 dbgregs.dr7 = env->dr[7];
2475 dbgregs.flags = 0;
2476
2477 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2478 }
2479
2480 static int kvm_get_debugregs(X86CPU *cpu)
2481 {
2482 CPUX86State *env = &cpu->env;
2483 struct kvm_debugregs dbgregs;
2484 int i, ret;
2485
2486 if (!kvm_has_debugregs()) {
2487 return 0;
2488 }
2489
2490 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2491 if (ret < 0) {
2492 return ret;
2493 }
2494 for (i = 0; i < 4; i++) {
2495 env->dr[i] = dbgregs.db[i];
2496 }
2497 env->dr[4] = env->dr[6] = dbgregs.dr6;
2498 env->dr[5] = env->dr[7] = dbgregs.dr7;
2499
2500 return 0;
2501 }
2502
2503 int kvm_arch_put_registers(CPUState *cpu, int level)
2504 {
2505 X86CPU *x86_cpu = X86_CPU(cpu);
2506 int ret;
2507
2508 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2509
2510 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2511 ret = kvm_put_msr_feature_control(x86_cpu);
2512 if (ret < 0) {
2513 return ret;
2514 }
2515 }
2516
2517 if (level == KVM_PUT_FULL_STATE) {
2518 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2519 * because TSC frequency mismatch shouldn't abort migration,
2520 * unless the user explicitly asked for a more strict TSC
2521 * setting (e.g. using an explicit "tsc-freq" option).
2522 */
2523 kvm_arch_set_tsc_khz(cpu);
2524 }
2525
2526 ret = kvm_getput_regs(x86_cpu, 1);
2527 if (ret < 0) {
2528 return ret;
2529 }
2530 ret = kvm_put_xsave(x86_cpu);
2531 if (ret < 0) {
2532 return ret;
2533 }
2534 ret = kvm_put_xcrs(x86_cpu);
2535 if (ret < 0) {
2536 return ret;
2537 }
2538 ret = kvm_put_sregs(x86_cpu);
2539 if (ret < 0) {
2540 return ret;
2541 }
2542 /* must be before kvm_put_msrs */
2543 ret = kvm_inject_mce_oldstyle(x86_cpu);
2544 if (ret < 0) {
2545 return ret;
2546 }
2547 ret = kvm_put_msrs(x86_cpu, level);
2548 if (ret < 0) {
2549 return ret;
2550 }
2551 if (level >= KVM_PUT_RESET_STATE) {
2552 ret = kvm_put_mp_state(x86_cpu);
2553 if (ret < 0) {
2554 return ret;
2555 }
2556 ret = kvm_put_apic(x86_cpu);
2557 if (ret < 0) {
2558 return ret;
2559 }
2560 }
2561
2562 ret = kvm_put_tscdeadline_msr(x86_cpu);
2563 if (ret < 0) {
2564 return ret;
2565 }
2566
2567 ret = kvm_put_vcpu_events(x86_cpu, level);
2568 if (ret < 0) {
2569 return ret;
2570 }
2571 ret = kvm_put_debugregs(x86_cpu);
2572 if (ret < 0) {
2573 return ret;
2574 }
2575 /* must be last */
2576 ret = kvm_guest_debug_workarounds(x86_cpu);
2577 if (ret < 0) {
2578 return ret;
2579 }
2580 return 0;
2581 }
2582
2583 int kvm_arch_get_registers(CPUState *cs)
2584 {
2585 X86CPU *cpu = X86_CPU(cs);
2586 int ret;
2587
2588 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2589
2590 ret = kvm_getput_regs(cpu, 0);
2591 if (ret < 0) {
2592 goto out;
2593 }
2594 ret = kvm_get_xsave(cpu);
2595 if (ret < 0) {
2596 goto out;
2597 }
2598 ret = kvm_get_xcrs(cpu);
2599 if (ret < 0) {
2600 goto out;
2601 }
2602 ret = kvm_get_sregs(cpu);
2603 if (ret < 0) {
2604 goto out;
2605 }
2606 ret = kvm_get_msrs(cpu);
2607 if (ret < 0) {
2608 goto out;
2609 }
2610 ret = kvm_get_mp_state(cpu);
2611 if (ret < 0) {
2612 goto out;
2613 }
2614 ret = kvm_get_apic(cpu);
2615 if (ret < 0) {
2616 goto out;
2617 }
2618 ret = kvm_get_vcpu_events(cpu);
2619 if (ret < 0) {
2620 goto out;
2621 }
2622 ret = kvm_get_debugregs(cpu);
2623 if (ret < 0) {
2624 goto out;
2625 }
2626 ret = 0;
2627 out:
2628 cpu_sync_bndcs_hflags(&cpu->env);
2629 return ret;
2630 }
2631
2632 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2633 {
2634 X86CPU *x86_cpu = X86_CPU(cpu);
2635 CPUX86State *env = &x86_cpu->env;
2636 int ret;
2637
2638 /* Inject NMI */
2639 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2640 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2641 qemu_mutex_lock_iothread();
2642 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2643 qemu_mutex_unlock_iothread();
2644 DPRINTF("injected NMI\n");
2645 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2646 if (ret < 0) {
2647 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2648 strerror(-ret));
2649 }
2650 }
2651 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2652 qemu_mutex_lock_iothread();
2653 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2654 qemu_mutex_unlock_iothread();
2655 DPRINTF("injected SMI\n");
2656 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2657 if (ret < 0) {
2658 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2659 strerror(-ret));
2660 }
2661 }
2662 }
2663
2664 if (!kvm_pic_in_kernel()) {
2665 qemu_mutex_lock_iothread();
2666 }
2667
2668 /* Force the VCPU out of its inner loop to process any INIT requests
2669 * or (for userspace APIC, but it is cheap to combine the checks here)
2670 * pending TPR access reports.
2671 */
2672 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2673 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2674 !(env->hflags & HF_SMM_MASK)) {
2675 cpu->exit_request = 1;
2676 }
2677 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2678 cpu->exit_request = 1;
2679 }
2680 }
2681
2682 if (!kvm_pic_in_kernel()) {
2683 /* Try to inject an interrupt if the guest can accept it */
2684 if (run->ready_for_interrupt_injection &&
2685 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2686 (env->eflags & IF_MASK)) {
2687 int irq;
2688
2689 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2690 irq = cpu_get_pic_interrupt(env);
2691 if (irq >= 0) {
2692 struct kvm_interrupt intr;
2693
2694 intr.irq = irq;
2695 DPRINTF("injected interrupt %d\n", irq);
2696 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2697 if (ret < 0) {
2698 fprintf(stderr,
2699 "KVM: injection failed, interrupt lost (%s)\n",
2700 strerror(-ret));
2701 }
2702 }
2703 }
2704
2705 /* If we have an interrupt but the guest is not ready to receive an
2706 * interrupt, request an interrupt window exit. This will
2707 * cause a return to userspace as soon as the guest is ready to
2708 * receive interrupts. */
2709 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2710 run->request_interrupt_window = 1;
2711 } else {
2712 run->request_interrupt_window = 0;
2713 }
2714
2715 DPRINTF("setting tpr\n");
2716 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2717
2718 qemu_mutex_unlock_iothread();
2719 }
2720 }
2721
2722 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2723 {
2724 X86CPU *x86_cpu = X86_CPU(cpu);
2725 CPUX86State *env = &x86_cpu->env;
2726
2727 if (run->flags & KVM_RUN_X86_SMM) {
2728 env->hflags |= HF_SMM_MASK;
2729 } else {
2730 env->hflags &= HF_SMM_MASK;
2731 }
2732 if (run->if_flag) {
2733 env->eflags |= IF_MASK;
2734 } else {
2735 env->eflags &= ~IF_MASK;
2736 }
2737
2738 /* We need to protect the apic state against concurrent accesses from
2739 * different threads in case the userspace irqchip is used. */
2740 if (!kvm_irqchip_in_kernel()) {
2741 qemu_mutex_lock_iothread();
2742 }
2743 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2744 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2745 if (!kvm_irqchip_in_kernel()) {
2746 qemu_mutex_unlock_iothread();
2747 }
2748 return cpu_get_mem_attrs(env);
2749 }
2750
2751 int kvm_arch_process_async_events(CPUState *cs)
2752 {
2753 X86CPU *cpu = X86_CPU(cs);
2754 CPUX86State *env = &cpu->env;
2755
2756 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2757 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2758 assert(env->mcg_cap);
2759
2760 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2761
2762 kvm_cpu_synchronize_state(cs);
2763
2764 if (env->exception_injected == EXCP08_DBLE) {
2765 /* this means triple fault */
2766 qemu_system_reset_request();
2767 cs->exit_request = 1;
2768 return 0;
2769 }
2770 env->exception_injected = EXCP12_MCHK;
2771 env->has_error_code = 0;
2772
2773 cs->halted = 0;
2774 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2775 env->mp_state = KVM_MP_STATE_RUNNABLE;
2776 }
2777 }
2778
2779 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2780 !(env->hflags & HF_SMM_MASK)) {
2781 kvm_cpu_synchronize_state(cs);
2782 do_cpu_init(cpu);
2783 }
2784
2785 if (kvm_irqchip_in_kernel()) {
2786 return 0;
2787 }
2788
2789 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2790 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2791 apic_poll_irq(cpu->apic_state);
2792 }
2793 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2794 (env->eflags & IF_MASK)) ||
2795 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2796 cs->halted = 0;
2797 }
2798 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2799 kvm_cpu_synchronize_state(cs);
2800 do_cpu_sipi(cpu);
2801 }
2802 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2803 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2804 kvm_cpu_synchronize_state(cs);
2805 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2806 env->tpr_access_type);
2807 }
2808
2809 return cs->halted;
2810 }
2811
2812 static int kvm_handle_halt(X86CPU *cpu)
2813 {
2814 CPUState *cs = CPU(cpu);
2815 CPUX86State *env = &cpu->env;
2816
2817 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2818 (env->eflags & IF_MASK)) &&
2819 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2820 cs->halted = 1;
2821 return EXCP_HLT;
2822 }
2823
2824 return 0;
2825 }
2826
2827 static int kvm_handle_tpr_access(X86CPU *cpu)
2828 {
2829 CPUState *cs = CPU(cpu);
2830 struct kvm_run *run = cs->kvm_run;
2831
2832 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2833 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2834 : TPR_ACCESS_READ);
2835 return 1;
2836 }
2837
2838 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2839 {
2840 static const uint8_t int3 = 0xcc;
2841
2842 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2843 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2844 return -EINVAL;
2845 }
2846 return 0;
2847 }
2848
2849 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2850 {
2851 uint8_t int3;
2852
2853 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2854 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2855 return -EINVAL;
2856 }
2857 return 0;
2858 }
2859
2860 static struct {
2861 target_ulong addr;
2862 int len;
2863 int type;
2864 } hw_breakpoint[4];
2865
2866 static int nb_hw_breakpoint;
2867
2868 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2869 {
2870 int n;
2871
2872 for (n = 0; n < nb_hw_breakpoint; n++) {
2873 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2874 (hw_breakpoint[n].len == len || len == -1)) {
2875 return n;
2876 }
2877 }
2878 return -1;
2879 }
2880
2881 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2882 target_ulong len, int type)
2883 {
2884 switch (type) {
2885 case GDB_BREAKPOINT_HW:
2886 len = 1;
2887 break;
2888 case GDB_WATCHPOINT_WRITE:
2889 case GDB_WATCHPOINT_ACCESS:
2890 switch (len) {
2891 case 1:
2892 break;
2893 case 2:
2894 case 4:
2895 case 8:
2896 if (addr & (len - 1)) {
2897 return -EINVAL;
2898 }
2899 break;
2900 default:
2901 return -EINVAL;
2902 }
2903 break;
2904 default:
2905 return -ENOSYS;
2906 }
2907
2908 if (nb_hw_breakpoint == 4) {
2909 return -ENOBUFS;
2910 }
2911 if (find_hw_breakpoint(addr, len, type) >= 0) {
2912 return -EEXIST;
2913 }
2914 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2915 hw_breakpoint[nb_hw_breakpoint].len = len;
2916 hw_breakpoint[nb_hw_breakpoint].type = type;
2917 nb_hw_breakpoint++;
2918
2919 return 0;
2920 }
2921
2922 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2923 target_ulong len, int type)
2924 {
2925 int n;
2926
2927 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2928 if (n < 0) {
2929 return -ENOENT;
2930 }
2931 nb_hw_breakpoint--;
2932 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2933
2934 return 0;
2935 }
2936
2937 void kvm_arch_remove_all_hw_breakpoints(void)
2938 {
2939 nb_hw_breakpoint = 0;
2940 }
2941
2942 static CPUWatchpoint hw_watchpoint;
2943
2944 static int kvm_handle_debug(X86CPU *cpu,
2945 struct kvm_debug_exit_arch *arch_info)
2946 {
2947 CPUState *cs = CPU(cpu);
2948 CPUX86State *env = &cpu->env;
2949 int ret = 0;
2950 int n;
2951
2952 if (arch_info->exception == 1) {
2953 if (arch_info->dr6 & (1 << 14)) {
2954 if (cs->singlestep_enabled) {
2955 ret = EXCP_DEBUG;
2956 }
2957 } else {
2958 for (n = 0; n < 4; n++) {
2959 if (arch_info->dr6 & (1 << n)) {
2960 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2961 case 0x0:
2962 ret = EXCP_DEBUG;
2963 break;
2964 case 0x1:
2965 ret = EXCP_DEBUG;
2966 cs->watchpoint_hit = &hw_watchpoint;
2967 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2968 hw_watchpoint.flags = BP_MEM_WRITE;
2969 break;
2970 case 0x3:
2971 ret = EXCP_DEBUG;
2972 cs->watchpoint_hit = &hw_watchpoint;
2973 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2974 hw_watchpoint.flags = BP_MEM_ACCESS;
2975 break;
2976 }
2977 }
2978 }
2979 }
2980 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2981 ret = EXCP_DEBUG;
2982 }
2983 if (ret == 0) {
2984 cpu_synchronize_state(cs);
2985 assert(env->exception_injected == -1);
2986
2987 /* pass to guest */
2988 env->exception_injected = arch_info->exception;
2989 env->has_error_code = 0;
2990 }
2991
2992 return ret;
2993 }
2994
2995 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2996 {
2997 const uint8_t type_code[] = {
2998 [GDB_BREAKPOINT_HW] = 0x0,
2999 [GDB_WATCHPOINT_WRITE] = 0x1,
3000 [GDB_WATCHPOINT_ACCESS] = 0x3
3001 };
3002 const uint8_t len_code[] = {
3003 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3004 };
3005 int n;
3006
3007 if (kvm_sw_breakpoints_active(cpu)) {
3008 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3009 }
3010 if (nb_hw_breakpoint > 0) {
3011 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3012 dbg->arch.debugreg[7] = 0x0600;
3013 for (n = 0; n < nb_hw_breakpoint; n++) {
3014 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3015 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3016 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3017 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3018 }
3019 }
3020 }
3021
3022 static bool host_supports_vmx(void)
3023 {
3024 uint32_t ecx, unused;
3025
3026 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3027 return ecx & CPUID_EXT_VMX;
3028 }
3029
3030 #define VMX_INVALID_GUEST_STATE 0x80000021
3031
3032 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3033 {
3034 X86CPU *cpu = X86_CPU(cs);
3035 uint64_t code;
3036 int ret;
3037
3038 switch (run->exit_reason) {
3039 case KVM_EXIT_HLT:
3040 DPRINTF("handle_hlt\n");
3041 qemu_mutex_lock_iothread();
3042 ret = kvm_handle_halt(cpu);
3043 qemu_mutex_unlock_iothread();
3044 break;
3045 case KVM_EXIT_SET_TPR:
3046 ret = 0;
3047 break;
3048 case KVM_EXIT_TPR_ACCESS:
3049 qemu_mutex_lock_iothread();
3050 ret = kvm_handle_tpr_access(cpu);
3051 qemu_mutex_unlock_iothread();
3052 break;
3053 case KVM_EXIT_FAIL_ENTRY:
3054 code = run->fail_entry.hardware_entry_failure_reason;
3055 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3056 code);
3057 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3058 fprintf(stderr,
3059 "\nIf you're running a guest on an Intel machine without "
3060 "unrestricted mode\n"
3061 "support, the failure can be most likely due to the guest "
3062 "entering an invalid\n"
3063 "state for Intel VT. For example, the guest maybe running "
3064 "in big real mode\n"
3065 "which is not supported on less recent Intel processors."
3066 "\n\n");
3067 }
3068 ret = -1;
3069 break;
3070 case KVM_EXIT_EXCEPTION:
3071 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3072 run->ex.exception, run->ex.error_code);
3073 ret = -1;
3074 break;
3075 case KVM_EXIT_DEBUG:
3076 DPRINTF("kvm_exit_debug\n");
3077 qemu_mutex_lock_iothread();
3078 ret = kvm_handle_debug(cpu, &run->debug.arch);
3079 qemu_mutex_unlock_iothread();
3080 break;
3081 case KVM_EXIT_HYPERV:
3082 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3083 break;
3084 case KVM_EXIT_IOAPIC_EOI:
3085 ioapic_eoi_broadcast(run->eoi.vector);
3086 ret = 0;
3087 break;
3088 default:
3089 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3090 ret = -1;
3091 break;
3092 }
3093
3094 return ret;
3095 }
3096
3097 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3098 {
3099 X86CPU *cpu = X86_CPU(cs);
3100 CPUX86State *env = &cpu->env;
3101
3102 kvm_cpu_synchronize_state(cs);
3103 return !(env->cr[0] & CR0_PE_MASK) ||
3104 ((env->segs[R_CS].selector & 3) != 3);
3105 }
3106
3107 void kvm_arch_init_irq_routing(KVMState *s)
3108 {
3109 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3110 /* If kernel can't do irq routing, interrupt source
3111 * override 0->2 cannot be set up as required by HPET.
3112 * So we have to disable it.
3113 */
3114 no_hpet = 1;
3115 }
3116 /* We know at this point that we're using the in-kernel
3117 * irqchip, so we can use irqfds, and on x86 we know
3118 * we can use msi via irqfd and GSI routing.
3119 */
3120 kvm_msi_via_irqfd_allowed = true;
3121 kvm_gsi_routing_allowed = true;
3122
3123 if (kvm_irqchip_is_split()) {
3124 int i;
3125
3126 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3127 MSI routes for signaling interrupts to the local apics. */
3128 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3129 struct MSIMessage msg = { 0x0, 0x0 };
3130 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3131 error_report("Could not enable split IRQ mode.");
3132 exit(1);
3133 }
3134 }
3135 }
3136 }
3137
3138 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3139 {
3140 int ret;
3141 if (machine_kernel_irqchip_split(ms)) {
3142 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3143 if (ret) {
3144 error_report("Could not enable split irqchip mode: %s\n",
3145 strerror(-ret));
3146 exit(1);
3147 } else {
3148 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3149 kvm_split_irqchip = true;
3150 return 1;
3151 }
3152 } else {
3153 return 0;
3154 }
3155 }
3156
3157 /* Classic KVM device assignment interface. Will remain x86 only. */
3158 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3159 uint32_t flags, uint32_t *dev_id)
3160 {
3161 struct kvm_assigned_pci_dev dev_data = {
3162 .segnr = dev_addr->domain,
3163 .busnr = dev_addr->bus,
3164 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3165 .flags = flags,
3166 };
3167 int ret;
3168
3169 dev_data.assigned_dev_id =
3170 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3171
3172 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3173 if (ret < 0) {
3174 return ret;
3175 }
3176
3177 *dev_id = dev_data.assigned_dev_id;
3178
3179 return 0;
3180 }
3181
3182 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3183 {
3184 struct kvm_assigned_pci_dev dev_data = {
3185 .assigned_dev_id = dev_id,
3186 };
3187
3188 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3189 }
3190
3191 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3192 uint32_t irq_type, uint32_t guest_irq)
3193 {
3194 struct kvm_assigned_irq assigned_irq = {
3195 .assigned_dev_id = dev_id,
3196 .guest_irq = guest_irq,
3197 .flags = irq_type,
3198 };
3199
3200 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3201 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3202 } else {
3203 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3204 }
3205 }
3206
3207 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3208 uint32_t guest_irq)
3209 {
3210 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3211 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3212
3213 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3214 }
3215
3216 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3217 {
3218 struct kvm_assigned_pci_dev dev_data = {
3219 .assigned_dev_id = dev_id,
3220 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3221 };
3222
3223 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3224 }
3225
3226 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3227 uint32_t type)
3228 {
3229 struct kvm_assigned_irq assigned_irq = {
3230 .assigned_dev_id = dev_id,
3231 .flags = type,
3232 };
3233
3234 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3235 }
3236
3237 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3238 {
3239 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3240 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3241 }
3242
3243 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3244 {
3245 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3246 KVM_DEV_IRQ_GUEST_MSI, virq);
3247 }
3248
3249 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3250 {
3251 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3252 KVM_DEV_IRQ_HOST_MSI);
3253 }
3254
3255 bool kvm_device_msix_supported(KVMState *s)
3256 {
3257 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3258 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3259 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3260 }
3261
3262 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3263 uint32_t nr_vectors)
3264 {
3265 struct kvm_assigned_msix_nr msix_nr = {
3266 .assigned_dev_id = dev_id,
3267 .entry_nr = nr_vectors,
3268 };
3269
3270 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3271 }
3272
3273 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3274 int virq)
3275 {
3276 struct kvm_assigned_msix_entry msix_entry = {
3277 .assigned_dev_id = dev_id,
3278 .gsi = virq,
3279 .entry = vector,
3280 };
3281
3282 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3283 }
3284
3285 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3286 {
3287 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3288 KVM_DEV_IRQ_GUEST_MSIX, 0);
3289 }
3290
3291 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3292 {
3293 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3294 KVM_DEV_IRQ_HOST_MSIX);
3295 }
3296
3297 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3298 uint64_t address, uint32_t data, PCIDevice *dev)
3299 {
3300 return 0;
3301 }
3302
3303 int kvm_arch_msi_data_to_gsi(uint32_t data)
3304 {
3305 abort();
3306 }
AR7 emulation for QEMU