target-ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "helper.h"
  21
  22 #include "helper_regs.h"
  23
  24 /*****************************************************************************/
  25 /* SPR accesses */
  26 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  27 {
  28     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  29              env->spr[sprn]);
  30 }
  31
  32 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  33 {
  34     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  35              env->spr[sprn]);
  36 }
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  40 {
  41     ppc_store_sdr1(env, val);
  42 }
  43
  44 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
  45 {
  46     target_ulong hid0;
  47
  48     hid0 = env->spr[SPR_HID0];
  49     if ((val ^ hid0) & 0x00000008) {
  50         /* Change current endianness */
  51         env->hflags &= ~(1 << MSR_LE);
  52         env->hflags_nmsr &= ~(1 << MSR_LE);
  53         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
  54         env->hflags |= env->hflags_nmsr;
  55         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
  56                  val & 0x8 ? 'l' : 'b', env->hflags);
  57     }
  58     env->spr[SPR_HID0] = (uint32_t)val;
  59 }
  60
  61 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
  62 {
  63     if (likely(env->pb[num] != value)) {
  64         env->pb[num] = value;
  65         /* Should be optimized */
  66         tlb_flush(env, 1);
  67     }
  68 }
  69
  70 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
  71 {
  72     store_40x_dbcr0(env, val);
  73 }
  74
  75 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
  76 {
  77     store_40x_sler(env, val);
  78 }
  79 #endif
  80 /*****************************************************************************/
  81 /* PowerPC 601 specific instructions (POWER bridge) */
  82
  83 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
  84 {
  85     switch (arg) {
  86     case 0x0CUL:
  87         /* Instruction cache line size */
  88         return env->icache_line_size;
  89         break;
  90     case 0x0DUL:
  91         /* Data cache line size */
  92         return env->dcache_line_size;
  93         break;
  94     case 0x0EUL:
  95         /* Minimum cache line size */
  96         return (env->icache_line_size < env->dcache_line_size) ?
  97             env->icache_line_size : env->dcache_line_size;
  98         break;
  99     case 0x0FUL:
 100         /* Maximum cache line size */
 101         return (env->icache_line_size > env->dcache_line_size) ?
 102             env->icache_line_size : env->dcache_line_size;
 103         break;
 104     default:
 105         /* Undefined */
 106         return 0;
 107         break;
 108     }
 109 }
 110
 111 /*****************************************************************************/
 112 /* Special registers manipulation */
 113
 114 /* GDBstub can read and write MSR... */
 115 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 116 {
 117     hreg_store_msr(env, value, 0);
 118 }