2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/sysbus.h"
27 #include "hw/scsi/esp.h"
32 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
33 * also produced as NCR89C100. See
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
39 static void esp_raise_irq(ESPState
*s
)
41 if (!(s
->rregs
[ESP_RSTAT
] & STAT_INT
)) {
42 s
->rregs
[ESP_RSTAT
] |= STAT_INT
;
43 qemu_irq_raise(s
->irq
);
44 trace_esp_raise_irq();
48 static void esp_lower_irq(ESPState
*s
)
50 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
51 s
->rregs
[ESP_RSTAT
] &= ~STAT_INT
;
52 qemu_irq_lower(s
->irq
);
53 trace_esp_lower_irq();
57 void esp_dma_enable(ESPState
*s
, int irq
, int level
)
61 trace_esp_dma_enable();
67 trace_esp_dma_disable();
72 void esp_request_cancelled(SCSIRequest
*req
)
74 ESPState
*s
= req
->hba_private
;
76 if (req
== s
->current_req
) {
77 scsi_req_unref(s
->current_req
);
78 s
->current_req
= NULL
;
79 s
->current_dev
= NULL
;
83 static uint32_t get_cmd(ESPState
*s
, uint8_t *buf
)
88 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
90 dmalen
= s
->rregs
[ESP_TCLO
];
91 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
92 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
93 s
->dma_memory_read(s
->dma_opaque
, buf
, dmalen
);
96 memcpy(buf
, s
->ti_buf
, dmalen
);
99 trace_esp_get_cmd(dmalen
, target
);
105 if (s
->current_req
) {
106 /* Started a new command before the old one finished. Cancel it. */
107 scsi_req_cancel(s
->current_req
);
111 s
->current_dev
= scsi_device_find(&s
->bus
, 0, target
, 0);
112 if (!s
->current_dev
) {
114 s
->rregs
[ESP_RSTAT
] = 0;
115 s
->rregs
[ESP_RINTR
] = INTR_DC
;
116 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
123 static void do_busid_cmd(ESPState
*s
, uint8_t *buf
, uint8_t busid
)
127 SCSIDevice
*current_lun
;
129 trace_esp_do_busid_cmd(busid
);
131 current_lun
= scsi_device_find(&s
->bus
, 0, s
->current_dev
->id
, lun
);
132 s
->current_req
= scsi_req_new(current_lun
, 0, lun
, buf
, s
);
133 datalen
= scsi_req_enqueue(s
->current_req
);
134 s
->ti_size
= datalen
;
136 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
140 s
->rregs
[ESP_RSTAT
] |= STAT_DI
;
142 s
->rregs
[ESP_RSTAT
] |= STAT_DO
;
144 scsi_req_continue(s
->current_req
);
146 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
147 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
151 static void do_cmd(ESPState
*s
, uint8_t *buf
)
153 uint8_t busid
= buf
[0];
155 do_busid_cmd(s
, &buf
[1], busid
);
158 static void handle_satn(ESPState
*s
)
163 if (s
->dma
&& !s
->dma_enabled
) {
164 s
->dma_cb
= handle_satn
;
167 len
= get_cmd(s
, buf
);
172 static void handle_s_without_atn(ESPState
*s
)
177 if (s
->dma
&& !s
->dma_enabled
) {
178 s
->dma_cb
= handle_s_without_atn
;
181 len
= get_cmd(s
, buf
);
183 do_busid_cmd(s
, buf
, 0);
187 static void handle_satn_stop(ESPState
*s
)
189 if (s
->dma
&& !s
->dma_enabled
) {
190 s
->dma_cb
= handle_satn_stop
;
193 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
);
195 trace_esp_handle_satn_stop(s
->cmdlen
);
197 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
198 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
199 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
204 static void write_response(ESPState
*s
)
206 trace_esp_write_response(s
->status
);
207 s
->ti_buf
[0] = s
->status
;
210 s
->dma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
211 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
212 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
213 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
218 s
->rregs
[ESP_RFLAGS
] = 2;
223 static void esp_dma_done(ESPState
*s
)
225 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
226 s
->rregs
[ESP_RINTR
] = INTR_BS
;
227 s
->rregs
[ESP_RSEQ
] = 0;
228 s
->rregs
[ESP_RFLAGS
] = 0;
229 s
->rregs
[ESP_TCLO
] = 0;
230 s
->rregs
[ESP_TCMID
] = 0;
231 s
->rregs
[ESP_TCHI
] = 0;
235 static void esp_do_dma(ESPState
*s
)
240 to_device
= (s
->ti_size
< 0);
243 trace_esp_do_dma(s
->cmdlen
, len
);
244 s
->dma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
248 do_cmd(s
, s
->cmdbuf
);
251 if (s
->async_len
== 0) {
252 /* Defer until data is available. */
255 if (len
> s
->async_len
) {
259 s
->dma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
261 s
->dma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
270 if (s
->async_len
== 0) {
271 scsi_req_continue(s
->current_req
);
272 /* If there is still data to be read from the device then
273 complete the DMA operation immediately. Otherwise defer
274 until the scsi layer has completed. */
275 if (to_device
|| s
->dma_left
!= 0 || s
->ti_size
== 0) {
280 /* Partially filled a scsi buffer. Complete immediately. */
284 void esp_command_complete(SCSIRequest
*req
, uint32_t status
,
287 ESPState
*s
= req
->hba_private
;
289 trace_esp_command_complete();
290 if (s
->ti_size
!= 0) {
291 trace_esp_command_complete_unexpected();
297 trace_esp_command_complete_fail();
300 s
->rregs
[ESP_RSTAT
] = STAT_ST
;
302 if (s
->current_req
) {
303 scsi_req_unref(s
->current_req
);
304 s
->current_req
= NULL
;
305 s
->current_dev
= NULL
;
309 void esp_transfer_data(SCSIRequest
*req
, uint32_t len
)
311 ESPState
*s
= req
->hba_private
;
313 trace_esp_transfer_data(s
->dma_left
, s
->ti_size
);
315 s
->async_buf
= scsi_req_get_buf(req
);
318 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
319 /* If this was the last part of a DMA transfer then the
320 completion interrupt is deferred to here. */
325 static void handle_ti(ESPState
*s
)
327 uint32_t dmalen
, minlen
;
329 if (s
->dma
&& !s
->dma_enabled
) {
330 s
->dma_cb
= handle_ti
;
334 dmalen
= s
->rregs
[ESP_TCLO
];
335 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
336 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
340 s
->dma_counter
= dmalen
;
343 minlen
= (dmalen
< 32) ? dmalen
: 32;
344 else if (s
->ti_size
< 0)
345 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
347 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
348 trace_esp_handle_ti(minlen
);
350 s
->dma_left
= minlen
;
351 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
353 } else if (s
->do_cmd
) {
354 trace_esp_handle_ti_cmd(s
->cmdlen
);
358 do_cmd(s
, s
->cmdbuf
);
363 void esp_hard_reset(ESPState
*s
)
365 memset(s
->rregs
, 0, ESP_REGS
);
366 memset(s
->wregs
, 0, ESP_REGS
);
367 s
->rregs
[ESP_TCHI
] = s
->chip_id
;
375 s
->rregs
[ESP_CFG1
] = 7;
378 static void esp_soft_reset(ESPState
*s
)
380 qemu_irq_lower(s
->irq
);
384 static void parent_esp_reset(ESPState
*s
, int irq
, int level
)
391 uint64_t esp_reg_read(ESPState
*s
, uint32_t saddr
)
395 trace_esp_mem_readb(saddr
, s
->rregs
[saddr
]);
398 if (s
->ti_size
> 0) {
400 if ((s
->rregs
[ESP_RSTAT
] & STAT_PIO_MASK
) == 0) {
402 qemu_log_mask(LOG_UNIMP
,
403 "esp: PIO data read not implemented\n");
404 s
->rregs
[ESP_FIFO
] = 0;
406 s
->rregs
[ESP_FIFO
] = s
->ti_buf
[s
->ti_rptr
++];
410 if (s
->ti_size
== 0) {
416 /* Clear sequence step, interrupt register and all status bits
418 old_val
= s
->rregs
[ESP_RINTR
];
419 s
->rregs
[ESP_RINTR
] = 0;
420 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
421 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
428 return s
->rregs
[saddr
];
431 void esp_reg_write(ESPState
*s
, uint32_t saddr
, uint64_t val
)
433 trace_esp_mem_writeb(saddr
, s
->wregs
[saddr
], val
);
438 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
442 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
443 } else if (s
->ti_size
== TI_BUFSZ
- 1) {
444 trace_esp_error_fifo_overrun();
447 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
451 s
->rregs
[saddr
] = val
;
454 /* Reload DMA counter. */
455 s
->rregs
[ESP_TCLO
] = s
->wregs
[ESP_TCLO
];
456 s
->rregs
[ESP_TCMID
] = s
->wregs
[ESP_TCMID
];
457 s
->rregs
[ESP_TCHI
] = s
->wregs
[ESP_TCHI
];
461 switch(val
& CMD_CMD
) {
463 trace_esp_mem_writeb_cmd_nop(val
);
466 trace_esp_mem_writeb_cmd_flush(val
);
468 s
->rregs
[ESP_RINTR
] = INTR_FC
;
469 s
->rregs
[ESP_RSEQ
] = 0;
470 s
->rregs
[ESP_RFLAGS
] = 0;
473 trace_esp_mem_writeb_cmd_reset(val
);
477 trace_esp_mem_writeb_cmd_bus_reset(val
);
478 s
->rregs
[ESP_RINTR
] = INTR_RST
;
479 if (!(s
->wregs
[ESP_CFG1
] & CFG1_RESREPT
)) {
487 trace_esp_mem_writeb_cmd_iccs(val
);
489 s
->rregs
[ESP_RINTR
] = INTR_FC
;
490 s
->rregs
[ESP_RSTAT
] |= STAT_MI
;
493 trace_esp_mem_writeb_cmd_msgacc(val
);
494 s
->rregs
[ESP_RINTR
] = INTR_DC
;
495 s
->rregs
[ESP_RSEQ
] = 0;
496 s
->rregs
[ESP_RFLAGS
] = 0;
500 trace_esp_mem_writeb_cmd_pad(val
);
501 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
502 s
->rregs
[ESP_RINTR
] = INTR_FC
;
503 s
->rregs
[ESP_RSEQ
] = 0;
506 trace_esp_mem_writeb_cmd_satn(val
);
509 trace_esp_mem_writeb_cmd_rstatn(val
);
512 trace_esp_mem_writeb_cmd_sel(val
);
513 handle_s_without_atn(s
);
516 trace_esp_mem_writeb_cmd_selatn(val
);
520 trace_esp_mem_writeb_cmd_selatns(val
);
524 trace_esp_mem_writeb_cmd_ensel(val
);
525 s
->rregs
[ESP_RINTR
] = 0;
528 trace_esp_mem_writeb_cmd_dissel(val
);
529 s
->rregs
[ESP_RINTR
] = 0;
533 trace_esp_error_unhandled_command(val
);
537 case ESP_WBUSID
... ESP_WSYNO
:
540 case ESP_CFG2
: case ESP_CFG3
:
541 case ESP_RES3
: case ESP_RES4
:
542 s
->rregs
[saddr
] = val
;
544 case ESP_WCCF
... ESP_WTEST
:
547 trace_esp_error_invalid_write(val
, saddr
);
550 s
->wregs
[saddr
] = val
;
553 static bool esp_mem_accepts(void *opaque
, hwaddr addr
,
554 unsigned size
, bool is_write
)
556 return (size
== 1) || (is_write
&& size
== 4);
559 const VMStateDescription vmstate_esp
= {
562 .minimum_version_id
= 3,
563 .minimum_version_id_old
= 3,
564 .fields
= (VMStateField
[]) {
565 VMSTATE_BUFFER(rregs
, ESPState
),
566 VMSTATE_BUFFER(wregs
, ESPState
),
567 VMSTATE_INT32(ti_size
, ESPState
),
568 VMSTATE_UINT32(ti_rptr
, ESPState
),
569 VMSTATE_UINT32(ti_wptr
, ESPState
),
570 VMSTATE_BUFFER(ti_buf
, ESPState
),
571 VMSTATE_UINT32(status
, ESPState
),
572 VMSTATE_UINT32(dma
, ESPState
),
573 VMSTATE_BUFFER(cmdbuf
, ESPState
),
574 VMSTATE_UINT32(cmdlen
, ESPState
),
575 VMSTATE_UINT32(do_cmd
, ESPState
),
576 VMSTATE_UINT32(dma_left
, ESPState
),
577 VMSTATE_END_OF_LIST()
588 static void sysbus_esp_mem_write(void *opaque
, hwaddr addr
,
589 uint64_t val
, unsigned int size
)
591 SysBusESPState
*sysbus
= opaque
;
594 saddr
= addr
>> sysbus
->it_shift
;
595 esp_reg_write(&sysbus
->esp
, saddr
, val
);
598 static uint64_t sysbus_esp_mem_read(void *opaque
, hwaddr addr
,
601 SysBusESPState
*sysbus
= opaque
;
604 saddr
= addr
>> sysbus
->it_shift
;
605 return esp_reg_read(&sysbus
->esp
, saddr
);
608 static const MemoryRegionOps sysbus_esp_mem_ops
= {
609 .read
= sysbus_esp_mem_read
,
610 .write
= sysbus_esp_mem_write
,
611 .endianness
= DEVICE_NATIVE_ENDIAN
,
612 .valid
.accepts
= esp_mem_accepts
,
615 void esp_init(hwaddr espaddr
, int it_shift
,
616 ESPDMAMemoryReadWriteFunc dma_memory_read
,
617 ESPDMAMemoryReadWriteFunc dma_memory_write
,
618 void *dma_opaque
, qemu_irq irq
, qemu_irq
*reset
,
619 qemu_irq
*dma_enable
)
623 SysBusESPState
*sysbus
;
626 dev
= qdev_create(NULL
, "esp");
627 sysbus
= DO_UPCAST(SysBusESPState
, busdev
.qdev
, dev
);
629 esp
->dma_memory_read
= dma_memory_read
;
630 esp
->dma_memory_write
= dma_memory_write
;
631 esp
->dma_opaque
= dma_opaque
;
632 sysbus
->it_shift
= it_shift
;
633 /* XXX for now until rc4030 has been changed to use DMA enable signal */
634 esp
->dma_enabled
= 1;
635 qdev_init_nofail(dev
);
636 s
= SYS_BUS_DEVICE(dev
);
637 sysbus_connect_irq(s
, 0, irq
);
638 sysbus_mmio_map(s
, 0, espaddr
);
639 *reset
= qdev_get_gpio_in(dev
, 0);
640 *dma_enable
= qdev_get_gpio_in(dev
, 1);
643 static const struct SCSIBusInfo esp_scsi_info
= {
645 .max_target
= ESP_MAX_DEVS
,
648 .transfer_data
= esp_transfer_data
,
649 .complete
= esp_command_complete
,
650 .cancel
= esp_request_cancelled
653 static void sysbus_esp_gpio_demux(void *opaque
, int irq
, int level
)
655 DeviceState
*d
= opaque
;
656 SysBusESPState
*sysbus
= container_of(d
, SysBusESPState
, busdev
.qdev
);
657 ESPState
*s
= &sysbus
->esp
;
661 parent_esp_reset(s
, irq
, level
);
664 esp_dma_enable(opaque
, irq
, level
);
669 static int sysbus_esp_init(SysBusDevice
*dev
)
671 SysBusESPState
*sysbus
= FROM_SYSBUS(SysBusESPState
, dev
);
672 ESPState
*s
= &sysbus
->esp
;
674 sysbus_init_irq(dev
, &s
->irq
);
675 assert(sysbus
->it_shift
!= -1);
677 s
->chip_id
= TCHI_FAS100A
;
678 memory_region_init_io(&sysbus
->iomem
, OBJECT(sysbus
), &sysbus_esp_mem_ops
,
679 sysbus
, "esp", ESP_REGS
<< sysbus
->it_shift
);
680 sysbus_init_mmio(dev
, &sysbus
->iomem
);
682 qdev_init_gpio_in(&dev
->qdev
, sysbus_esp_gpio_demux
, 2);
684 scsi_bus_new(&s
->bus
, &dev
->qdev
, &esp_scsi_info
, NULL
);
685 return scsi_bus_legacy_handle_cmdline(&s
->bus
);
688 static void sysbus_esp_hard_reset(DeviceState
*dev
)
690 SysBusESPState
*sysbus
= DO_UPCAST(SysBusESPState
, busdev
.qdev
, dev
);
691 esp_hard_reset(&sysbus
->esp
);
694 static const VMStateDescription vmstate_sysbus_esp_scsi
= {
695 .name
= "sysbusespscsi",
697 .minimum_version_id
= 0,
698 .minimum_version_id_old
= 0,
699 .fields
= (VMStateField
[]) {
700 VMSTATE_STRUCT(esp
, SysBusESPState
, 0, vmstate_esp
, ESPState
),
701 VMSTATE_END_OF_LIST()
705 static void sysbus_esp_class_init(ObjectClass
*klass
, void *data
)
707 DeviceClass
*dc
= DEVICE_CLASS(klass
);
708 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
710 k
->init
= sysbus_esp_init
;
711 dc
->reset
= sysbus_esp_hard_reset
;
712 dc
->vmsd
= &vmstate_sysbus_esp_scsi
;
715 static const TypeInfo sysbus_esp_info
= {
717 .parent
= TYPE_SYS_BUS_DEVICE
,
718 .instance_size
= sizeof(SysBusESPState
),
719 .class_init
= sysbus_esp_class_init
,
722 static void esp_register_types(void)
724 type_register_static(&sysbus_esp_info
);
727 type_init(esp_register_types
)