hw/riscv/virt.c

   1 /*
   2  * QEMU RISC-V VirtIO Board
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * RISC-V machine with 16550a UART and VirtIO MMIO
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/units.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "qapi/error.h"
  26 #include "hw/hw.h"
  27 #include "hw/boards.h"
  28 #include "hw/loader.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/char/serial.h"
  31 #include "target/riscv/cpu.h"
  32 #include "hw/riscv/riscv_htif.h"
  33 #include "hw/riscv/riscv_hart.h"
  34 #include "hw/riscv/sifive_plic.h"
  35 #include "hw/riscv/sifive_clint.h"
  36 #include "hw/riscv/sifive_test.h"
  37 #include "hw/riscv/virt.h"
  38 #include "chardev/char.h"
  39 #include "sysemu/arch_init.h"
  40 #include "sysemu/device_tree.h"
  41 #include "exec/address-spaces.h"
  42 #include "elf.h"
  43
  44 #include <libfdt.h>
  45
  46 static const struct MemmapEntry {
  47     hwaddr base;
  48     hwaddr size;
  49 } virt_memmap[] = {
  50     [VIRT_DEBUG] =    {        0x0,      0x100 },
  51     [VIRT_MROM] =     {     0x1000,    0x11000 },
  52     [VIRT_TEST] =     {   0x100000,     0x1000 },
  53     [VIRT_CLINT] =    {  0x2000000,    0x10000 },
  54     [VIRT_PLIC] =     {  0xc000000,  0x4000000 },
  55     [VIRT_UART0] =    { 0x10000000,      0x100 },
  56     [VIRT_VIRTIO] =   { 0x10001000,     0x1000 },
  57     [VIRT_DRAM] =     { 0x80000000,        0x0 },
  58 };
  59
  60 static uint64_t load_kernel(const char *kernel_filename)
  61 {
  62     uint64_t kernel_entry, kernel_high;
  63
  64     if (load_elf(kernel_filename, NULL, NULL,
  65                  &kernel_entry, NULL, &kernel_high,
  66                  0, EM_RISCV, 1, 0) < 0) {
  67         error_report("qemu: could not load kernel '%s'", kernel_filename);
  68         exit(1);
  69     }
  70     return kernel_entry;
  71 }
  72
  73 static hwaddr load_initrd(const char *filename, uint64_t mem_size,
  74                           uint64_t kernel_entry, hwaddr *start)
  75 {
  76     int size;
  77
  78     /* We want to put the initrd far enough into RAM that when the
  79      * kernel is uncompressed it will not clobber the initrd. However
  80      * on boards without much RAM we must ensure that we still leave
  81      * enough room for a decent sized initrd, and on boards with large
  82      * amounts of RAM we must avoid the initrd being so far up in RAM
  83      * that it is outside lowmem and inaccessible to the kernel.
  84      * So for boards with less  than 256MB of RAM we put the initrd
  85      * halfway into RAM, and for boards with 256MB of RAM or more we put
  86      * the initrd at 128MB.
  87      */
  88     *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
  89
  90     size = load_ramdisk(filename, *start, mem_size - *start);
  91     if (size == -1) {
  92         size = load_image_targphys(filename, *start, mem_size - *start);
  93         if (size == -1) {
  94             error_report("qemu: could not load ramdisk '%s'", filename);
  95             exit(1);
  96         }
  97     }
  98     return *start + size;
  99 }
 100
 101 static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 102     uint64_t mem_size, const char *cmdline)
 103 {
 104     void *fdt;
 105     int cpu;
 106     uint32_t *cells;
 107     char *nodename;
 108     uint32_t plic_phandle, phandle = 1;
 109     int i;
 110
 111     fdt = s->fdt = create_device_tree(&s->fdt_size);
 112     if (!fdt) {
 113         error_report("create_device_tree() failed");
 114         exit(1);
 115     }
 116
 117     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
 118     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
 119     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 120     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 121
 122     qemu_fdt_add_subnode(fdt, "/soc");
 123     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 124     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
 125     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 126     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 127
 128     nodename = g_strdup_printf("/memory@%lx",
 129         (long)memmap[VIRT_DRAM].base);
 130     qemu_fdt_add_subnode(fdt, nodename);
 131     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 132         memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
 133         mem_size >> 32, mem_size);
 134     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 135     g_free(nodename);
 136
 137     qemu_fdt_add_subnode(fdt, "/cpus");
 138     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 139                           SIFIVE_CLINT_TIMEBASE_FREQ);
 140     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 141     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 142
 143     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 144         int cpu_phandle = phandle++;
 145         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 146         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 147         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 148         qemu_fdt_add_subnode(fdt, nodename);
 149         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 150                               VIRT_CLOCK_FREQ);
 151         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 152         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 153         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 154         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 155         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 156         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 157         qemu_fdt_add_subnode(fdt, intc);
 158         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 159         qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
 160         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 161         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 162         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 163         g_free(isa);
 164         g_free(intc);
 165         g_free(nodename);
 166     }
 167
 168     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 169     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 170         nodename =
 171             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 172         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 173         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 174         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 175         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 176         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 177         g_free(nodename);
 178     }
 179     nodename = g_strdup_printf("/soc/clint@%lx",
 180         (long)memmap[VIRT_CLINT].base);
 181     qemu_fdt_add_subnode(fdt, nodename);
 182     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 183     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 184         0x0, memmap[VIRT_CLINT].base,
 185         0x0, memmap[VIRT_CLINT].size);
 186     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 187         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 188     g_free(cells);
 189     g_free(nodename);
 190
 191     plic_phandle = phandle++;
 192     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 193     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 194         nodename =
 195             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 196         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 197         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 198         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 199         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 200         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 201         g_free(nodename);
 202     }
 203     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 204         (long)memmap[VIRT_PLIC].base);
 205     qemu_fdt_add_subnode(fdt, nodename);
 206     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 207     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 208     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 209     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 210         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 211     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 212         0x0, memmap[VIRT_PLIC].base,
 213         0x0, memmap[VIRT_PLIC].size);
 214     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 215     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 216     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 217     qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
 218     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
 219     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 220     g_free(cells);
 221     g_free(nodename);
 222
 223     for (i = 0; i < VIRTIO_COUNT; i++) {
 224         nodename = g_strdup_printf("/virtio_mmio@%lx",
 225             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
 226         qemu_fdt_add_subnode(fdt, nodename);
 227         qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
 228         qemu_fdt_setprop_cells(fdt, nodename, "reg",
 229             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 230             0x0, memmap[VIRT_VIRTIO].size);
 231         qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 232         qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
 233         g_free(nodename);
 234     }
 235
 236     nodename = g_strdup_printf("/test@%lx",
 237         (long)memmap[VIRT_TEST].base);
 238     qemu_fdt_add_subnode(fdt, nodename);
 239     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
 240     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 241         0x0, memmap[VIRT_TEST].base,
 242         0x0, memmap[VIRT_TEST].size);
 243
 244     nodename = g_strdup_printf("/uart@%lx",
 245         (long)memmap[VIRT_UART0].base);
 246     qemu_fdt_add_subnode(fdt, nodename);
 247     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 248     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 249         0x0, memmap[VIRT_UART0].base,
 250         0x0, memmap[VIRT_UART0].size);
 251     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 252         qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 253         qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
 254
 255     qemu_fdt_add_subnode(fdt, "/chosen");
 256     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 257     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 258     g_free(nodename);
 259
 260     return fdt;
 261 }
 262
 263 static void riscv_virt_board_init(MachineState *machine)
 264 {
 265     const struct MemmapEntry *memmap = virt_memmap;
 266
 267     RISCVVirtState *s = g_new0(RISCVVirtState, 1);
 268     MemoryRegion *system_memory = get_system_memory();
 269     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 270     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 271     char *plic_hart_config;
 272     size_t plic_hart_config_len;
 273     int i;
 274     void *fdt;
 275
 276     /* Initialize SOC */
 277     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
 278                             TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
 279     object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
 280                             &error_abort);
 281     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 282                             &error_abort);
 283     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 284                             &error_abort);
 285
 286     /* register system main memory (actual RAM) */
 287     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 288                            machine->ram_size, &error_fatal);
 289     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 290         main_mem);
 291
 292     /* create device tree */
 293     fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 294
 295     /* boot rom */
 296     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
 297                            memmap[VIRT_MROM].size, &error_fatal);
 298     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
 299                                 mask_rom);
 300
 301     if (machine->kernel_filename) {
 302         uint64_t kernel_entry = load_kernel(machine->kernel_filename);
 303
 304         if (machine->initrd_filename) {
 305             hwaddr start;
 306             hwaddr end = load_initrd(machine->initrd_filename,
 307                                      machine->ram_size, kernel_entry,
 308                                      &start);
 309             qemu_fdt_setprop_cell(fdt, "/chosen",
 310                                   "linux,initrd-start", start);
 311             qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 312                                   end);
 313         }
 314     }
 315
 316     /* reset vector */
 317     uint32_t reset_vec[8] = {
 318         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 319         0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 320         0xf1402573,                  /*     csrr   a0, mhartid  */
 321 #if defined(TARGET_RISCV32)
 322         0x0182a283,                  /*     lw     t0, 24(t0) */
 323 #elif defined(TARGET_RISCV64)
 324         0x0182b283,                  /*     ld     t0, 24(t0) */
 325 #endif
 326         0x00028067,                  /*     jr     t0 */
 327         0x00000000,
 328         memmap[VIRT_DRAM].base,      /* start: .dword memmap[VIRT_DRAM].base */
 329         0x00000000,
 330                                      /* dtb: */
 331     };
 332
 333     /* copy in the reset vector in little_endian byte order */
 334     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 335         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 336     }
 337     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 338                           memmap[VIRT_MROM].base, &address_space_memory);
 339
 340     /* copy in the device tree */
 341     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 342             memmap[VIRT_MROM].size - sizeof(reset_vec)) {
 343         error_report("not enough space to store device-tree");
 344         exit(1);
 345     }
 346     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 347     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 348                           memmap[VIRT_MROM].base + sizeof(reset_vec),
 349                           &address_space_memory);
 350
 351     /* create PLIC hart topology configuration string */
 352     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 353     plic_hart_config = g_malloc0(plic_hart_config_len);
 354     for (i = 0; i < smp_cpus; i++) {
 355         if (i != 0) {
 356             strncat(plic_hart_config, ",", plic_hart_config_len);
 357         }
 358         strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
 359         plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 360     }
 361
 362     /* MMIO */
 363     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 364         plic_hart_config,
 365         VIRT_PLIC_NUM_SOURCES,
 366         VIRT_PLIC_NUM_PRIORITIES,
 367         VIRT_PLIC_PRIORITY_BASE,
 368         VIRT_PLIC_PENDING_BASE,
 369         VIRT_PLIC_ENABLE_BASE,
 370         VIRT_PLIC_ENABLE_STRIDE,
 371         VIRT_PLIC_CONTEXT_BASE,
 372         VIRT_PLIC_CONTEXT_STRIDE,
 373         memmap[VIRT_PLIC].size);
 374     sifive_clint_create(memmap[VIRT_CLINT].base,
 375         memmap[VIRT_CLINT].size, smp_cpus,
 376         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 377     sifive_test_create(memmap[VIRT_TEST].base);
 378
 379     for (i = 0; i < VIRTIO_COUNT; i++) {
 380         sysbus_create_simple("virtio-mmio",
 381             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 382             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
 383     }
 384
 385     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 386         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
 387         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 388 }
 389
 390 static void riscv_virt_board_machine_init(MachineClass *mc)
 391 {
 392     mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
 393     mc->init = riscv_virt_board_init;
 394     mc->max_cpus = 8; /* hardcoded limit in BBL */
 395 }
 396
 397 DEFINE_MACHINE("virt", riscv_virt_board_machine_init)