target-i386/cpu-qom.h

   1 /*
   2  * QEMU x86 CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20 #ifndef QEMU_I386_CPU_QOM_H
  21 #define QEMU_I386_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24 #include "cpu.h"
  25 #include "qapi/error.h"
  26
  27 #ifdef TARGET_X86_64
  28 #define TYPE_X86_CPU "x86_64-cpu"
  29 #else
  30 #define TYPE_X86_CPU "i386-cpu"
  31 #endif
  32
  33 #define X86_CPU_CLASS(klass) \
  34     OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
  35 #define X86_CPU(obj) \
  36     OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
  37 #define X86_CPU_GET_CLASS(obj) \
  38     OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
  39
  40 /**
  41  * X86CPUClass:
  42  * @parent_realize: The parent class' realize handler.
  43  * @parent_reset: The parent class' reset handler.
  44  *
  45  * An x86 CPU model or family.
  46  */
  47 typedef struct X86CPUClass {
  48     /*< private >*/
  49     CPUClass parent_class;
  50     /*< public >*/
  51
  52     DeviceRealize parent_realize;
  53     void (*parent_reset)(CPUState *cpu);
  54 } X86CPUClass;
  55
  56 /**
  57  * X86CPU:
  58  * @env: #CPUX86State
  59  *
  60  * An x86 CPU.
  61  */
  62 typedef struct X86CPU {
  63     /*< private >*/
  64     CPUState parent_obj;
  65     /*< public >*/
  66
  67     CPUX86State env;
  68
  69     bool hyperv_vapic;
  70     bool hyperv_relaxed_timing;
  71     int hyperv_spinlock_attempts;
  72
  73     /* if true the CPUID code directly forward host cache leaves to the guest */
  74     bool cache_info_passthrough;
  75
  76     /* Features that were filtered out because of missing host capabilities */
  77     uint32_t filtered_features[FEATURE_WORDS];
  78
  79     /* Enable PMU CPUID bits. This can't be enabled by default yet because
  80      * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
  81      * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
  82      * capabilities) directly to the guest.
  83      */
  84     bool enable_pmu;
  85 } X86CPU;
  86
  87 static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
  88 {
  89     return container_of(env, X86CPU, env);
  90 }
  91
  92 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
  93
  94 #define ENV_OFFSET offsetof(X86CPU, env)
  95
  96 #ifndef CONFIG_USER_ONLY
  97 extern const struct VMStateDescription vmstate_x86_cpu;
  98 #endif
  99
 100 /**
 101  * x86_cpu_do_interrupt:
 102  * @cpu: vCPU the interrupt is to be handled by.
 103  */
 104 void x86_cpu_do_interrupt(CPUState *cpu);
 105
 106 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 107                              int cpuid, void *opaque);
 108 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 109                              int cpuid, void *opaque);
 110 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 111                                  void *opaque);
 112 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 113                                  void *opaque);
 114
 115 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 116                                 Error **errp);
 117
 118 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 119                         int flags);
 120
 121 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 122
 123 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 124 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 125
 126 #endif