tests/libqos/virtio-pci.c

   1 /*
   2  * libqos virtio PCI driver
   3  *
   4  * Copyright (c) 2014 Marc Marí
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "libqtest.h"
  12 #include "libqos/virtio.h"
  13 #include "libqos/virtio-pci.h"
  14 #include "libqos/pci.h"
  15 #include "libqos/pci-pc.h"
  16 #include "libqos/malloc.h"
  17 #include "libqos/malloc-pc.h"
  18 #include "libqos/qgraph.h"
  19 #include "standard-headers/linux/virtio_ring.h"
  20 #include "standard-headers/linux/virtio_pci.h"
  21
  22 #include "hw/pci/pci.h"
  23 #include "hw/pci/pci_regs.h"
  24
  25 /* virtio-pci is a superclass of all virtio-xxx-pci devices;
  26  * the relation between virtio-pci and virtio-xxx-pci is implicit,
  27  * and therefore virtio-pci does not produce virtio and is not
  28  * reached by any edge, not even as a "contains" edge.
  29  * In facts, every device is a QVirtioPCIDevice with
  30  * additional fields, since every one has its own
  31  * number of queues and various attributes.
  32  * Virtio-pci provides default functions to start the
  33  * hw and destroy the object, and nodes that want to
  34  * override them should always remember to call the
  35  * original qvirtio_pci_destructor and qvirtio_pci_start_hw.
  36  */
  37
  38 static inline bool qvirtio_pci_is_big_endian(QVirtioPCIDevice *dev)
  39 {
  40     QPCIBus *bus = dev->pdev->bus;
  41
  42     /* FIXME: virtio 1.0 is always little-endian */
  43     return qtest_big_endian(bus->qts);
  44 }
  45
  46 #define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
  47
  48 static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off)
  49 {
  50     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  51     return qpci_io_readb(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  52 }
  53
  54 /* PCI is always read in little-endian order
  55  * but virtio ( < 1.0) is in guest order
  56  * so with a big-endian guest the order has been reversed,
  57  * reverse it again
  58  * virtio-1.0 is always little-endian, like PCI, but this
  59  * case will be managed inside qvirtio_pci_is_big_endian()
  60  */
  61
  62 static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off)
  63 {
  64     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  65     uint16_t value;
  66
  67     value = qpci_io_readw(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  68     if (qvirtio_is_big_endian(d)) {
  69         value = bswap16(value);
  70     }
  71     return value;
  72 }
  73
  74 static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
  75 {
  76     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  77     uint32_t value;
  78
  79     value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  80     if (qvirtio_is_big_endian(d)) {
  81         value = bswap32(value);
  82     }
  83     return value;
  84 }
  85
  86 static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
  87 {
  88     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
  89     uint64_t val;
  90
  91     val = qpci_io_readq(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
  92     if (qvirtio_is_big_endian(d)) {
  93         val = bswap64(val);
  94     }
  95
  96     return val;
  97 }
  98
  99 static uint64_t qvirtio_pci_get_features(QVirtioDevice *d)
 100 {
 101     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 102     return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_HOST_FEATURES);
 103 }
 104
 105 static void qvirtio_pci_set_features(QVirtioDevice *d, uint64_t features)
 106 {
 107     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 108     qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES, features);
 109 }
 110
 111 static uint64_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
 112 {
 113     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 114     return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES);
 115 }
 116
 117 static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
 118 {
 119     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 120     return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS);
 121 }
 122
 123 static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
 124 {
 125     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 126     qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS, status);
 127 }
 128
 129 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
 130 {
 131     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 132     QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
 133     uint32_t data;
 134
 135     if (dev->pdev->msix_enabled) {
 136         g_assert_cmpint(vqpci->msix_entry, !=, -1);
 137         if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
 138             /* No ISR checking should be done if masked, but read anyway */
 139             return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
 140         } else {
 141             data = qtest_readl(dev->pdev->bus->qts, vqpci->msix_addr);
 142             if (data == vqpci->msix_data) {
 143                 qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0);
 144                 return true;
 145             } else {
 146                 return false;
 147             }
 148         }
 149     } else {
 150         return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1;
 151     }
 152 }
 153
 154 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
 155 {
 156     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 157     uint32_t data;
 158
 159     if (dev->pdev->msix_enabled) {
 160         g_assert_cmpint(dev->config_msix_entry, !=, -1);
 161         if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
 162             /* No ISR checking should be done if masked, but read anyway */
 163             return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
 164         } else {
 165             data = qtest_readl(dev->pdev->bus->qts, dev->config_msix_addr);
 166             if (data == dev->config_msix_data) {
 167                 qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0);
 168                 return true;
 169             } else {
 170                 return false;
 171             }
 172         }
 173     } else {
 174         return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2;
 175     }
 176 }
 177
 178 static void qvirtio_pci_wait_config_isr_status(QVirtioDevice *d,
 179                                                gint64 timeout_us)
 180 {
 181     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 182     gint64 start_time = g_get_monotonic_time();
 183
 184     do {
 185         g_assert(g_get_monotonic_time() - start_time <= timeout_us);
 186         qtest_clock_step(dev->pdev->bus->qts, 100);
 187     } while (!qvirtio_pci_get_config_isr_status(d));
 188 }
 189
 190 static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
 191 {
 192     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 193     qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_SEL, index);
 194 }
 195
 196 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
 197 {
 198     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 199     return qpci_io_readw(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NUM);
 200 }
 201
 202 static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
 203 {
 204     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 205     qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn);
 206 }
 207
 208 static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
 209                                         QGuestAllocator *alloc, uint16_t index)
 210 {
 211     uint64_t feat;
 212     uint64_t addr;
 213     QVirtQueuePCI *vqpci;
 214     QVirtioPCIDevice *qvpcidev = container_of(d, QVirtioPCIDevice, vdev);
 215
 216     vqpci = g_malloc0(sizeof(*vqpci));
 217     feat = qvirtio_pci_get_guest_features(d);
 218
 219     qvirtio_pci_queue_select(d, index);
 220     vqpci->vq.index = index;
 221     vqpci->vq.size = qvirtio_pci_get_queue_size(d);
 222     vqpci->vq.free_head = 0;
 223     vqpci->vq.num_free = vqpci->vq.size;
 224     vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
 225     vqpci->vq.indirect = feat & (1ull << VIRTIO_RING_F_INDIRECT_DESC);
 226     vqpci->vq.event = feat & (1ull << VIRTIO_RING_F_EVENT_IDX);
 227
 228     vqpci->msix_entry = -1;
 229     vqpci->msix_addr = 0;
 230     vqpci->msix_data = 0x12345678;
 231
 232     /* Check different than 0 */
 233     g_assert_cmpint(vqpci->vq.size, !=, 0);
 234
 235     /* Check power of 2 */
 236     g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
 237
 238     addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
 239                                           VIRTIO_PCI_VRING_ALIGN));
 240     qvring_init(qvpcidev->pdev->bus->qts, alloc, &vqpci->vq, addr);
 241     qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALIGN);
 242
 243     return &vqpci->vq;
 244 }
 245
 246 static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq,
 247                                           QGuestAllocator *alloc)
 248 {
 249     QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
 250
 251     guest_free(alloc, vq->desc);
 252     g_free(vqpci);
 253 }
 254
 255 static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
 256 {
 257     QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
 258     qpci_io_writew(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
 259 }
 260
 261 const QVirtioBus qvirtio_pci = {
 262     .config_readb = qvirtio_pci_config_readb,
 263     .config_readw = qvirtio_pci_config_readw,
 264     .config_readl = qvirtio_pci_config_readl,
 265     .config_readq = qvirtio_pci_config_readq,
 266     .get_features = qvirtio_pci_get_features,
 267     .set_features = qvirtio_pci_set_features,
 268     .get_guest_features = qvirtio_pci_get_guest_features,
 269     .get_status = qvirtio_pci_get_status,
 270     .set_status = qvirtio_pci_set_status,
 271     .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
 272     .wait_config_isr_status = qvirtio_pci_wait_config_isr_status,
 273     .queue_select = qvirtio_pci_queue_select,
 274     .get_queue_size = qvirtio_pci_get_queue_size,
 275     .set_queue_address = qvirtio_pci_set_queue_address,
 276     .virtqueue_setup = qvirtio_pci_virtqueue_setup,
 277     .virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup,
 278     .virtqueue_kick = qvirtio_pci_virtqueue_kick,
 279 };
 280
 281 void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
 282 {
 283     qpci_device_enable(d->pdev);
 284     d->bar = qpci_iomap(d->pdev, 0, NULL);
 285 }
 286
 287 void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
 288 {
 289     qpci_iounmap(d->pdev, d->bar);
 290 }
 291
 292 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
 293                                         QGuestAllocator *alloc, uint16_t entry)
 294 {
 295     uint16_t vector;
 296     uint32_t control;
 297     uint64_t off;
 298
 299     g_assert(d->pdev->msix_enabled);
 300     off = d->pdev->msix_table_off + (entry * 16);
 301
 302     g_assert_cmpint(entry, >=, 0);
 303     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 304     vqpci->msix_entry = entry;
 305
 306     vqpci->msix_addr = guest_alloc(alloc, 4);
 307     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 308                    off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL);
 309     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 310                    off + PCI_MSIX_ENTRY_UPPER_ADDR,
 311                    (vqpci->msix_addr >> 32) & ~0UL);
 312     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 313                    off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
 314
 315     control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
 316                             off + PCI_MSIX_ENTRY_VECTOR_CTRL);
 317     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 318                    off + PCI_MSIX_ENTRY_VECTOR_CTRL,
 319                    control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 320
 321     qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
 322     qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR, entry);
 323     vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR);
 324     g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
 325 }
 326
 327 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
 328                                         QGuestAllocator *alloc, uint16_t entry)
 329 {
 330     uint16_t vector;
 331     uint32_t control;
 332     uint64_t off;
 333
 334     g_assert(d->pdev->msix_enabled);
 335     off = d->pdev->msix_table_off + (entry * 16);
 336
 337     g_assert_cmpint(entry, >=, 0);
 338     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 339     d->config_msix_entry = entry;
 340
 341     d->config_msix_data = 0x12345678;
 342     d->config_msix_addr = guest_alloc(alloc, 4);
 343
 344     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 345                    off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL);
 346     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 347                    off + PCI_MSIX_ENTRY_UPPER_ADDR,
 348                    (d->config_msix_addr >> 32) & ~0UL);
 349     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 350                    off + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
 351
 352     control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
 353                             off + PCI_MSIX_ENTRY_VECTOR_CTRL);
 354     qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
 355                    off + PCI_MSIX_ENTRY_VECTOR_CTRL,
 356                    control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 357
 358     qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR, entry);
 359     vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR);
 360     g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
 361 }
 362
 363 void qvirtio_pci_destructor(QOSGraphObject *obj)
 364 {
 365     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
 366     qvirtio_pci_device_disable(dev);
 367     g_free(dev->pdev);
 368 }
 369
 370 void qvirtio_pci_start_hw(QOSGraphObject *obj)
 371 {
 372     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
 373     qvirtio_pci_device_enable(dev);
 374     qvirtio_start_device(&dev->vdev);
 375 }
 376
 377 static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice *dev, QPCIDevice *pci_dev)
 378 {
 379     dev->pdev = pci_dev;
 380     dev->vdev.device_type = qpci_config_readw(pci_dev, PCI_SUBSYSTEM_ID);
 381
 382     dev->config_msix_entry = -1;
 383
 384     dev->vdev.bus = &qvirtio_pci;
 385     dev->vdev.big_endian = qvirtio_pci_is_big_endian(dev);
 386
 387     /* each virtio-xxx-pci device should override at least this function */
 388     dev->obj.get_driver = NULL;
 389     dev->obj.start_hw = qvirtio_pci_start_hw;
 390     dev->obj.destructor = qvirtio_pci_destructor;
 391 }
 392
 393 void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * addr)
 394 {
 395     QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
 396     g_assert_nonnull(pci_dev);
 397     qvirtio_pci_init_from_pcidev(dev, pci_dev);
 398 }
 399
 400 QVirtioPCIDevice *virtio_pci_new(QPCIBus *bus, QPCIAddress * addr)
 401 {
 402     QVirtioPCIDevice *dev;
 403     QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
 404     if (!pci_dev) {
 405         return NULL;
 406     }
 407
 408     dev = g_new0(QVirtioPCIDevice, 1);
 409     qvirtio_pci_init_from_pcidev(dev, pci_dev);
 410     dev->obj.free = g_free;
 411     return dev;
 412 }