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aio-win32: avoid out-of-bounds access to the events array
[qemu/ar7.git] / hw / sparc / sun4m.c
blob78f87a25701d09930881c444a7ab64169df66724
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/error-report.h"
26 #include "qemu/timer.h"
27 #include "hw/sparc/sun4m.h"
28 #include "hw/timer/m48t59.h"
29 #include "hw/sparc/sparc32_dma.h"
30 #include "hw/block/fdc.h"
31 #include "sysemu/sysemu.h"
32 #include "net/net.h"
33 #include "hw/boards.h"
34 #include "hw/nvram/openbios_firmware_abi.h"
35 #include "hw/scsi/esp.h"
36 #include "hw/i386/pc.h"
37 #include "hw/isa/isa.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/char/escc.h"
40 #include "hw/empty_slot.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "sysemu/blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * See for example: http://www.sunhelp.org/faq/sunref1.html
60 */
61
62 #define KERNEL_LOAD_ADDR 0x00004000
63 #define CMDLINE_ADDR 0x007ff000
64 #define INITRD_LOAD_ADDR 0x00800000
65 #define PROM_SIZE_MAX (1024 * 1024)
66 #define PROM_VADDR 0xffd00000
67 #define PROM_FILENAME "openbios-sparc32"
68 #define CFG_ADDR 0xd00000510ULL
69 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
70 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
71 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
72
73 #define MAX_CPUS 16
74 #define MAX_PILS 16
75 #define MAX_VSIMMS 4
76
77 #define ESCC_CLOCK 4915200
78
79 struct sun4m_hwdef {
80 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
81 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
82 hwaddr serial_base, fd_base;
83 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
84 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
85 hwaddr bpp_base, dbri_base, sx_base;
86 struct {
87 hwaddr reg_base, vram_base;
88 } vsimm[MAX_VSIMMS];
89 hwaddr ecc_base;
90 uint64_t max_mem;
91 const char * const default_cpu_model;
92 uint32_t ecc_version;
93 uint32_t iommu_version;
94 uint16_t machine_id;
95 uint8_t nvram_machine_id;
96 };
97
98 int DMA_get_channel_mode (int nchan)
99 {
100 return 0;
101 }
102 int DMA_read_memory (int nchan, void *buf, int pos, int size)
103 {
104 return 0;
105 }
106 int DMA_write_memory (int nchan, void *buf, int pos, int size)
107 {
108 return 0;
109 }
110 void DMA_hold_DREQ (int nchan) {}
111 void DMA_release_DREQ (int nchan) {}
112 void DMA_schedule(int nchan) {}
113
114 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
115 {
116 }
117
118 void DMA_register_channel (int nchan,
119 DMA_transfer_handler transfer_handler,
120 void *opaque)
121 {
122 }
123
124 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
125 {
126 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
127 return 0;
128 }
129
130 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
131 const char *cmdline, const char *boot_devices,
132 ram_addr_t RAM_size, uint32_t kernel_size,
133 int width, int height, int depth,
134 int nvram_machine_id, const char *arch)
135 {
136 unsigned int i;
137 uint32_t start, end;
138 uint8_t image[0x1ff0];
139 struct OpenBIOS_nvpart_v1 *part_header;
140
141 memset(image, '\0', sizeof(image));
142
143 start = 0;
144
145 // OpenBIOS nvram variables
146 // Variable partition
147 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
148 part_header->signature = OPENBIOS_PART_SYSTEM;
149 pstrcpy(part_header->name, sizeof(part_header->name), "system");
150
151 end = start + sizeof(struct OpenBIOS_nvpart_v1);
152 for (i = 0; i < nb_prom_envs; i++)
153 end = OpenBIOS_set_var(image, end, prom_envs[i]);
154
155 // End marker
156 image[end++] = '\0';
157
158 end = start + ((end - start + 15) & ~15);
159 OpenBIOS_finish_partition(part_header, end - start);
160
161 // free partition
162 start = end;
163 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
164 part_header->signature = OPENBIOS_PART_FREE;
165 pstrcpy(part_header->name, sizeof(part_header->name), "free");
166
167 end = 0x1fd0;
168 OpenBIOS_finish_partition(part_header, end - start);
169
170 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
171 nvram_machine_id);
172
173 for (i = 0; i < sizeof(image); i++)
174 m48t59_write(nvram, i, image[i]);
175 }
176
177 static DeviceState *slavio_intctl;
178
179 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
180 {
181 if (slavio_intctl)
182 slavio_pic_info(mon, slavio_intctl);
183 }
184
185 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
186 {
187 if (slavio_intctl)
188 slavio_irq_info(mon, slavio_intctl);
189 }
190
191 void cpu_check_irqs(CPUSPARCState *env)
192 {
193 CPUState *cs;
194
195 if (env->pil_in && (env->interrupt_index == 0 ||
196 (env->interrupt_index & ~15) == TT_EXTINT)) {
197 unsigned int i;
198
199 for (i = 15; i > 0; i--) {
200 if (env->pil_in & (1 << i)) {
201 int old_interrupt = env->interrupt_index;
202
203 env->interrupt_index = TT_EXTINT | i;
204 if (old_interrupt != env->interrupt_index) {
205 cs = CPU(sparc_env_get_cpu(env));
206 trace_sun4m_cpu_interrupt(i);
207 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
208 }
209 break;
210 }
211 }
212 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
213 cs = CPU(sparc_env_get_cpu(env));
214 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
215 env->interrupt_index = 0;
216 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
217 }
218 }
219
220 static void cpu_kick_irq(SPARCCPU *cpu)
221 {
222 CPUSPARCState *env = &cpu->env;
223 CPUState *cs = CPU(cpu);
224
225 cs->halted = 0;
226 cpu_check_irqs(env);
227 qemu_cpu_kick(cs);
228 }
229
230 static void cpu_set_irq(void *opaque, int irq, int level)
231 {
232 SPARCCPU *cpu = opaque;
233 CPUSPARCState *env = &cpu->env;
234
235 if (level) {
236 trace_sun4m_cpu_set_irq_raise(irq);
237 env->pil_in |= 1 << irq;
238 cpu_kick_irq(cpu);
239 } else {
240 trace_sun4m_cpu_set_irq_lower(irq);
241 env->pil_in &= ~(1 << irq);
242 cpu_check_irqs(env);
243 }
244 }
245
246 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
247 {
248 }
249
250 static void main_cpu_reset(void *opaque)
251 {
252 SPARCCPU *cpu = opaque;
253 CPUState *cs = CPU(cpu);
254
255 cpu_reset(cs);
256 cs->halted = 0;
257 }
258
259 static void secondary_cpu_reset(void *opaque)
260 {
261 SPARCCPU *cpu = opaque;
262 CPUState *cs = CPU(cpu);
263
264 cpu_reset(cs);
265 cs->halted = 1;
266 }
267
268 static void cpu_halt_signal(void *opaque, int irq, int level)
269 {
270 if (level && current_cpu) {
271 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
272 }
273 }
274
275 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
276 {
277 return addr - 0xf0000000ULL;
278 }
279
280 static unsigned long sun4m_load_kernel(const char *kernel_filename,
281 const char *initrd_filename,
282 ram_addr_t RAM_size)
283 {
284 int linux_boot;
285 unsigned int i;
286 long initrd_size, kernel_size;
287 uint8_t *ptr;
288
289 linux_boot = (kernel_filename != NULL);
290
291 kernel_size = 0;
292 if (linux_boot) {
293 int bswap_needed;
294
295 #ifdef BSWAP_NEEDED
296 bswap_needed = 1;
297 #else
298 bswap_needed = 0;
299 #endif
300 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
301 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
302 if (kernel_size < 0)
303 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
304 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
305 TARGET_PAGE_SIZE);
306 if (kernel_size < 0)
307 kernel_size = load_image_targphys(kernel_filename,
308 KERNEL_LOAD_ADDR,
309 RAM_size - KERNEL_LOAD_ADDR);
310 if (kernel_size < 0) {
311 fprintf(stderr, "qemu: could not load kernel '%s'\n",
312 kernel_filename);
313 exit(1);
314 }
315
316 /* load initrd */
317 initrd_size = 0;
318 if (initrd_filename) {
319 initrd_size = load_image_targphys(initrd_filename,
320 INITRD_LOAD_ADDR,
321 RAM_size - INITRD_LOAD_ADDR);
322 if (initrd_size < 0) {
323 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
324 initrd_filename);
325 exit(1);
326 }
327 }
328 if (initrd_size > 0) {
329 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
330 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
331 if (ldl_p(ptr) == 0x48647253) { // HdrS
332 stl_p(ptr + 16, INITRD_LOAD_ADDR);
333 stl_p(ptr + 20, initrd_size);
334 break;
335 }
336 }
337 }
338 }
339 return kernel_size;
340 }
341
342 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
343 {
344 DeviceState *dev;
345 SysBusDevice *s;
346
347 dev = qdev_create(NULL, "iommu");
348 qdev_prop_set_uint32(dev, "version", version);
349 qdev_init_nofail(dev);
350 s = SYS_BUS_DEVICE(dev);
351 sysbus_connect_irq(s, 0, irq);
352 sysbus_mmio_map(s, 0, addr);
353
354 return s;
355 }
356
357 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
358 void *iommu, qemu_irq *dev_irq, int is_ledma)
359 {
360 DeviceState *dev;
361 SysBusDevice *s;
362
363 dev = qdev_create(NULL, "sparc32_dma");
364 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
365 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
366 qdev_init_nofail(dev);
367 s = SYS_BUS_DEVICE(dev);
368 sysbus_connect_irq(s, 0, parent_irq);
369 *dev_irq = qdev_get_gpio_in(dev, 0);
370 sysbus_mmio_map(s, 0, daddr);
371
372 return s;
373 }
374
375 static void lance_init(NICInfo *nd, hwaddr leaddr,
376 void *dma_opaque, qemu_irq irq)
377 {
378 DeviceState *dev;
379 SysBusDevice *s;
380 qemu_irq reset;
381
382 qemu_check_nic_model(&nd_table[0], "lance");
383
384 dev = qdev_create(NULL, "lance");
385 qdev_set_nic_properties(dev, nd);
386 qdev_prop_set_ptr(dev, "dma", dma_opaque);
387 qdev_init_nofail(dev);
388 s = SYS_BUS_DEVICE(dev);
389 sysbus_mmio_map(s, 0, leaddr);
390 sysbus_connect_irq(s, 0, irq);
391 reset = qdev_get_gpio_in(dev, 0);
392 qdev_connect_gpio_out(dma_opaque, 0, reset);
393 }
394
395 static DeviceState *slavio_intctl_init(hwaddr addr,
396 hwaddr addrg,
397 qemu_irq **parent_irq)
398 {
399 DeviceState *dev;
400 SysBusDevice *s;
401 unsigned int i, j;
402
403 dev = qdev_create(NULL, "slavio_intctl");
404 qdev_init_nofail(dev);
405
406 s = SYS_BUS_DEVICE(dev);
407
408 for (i = 0; i < MAX_CPUS; i++) {
409 for (j = 0; j < MAX_PILS; j++) {
410 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
411 }
412 }
413 sysbus_mmio_map(s, 0, addrg);
414 for (i = 0; i < MAX_CPUS; i++) {
415 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
416 }
417
418 return dev;
419 }
420
421 #define SYS_TIMER_OFFSET 0x10000ULL
422 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
423
424 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
425 qemu_irq *cpu_irqs, unsigned int num_cpus)
426 {
427 DeviceState *dev;
428 SysBusDevice *s;
429 unsigned int i;
430
431 dev = qdev_create(NULL, "slavio_timer");
432 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
433 qdev_init_nofail(dev);
434 s = SYS_BUS_DEVICE(dev);
435 sysbus_connect_irq(s, 0, master_irq);
436 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
437
438 for (i = 0; i < MAX_CPUS; i++) {
439 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
440 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
441 }
442 }
443
444 static qemu_irq slavio_system_powerdown;
445
446 static void slavio_powerdown_req(Notifier *n, void *opaque)
447 {
448 qemu_irq_raise(slavio_system_powerdown);
449 }
450
451 static Notifier slavio_system_powerdown_notifier = {
452 .notify = slavio_powerdown_req
453 };
454
455 #define MISC_LEDS 0x01600000
456 #define MISC_CFG 0x01800000
457 #define MISC_DIAG 0x01a00000
458 #define MISC_MDM 0x01b00000
459 #define MISC_SYS 0x01f00000
460
461 static void slavio_misc_init(hwaddr base,
462 hwaddr aux1_base,
463 hwaddr aux2_base, qemu_irq irq,
464 qemu_irq fdc_tc)
465 {
466 DeviceState *dev;
467 SysBusDevice *s;
468
469 dev = qdev_create(NULL, "slavio_misc");
470 qdev_init_nofail(dev);
471 s = SYS_BUS_DEVICE(dev);
472 if (base) {
473 /* 8 bit registers */
474 /* Slavio control */
475 sysbus_mmio_map(s, 0, base + MISC_CFG);
476 /* Diagnostics */
477 sysbus_mmio_map(s, 1, base + MISC_DIAG);
478 /* Modem control */
479 sysbus_mmio_map(s, 2, base + MISC_MDM);
480 /* 16 bit registers */
481 /* ss600mp diag LEDs */
482 sysbus_mmio_map(s, 3, base + MISC_LEDS);
483 /* 32 bit registers */
484 /* System control */
485 sysbus_mmio_map(s, 4, base + MISC_SYS);
486 }
487 if (aux1_base) {
488 /* AUX 1 (Misc System Functions) */
489 sysbus_mmio_map(s, 5, aux1_base);
490 }
491 if (aux2_base) {
492 /* AUX 2 (Software Powerdown Control) */
493 sysbus_mmio_map(s, 6, aux2_base);
494 }
495 sysbus_connect_irq(s, 0, irq);
496 sysbus_connect_irq(s, 1, fdc_tc);
497 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
498 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
499 }
500
501 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
502 {
503 DeviceState *dev;
504 SysBusDevice *s;
505
506 dev = qdev_create(NULL, "eccmemctl");
507 qdev_prop_set_uint32(dev, "version", version);
508 qdev_init_nofail(dev);
509 s = SYS_BUS_DEVICE(dev);
510 sysbus_connect_irq(s, 0, irq);
511 sysbus_mmio_map(s, 0, base);
512 if (version == 0) { // SS-600MP only
513 sysbus_mmio_map(s, 1, base + 0x1000);
514 }
515 }
516
517 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
518 {
519 DeviceState *dev;
520 SysBusDevice *s;
521
522 dev = qdev_create(NULL, "apc");
523 qdev_init_nofail(dev);
524 s = SYS_BUS_DEVICE(dev);
525 /* Power management (APC) XXX: not a Slavio device */
526 sysbus_mmio_map(s, 0, power_base);
527 sysbus_connect_irq(s, 0, cpu_halt);
528 }
529
530 static void tcx_init(hwaddr addr, int vram_size, int width,
531 int height, int depth)
532 {
533 DeviceState *dev;
534 SysBusDevice *s;
535
536 dev = qdev_create(NULL, "SUNW,tcx");
537 qdev_prop_set_uint32(dev, "vram_size", vram_size);
538 qdev_prop_set_uint16(dev, "width", width);
539 qdev_prop_set_uint16(dev, "height", height);
540 qdev_prop_set_uint16(dev, "depth", depth);
541 qdev_prop_set_uint64(dev, "prom_addr", addr);
542 qdev_init_nofail(dev);
543 s = SYS_BUS_DEVICE(dev);
544 /* FCode ROM */
545 sysbus_mmio_map(s, 0, addr);
546 /* DAC */
547 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
548 /* TEC (dummy) */
549 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
550 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
551 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
552 /* 8-bit plane */
553 sysbus_mmio_map(s, 4, addr + 0x00800000ULL);
554 if (depth == 24) {
555 /* 24-bit plane */
556 sysbus_mmio_map(s, 5, addr + 0x02000000ULL);
557 /* Control plane */
558 sysbus_mmio_map(s, 6, addr + 0x0a000000ULL);
559 } else {
560 /* THC 8 bit (dummy) */
561 sysbus_mmio_map(s, 5, addr + 0x00300000ULL);
562 }
563 }
564
565 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
566 int height, int depth)
567 {
568 DeviceState *dev;
569 SysBusDevice *s;
570
571 dev = qdev_create(NULL, "cgthree");
572 qdev_prop_set_uint32(dev, "vram-size", vram_size);
573 qdev_prop_set_uint16(dev, "width", width);
574 qdev_prop_set_uint16(dev, "height", height);
575 qdev_prop_set_uint16(dev, "depth", depth);
576 qdev_prop_set_uint64(dev, "prom-addr", addr);
577 qdev_init_nofail(dev);
578 s = SYS_BUS_DEVICE(dev);
579
580 /* FCode ROM */
581 sysbus_mmio_map(s, 0, addr);
582 /* DAC */
583 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
584 /* 8-bit plane */
585 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
586
587 sysbus_connect_irq(s, 0, irq);
588 }
589
590 /* NCR89C100/MACIO Internal ID register */
591
592 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
593
594 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
595
596 static void idreg_init(hwaddr addr)
597 {
598 DeviceState *dev;
599 SysBusDevice *s;
600
601 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
602 qdev_init_nofail(dev);
603 s = SYS_BUS_DEVICE(dev);
604
605 sysbus_mmio_map(s, 0, addr);
606 cpu_physical_memory_write_rom(&address_space_memory,
607 addr, idreg_data, sizeof(idreg_data));
608 }
609
610 #define MACIO_ID_REGISTER(obj) \
611 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
612
613 typedef struct IDRegState {
614 SysBusDevice parent_obj;
615
616 MemoryRegion mem;
617 } IDRegState;
618
619 static int idreg_init1(SysBusDevice *dev)
620 {
621 IDRegState *s = MACIO_ID_REGISTER(dev);
622
623 memory_region_init_ram(&s->mem, OBJECT(s),
624 "sun4m.idreg", sizeof(idreg_data), &error_abort);
625 vmstate_register_ram_global(&s->mem);
626 memory_region_set_readonly(&s->mem, true);
627 sysbus_init_mmio(dev, &s->mem);
628 return 0;
629 }
630
631 static void idreg_class_init(ObjectClass *klass, void *data)
632 {
633 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
634
635 k->init = idreg_init1;
636 }
637
638 static const TypeInfo idreg_info = {
639 .name = TYPE_MACIO_ID_REGISTER,
640 .parent = TYPE_SYS_BUS_DEVICE,
641 .instance_size = sizeof(IDRegState),
642 .class_init = idreg_class_init,
643 };
644
645 #define TYPE_TCX_AFX "tcx_afx"
646 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
647
648 typedef struct AFXState {
649 SysBusDevice parent_obj;
650
651 MemoryRegion mem;
652 } AFXState;
653
654 /* SS-5 TCX AFX register */
655 static void afx_init(hwaddr addr)
656 {
657 DeviceState *dev;
658 SysBusDevice *s;
659
660 dev = qdev_create(NULL, TYPE_TCX_AFX);
661 qdev_init_nofail(dev);
662 s = SYS_BUS_DEVICE(dev);
663
664 sysbus_mmio_map(s, 0, addr);
665 }
666
667 static int afx_init1(SysBusDevice *dev)
668 {
669 AFXState *s = TCX_AFX(dev);
670
671 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_abort);
672 vmstate_register_ram_global(&s->mem);
673 sysbus_init_mmio(dev, &s->mem);
674 return 0;
675 }
676
677 static void afx_class_init(ObjectClass *klass, void *data)
678 {
679 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
680
681 k->init = afx_init1;
682 }
683
684 static const TypeInfo afx_info = {
685 .name = TYPE_TCX_AFX,
686 .parent = TYPE_SYS_BUS_DEVICE,
687 .instance_size = sizeof(AFXState),
688 .class_init = afx_class_init,
689 };
690
691 #define TYPE_OPENPROM "openprom"
692 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
693
694 typedef struct PROMState {
695 SysBusDevice parent_obj;
696
697 MemoryRegion prom;
698 } PROMState;
699
700 /* Boot PROM (OpenBIOS) */
701 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
702 {
703 hwaddr *base_addr = (hwaddr *)opaque;
704 return addr + *base_addr - PROM_VADDR;
705 }
706
707 static void prom_init(hwaddr addr, const char *bios_name)
708 {
709 DeviceState *dev;
710 SysBusDevice *s;
711 char *filename;
712 int ret;
713
714 dev = qdev_create(NULL, TYPE_OPENPROM);
715 qdev_init_nofail(dev);
716 s = SYS_BUS_DEVICE(dev);
717
718 sysbus_mmio_map(s, 0, addr);
719
720 /* load boot prom */
721 if (bios_name == NULL) {
722 bios_name = PROM_FILENAME;
723 }
724 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
725 if (filename) {
726 ret = load_elf(filename, translate_prom_address, &addr, NULL,
727 NULL, NULL, 1, ELF_MACHINE, 0);
728 if (ret < 0 || ret > PROM_SIZE_MAX) {
729 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
730 }
731 g_free(filename);
732 } else {
733 ret = -1;
734 }
735 if (ret < 0 || ret > PROM_SIZE_MAX) {
736 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
737 exit(1);
738 }
739 }
740
741 static int prom_init1(SysBusDevice *dev)
742 {
743 PROMState *s = OPENPROM(dev);
744
745 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
746 &error_abort);
747 vmstate_register_ram_global(&s->prom);
748 memory_region_set_readonly(&s->prom, true);
749 sysbus_init_mmio(dev, &s->prom);
750 return 0;
751 }
752
753 static Property prom_properties[] = {
754 {/* end of property list */},
755 };
756
757 static void prom_class_init(ObjectClass *klass, void *data)
758 {
759 DeviceClass *dc = DEVICE_CLASS(klass);
760 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
761
762 k->init = prom_init1;
763 dc->props = prom_properties;
764 }
765
766 static const TypeInfo prom_info = {
767 .name = TYPE_OPENPROM,
768 .parent = TYPE_SYS_BUS_DEVICE,
769 .instance_size = sizeof(PROMState),
770 .class_init = prom_class_init,
771 };
772
773 #define TYPE_SUN4M_MEMORY "memory"
774 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
775
776 typedef struct RamDevice {
777 SysBusDevice parent_obj;
778
779 MemoryRegion ram;
780 uint64_t size;
781 } RamDevice;
782
783 /* System RAM */
784 static int ram_init1(SysBusDevice *dev)
785 {
786 RamDevice *d = SUN4M_RAM(dev);
787
788 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size,
789 &error_abort);
790 vmstate_register_ram_global(&d->ram);
791 sysbus_init_mmio(dev, &d->ram);
792 return 0;
793 }
794
795 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
796 uint64_t max_mem)
797 {
798 DeviceState *dev;
799 SysBusDevice *s;
800 RamDevice *d;
801
802 /* allocate RAM */
803 if ((uint64_t)RAM_size > max_mem) {
804 fprintf(stderr,
805 "qemu: Too much memory for this machine: %d, maximum %d\n",
806 (unsigned int)(RAM_size / (1024 * 1024)),
807 (unsigned int)(max_mem / (1024 * 1024)));
808 exit(1);
809 }
810 dev = qdev_create(NULL, "memory");
811 s = SYS_BUS_DEVICE(dev);
812
813 d = SUN4M_RAM(dev);
814 d->size = RAM_size;
815 qdev_init_nofail(dev);
816
817 sysbus_mmio_map(s, 0, addr);
818 }
819
820 static Property ram_properties[] = {
821 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
822 DEFINE_PROP_END_OF_LIST(),
823 };
824
825 static void ram_class_init(ObjectClass *klass, void *data)
826 {
827 DeviceClass *dc = DEVICE_CLASS(klass);
828 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
829
830 k->init = ram_init1;
831 dc->props = ram_properties;
832 }
833
834 static const TypeInfo ram_info = {
835 .name = TYPE_SUN4M_MEMORY,
836 .parent = TYPE_SYS_BUS_DEVICE,
837 .instance_size = sizeof(RamDevice),
838 .class_init = ram_class_init,
839 };
840
841 static void cpu_devinit(const char *cpu_model, unsigned int id,
842 uint64_t prom_addr, qemu_irq **cpu_irqs)
843 {
844 CPUState *cs;
845 SPARCCPU *cpu;
846 CPUSPARCState *env;
847
848 cpu = cpu_sparc_init(cpu_model);
849 if (cpu == NULL) {
850 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
851 exit(1);
852 }
853 env = &cpu->env;
854
855 cpu_sparc_set_id(env, id);
856 if (id == 0) {
857 qemu_register_reset(main_cpu_reset, cpu);
858 } else {
859 qemu_register_reset(secondary_cpu_reset, cpu);
860 cs = CPU(cpu);
861 cs->halted = 1;
862 }
863 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
864 env->prom_addr = prom_addr;
865 }
866
867 static void dummy_fdc_tc(void *opaque, int irq, int level)
868 {
869 }
870
871 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
872 MachineState *machine)
873 {
874 const char *cpu_model = machine->cpu_model;
875 unsigned int i;
876 void *iommu, *espdma, *ledma, *nvram;
877 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
878 espdma_irq, ledma_irq;
879 qemu_irq esp_reset, dma_enable;
880 qemu_irq fdc_tc;
881 qemu_irq *cpu_halt;
882 unsigned long kernel_size;
883 DriveInfo *fd[MAX_FD];
884 FWCfgState *fw_cfg;
885 unsigned int num_vsimms;
886
887 /* init CPUs */
888 if (!cpu_model)
889 cpu_model = hwdef->default_cpu_model;
890
891 for(i = 0; i < smp_cpus; i++) {
892 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
893 }
894
895 for (i = smp_cpus; i < MAX_CPUS; i++)
896 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
897
898
899 /* set up devices */
900 ram_init(0, machine->ram_size, hwdef->max_mem);
901 /* models without ECC don't trap when missing ram is accessed */
902 if (!hwdef->ecc_base) {
903 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
904 }
905
906 prom_init(hwdef->slavio_base, bios_name);
907
908 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
909 hwdef->intctl_base + 0x10000ULL,
910 cpu_irqs);
911
912 for (i = 0; i < 32; i++) {
913 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
914 }
915 for (i = 0; i < MAX_CPUS; i++) {
916 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
917 }
918
919 if (hwdef->idreg_base) {
920 idreg_init(hwdef->idreg_base);
921 }
922
923 if (hwdef->afx_base) {
924 afx_init(hwdef->afx_base);
925 }
926
927 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
928 slavio_irq[30]);
929
930 if (hwdef->iommu_pad_base) {
931 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
932 Software shouldn't use aliased addresses, neither should it crash
933 when does. Using empty_slot instead of aliasing can help with
934 debugging such accesses */
935 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
936 }
937
938 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
939 iommu, &espdma_irq, 0);
940
941 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
942 slavio_irq[16], iommu, &ledma_irq, 1);
943
944 if (graphic_depth != 8 && graphic_depth != 24) {
945 error_report("Unsupported depth: %d", graphic_depth);
946 exit (1);
947 }
948 num_vsimms = 0;
949 if (num_vsimms == 0) {
950 if (vga_interface_type == VGA_CG3) {
951 if (graphic_depth != 8) {
952 error_report("Unsupported depth: %d", graphic_depth);
953 exit(1);
954 }
955
956 if (!(graphic_width == 1024 && graphic_height == 768) &&
957 !(graphic_width == 1152 && graphic_height == 900)) {
958 error_report("Unsupported resolution: %d x %d", graphic_width,
959 graphic_height);
960 exit(1);
961 }
962
963 /* sbus irq 5 */
964 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
965 graphic_width, graphic_height, graphic_depth);
966 } else {
967 /* If no display specified, default to TCX */
968 if (graphic_depth != 8 && graphic_depth != 24) {
969 error_report("Unsupported depth: %d", graphic_depth);
970 exit(1);
971 }
972
973 if (!(graphic_width == 1024 && graphic_height == 768)) {
974 error_report("Unsupported resolution: %d x %d",
975 graphic_width, graphic_height);
976 exit(1);
977 }
978
979 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
980 graphic_depth);
981 }
982 }
983
984 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
985 /* vsimm registers probed by OBP */
986 if (hwdef->vsimm[i].reg_base) {
987 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
988 }
989 }
990
991 if (hwdef->sx_base) {
992 empty_slot_init(hwdef->sx_base, 0x2000);
993 }
994
995 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
996
997 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
998
999 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1000
1001 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1002 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1003 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1004 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1005 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1006 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1007
1008 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1009 if (hwdef->apc_base) {
1010 apc_init(hwdef->apc_base, cpu_halt[0]);
1011 }
1012
1013 if (hwdef->fd_base) {
1014 /* there is zero or one floppy drive */
1015 memset(fd, 0, sizeof(fd));
1016 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1017 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1018 &fdc_tc);
1019 } else {
1020 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1021 }
1022
1023 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1024 slavio_irq[30], fdc_tc);
1025
1026 if (drive_get_max_bus(IF_SCSI) > 0) {
1027 fprintf(stderr, "qemu: too many SCSI bus\n");
1028 exit(1);
1029 }
1030
1031 esp_init(hwdef->esp_base, 2,
1032 espdma_memory_read, espdma_memory_write,
1033 espdma, espdma_irq, &esp_reset, &dma_enable);
1034
1035 qdev_connect_gpio_out(espdma, 0, esp_reset);
1036 qdev_connect_gpio_out(espdma, 1, dma_enable);
1037
1038 if (hwdef->cs_base) {
1039 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1040 slavio_irq[5]);
1041 }
1042
1043 if (hwdef->dbri_base) {
1044 /* ISDN chip with attached CS4215 audio codec */
1045 /* prom space */
1046 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1047 /* reg space */
1048 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1049 }
1050
1051 if (hwdef->bpp_base) {
1052 /* parallel port */
1053 empty_slot_init(hwdef->bpp_base, 0x20);
1054 }
1055
1056 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1057 machine->initrd_filename,
1058 machine->ram_size);
1059
1060 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1061 machine->boot_order, machine->ram_size, kernel_size,
1062 graphic_width, graphic_height, graphic_depth,
1063 hwdef->nvram_machine_id, "Sun4m");
1064
1065 if (hwdef->ecc_base)
1066 ecc_init(hwdef->ecc_base, slavio_irq[28],
1067 hwdef->ecc_version);
1068
1069 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1070 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1071 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1072 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1073 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1077 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1079 if (machine->kernel_cmdline) {
1080 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1081 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1082 machine->kernel_cmdline);
1083 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1084 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1085 strlen(machine->kernel_cmdline) + 1);
1086 } else {
1087 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1088 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1089 }
1090 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1091 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1092 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1093 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1094 }
1095
1096 enum {
1097 ss5_id = 32,
1098 vger_id,
1099 lx_id,
1100 ss4_id,
1101 scls_id,
1102 sbook_id,
1103 ss10_id = 64,
1104 ss20_id,
1105 ss600mp_id,
1106 };
1107
1108 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1109 /* SS-5 */
1110 {
1111 .iommu_base = 0x10000000,
1112 .iommu_pad_base = 0x10004000,
1113 .iommu_pad_len = 0x0fffb000,
1114 .tcx_base = 0x50000000,
1115 .cs_base = 0x6c000000,
1116 .slavio_base = 0x70000000,
1117 .ms_kb_base = 0x71000000,
1118 .serial_base = 0x71100000,
1119 .nvram_base = 0x71200000,
1120 .fd_base = 0x71400000,
1121 .counter_base = 0x71d00000,
1122 .intctl_base = 0x71e00000,
1123 .idreg_base = 0x78000000,
1124 .dma_base = 0x78400000,
1125 .esp_base = 0x78800000,
1126 .le_base = 0x78c00000,
1127 .apc_base = 0x6a000000,
1128 .afx_base = 0x6e000000,
1129 .aux1_base = 0x71900000,
1130 .aux2_base = 0x71910000,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = ss5_id,
1133 .iommu_version = 0x05000000,
1134 .max_mem = 0x10000000,
1135 .default_cpu_model = "Fujitsu MB86904",
1136 },
1137 /* SS-10 */
1138 {
1139 .iommu_base = 0xfe0000000ULL,
1140 .tcx_base = 0xe20000000ULL,
1141 .slavio_base = 0xff0000000ULL,
1142 .ms_kb_base = 0xff1000000ULL,
1143 .serial_base = 0xff1100000ULL,
1144 .nvram_base = 0xff1200000ULL,
1145 .fd_base = 0xff1700000ULL,
1146 .counter_base = 0xff1300000ULL,
1147 .intctl_base = 0xff1400000ULL,
1148 .idreg_base = 0xef0000000ULL,
1149 .dma_base = 0xef0400000ULL,
1150 .esp_base = 0xef0800000ULL,
1151 .le_base = 0xef0c00000ULL,
1152 .apc_base = 0xefa000000ULL, // XXX should not exist
1153 .aux1_base = 0xff1800000ULL,
1154 .aux2_base = 0xff1a01000ULL,
1155 .ecc_base = 0xf00000000ULL,
1156 .ecc_version = 0x10000000, // version 0, implementation 1
1157 .nvram_machine_id = 0x72,
1158 .machine_id = ss10_id,
1159 .iommu_version = 0x03000000,
1160 .max_mem = 0xf00000000ULL,
1161 .default_cpu_model = "TI SuperSparc II",
1162 },
1163 /* SS-600MP */
1164 {
1165 .iommu_base = 0xfe0000000ULL,
1166 .tcx_base = 0xe20000000ULL,
1167 .slavio_base = 0xff0000000ULL,
1168 .ms_kb_base = 0xff1000000ULL,
1169 .serial_base = 0xff1100000ULL,
1170 .nvram_base = 0xff1200000ULL,
1171 .counter_base = 0xff1300000ULL,
1172 .intctl_base = 0xff1400000ULL,
1173 .dma_base = 0xef0081000ULL,
1174 .esp_base = 0xef0080000ULL,
1175 .le_base = 0xef0060000ULL,
1176 .apc_base = 0xefa000000ULL, // XXX should not exist
1177 .aux1_base = 0xff1800000ULL,
1178 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1179 .ecc_base = 0xf00000000ULL,
1180 .ecc_version = 0x00000000, // version 0, implementation 0
1181 .nvram_machine_id = 0x71,
1182 .machine_id = ss600mp_id,
1183 .iommu_version = 0x01000000,
1184 .max_mem = 0xf00000000ULL,
1185 .default_cpu_model = "TI SuperSparc II",
1186 },
1187 /* SS-20 */
1188 {
1189 .iommu_base = 0xfe0000000ULL,
1190 .tcx_base = 0xe20000000ULL,
1191 .slavio_base = 0xff0000000ULL,
1192 .ms_kb_base = 0xff1000000ULL,
1193 .serial_base = 0xff1100000ULL,
1194 .nvram_base = 0xff1200000ULL,
1195 .fd_base = 0xff1700000ULL,
1196 .counter_base = 0xff1300000ULL,
1197 .intctl_base = 0xff1400000ULL,
1198 .idreg_base = 0xef0000000ULL,
1199 .dma_base = 0xef0400000ULL,
1200 .esp_base = 0xef0800000ULL,
1201 .le_base = 0xef0c00000ULL,
1202 .bpp_base = 0xef4800000ULL,
1203 .apc_base = 0xefa000000ULL, // XXX should not exist
1204 .aux1_base = 0xff1800000ULL,
1205 .aux2_base = 0xff1a01000ULL,
1206 .dbri_base = 0xee0000000ULL,
1207 .sx_base = 0xf80000000ULL,
1208 .vsimm = {
1209 {
1210 .reg_base = 0x9c000000ULL,
1211 .vram_base = 0xfc000000ULL
1212 }, {
1213 .reg_base = 0x90000000ULL,
1214 .vram_base = 0xf0000000ULL
1215 }, {
1216 .reg_base = 0x94000000ULL
1217 }, {
1218 .reg_base = 0x98000000ULL
1219 }
1220 },
1221 .ecc_base = 0xf00000000ULL,
1222 .ecc_version = 0x20000000, // version 0, implementation 2
1223 .nvram_machine_id = 0x72,
1224 .machine_id = ss20_id,
1225 .iommu_version = 0x13000000,
1226 .max_mem = 0xf00000000ULL,
1227 .default_cpu_model = "TI SuperSparc II",
1228 },
1229 /* Voyager */
1230 {
1231 .iommu_base = 0x10000000,
1232 .tcx_base = 0x50000000,
1233 .slavio_base = 0x70000000,
1234 .ms_kb_base = 0x71000000,
1235 .serial_base = 0x71100000,
1236 .nvram_base = 0x71200000,
1237 .fd_base = 0x71400000,
1238 .counter_base = 0x71d00000,
1239 .intctl_base = 0x71e00000,
1240 .idreg_base = 0x78000000,
1241 .dma_base = 0x78400000,
1242 .esp_base = 0x78800000,
1243 .le_base = 0x78c00000,
1244 .apc_base = 0x71300000, // pmc
1245 .aux1_base = 0x71900000,
1246 .aux2_base = 0x71910000,
1247 .nvram_machine_id = 0x80,
1248 .machine_id = vger_id,
1249 .iommu_version = 0x05000000,
1250 .max_mem = 0x10000000,
1251 .default_cpu_model = "Fujitsu MB86904",
1252 },
1253 /* LX */
1254 {
1255 .iommu_base = 0x10000000,
1256 .iommu_pad_base = 0x10004000,
1257 .iommu_pad_len = 0x0fffb000,
1258 .tcx_base = 0x50000000,
1259 .slavio_base = 0x70000000,
1260 .ms_kb_base = 0x71000000,
1261 .serial_base = 0x71100000,
1262 .nvram_base = 0x71200000,
1263 .fd_base = 0x71400000,
1264 .counter_base = 0x71d00000,
1265 .intctl_base = 0x71e00000,
1266 .idreg_base = 0x78000000,
1267 .dma_base = 0x78400000,
1268 .esp_base = 0x78800000,
1269 .le_base = 0x78c00000,
1270 .aux1_base = 0x71900000,
1271 .aux2_base = 0x71910000,
1272 .nvram_machine_id = 0x80,
1273 .machine_id = lx_id,
1274 .iommu_version = 0x04000000,
1275 .max_mem = 0x10000000,
1276 .default_cpu_model = "TI MicroSparc I",
1277 },
1278 /* SS-4 */
1279 {
1280 .iommu_base = 0x10000000,
1281 .tcx_base = 0x50000000,
1282 .cs_base = 0x6c000000,
1283 .slavio_base = 0x70000000,
1284 .ms_kb_base = 0x71000000,
1285 .serial_base = 0x71100000,
1286 .nvram_base = 0x71200000,
1287 .fd_base = 0x71400000,
1288 .counter_base = 0x71d00000,
1289 .intctl_base = 0x71e00000,
1290 .idreg_base = 0x78000000,
1291 .dma_base = 0x78400000,
1292 .esp_base = 0x78800000,
1293 .le_base = 0x78c00000,
1294 .apc_base = 0x6a000000,
1295 .aux1_base = 0x71900000,
1296 .aux2_base = 0x71910000,
1297 .nvram_machine_id = 0x80,
1298 .machine_id = ss4_id,
1299 .iommu_version = 0x05000000,
1300 .max_mem = 0x10000000,
1301 .default_cpu_model = "Fujitsu MB86904",
1302 },
1303 /* SPARCClassic */
1304 {
1305 .iommu_base = 0x10000000,
1306 .tcx_base = 0x50000000,
1307 .slavio_base = 0x70000000,
1308 .ms_kb_base = 0x71000000,
1309 .serial_base = 0x71100000,
1310 .nvram_base = 0x71200000,
1311 .fd_base = 0x71400000,
1312 .counter_base = 0x71d00000,
1313 .intctl_base = 0x71e00000,
1314 .idreg_base = 0x78000000,
1315 .dma_base = 0x78400000,
1316 .esp_base = 0x78800000,
1317 .le_base = 0x78c00000,
1318 .apc_base = 0x6a000000,
1319 .aux1_base = 0x71900000,
1320 .aux2_base = 0x71910000,
1321 .nvram_machine_id = 0x80,
1322 .machine_id = scls_id,
1323 .iommu_version = 0x05000000,
1324 .max_mem = 0x10000000,
1325 .default_cpu_model = "TI MicroSparc I",
1326 },
1327 /* SPARCbook */
1328 {
1329 .iommu_base = 0x10000000,
1330 .tcx_base = 0x50000000, // XXX
1331 .slavio_base = 0x70000000,
1332 .ms_kb_base = 0x71000000,
1333 .serial_base = 0x71100000,
1334 .nvram_base = 0x71200000,
1335 .fd_base = 0x71400000,
1336 .counter_base = 0x71d00000,
1337 .intctl_base = 0x71e00000,
1338 .idreg_base = 0x78000000,
1339 .dma_base = 0x78400000,
1340 .esp_base = 0x78800000,
1341 .le_base = 0x78c00000,
1342 .apc_base = 0x6a000000,
1343 .aux1_base = 0x71900000,
1344 .aux2_base = 0x71910000,
1345 .nvram_machine_id = 0x80,
1346 .machine_id = sbook_id,
1347 .iommu_version = 0x05000000,
1348 .max_mem = 0x10000000,
1349 .default_cpu_model = "TI MicroSparc I",
1350 },
1351 };
1352
1353 /* SPARCstation 5 hardware initialisation */
1354 static void ss5_init(MachineState *machine)
1355 {
1356 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1357 }
1358
1359 /* SPARCstation 10 hardware initialisation */
1360 static void ss10_init(MachineState *machine)
1361 {
1362 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1363 }
1364
1365 /* SPARCserver 600MP hardware initialisation */
1366 static void ss600mp_init(MachineState *machine)
1367 {
1368 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1369 }
1370
1371 /* SPARCstation 20 hardware initialisation */
1372 static void ss20_init(MachineState *machine)
1373 {
1374 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1375 }
1376
1377 /* SPARCstation Voyager hardware initialisation */
1378 static void vger_init(MachineState *machine)
1379 {
1380 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1381 }
1382
1383 /* SPARCstation LX hardware initialisation */
1384 static void ss_lx_init(MachineState *machine)
1385 {
1386 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1387 }
1388
1389 /* SPARCstation 4 hardware initialisation */
1390 static void ss4_init(MachineState *machine)
1391 {
1392 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1393 }
1394
1395 /* SPARCClassic hardware initialisation */
1396 static void scls_init(MachineState *machine)
1397 {
1398 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1399 }
1400
1401 /* SPARCbook hardware initialisation */
1402 static void sbook_init(MachineState *machine)
1403 {
1404 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1405 }
1406
1407 static QEMUMachine ss5_machine = {
1408 .name = "SS-5",
1409 .desc = "Sun4m platform, SPARCstation 5",
1410 .init = ss5_init,
1411 .block_default_type = IF_SCSI,
1412 .is_default = 1,
1413 .default_boot_order = "c",
1414 };
1415
1416 static QEMUMachine ss10_machine = {
1417 .name = "SS-10",
1418 .desc = "Sun4m platform, SPARCstation 10",
1419 .init = ss10_init,
1420 .block_default_type = IF_SCSI,
1421 .max_cpus = 4,
1422 .default_boot_order = "c",
1423 };
1424
1425 static QEMUMachine ss600mp_machine = {
1426 .name = "SS-600MP",
1427 .desc = "Sun4m platform, SPARCserver 600MP",
1428 .init = ss600mp_init,
1429 .block_default_type = IF_SCSI,
1430 .max_cpus = 4,
1431 .default_boot_order = "c",
1432 };
1433
1434 static QEMUMachine ss20_machine = {
1435 .name = "SS-20",
1436 .desc = "Sun4m platform, SPARCstation 20",
1437 .init = ss20_init,
1438 .block_default_type = IF_SCSI,
1439 .max_cpus = 4,
1440 .default_boot_order = "c",
1441 };
1442
1443 static QEMUMachine voyager_machine = {
1444 .name = "Voyager",
1445 .desc = "Sun4m platform, SPARCstation Voyager",
1446 .init = vger_init,
1447 .block_default_type = IF_SCSI,
1448 .default_boot_order = "c",
1449 };
1450
1451 static QEMUMachine ss_lx_machine = {
1452 .name = "LX",
1453 .desc = "Sun4m platform, SPARCstation LX",
1454 .init = ss_lx_init,
1455 .block_default_type = IF_SCSI,
1456 .default_boot_order = "c",
1457 };
1458
1459 static QEMUMachine ss4_machine = {
1460 .name = "SS-4",
1461 .desc = "Sun4m platform, SPARCstation 4",
1462 .init = ss4_init,
1463 .block_default_type = IF_SCSI,
1464 .default_boot_order = "c",
1465 };
1466
1467 static QEMUMachine scls_machine = {
1468 .name = "SPARCClassic",
1469 .desc = "Sun4m platform, SPARCClassic",
1470 .init = scls_init,
1471 .block_default_type = IF_SCSI,
1472 .default_boot_order = "c",
1473 };
1474
1475 static QEMUMachine sbook_machine = {
1476 .name = "SPARCbook",
1477 .desc = "Sun4m platform, SPARCbook",
1478 .init = sbook_init,
1479 .block_default_type = IF_SCSI,
1480 .default_boot_order = "c",
1481 };
1482
1483 static void sun4m_register_types(void)
1484 {
1485 type_register_static(&idreg_info);
1486 type_register_static(&afx_info);
1487 type_register_static(&prom_info);
1488 type_register_static(&ram_info);
1489 }
1490
1491 static void sun4m_machine_init(void)
1492 {
1493 qemu_register_machine(&ss5_machine);
1494 qemu_register_machine(&ss10_machine);
1495 qemu_register_machine(&ss600mp_machine);
1496 qemu_register_machine(&ss20_machine);
1497 qemu_register_machine(&voyager_machine);
1498 qemu_register_machine(&ss_lx_machine);
1499 qemu_register_machine(&ss4_machine);
1500 qemu_register_machine(&scls_machine);
1501 qemu_register_machine(&sbook_machine);
1502 }
1503
1504 type_init(sun4m_register_types)
1505 machine_init(sun4m_machine_init);
AR7 emulation for QEMU