tests/e1000e-test.c

   1  /*
   2  * QTest testcase for e1000e NIC
   3  *
   4  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   5  * Developed by Daynix Computing LTD (http://www.daynix.com)
   6  *
   7  * Authors:
   8  * Dmitry Fleytman <dmitry@daynix.com>
   9  * Leonid Bloch <leonid@daynix.com>
  10  * Yan Vugenfirer <yan@daynix.com>
  11  *
  12  * This library is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU Lesser General Public
  14  * License as published by the Free Software Foundation; either
  15  * version 2 of the License, or (at your option) any later version.
  16  *
  17  * This library is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * Lesser General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU Lesser General Public
  23  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26
  27 #include "qemu/osdep.h"
  28 #include <glib.h>
  29 #include "libqtest.h"
  30 #include "qemu-common.h"
  31 #include "libqos/pci-pc.h"
  32 #include "qemu/sockets.h"
  33 #include "qemu/iov.h"
  34 #include "qemu/bitops.h"
  35 #include "libqos/malloc.h"
  36 #include "libqos/malloc-pc.h"
  37 #include "libqos/malloc-generic.h"
  38
  39 #define E1000E_IMS      (0x00d0)
  40
  41 #define E1000E_STATUS   (0x0008)
  42 #define E1000E_STATUS_LU BIT(1)
  43 #define E1000E_STATUS_ASDV1000 BIT(9)
  44
  45 #define E1000E_CTRL     (0x0000)
  46 #define E1000E_CTRL_RESET BIT(26)
  47
  48 #define E1000E_RCTL     (0x0100)
  49 #define E1000E_RCTL_EN  BIT(1)
  50 #define E1000E_RCTL_UPE BIT(3)
  51 #define E1000E_RCTL_MPE BIT(4)
  52
  53 #define E1000E_RFCTL     (0x5008)
  54 #define E1000E_RFCTL_EXTEN  BIT(15)
  55
  56 #define E1000E_TCTL     (0x0400)
  57 #define E1000E_TCTL_EN  BIT(1)
  58
  59 #define E1000E_CTRL_EXT             (0x0018)
  60 #define E1000E_CTRL_EXT_DRV_LOAD    BIT(28)
  61 #define E1000E_CTRL_EXT_TXLSFLOW    BIT(22)
  62
  63 #define E1000E_RX0_MSG_ID           (0)
  64 #define E1000E_TX0_MSG_ID           (1)
  65 #define E1000E_OTHER_MSG_ID         (2)
  66
  67 #define E1000E_IVAR                 (0x00E4)
  68 #define E1000E_IVAR_TEST_CFG        ((E1000E_RX0_MSG_ID << 0)    | BIT(3)  | \
  69                                      (E1000E_TX0_MSG_ID << 8)    | BIT(11) | \
  70                                      (E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
  71                                      BIT(31))
  72
  73 #define E1000E_RING_LEN             (0x1000)
  74 #define E1000E_TXD_LEN              (16)
  75 #define E1000E_RXD_LEN              (16)
  76
  77 #define E1000E_TDBAL    (0x3800)
  78 #define E1000E_TDBAH    (0x3804)
  79 #define E1000E_TDLEN    (0x3808)
  80 #define E1000E_TDH      (0x3810)
  81 #define E1000E_TDT      (0x3818)
  82
  83 #define E1000E_RDBAL    (0x2800)
  84 #define E1000E_RDBAH    (0x2804)
  85 #define E1000E_RDLEN    (0x2808)
  86 #define E1000E_RDH      (0x2810)
  87 #define E1000E_RDT      (0x2818)
  88
  89 typedef struct e1000e_device {
  90     QPCIDevice *pci_dev;
  91     void *mac_regs;
  92
  93     uint64_t tx_ring;
  94     uint64_t rx_ring;
  95 } e1000e_device;
  96
  97 static int test_sockets[2];
  98 static QGuestAllocator *test_alloc;
  99 static QPCIBus *test_bus;
 100
 101 static void e1000e_pci_foreach_callback(QPCIDevice *dev, int devfn, void *data)
 102 {
 103     *(QPCIDevice **) data = dev;
 104 }
 105
 106 static QPCIDevice *e1000e_device_find(QPCIBus *bus)
 107 {
 108     static const int e1000e_vendor_id = 0x8086;
 109     static const int e1000e_dev_id = 0x10D3;
 110
 111     QPCIDevice *e1000e_dev = NULL;
 112
 113     qpci_device_foreach(bus, e1000e_vendor_id, e1000e_dev_id,
 114         e1000e_pci_foreach_callback, &e1000e_dev);
 115
 116     g_assert_nonnull(e1000e_dev);
 117
 118     return e1000e_dev;
 119 }
 120
 121 static void e1000e_macreg_write(e1000e_device *d, uint32_t reg, uint32_t val)
 122 {
 123     qpci_io_writel(d->pci_dev, d->mac_regs + reg, val);
 124 }
 125
 126 static uint32_t e1000e_macreg_read(e1000e_device *d, uint32_t reg)
 127 {
 128     return qpci_io_readl(d->pci_dev, d->mac_regs + reg);
 129 }
 130
 131 static void e1000e_device_init(QPCIBus *bus, e1000e_device *d)
 132 {
 133     uint32_t val;
 134
 135     d->pci_dev = e1000e_device_find(bus);
 136
 137     /* Enable the device */
 138     qpci_device_enable(d->pci_dev);
 139
 140     /* Map BAR0 (mac registers) */
 141     d->mac_regs = qpci_iomap(d->pci_dev, 0, NULL);
 142     g_assert_nonnull(d->mac_regs);
 143
 144     /* Reset the device */
 145     val = e1000e_macreg_read(d, E1000E_CTRL);
 146     e1000e_macreg_write(d, E1000E_CTRL, val | E1000E_CTRL_RESET);
 147
 148     /* Enable and configure MSI-X */
 149     qpci_msix_enable(d->pci_dev);
 150     e1000e_macreg_write(d, E1000E_IVAR, E1000E_IVAR_TEST_CFG);
 151
 152     /* Check the device status - link and speed */
 153     val = e1000e_macreg_read(d, E1000E_STATUS);
 154     g_assert_cmphex(val & (E1000E_STATUS_LU | E1000E_STATUS_ASDV1000),
 155         ==, E1000E_STATUS_LU | E1000E_STATUS_ASDV1000);
 156
 157     /* Initialize TX/RX logic */
 158     e1000e_macreg_write(d, E1000E_RCTL, 0);
 159     e1000e_macreg_write(d, E1000E_TCTL, 0);
 160
 161     /* Notify the device that the driver is ready */
 162     val = e1000e_macreg_read(d, E1000E_CTRL_EXT);
 163     e1000e_macreg_write(d, E1000E_CTRL_EXT,
 164         val | E1000E_CTRL_EXT_DRV_LOAD | E1000E_CTRL_EXT_TXLSFLOW);
 165
 166     /* Allocate and setup TX ring */
 167     d->tx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
 168     g_assert(d->tx_ring != 0);
 169
 170     e1000e_macreg_write(d, E1000E_TDBAL, (uint32_t) d->tx_ring);
 171     e1000e_macreg_write(d, E1000E_TDBAH, (uint32_t) (d->tx_ring >> 32));
 172     e1000e_macreg_write(d, E1000E_TDLEN, E1000E_RING_LEN);
 173     e1000e_macreg_write(d, E1000E_TDT, 0);
 174     e1000e_macreg_write(d, E1000E_TDH, 0);
 175
 176     /* Enable transmit */
 177     e1000e_macreg_write(d, E1000E_TCTL, E1000E_TCTL_EN);
 178
 179     /* Allocate and setup RX ring */
 180     d->rx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
 181     g_assert(d->rx_ring != 0);
 182
 183     e1000e_macreg_write(d, E1000E_RDBAL, (uint32_t)d->rx_ring);
 184     e1000e_macreg_write(d, E1000E_RDBAH, (uint32_t)(d->rx_ring >> 32));
 185     e1000e_macreg_write(d, E1000E_RDLEN, E1000E_RING_LEN);
 186     e1000e_macreg_write(d, E1000E_RDT, 0);
 187     e1000e_macreg_write(d, E1000E_RDH, 0);
 188
 189     /* Enable receive */
 190     e1000e_macreg_write(d, E1000E_RFCTL, E1000E_RFCTL_EXTEN);
 191     e1000e_macreg_write(d, E1000E_RCTL, E1000E_RCTL_EN  |
 192                                         E1000E_RCTL_UPE |
 193                                         E1000E_RCTL_MPE);
 194
 195     /* Enable all interrupts */
 196     e1000e_macreg_write(d, E1000E_IMS, 0xFFFFFFFF);
 197 }
 198
 199 static void e1000e_tx_ring_push(e1000e_device *d, void *descr)
 200 {
 201     uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
 202     uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000E_TXD_LEN;
 203
 204     memwrite(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
 205     e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
 206
 207     /* Read WB data for the packet transmitted */
 208     memread(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
 209 }
 210
 211 static void e1000e_rx_ring_push(e1000e_device *d, void *descr)
 212 {
 213     uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
 214     uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000E_RXD_LEN;
 215
 216     memwrite(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
 217     e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
 218
 219     /* Read WB data for the packet received */
 220     memread(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
 221 }
 222
 223 static void e1000e_wait_isr(e1000e_device *d, uint16_t msg_id)
 224 {
 225     guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
 226
 227     do {
 228         if (qpci_msix_pending(d->pci_dev, msg_id)) {
 229             return;
 230         }
 231         clock_step(10000);
 232     } while (g_get_monotonic_time() < end_time);
 233
 234     g_error("Timeout expired");
 235 }
 236
 237 static void e1000e_send_verify(e1000e_device *d)
 238 {
 239     struct {
 240         uint64_t buffer_addr;
 241         union {
 242             uint32_t data;
 243             struct {
 244                 uint16_t length;
 245                 uint8_t cso;
 246                 uint8_t cmd;
 247             } flags;
 248         } lower;
 249         union {
 250             uint32_t data;
 251             struct {
 252                 uint8_t status;
 253                 uint8_t css;
 254                 uint16_t special;
 255             } fields;
 256         } upper;
 257     } descr;
 258
 259     static const uint32_t dtyp_data = BIT(20);
 260     static const uint32_t dtyp_ext  = BIT(29);
 261     static const uint32_t dcmd_rs   = BIT(27);
 262     static const uint32_t dcmd_eop  = BIT(24);
 263     static const uint32_t dsta_dd   = BIT(0);
 264     static const int data_len = 64;
 265     char buffer[64];
 266     int ret;
 267     uint32_t recv_len;
 268
 269     /* Prepare test data buffer */
 270     uint64_t data = guest_alloc(test_alloc, data_len);
 271     memwrite(data, "TEST", 5);
 272
 273     /* Prepare TX descriptor */
 274     memset(&descr, 0, sizeof(descr));
 275     descr.buffer_addr = cpu_to_le64(data);
 276     descr.lower.data = cpu_to_le32(dcmd_rs   |
 277                                    dcmd_eop  |
 278                                    dtyp_ext  |
 279                                    dtyp_data |
 280                                    data_len);
 281
 282     /* Put descriptor to the ring */
 283     e1000e_tx_ring_push(d, &descr);
 284
 285     /* Wait for TX WB interrupt */
 286     e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
 287
 288     /* Check DD bit */
 289     g_assert_cmphex(le32_to_cpu(descr.upper.data) & dsta_dd, ==, dsta_dd);
 290
 291     /* Check data sent to the backend */
 292     ret = qemu_recv(test_sockets[0], &recv_len, sizeof(recv_len), 0);
 293     g_assert_cmpint(ret, == , sizeof(recv_len));
 294     qemu_recv(test_sockets[0], buffer, 64, 0);
 295     g_assert_cmpstr(buffer, == , "TEST");
 296
 297     /* Free test data buffer */
 298     guest_free(test_alloc, data);
 299 }
 300
 301 static void e1000e_receive_verify(e1000e_device *d)
 302 {
 303     union {
 304         struct {
 305             uint64_t buffer_addr;
 306             uint64_t reserved;
 307         } read;
 308         struct {
 309             struct {
 310                 uint32_t mrq;
 311                 union {
 312                     uint32_t rss;
 313                     struct {
 314                         uint16_t ip_id;
 315                         uint16_t csum;
 316                     } csum_ip;
 317                 } hi_dword;
 318             } lower;
 319             struct {
 320                 uint32_t status_error;
 321                 uint16_t length;
 322                 uint16_t vlan;
 323             } upper;
 324         } wb;
 325     } descr;
 326
 327     static const uint32_t esta_dd = BIT(0);
 328
 329     char test[] = "TEST";
 330     int len = htonl(sizeof(test));
 331     struct iovec iov[] = {
 332         {
 333             .iov_base = &len,
 334             .iov_len = sizeof(len),
 335         },{
 336             .iov_base = test,
 337             .iov_len = sizeof(test),
 338         },
 339     };
 340
 341     static const int data_len = 64;
 342     char buffer[64];
 343     int ret;
 344
 345     /* Send a dummy packet to device's socket*/
 346     ret = iov_send(test_sockets[0], iov, 2, 0, sizeof(len) + sizeof(test));
 347     g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
 348
 349     /* Prepare test data buffer */
 350     uint64_t data = guest_alloc(test_alloc, data_len);
 351
 352     /* Prepare RX descriptor */
 353     memset(&descr, 0, sizeof(descr));
 354     descr.read.buffer_addr = cpu_to_le64(data);
 355
 356     /* Put descriptor to the ring */
 357     e1000e_rx_ring_push(d, &descr);
 358
 359     /* Wait for TX WB interrupt */
 360     e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
 361
 362     /* Check DD bit */
 363     g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
 364         esta_dd, ==, esta_dd);
 365
 366     /* Check data sent to the backend */
 367     memread(data, buffer, sizeof(buffer));
 368     g_assert_cmpstr(buffer, == , "TEST");
 369
 370     /* Free test data buffer */
 371     guest_free(test_alloc, data);
 372 }
 373
 374 static void e1000e_device_clear(QPCIBus *bus, e1000e_device *d)
 375 {
 376     qpci_iounmap(d->pci_dev, d->mac_regs);
 377     qpci_msix_disable(d->pci_dev);
 378 }
 379
 380 static void data_test_init(e1000e_device *d)
 381 {
 382     char *cmdline;
 383
 384     int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
 385     g_assert_cmpint(ret, != , -1);
 386
 387     cmdline = g_strdup_printf("-netdev socket,fd=%d,id=hs0 "
 388                               "-device e1000e,netdev=hs0", test_sockets[1]);
 389     g_assert_nonnull(cmdline);
 390
 391     qtest_start(cmdline);
 392     g_free(cmdline);
 393
 394     test_bus = qpci_init_pc();
 395     g_assert_nonnull(test_bus);
 396
 397     test_alloc = pc_alloc_init();
 398     g_assert_nonnull(test_alloc);
 399
 400     e1000e_device_init(test_bus, d);
 401 }
 402
 403 static void data_test_clear(e1000e_device *d)
 404 {
 405     e1000e_device_clear(test_bus, d);
 406     close(test_sockets[0]);
 407     pc_alloc_uninit(test_alloc);
 408     qpci_free_pc(test_bus);
 409     qtest_end();
 410 }
 411
 412 static void test_e1000e_init(gconstpointer data)
 413 {
 414     e1000e_device d;
 415
 416     data_test_init(&d);
 417     data_test_clear(&d);
 418 }
 419
 420 static void test_e1000e_tx(gconstpointer data)
 421 {
 422     e1000e_device d;
 423
 424     data_test_init(&d);
 425     e1000e_send_verify(&d);
 426     data_test_clear(&d);
 427 }
 428
 429 static void test_e1000e_rx(gconstpointer data)
 430 {
 431     e1000e_device d;
 432
 433     data_test_init(&d);
 434     e1000e_receive_verify(&d);
 435     data_test_clear(&d);
 436 }
 437
 438 static void test_e1000e_multiple_transfers(gconstpointer data)
 439 {
 440     static const long iterations = 4 * 1024;
 441     long i;
 442
 443     e1000e_device d;
 444
 445     data_test_init(&d);
 446
 447     for (i = 0; i < iterations; i++) {
 448         e1000e_send_verify(&d);
 449         e1000e_receive_verify(&d);
 450     }
 451
 452     data_test_clear(&d);
 453 }
 454
 455 static void test_e1000e_hotplug(gconstpointer data)
 456 {
 457     static const uint8_t slot = 0x06;
 458
 459     qtest_start("-device e1000e");
 460
 461     qpci_plug_device_test("e1000e", "e1000e_net", slot, NULL);
 462     qpci_unplug_acpi_device_test("e1000e_net", slot);
 463
 464     qtest_end();
 465 }
 466
 467 int main(int argc, char **argv)
 468 {
 469     g_test_init(&argc, &argv, NULL);
 470
 471     qtest_add_data_func("e1000e/init", NULL, test_e1000e_init);
 472     qtest_add_data_func("e1000e/tx", NULL, test_e1000e_tx);
 473     qtest_add_data_func("e1000e/rx", NULL, test_e1000e_rx);
 474     qtest_add_data_func("e1000e/multiple_transfers", NULL,
 475         test_e1000e_multiple_transfers);
 476     qtest_add_data_func("e1000e/hotplug", NULL, test_e1000e_hotplug);
 477
 478     return g_test_run();
 479 }