11 # CXL has a number of separate event logs for different types of
12 # events. Each such event log is handled and signaled independently.
14 # @informational: Information Event Log
16 # @warning: Warning Event Log
18 # @failure: Failure Event Log
20 # @fatal: Fatal Event Log
24 { 'enum': 'CxlEventLog',
25 'data': ['informational',
32 # @cxl-inject-general-media-event:
34 # Inject an event record for a General Media Event (CXL r3.0
35 # 8.2.9.2.1.1). This event type is reported via one of the event logs
36 # specified via the log parameter.
38 # @path: CXL type 3 device canonical QOM path
40 # @log: event log to add the event to
42 # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
43 # Record Format, Event Record Flags for subfield definitions.
45 # @dpa: Device Physical Address (relative to @path device). Note
46 # lower bits include some flags. See CXL r3.0 Table 8-43 General
47 # Media Event Record, Physical Address.
49 # @descriptor: Memory Event Descriptor with additional memory event
50 # information. See CXL r3.0 Table 8-43 General Media Event
51 # Record, Memory Event Descriptor for bit definitions.
53 # @type: Type of memory event that occurred. See CXL r3.0 Table 8-43
54 # General Media Event Record, Memory Event Type for possible
57 # @transaction-type: Type of first transaction that caused the event
58 # to occur. See CXL r3.0 Table 8-43 General Media Event Record,
59 # Transaction Type for possible values.
61 # @channel: The channel of the memory event location. A channel is an
62 # interface that can be independently accessed for a transaction.
64 # @rank: The rank of the memory event location. A rank is a set of
65 # memory devices on a channel that together execute a transaction.
67 # @device: Bitmask that represents all devices in the rank associated
68 # with the memory event location.
70 # @component-id: Device specific component identifier for the event.
71 # May describe a field replaceable sub-component of the device.
75 { 'command': 'cxl-inject-general-media-event',
76 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
77 'dpa': 'uint64', 'descriptor': 'uint8',
78 'type': 'uint8', 'transaction-type': 'uint8',
79 '*channel': 'uint8', '*rank': 'uint8',
80 '*device': 'uint32', '*component-id': 'str' } }
83 # @cxl-inject-dram-event:
85 # Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
86 # This event type is reported via one of the event logs specified via
89 # @path: CXL type 3 device canonical QOM path
91 # @log: Event log to add the event to
93 # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
94 # Record Format, Event Record Flags for subfield definitions.
96 # @dpa: Device Physical Address (relative to @path device). Note
97 # lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
98 # Event Record, Physical Address.
100 # @descriptor: Memory Event Descriptor with additional memory event
101 # information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
102 # Event Descriptor for bit definitions.
104 # @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
105 # DRAM Event Record, Memory Event Type for possible values.
107 # @transaction-type: Type of first transaction that caused the event
108 # to occur. See CXL r3.0 Table 8-44 DRAM Event Record,
109 # Transaction Type for possible values.
111 # @channel: The channel of the memory event location. A channel is an
112 # interface that can be independently accessed for a transaction.
114 # @rank: The rank of the memory event location. A rank is a set of
115 # memory devices on a channel that together execute a transaction.
117 # @nibble-mask: Identifies one or more nibbles that the error affects
119 # @bank-group: Bank group of the memory event location, incorporating
122 # @bank: Bank of the memory event location. A single bank is accessed
123 # per read or write of the memory.
125 # @row: Row address within the DRAM.
127 # @column: Column address within the DRAM.
129 # @correction-mask: Bits within each nibble. Used in order of bits
130 # set in the nibble-mask. Up to 4 nibbles may be covered.
134 { 'command': 'cxl-inject-dram-event',
135 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
136 'dpa': 'uint64', 'descriptor': 'uint8',
137 'type': 'uint8', 'transaction-type': 'uint8',
138 '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
139 '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
140 '*column': 'uint16', '*correction-mask': [ 'uint64' ]
144 # @cxl-inject-memory-module-event:
146 # Inject an event record for a Memory Module Event (CXL r3.0
147 # 8.2.9.2.1.3). This event includes a copy of the Device Health info
148 # at the time of the event.
150 # @path: CXL type 3 device canonical QOM path
152 # @log: Event Log to add the event to
154 # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
155 # Record Format, Event Record Flags for subfield definitions.
157 # @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
158 # Event Record for bit definitions for bit definiions.
160 # @health-status: Overall health summary bitmap. See CXL r3.0 Table
161 # 8-100 Get Health Info Output Payload, Health Status for bit
164 # @media-status: Overall media health summary. See CXL r3.0 Table
165 # 8-100 Get Health Info Output Payload, Media Status for bit
168 # @additional-status: See CXL r3.0 Table 8-100 Get Health Info Output
169 # Payload, Additional Status for subfield definitions.
171 # @life-used: Percentage (0-100) of factory expected life span.
173 # @temperature: Device temperature in degrees Celsius.
175 # @dirty-shutdown-count: Number of times the device has been unable to
176 # determine whether data loss may have occurred.
178 # @corrected-volatile-error-count: Total number of correctable errors
179 # in volatile memory.
181 # @corrected-persistent-error-count: Total number of correctable
182 # errors in persistent memory
186 { 'command': 'cxl-inject-memory-module-event',
187 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
188 'type': 'uint8', 'health-status': 'uint8',
189 'media-status': 'uint8', 'additional-status': 'uint8',
190 'life-used': 'uint8', 'temperature' : 'int16',
191 'dirty-shutdown-count': 'uint32',
192 'corrected-volatile-error-count': 'uint32',
193 'corrected-persistent-error-count': 'uint32'
197 # @cxl-inject-poison:
199 # Poison records indicate that a CXL memory device knows that a
200 # particular memory region may be corrupted. This may be because of
201 # locally detected errors (e.g. ECC failure) or poisoned writes
202 # received from other components in the system. This injection
203 # mechanism enables testing of the OS handling of poison records which
204 # may be queried via the CXL mailbox.
206 # @path: CXL type 3 device canonical QOM path
208 # @start: Start address; must be 64 byte aligned.
210 # @length: Length of poison to inject; must be a multiple of 64 bytes.
214 { 'command': 'cxl-inject-poison',
215 'data': { 'path': 'str', 'start': 'uint64', 'length': 'size' }}
218 # @CxlUncorErrorType:
220 # Type of uncorrectable CXL error to inject. These errors are
221 # reported via an AER uncorrectable internal error with additional
222 # information logged at the CXL device.
224 # @cache-data-parity: Data error such as data parity or data ECC error
227 # @cache-address-parity: Address parity or other errors associated
228 # with the address field on CXL.cache
230 # @cache-be-parity: Byte enable parity or other byte enable errors on
233 # @cache-data-ecc: ECC error on CXL.cache
235 # @mem-data-parity: Data error such as data parity or data ECC error
238 # @mem-address-parity: Address parity or other errors associated with
239 # the address field on CXL.mem
241 # @mem-be-parity: Byte enable parity or other byte enable errors on
244 # @mem-data-ecc: Data ECC error on CXL.mem.
246 # @reinit-threshold: REINIT threshold hit.
248 # @rsvd-encoding: Received unrecognized encoding.
250 # @poison-received: Received poison from the peer.
252 # @receiver-overflow: Buffer overflows (first 3 bits of header log
255 # @internal: Component specific error
257 # @cxl-ide-tx: Integrity and data encryption tx error.
259 # @cxl-ide-rx: Integrity and data encryption rx error.
264 { 'enum': 'CxlUncorErrorType',
265 'data': ['cache-data-parity',
266 'cache-address-parity',
270 'mem-address-parity',
284 # @CXLUncorErrorRecord:
286 # Record of a single error including header log.
288 # @type: Type of error
290 # @header: 16 DWORD of header.
294 { 'struct': 'CXLUncorErrorRecord',
296 'type': 'CxlUncorErrorType',
297 'header': [ 'uint32' ]
302 # @cxl-inject-uncorrectable-errors:
304 # Command to allow injection of multiple errors in one go. This
305 # allows testing of multiple header log handling in the OS.
307 # @path: CXL Type 3 device canonical QOM path
309 # @errors: Errors to inject
313 { 'command': 'cxl-inject-uncorrectable-errors',
314 'data': { 'path': 'str',
315 'errors': [ 'CXLUncorErrorRecord' ] }}
320 # Type of CXL correctable error to inject
322 # @cache-data-ecc: Data ECC error on CXL.cache
324 # @mem-data-ecc: Data ECC error on CXL.mem
326 # @crc-threshold: Component specific and applicable to 68 byte Flit
329 # @cache-poison-received: Received poison from a peer on CXL.cache.
331 # @mem-poison-received: Received poison from a peer on CXL.mem
333 # @physical: Received error indication from the physical layer.
337 { 'enum': 'CxlCorErrorType',
338 'data': ['cache-data-ecc',
342 'cache-poison-received',
343 'mem-poison-received',
348 # @cxl-inject-correctable-error:
350 # Command to inject a single correctable error. Multiple error
351 # injection of this error type is not interesting as there is no
352 # associated header log. These errors are reported via AER as a
353 # correctable internal error, with additional detail available from
356 # @path: CXL Type 3 device canonical QOM path
358 # @type: Type of error.
362 {'command': 'cxl-inject-correctable-error',
363 'data': {'path': 'str', 'type': 'CxlCorErrorType'}}
366 # @CxlDynamicCapacityExtent:
368 # A single dynamic capacity extent. This is a contiguous allocation
369 # of memory by Device Physical Address within a single Dynamic
370 # Capacity Region on a CXL Type 3 Device.
372 # @offset: The offset (in bytes) to the start of the region
373 # where the extent belongs to.
375 # @len: The length of the extent in bytes.
379 { 'struct': 'CxlDynamicCapacityExtent',
387 # @CxlExtentSelectionPolicy:
389 # The policy to use for selecting which extents comprise the added
390 # capacity, as defined in Compute Express Link (CXL) Specification,
391 # Revision 3.1, Table 7-70.
393 # @free: Device is responsible for allocating the requested memory
394 # capacity and is free to do this using any combination of
397 # @contiguous: Device is responsible for allocating the requested
398 # memory capacity but must do so as a single contiguous
401 # @prescriptive: The precise set of extents to be allocated is
402 # specified by the command. Thus allocation is being managed
403 # by the issuer of the allocation command, not the device.
405 # @enable-shared-access: Capacity has already been allocated to a
406 # different host using free, contiguous or prescriptive policy
407 # with a known tag. This policy then instructs the device to
408 # make the capacity with the specified tag available to an
409 # additional host. Capacity is implicit as it matches that
410 # already associated with the tag. Note that the extent list
411 # (and hence Device Physical Addresses) used are per host, so
412 # a device may use different representations on each host.
413 # The ordering of the extents provided to each host is indicated
414 # to the host using per extent sequence numbers generated by
415 # the device. Has a similar meaning for temporal sharing, but
416 # in that case there may be only one host involved.
420 { 'enum': 'CxlExtentSelectionPolicy',
424 'enable-shared-access']
428 # @cxl-add-dynamic-capacity:
430 # Initiate adding dynamic capacity extents to a host. This simulates
431 # operations defined in Compute Express Link (CXL) Specification,
432 # Revision 3.1, Section 7.6.7.6.5. Note that, currently, establishing
433 # success or failure of the full Add Dynamic Capacity flow requires
434 # out of band communication with the OS of the CXL host.
436 # @path: path to the CXL Dynamic Capacity Device in the QOM tree.
438 # @host-id: The "Host ID" field as defined in Compute Express Link
439 # (CXL) Specification, Revision 3.1, Table 7-70.
441 # @selection-policy: The "Selection Policy" bits as defined in
442 # Compute Express Link (CXL) Specification, Revision 3.1,
443 # Table 7-70. It specifies the policy to use for selecting
444 # which extents comprise the added capacity.
446 # @region: The "Region Number" field as defined in Compute Express
447 # Link (CXL) Specification, Revision 3.1, Table 7-70. Valid
450 # @tag: The "Tag" field as defined in Compute Express Link (CXL)
451 # Specification, Revision 3.1, Table 7-70.
453 # @extents: The "Extent List" field as defined in Compute Express Link
454 # (CXL) Specification, Revision 3.1, Table 7-70.
458 # @unstable: For now this command is subject to change.
462 { 'command': 'cxl-add-dynamic-capacity',
463 'data': { 'path': 'str',
465 'selection-policy': 'CxlExtentSelectionPolicy',
468 'extents': [ 'CxlDynamicCapacityExtent' ]
470 'features': [ 'unstable' ]
474 # @CxlExtentRemovalPolicy:
476 # The policy to use for selecting which extents comprise the released
477 # capacity, defined in the "Flags" field in Compute Express Link (CXL)
478 # Specification, Revision 3.1, Table 7-71.
480 # @tag-based: Extents are selected by the device based on tag, with
481 # no requirement for contiguous extents.
483 # @prescriptive: Extent list of capacity to release is included in
484 # the request payload.
488 { 'enum': 'CxlExtentRemovalPolicy',
489 'data': ['tag-based',
494 # @cxl-release-dynamic-capacity:
496 # Initiate release of dynamic capacity extents from a host. This
497 # simulates operations defined in Compute Express Link (CXL)
498 # Specification, Revision 3.1, Section 7.6.7.6.6. Note that,
499 # currently, success or failure of the full Release Dynamic Capacity
500 # flow requires out of band communication with the OS of the CXL host.
502 # @path: path to the CXL Dynamic Capacity Device in the QOM tree.
504 # @host-id: The "Host ID" field as defined in Compute Express Link
505 # (CXL) Specification, Revision 3.1, Table 7-71.
507 # @removal-policy: Bit[3:0] of the "Flags" field as defined in
508 # Compute Express Link (CXL) Specification, Revision 3.1,
511 # @forced-removal: Bit[4] of the "Flags" field in Compute Express
512 # Link (CXL) Specification, Revision 3.1, Table 7-71. When set,
513 # the device does not wait for a Release Dynamic Capacity command
514 # from the host. Instead, the host immediately looses access to
515 # the released capacity.
517 # @sanitize-on-release: Bit[5] of the "Flags" field in Compute
518 # Express Link (CXL) Specification, Revision 3.1, Table 7-71.
519 # When set, the device should sanitize all released capacity as
520 # a result of this request. This ensures that all user data
521 # and metadata is made permanently unavailable by whatever
522 # means is appropriate for the media type. Note that changing
523 # encryption keys is not sufficient.
525 # @region: The "Region Number" field as defined in Compute Express
526 # Link Specification, Revision 3.1, Table 7-71. Valid range
529 # @tag: The "Tag" field as defined in Compute Express Link (CXL)
530 # Specification, Revision 3.1, Table 7-71.
532 # @extents: The "Extent List" field as defined in Compute Express
533 # Link (CXL) Specification, Revision 3.1, Table 7-71.
537 # @unstable: For now this command is subject to change.
541 { 'command': 'cxl-release-dynamic-capacity',
542 'data': { 'path': 'str',
544 'removal-policy': 'CxlExtentRemovalPolicy',
545 '*forced-removal': 'bool',
546 '*sanitize-on-release': 'bool',
549 'extents': [ 'CxlDynamicCapacityExtent' ]
551 'features': [ 'unstable' ]