hw/ppc/ppc440_pcix.c

   1 /*
   2  * Emulation of the ibm,plb-pcix PCI controller
   3  * This is found in some 440 SoCs e.g. the 460EX.
   4  *
   5  * Copyright (c) 2016-2018 BALATON Zoltan
   6  *
   7  * Derived from ppc4xx_pci.c and pci-host/ppce500.c
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qemu/error-report.h"
  24 #include "hw/hw.h"
  25 #include "hw/ppc/ppc.h"
  26 #include "hw/ppc/ppc4xx.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "exec/address-spaces.h"
  30 #include "trace.h"
  31
  32 struct PLBOutMap {
  33     uint64_t la;
  34     uint64_t pcia;
  35     uint32_t sa;
  36     MemoryRegion mr;
  37 };
  38
  39 struct PLBInMap {
  40     uint64_t sa;
  41     uint64_t la;
  42     MemoryRegion mr;
  43 };
  44
  45 #define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
  46 #define PPC440_PCIX_HOST_BRIDGE(obj) \
  47     OBJECT_CHECK(PPC440PCIXState, (obj), TYPE_PPC440_PCIX_HOST_BRIDGE)
  48
  49 #define PPC440_PCIX_NR_POMS 3
  50 #define PPC440_PCIX_NR_PIMS 3
  51
  52 typedef struct PPC440PCIXState {
  53     PCIHostState parent_obj;
  54
  55     PCIDevice *dev;
  56     struct PLBOutMap pom[PPC440_PCIX_NR_POMS];
  57     struct PLBInMap pim[PPC440_PCIX_NR_PIMS];
  58     uint32_t sts;
  59     qemu_irq irq[PCI_NUM_PINS];
  60     AddressSpace bm_as;
  61     MemoryRegion bm;
  62
  63     MemoryRegion container;
  64     MemoryRegion iomem;
  65     MemoryRegion busmem;
  66 } PPC440PCIXState;
  67
  68 #define PPC440_REG_BASE     0x80000
  69 #define PPC440_REG_SIZE     0xff
  70
  71 #define PCIC0_CFGADDR       0x0
  72 #define PCIC0_CFGDATA       0x4
  73
  74 #define PCIX0_POM0LAL       0x68
  75 #define PCIX0_POM0LAH       0x6c
  76 #define PCIX0_POM0SA        0x70
  77 #define PCIX0_POM0PCIAL     0x74
  78 #define PCIX0_POM0PCIAH     0x78
  79 #define PCIX0_POM1LAL       0x7c
  80 #define PCIX0_POM1LAH       0x80
  81 #define PCIX0_POM1SA        0x84
  82 #define PCIX0_POM1PCIAL     0x88
  83 #define PCIX0_POM1PCIAH     0x8c
  84 #define PCIX0_POM2SA        0x90
  85
  86 #define PCIX0_PIM0SAL       0x98
  87 #define PCIX0_PIM0LAL       0x9c
  88 #define PCIX0_PIM0LAH       0xa0
  89 #define PCIX0_PIM1SA        0xa4
  90 #define PCIX0_PIM1LAL       0xa8
  91 #define PCIX0_PIM1LAH       0xac
  92 #define PCIX0_PIM2SAL       0xb0
  93 #define PCIX0_PIM2LAL       0xb4
  94 #define PCIX0_PIM2LAH       0xb8
  95 #define PCIX0_PIM0SAH       0xf8
  96 #define PCIX0_PIM2SAH       0xfc
  97
  98 #define PCIX0_STS           0xe0
  99
 100 #define PCI_ALL_SIZE        (PPC440_REG_BASE + PPC440_REG_SIZE)
 101
 102 static void ppc440_pcix_clear_region(MemoryRegion *parent,
 103                                      MemoryRegion *mem)
 104 {
 105     if (memory_region_is_mapped(mem)) {
 106         memory_region_del_subregion(parent, mem);
 107         object_unparent(OBJECT(mem));
 108     }
 109 }
 110
 111 /* DMA mapping */
 112 static void ppc440_pcix_update_pim(PPC440PCIXState *s, int idx)
 113 {
 114     MemoryRegion *mem = &s->pim[idx].mr;
 115     char *name;
 116     uint64_t size;
 117
 118     /* Before we modify anything, unmap and destroy the region */
 119     ppc440_pcix_clear_region(&s->bm, mem);
 120
 121     if (!(s->pim[idx].sa & 1)) {
 122         /* Not enabled, nothing to do */
 123         return;
 124     }
 125
 126     name = g_strdup_printf("PCI Inbound Window %d", idx);
 127     size = ~(s->pim[idx].sa & ~7ULL) + 1;
 128     memory_region_init_alias(mem, OBJECT(s), name, get_system_memory(),
 129                              s->pim[idx].la, size);
 130     memory_region_add_subregion_overlap(&s->bm, 0, mem, -1);
 131     g_free(name);
 132
 133     trace_ppc440_pcix_update_pim(idx, size, s->pim[idx].la);
 134 }
 135
 136 /* BAR mapping */
 137 static void ppc440_pcix_update_pom(PPC440PCIXState *s, int idx)
 138 {
 139     MemoryRegion *mem = &s->pom[idx].mr;
 140     MemoryRegion *address_space_mem = get_system_memory();
 141     char *name;
 142     uint32_t size;
 143
 144     /* Before we modify anything, unmap and destroy the region */
 145     ppc440_pcix_clear_region(address_space_mem, mem);
 146
 147     if (!(s->pom[idx].sa & 1)) {
 148         /* Not enabled, nothing to do */
 149         return;
 150     }
 151
 152     name = g_strdup_printf("PCI Outbound Window %d", idx);
 153     size = ~(s->pom[idx].sa & 0xfffffffe) + 1;
 154     if (!size) {
 155         size = 0xffffffff;
 156     }
 157     memory_region_init_alias(mem, OBJECT(s), name, &s->busmem,
 158                              s->pom[idx].pcia, size);
 159     memory_region_add_subregion(address_space_mem, s->pom[idx].la, mem);
 160     g_free(name);
 161
 162     trace_ppc440_pcix_update_pom(idx, size, s->pom[idx].la, s->pom[idx].pcia);
 163 }
 164
 165 static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
 166                                    uint64_t val, unsigned size)
 167 {
 168     struct PPC440PCIXState *s = opaque;
 169
 170     trace_ppc440_pcix_reg_read(addr, val);
 171     switch (addr) {
 172     case PCI_VENDOR_ID ... PCI_MAX_LAT:
 173         stl_le_p(s->dev->config + addr, val);
 174         break;
 175
 176     case PCIX0_POM0LAL:
 177         s->pom[0].la &= 0xffffffff00000000ULL;
 178         s->pom[0].la |= val;
 179         ppc440_pcix_update_pom(s, 0);
 180         break;
 181     case PCIX0_POM0LAH:
 182         s->pom[0].la &= 0xffffffffULL;
 183         s->pom[0].la |= val << 32;
 184         ppc440_pcix_update_pom(s, 0);
 185         break;
 186     case PCIX0_POM0SA:
 187         s->pom[0].sa = val;
 188         ppc440_pcix_update_pom(s, 0);
 189         break;
 190     case PCIX0_POM0PCIAL:
 191         s->pom[0].pcia &= 0xffffffff00000000ULL;
 192         s->pom[0].pcia |= val;
 193         ppc440_pcix_update_pom(s, 0);
 194         break;
 195     case PCIX0_POM0PCIAH:
 196         s->pom[0].pcia &= 0xffffffffULL;
 197         s->pom[0].pcia |= val << 32;
 198         ppc440_pcix_update_pom(s, 0);
 199         break;
 200     case PCIX0_POM1LAL:
 201         s->pom[1].la &= 0xffffffff00000000ULL;
 202         s->pom[1].la |= val;
 203         ppc440_pcix_update_pom(s, 1);
 204         break;
 205     case PCIX0_POM1LAH:
 206         s->pom[1].la &= 0xffffffffULL;
 207         s->pom[1].la |= val << 32;
 208         ppc440_pcix_update_pom(s, 1);
 209         break;
 210     case PCIX0_POM1SA:
 211         s->pom[1].sa = val;
 212         ppc440_pcix_update_pom(s, 1);
 213         break;
 214     case PCIX0_POM1PCIAL:
 215         s->pom[1].pcia &= 0xffffffff00000000ULL;
 216         s->pom[1].pcia |= val;
 217         ppc440_pcix_update_pom(s, 1);
 218         break;
 219     case PCIX0_POM1PCIAH:
 220         s->pom[1].pcia &= 0xffffffffULL;
 221         s->pom[1].pcia |= val << 32;
 222         ppc440_pcix_update_pom(s, 1);
 223         break;
 224     case PCIX0_POM2SA:
 225         s->pom[2].sa = val;
 226         break;
 227
 228     case PCIX0_PIM0SAL:
 229         s->pim[0].sa &= 0xffffffff00000000ULL;
 230         s->pim[0].sa |= val;
 231         ppc440_pcix_update_pim(s, 0);
 232         break;
 233     case PCIX0_PIM0LAL:
 234         s->pim[0].la &= 0xffffffff00000000ULL;
 235         s->pim[0].la |= val;
 236         ppc440_pcix_update_pim(s, 0);
 237         break;
 238     case PCIX0_PIM0LAH:
 239         s->pim[0].la &= 0xffffffffULL;
 240         s->pim[0].la |= val << 32;
 241         ppc440_pcix_update_pim(s, 0);
 242         break;
 243     case PCIX0_PIM1SA:
 244         s->pim[1].sa = val;
 245         ppc440_pcix_update_pim(s, 1);
 246         break;
 247     case PCIX0_PIM1LAL:
 248         s->pim[1].la &= 0xffffffff00000000ULL;
 249         s->pim[1].la |= val;
 250         ppc440_pcix_update_pim(s, 1);
 251         break;
 252     case PCIX0_PIM1LAH:
 253         s->pim[1].la &= 0xffffffffULL;
 254         s->pim[1].la |= val << 32;
 255         ppc440_pcix_update_pim(s, 1);
 256         break;
 257     case PCIX0_PIM2SAL:
 258         s->pim[2].sa &= 0xffffffff00000000ULL;
 259         s->pim[2].sa = val;
 260         ppc440_pcix_update_pim(s, 2);
 261         break;
 262     case PCIX0_PIM2LAL:
 263         s->pim[2].la &= 0xffffffff00000000ULL;
 264         s->pim[2].la |= val;
 265         ppc440_pcix_update_pim(s, 2);
 266         break;
 267     case PCIX0_PIM2LAH:
 268         s->pim[2].la &= 0xffffffffULL;
 269         s->pim[2].la |= val << 32;
 270         ppc440_pcix_update_pim(s, 2);
 271         break;
 272
 273     case PCIX0_STS:
 274         s->sts = val;
 275         break;
 276
 277     case PCIX0_PIM0SAH:
 278         s->pim[0].sa &= 0xffffffffULL;
 279         s->pim[0].sa |= val << 32;
 280         ppc440_pcix_update_pim(s, 0);
 281         break;
 282     case PCIX0_PIM2SAH:
 283         s->pim[2].sa &= 0xffffffffULL;
 284         s->pim[2].sa |= val << 32;
 285         ppc440_pcix_update_pim(s, 2);
 286         break;
 287
 288     default:
 289         error_report("%s: unhandled PCI internal register 0x%lx", __func__,
 290                      (unsigned long)addr);
 291         break;
 292     }
 293 }
 294
 295 static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr,
 296                                      unsigned size)
 297 {
 298     struct PPC440PCIXState *s = opaque;
 299     uint32_t val;
 300
 301     switch (addr) {
 302     case PCI_VENDOR_ID ... PCI_MAX_LAT:
 303         val = ldl_le_p(s->dev->config + addr);
 304         break;
 305
 306     case PCIX0_POM0LAL:
 307         val = s->pom[0].la;
 308         break;
 309     case PCIX0_POM0LAH:
 310         val = s->pom[0].la >> 32;
 311         break;
 312     case PCIX0_POM0SA:
 313         val = s->pom[0].sa;
 314         break;
 315     case PCIX0_POM0PCIAL:
 316         val = s->pom[0].pcia;
 317         break;
 318     case PCIX0_POM0PCIAH:
 319         val = s->pom[0].pcia >> 32;
 320         break;
 321     case PCIX0_POM1LAL:
 322         val = s->pom[1].la;
 323         break;
 324     case PCIX0_POM1LAH:
 325         val = s->pom[1].la >> 32;
 326         break;
 327     case PCIX0_POM1SA:
 328         val = s->pom[1].sa;
 329         break;
 330     case PCIX0_POM1PCIAL:
 331         val = s->pom[1].pcia;
 332         break;
 333     case PCIX0_POM1PCIAH:
 334         val = s->pom[1].pcia >> 32;
 335         break;
 336     case PCIX0_POM2SA:
 337         val = s->pom[2].sa;
 338         break;
 339
 340     case PCIX0_PIM0SAL:
 341         val = s->pim[0].sa;
 342         break;
 343     case PCIX0_PIM0LAL:
 344         val = s->pim[0].la;
 345         break;
 346     case PCIX0_PIM0LAH:
 347         val = s->pim[0].la >> 32;
 348         break;
 349     case PCIX0_PIM1SA:
 350         val = s->pim[1].sa;
 351         break;
 352     case PCIX0_PIM1LAL:
 353         val = s->pim[1].la;
 354         break;
 355     case PCIX0_PIM1LAH:
 356         val = s->pim[1].la >> 32;
 357         break;
 358     case PCIX0_PIM2SAL:
 359         val = s->pim[2].sa;
 360         break;
 361     case PCIX0_PIM2LAL:
 362         val = s->pim[2].la;
 363         break;
 364     case PCIX0_PIM2LAH:
 365         val = s->pim[2].la >> 32;
 366         break;
 367
 368     case PCIX0_STS:
 369         val = s->sts;
 370         break;
 371
 372     case PCIX0_PIM0SAH:
 373         val = s->pim[0].sa  >> 32;
 374         break;
 375     case PCIX0_PIM2SAH:
 376         val = s->pim[2].sa  >> 32;
 377         break;
 378
 379     default:
 380         error_report("%s: invalid PCI internal register 0x%lx", __func__,
 381                      (unsigned long)addr);
 382         val = 0;
 383     }
 384
 385     trace_ppc440_pcix_reg_read(addr, val);
 386     return val;
 387 }
 388
 389 static const MemoryRegionOps pci_reg_ops = {
 390     .read = ppc440_pcix_reg_read4,
 391     .write = ppc440_pcix_reg_write4,
 392     .endianness = DEVICE_LITTLE_ENDIAN,
 393 };
 394
 395 static void ppc440_pcix_reset(DeviceState *dev)
 396 {
 397     struct PPC440PCIXState *s = PPC440_PCIX_HOST_BRIDGE(dev);
 398     int i;
 399
 400     for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {
 401         ppc440_pcix_clear_region(get_system_memory(), &s->pom[i].mr);
 402     }
 403     for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
 404         ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr);
 405     }
 406     memset(s->pom, 0, sizeof(s->pom));
 407     memset(s->pim, 0, sizeof(s->pim));
 408     for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
 409         s->pim[i].sa = 0xffffffff00000000ULL;
 410     }
 411     s->sts = 0;
 412 }
 413
 414 /* All pins from each slot are tied to a single board IRQ.
 415  * This may need further refactoring for other boards. */
 416 static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
 417 {
 418     int slot = pci_dev->devfn >> 3;
 419     trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, slot);
 420     return slot - 1;
 421 }
 422
 423 static void ppc440_pcix_set_irq(void *opaque, int irq_num, int level)
 424 {
 425     qemu_irq *pci_irqs = opaque;
 426
 427     trace_ppc440_pcix_set_irq(irq_num);
 428     if (irq_num < 0) {
 429         error_report("%s: PCI irq %d", __func__, irq_num);
 430         return;
 431     }
 432     qemu_set_irq(pci_irqs[irq_num], level);
 433 }
 434
 435 static AddressSpace *ppc440_pcix_set_iommu(PCIBus *b, void *opaque, int devfn)
 436 {
 437     PPC440PCIXState *s = opaque;
 438
 439     return &s->bm_as;
 440 }
 441
 442 /* The default pci_host_data_{read,write} functions in pci/pci_host.c
 443  * deny access to registers without bit 31 set but our clients want
 444  * this to work so we have to override these here */
 445 static void pci_host_data_write(void *opaque, hwaddr addr,
 446                                 uint64_t val, unsigned len)
 447 {
 448     PCIHostState *s = opaque;
 449     pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 450 }
 451
 452 static uint64_t pci_host_data_read(void *opaque,
 453                                    hwaddr addr, unsigned len)
 454 {
 455     PCIHostState *s = opaque;
 456     uint32_t val;
 457     val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 458     return val;
 459 }
 460
 461 const MemoryRegionOps ppc440_pcix_host_data_ops = {
 462     .read = pci_host_data_read,
 463     .write = pci_host_data_write,
 464     .endianness = DEVICE_LITTLE_ENDIAN,
 465 };
 466
 467 static int ppc440_pcix_initfn(SysBusDevice *dev)
 468 {
 469     PPC440PCIXState *s;
 470     PCIHostState *h;
 471     int i;
 472
 473     h = PCI_HOST_BRIDGE(dev);
 474     s = PPC440_PCIX_HOST_BRIDGE(dev);
 475
 476     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 477         sysbus_init_irq(dev, &s->irq[i]);
 478     }
 479
 480     memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
 481     h->bus = pci_register_root_bus(DEVICE(dev), NULL, ppc440_pcix_set_irq,
 482                          ppc440_pcix_map_irq, s->irq, &s->busmem,
 483                          get_system_io(), PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
 484
 485     s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bridge");
 486
 487     memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
 488     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
 489     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 490     pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);
 491
 492     memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
 493     memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops,
 494                           h, "pci-conf-idx", 4);
 495     memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_ops,
 496                           h, "pci-conf-data", 4);
 497     memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
 498                           "pci.reg", PPC440_REG_SIZE);
 499     memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
 500     memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
 501     memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
 502     sysbus_init_mmio(dev, &s->container);
 503
 504     return 0;
 505 }
 506
 507 static void ppc440_pcix_class_init(ObjectClass *klass, void *data)
 508 {
 509     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 510     DeviceClass *dc = DEVICE_CLASS(klass);
 511
 512     k->init = ppc440_pcix_initfn;
 513     dc->reset = ppc440_pcix_reset;
 514 }
 515
 516 static const TypeInfo ppc440_pcix_info = {
 517     .name          = TYPE_PPC440_PCIX_HOST_BRIDGE,
 518     .parent        = TYPE_PCI_HOST_BRIDGE,
 519     .instance_size = sizeof(PPC440PCIXState),
 520     .class_init    = ppc440_pcix_class_init,
 521 };
 522
 523 static void ppc440_pcix_register_types(void)
 524 {
 525     type_register_static(&ppc440_pcix_info);
 526 }
 527
 528 type_init(ppc440_pcix_register_types)