hw/intc/ompic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Authors: Stafford Horne <shorne@gmail.com>
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qemu/log.h"
  11 #include "qemu/module.h"
  12 #include "qapi/error.h"
  13 #include "hw/irq.h"
  14 #include "hw/qdev-properties.h"
  15 #include "hw/sysbus.h"
  16 #include "migration/vmstate.h"
  17 #include "exec/memory.h"
  18 #include "qom/object.h"
  19
  20 #define TYPE_OR1K_OMPIC "or1k-ompic"
  21 typedef struct OR1KOMPICState OR1KOMPICState;
  22 DECLARE_INSTANCE_CHECKER(OR1KOMPICState, OR1K_OMPIC,
  23                          TYPE_OR1K_OMPIC)
  24
  25 #define OMPIC_CTRL_IRQ_ACK  (1 << 31)
  26 #define OMPIC_CTRL_IRQ_GEN  (1 << 30)
  27 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff)
  28
  29 #define OMPIC_REG(addr)     (((addr) >> 2) & 0x1)
  30 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f)
  31 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f)
  32
  33 #define OMPIC_STATUS_IRQ_PENDING (1 << 30)
  34 #define OMPIC_STATUS_SRC(cpu)    (((cpu) & 0x3fff) << 16)
  35 #define OMPIC_STATUS_DATA(data)  ((data) & 0xffff)
  36
  37 #define OMPIC_CONTROL 0
  38 #define OMPIC_STATUS  1
  39
  40 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */
  41 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */
  42
  43 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState;
  44
  45 struct OR1KOMPICCPUState {
  46     qemu_irq irq;
  47     uint32_t status;
  48     uint32_t control;
  49 };
  50
  51 struct OR1KOMPICState {
  52     SysBusDevice parent_obj;
  53     MemoryRegion mr;
  54
  55     OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS];
  56
  57     uint32_t num_cpus;
  58 };
  59
  60 static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size)
  61 {
  62     OR1KOMPICState *s = opaque;
  63     int src_cpu = OMPIC_SRC_CPU(addr);
  64
  65     /* We can only write to control control, write control + update status */
  66     if (OMPIC_REG(addr) == OMPIC_CONTROL) {
  67         return s->cpus[src_cpu].control;
  68     } else {
  69         return s->cpus[src_cpu].status;
  70    }
  71
  72 }
  73
  74 static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
  75 {
  76     OR1KOMPICState *s = opaque;
  77     /* We can only write to control control, write control + update status */
  78     if (OMPIC_REG(addr) == OMPIC_CONTROL) {
  79         int src_cpu = OMPIC_SRC_CPU(addr);
  80
  81         s->cpus[src_cpu].control = data;
  82
  83         if (data & OMPIC_CTRL_IRQ_GEN) {
  84             int dst_cpu = OMPIC_CTRL_DST(data);
  85
  86             s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING |
  87                 OMPIC_STATUS_SRC(src_cpu) |
  88                 OMPIC_STATUS_DATA(data);
  89
  90             qemu_irq_raise(s->cpus[dst_cpu].irq);
  91         }
  92         if (data & OMPIC_CTRL_IRQ_ACK) {
  93             s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING;
  94             qemu_irq_lower(s->cpus[src_cpu].irq);
  95         }
  96     }
  97 }
  98
  99 static const MemoryRegionOps ompic_ops = {
 100     .read = ompic_read,
 101     .write = ompic_write,
 102     .endianness = DEVICE_NATIVE_ENDIAN,
 103     .impl = {
 104         .max_access_size = 8,
 105     },
 106 };
 107
 108 static void or1k_ompic_init(Object *obj)
 109 {
 110     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 111     OR1KOMPICState *s = OR1K_OMPIC(obj);
 112
 113     memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s,
 114                           "or1k-ompic", OMPIC_ADDRSPACE_SZ);
 115     sysbus_init_mmio(sbd, &s->mr);
 116 }
 117
 118 static void or1k_ompic_realize(DeviceState *dev, Error **errp)
 119 {
 120     OR1KOMPICState *s = OR1K_OMPIC(dev);
 121     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 122     int i;
 123
 124     if (s->num_cpus > OMPIC_MAX_CPUS) {
 125         error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus);
 126         return;
 127     }
 128     /* Init IRQ sources for all CPUs */
 129     for (i = 0; i < s->num_cpus; i++) {
 130         sysbus_init_irq(sbd, &s->cpus[i].irq);
 131     }
 132 }
 133
 134 static Property or1k_ompic_properties[] = {
 135     DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1),
 136     DEFINE_PROP_END_OF_LIST(),
 137 };
 138
 139 static const VMStateDescription vmstate_or1k_ompic_cpu = {
 140     .name = "or1k_ompic_cpu",
 141     .version_id = 1,
 142     .minimum_version_id = 1,
 143     .fields = (VMStateField[]) {
 144          VMSTATE_UINT32(status, OR1KOMPICCPUState),
 145          VMSTATE_UINT32(control, OR1KOMPICCPUState),
 146          VMSTATE_END_OF_LIST()
 147     }
 148 };
 149
 150 static const VMStateDescription vmstate_or1k_ompic = {
 151     .name = TYPE_OR1K_OMPIC,
 152     .version_id = 1,
 153     .minimum_version_id = 1,
 154     .fields = (VMStateField[]) {
 155          VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1,
 156              vmstate_or1k_ompic_cpu, OR1KOMPICCPUState),
 157          VMSTATE_UINT32(num_cpus, OR1KOMPICState),
 158          VMSTATE_END_OF_LIST()
 159     }
 160 };
 161
 162 static void or1k_ompic_class_init(ObjectClass *klass, void *data)
 163 {
 164     DeviceClass *dc = DEVICE_CLASS(klass);
 165
 166     device_class_set_props(dc, or1k_ompic_properties);
 167     dc->realize = or1k_ompic_realize;
 168     dc->vmsd = &vmstate_or1k_ompic;
 169 }
 170
 171 static const TypeInfo or1k_ompic_info = {
 172     .name          = TYPE_OR1K_OMPIC,
 173     .parent        = TYPE_SYS_BUS_DEVICE,
 174     .instance_size = sizeof(OR1KOMPICState),
 175     .instance_init = or1k_ompic_init,
 176     .class_init    = or1k_ompic_class_init,
 177 };
 178
 179 static void or1k_ompic_register_types(void)
 180 {
 181     type_register_static(&or1k_ompic_info);
 182 }
 183
 184 type_init(or1k_ompic_register_types)