hw/intc/arm_gicv2m.c

   1 /*
   2  *  GICv2m extension for MSI/MSI-x support with a GICv2-based system
   3  *
   4  * Copyright (C) 2015 Linaro, All rights reserved.
   5  *
   6  * Author: Christoffer Dall <christoffer.dall@linaro.org>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /* This file implements an emulated GICv2m widget as described in the ARM
  23  * Server Base System Architecture (SBSA) specification Version 2.2
  24  * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
  25  * identification registers and with a single non-secure MSI register frame.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/irq.h"
  32 #include "hw/pci/msi.h"
  33 #include "hw/qdev-properties.h"
  34 #include "sysemu/kvm.h"
  35 #include "qemu/log.h"
  36 #include "qemu/module.h"
  37 #include "qom/object.h"
  38
  39 #define TYPE_ARM_GICV2M "arm-gicv2m"
  40 typedef struct ARMGICv2mState ARMGICv2mState;
  41 DECLARE_INSTANCE_CHECKER(ARMGICv2mState, ARM_GICV2M,
  42                          TYPE_ARM_GICV2M)
  43
  44 #define GICV2M_NUM_SPI_MAX 128
  45
  46 #define V2M_MSI_TYPER           0x008
  47 #define V2M_MSI_SETSPI_NS       0x040
  48 #define V2M_MSI_IIDR            0xFCC
  49 #define V2M_IIDR0               0xFD0
  50 #define V2M_IIDR11              0xFFC
  51
  52 #define PRODUCT_ID_QEMU         0x51 /* ASCII code Q */
  53
  54 struct ARMGICv2mState {
  55     SysBusDevice parent_obj;
  56
  57     MemoryRegion iomem;
  58     qemu_irq spi[GICV2M_NUM_SPI_MAX];
  59
  60     uint32_t base_spi;
  61     uint32_t num_spi;
  62 };
  63
  64 static void gicv2m_set_irq(void *opaque, int irq)
  65 {
  66     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  67
  68     qemu_irq_pulse(s->spi[irq]);
  69 }
  70
  71 static uint64_t gicv2m_read(void *opaque, hwaddr offset,
  72                             unsigned size)
  73 {
  74     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  75     uint32_t val;
  76
  77     if (size != 4) {
  78         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size);
  79         return 0;
  80     }
  81
  82     switch (offset) {
  83     case V2M_MSI_TYPER:
  84         val = (s->base_spi + 32) << 16;
  85         val |= s->num_spi;
  86         return val;
  87     case V2M_MSI_IIDR:
  88         /* We don't have any valid implementor so we leave that field as zero
  89          * and we return 0 in the arch revision as per the spec.
  90          */
  91         return (PRODUCT_ID_QEMU << 20);
  92     case V2M_IIDR0 ... V2M_IIDR11:
  93         /* We do not implement any optional identification registers and the
  94          * mandatory MSI_PIDR2 register reads as 0x0, so we capture all
  95          * implementation defined registers here.
  96          */
  97         return 0;
  98     default:
  99         qemu_log_mask(LOG_GUEST_ERROR,
 100                       "gicv2m_read: Bad offset %x\n", (int)offset);
 101         return 0;
 102     }
 103 }
 104
 105 static void gicv2m_write(void *opaque, hwaddr offset,
 106                         uint64_t value, unsigned size)
 107 {
 108     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
 109
 110     if (size != 2 && size != 4) {
 111         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size);
 112         return;
 113     }
 114
 115     switch (offset) {
 116     case V2M_MSI_SETSPI_NS: {
 117         int spi;
 118
 119         spi = (value & 0x3ff) - (s->base_spi + 32);
 120         if (spi >= 0 && spi < s->num_spi) {
 121             gicv2m_set_irq(s, spi);
 122         }
 123         return;
 124     }
 125     default:
 126         qemu_log_mask(LOG_GUEST_ERROR,
 127                       "gicv2m_write: Bad offset %x\n", (int)offset);
 128     }
 129 }
 130
 131 static const MemoryRegionOps gicv2m_ops = {
 132     .read = gicv2m_read,
 133     .write = gicv2m_write,
 134     .endianness = DEVICE_LITTLE_ENDIAN,
 135 };
 136
 137 static void gicv2m_realize(DeviceState *dev, Error **errp)
 138 {
 139     ARMGICv2mState *s = ARM_GICV2M(dev);
 140     int i;
 141
 142     if (s->num_spi > GICV2M_NUM_SPI_MAX) {
 143         error_setg(errp,
 144                    "requested %u SPIs exceeds GICv2m frame maximum %d",
 145                    s->num_spi, GICV2M_NUM_SPI_MAX);
 146         return;
 147     }
 148
 149     if (s->base_spi + 32 > 1020 - s->num_spi) {
 150         error_setg(errp,
 151                    "requested base SPI %u+%u exceeds max. number 1020",
 152                    s->base_spi + 32, s->num_spi);
 153         return;
 154     }
 155
 156     for (i = 0; i < s->num_spi; i++) {
 157         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]);
 158     }
 159
 160     msi_nonbroken = true;
 161     kvm_gsi_direct_mapping = true;
 162     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 163 }
 164
 165 static void gicv2m_init(Object *obj)
 166 {
 167     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 168     ARMGICv2mState *s = ARM_GICV2M(obj);
 169
 170     memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s,
 171                           "gicv2m", 0x1000);
 172     sysbus_init_mmio(sbd, &s->iomem);
 173 }
 174
 175 static Property gicv2m_properties[] = {
 176     DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
 177     DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
 178     DEFINE_PROP_END_OF_LIST(),
 179 };
 180
 181 static void gicv2m_class_init(ObjectClass *klass, void *data)
 182 {
 183     DeviceClass *dc = DEVICE_CLASS(klass);
 184
 185     device_class_set_props(dc, gicv2m_properties);
 186     dc->realize = gicv2m_realize;
 187 }
 188
 189 static const TypeInfo gicv2m_info = {
 190     .name          = TYPE_ARM_GICV2M,
 191     .parent        = TYPE_SYS_BUS_DEVICE,
 192     .instance_size = sizeof(ARMGICv2mState),
 193     .instance_init = gicv2m_init,
 194     .class_init    = gicv2m_class_init,
 195 };
 196
 197 static void gicv2m_register_types(void)
 198 {
 199     type_register_static(&gicv2m_info);
 200 }
 201
 202 type_init(gicv2m_register_types)