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target/ppc: turned SPR R/W callbacks not static
[qemu/ar7.git] / target / ppc / translate.c
blobaba9cf0a40b4846002299355baaa4d865986323f
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
37 #include "exec/log.h"
38 #include "qemu/atomic128.h"
39 #include "spr_tcg.h"
40
41
42 #define CPU_SINGLE_STEP 0x1
43 #define CPU_BRANCH_STEP 0x2
44 #define GDBSTUB_SINGLE_STEP 0x4
45
46 /* Include definitions for instructions classes and implementations flags */
47 /* #define PPC_DEBUG_DISAS */
48 /* #define DO_PPC_STATISTICS */
49
50 #ifdef PPC_DEBUG_DISAS
51 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
52 #else
53 # define LOG_DISAS(...) do { } while (0)
54 #endif
55 /*****************************************************************************/
56 /* Code translation helpers */
57
58 /* global register indexes */
59 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
60 + 10 * 4 + 22 * 5 /* SPE GPRh */
61 + 8 * 5 /* CRF */];
62 static TCGv cpu_gpr[32];
63 static TCGv cpu_gprh[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_msr;
67 static TCGv cpu_ctr;
68 static TCGv cpu_lr;
69 #if defined(TARGET_PPC64)
70 static TCGv cpu_cfar;
71 #endif
72 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
73 static TCGv cpu_reserve;
74 static TCGv cpu_reserve_val;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char *p;
84 size_t cpu_reg_names_size;
85
86 p = cpu_reg_names;
87 cpu_reg_names_size = sizeof(cpu_reg_names);
88
89 for (i = 0; i < 8; i++) {
90 snprintf(p, cpu_reg_names_size, "crf%d", i);
91 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
92 offsetof(CPUPPCState, crf[i]), p);
93 p += 5;
94 cpu_reg_names_size -= 5;
95 }
96
97 for (i = 0; i < 32; i++) {
98 snprintf(p, cpu_reg_names_size, "r%d", i);
99 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
100 offsetof(CPUPPCState, gpr[i]), p);
101 p += (i < 10) ? 3 : 4;
102 cpu_reg_names_size -= (i < 10) ? 3 : 4;
103 snprintf(p, cpu_reg_names_size, "r%dH", i);
104 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
105 offsetof(CPUPPCState, gprh[i]), p);
106 p += (i < 10) ? 4 : 5;
107 cpu_reg_names_size -= (i < 10) ? 4 : 5;
108 }
109
110 cpu_nip = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, nip), "nip");
112
113 cpu_msr = tcg_global_mem_new(cpu_env,
114 offsetof(CPUPPCState, msr), "msr");
115
116 cpu_ctr = tcg_global_mem_new(cpu_env,
117 offsetof(CPUPPCState, ctr), "ctr");
118
119 cpu_lr = tcg_global_mem_new(cpu_env,
120 offsetof(CPUPPCState, lr), "lr");
121
122 #if defined(TARGET_PPC64)
123 cpu_cfar = tcg_global_mem_new(cpu_env,
124 offsetof(CPUPPCState, cfar), "cfar");
125 #endif
126
127 cpu_xer = tcg_global_mem_new(cpu_env,
128 offsetof(CPUPPCState, xer), "xer");
129 cpu_so = tcg_global_mem_new(cpu_env,
130 offsetof(CPUPPCState, so), "SO");
131 cpu_ov = tcg_global_mem_new(cpu_env,
132 offsetof(CPUPPCState, ov), "OV");
133 cpu_ca = tcg_global_mem_new(cpu_env,
134 offsetof(CPUPPCState, ca), "CA");
135 cpu_ov32 = tcg_global_mem_new(cpu_env,
136 offsetof(CPUPPCState, ov32), "OV32");
137 cpu_ca32 = tcg_global_mem_new(cpu_env,
138 offsetof(CPUPPCState, ca32), "CA32");
139
140 cpu_reserve = tcg_global_mem_new(cpu_env,
141 offsetof(CPUPPCState, reserve_addr),
142 "reserve_addr");
143 cpu_reserve_val = tcg_global_mem_new(cpu_env,
144 offsetof(CPUPPCState, reserve_val),
145 "reserve_val");
146
147 cpu_fpscr = tcg_global_mem_new(cpu_env,
148 offsetof(CPUPPCState, fpscr), "fpscr");
149
150 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
151 offsetof(CPUPPCState, access_type),
152 "access_type");
153 }
154
155 /* internal defines */
156 struct DisasContext {
157 DisasContextBase base;
158 uint32_t opcode;
159 uint32_t exception;
160 /* Routine used to access memory */
161 bool pr, hv, dr, le_mode;
162 bool lazy_tlb_flush;
163 bool need_access_type;
164 int mem_idx;
165 int access_type;
166 /* Translation flags */
167 MemOp default_tcg_memop_mask;
168 #if defined(TARGET_PPC64)
169 bool sf_mode;
170 bool has_cfar;
171 #endif
172 bool fpu_enabled;
173 bool altivec_enabled;
174 bool vsx_enabled;
175 bool spe_enabled;
176 bool tm_enabled;
177 bool gtse;
178 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
179 int singlestep_enabled;
180 uint32_t flags;
181 uint64_t insns_flags;
182 uint64_t insns_flags2;
183 };
184
185 /* Return true iff byteswap is needed in a scalar memop */
186 static inline bool need_byteswap(const DisasContext *ctx)
187 {
188 #if defined(TARGET_WORDS_BIGENDIAN)
189 return ctx->le_mode;
190 #else
191 return !ctx->le_mode;
192 #endif
193 }
194
195 /* True when active word size < size of target_long. */
196 #ifdef TARGET_PPC64
197 # define NARROW_MODE(C) (!(C)->sf_mode)
198 #else
199 # define NARROW_MODE(C) 0
200 #endif
201
202 struct opc_handler_t {
203 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
204 uint32_t inval1;
205 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
206 uint32_t inval2;
207 /* instruction type */
208 uint64_t type;
209 /* extended instruction type */
210 uint64_t type2;
211 /* handler */
212 void (*handler)(DisasContext *ctx);
213 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
214 const char *oname;
215 #endif
216 #if defined(DO_PPC_STATISTICS)
217 uint64_t count;
218 #endif
219 };
220
221 /* SPR load/store helpers */
222 static inline void gen_load_spr(TCGv t, int reg)
223 {
224 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
225 }
226
227 static inline void gen_store_spr(int reg, TCGv t)
228 {
229 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
230 }
231
232 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
233 {
234 if (ctx->need_access_type && ctx->access_type != access_type) {
235 tcg_gen_movi_i32(cpu_access_type, access_type);
236 ctx->access_type = access_type;
237 }
238 }
239
240 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
241 {
242 if (NARROW_MODE(ctx)) {
243 nip = (uint32_t)nip;
244 }
245 tcg_gen_movi_tl(cpu_nip, nip);
246 }
247
248 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
249 {
250 TCGv_i32 t0, t1;
251
252 /*
253 * These are all synchronous exceptions, we set the PC back to the
254 * faulting instruction
255 */
256 if (ctx->exception == POWERPC_EXCP_NONE) {
257 gen_update_nip(ctx, ctx->base.pc_next - 4);
258 }
259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
261 gen_helper_raise_exception_err(cpu_env, t0, t1);
262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
264 ctx->exception = (excp);
265 }
266
267 static void gen_exception(DisasContext *ctx, uint32_t excp)
268 {
269 TCGv_i32 t0;
270
271 /*
272 * These are all synchronous exceptions, we set the PC back to the
273 * faulting instruction
274 */
275 if (ctx->exception == POWERPC_EXCP_NONE) {
276 gen_update_nip(ctx, ctx->base.pc_next - 4);
277 }
278 t0 = tcg_const_i32(excp);
279 gen_helper_raise_exception(cpu_env, t0);
280 tcg_temp_free_i32(t0);
281 ctx->exception = (excp);
282 }
283
284 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
285 target_ulong nip)
286 {
287 TCGv_i32 t0;
288
289 gen_update_nip(ctx, nip);
290 t0 = tcg_const_i32(excp);
291 gen_helper_raise_exception(cpu_env, t0);
292 tcg_temp_free_i32(t0);
293 ctx->exception = (excp);
294 }
295
296 /*
297 * Tells the caller what is the appropriate exception to generate and prepares
298 * SPR registers for this exception.
299 *
300 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
301 * POWERPC_EXCP_DEBUG (on BookE).
302 */
303 static uint32_t gen_prep_dbgex(DisasContext *ctx)
304 {
305 if (ctx->flags & POWERPC_FLAG_DE) {
306 target_ulong dbsr = 0;
307 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
308 dbsr = DBCR0_ICMP;
309 } else {
310 /* Must have been branch */
311 dbsr = DBCR0_BRT;
312 }
313 TCGv t0 = tcg_temp_new();
314 gen_load_spr(t0, SPR_BOOKE_DBSR);
315 tcg_gen_ori_tl(t0, t0, dbsr);
316 gen_store_spr(SPR_BOOKE_DBSR, t0);
317 tcg_temp_free(t0);
318 return POWERPC_EXCP_DEBUG;
319 } else {
320 return POWERPC_EXCP_TRACE;
321 }
322 }
323
324 static void gen_debug_exception(DisasContext *ctx)
325 {
326 TCGv_i32 t0;
327
328 /*
329 * These are all synchronous exceptions, we set the PC back to the
330 * faulting instruction
331 */
332 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
333 (ctx->exception != POWERPC_EXCP_SYNC)) {
334 gen_update_nip(ctx, ctx->base.pc_next);
335 }
336 t0 = tcg_const_i32(EXCP_DEBUG);
337 gen_helper_raise_exception(cpu_env, t0);
338 tcg_temp_free_i32(t0);
339 }
340
341 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
342 {
343 /* Will be converted to program check if needed */
344 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
345 }
346
347 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
348 {
349 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
350 }
351
352 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
353 {
354 /* Will be converted to program check if needed */
355 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
356 }
357
358 /* Stop translation */
359 static inline void gen_stop_exception(DisasContext *ctx)
360 {
361 gen_update_nip(ctx, ctx->base.pc_next);
362 ctx->exception = POWERPC_EXCP_STOP;
363 }
364
365 #ifndef CONFIG_USER_ONLY
366 /* No need to update nip here, as execution flow will change */
367 static inline void gen_sync_exception(DisasContext *ctx)
368 {
369 ctx->exception = POWERPC_EXCP_SYNC;
370 }
371 #endif
372
373 /*****************************************************************************/
374 /* SPR READ/WRITE CALLBACKS */
375
376 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
377 {
378 #if 0
379 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
380 printf("ERROR: try to access SPR %d !\n", sprn);
381 #endif
382 }
383 #define SPR_NOACCESS (&spr_noaccess)
384
385 /* #define PPC_DUMP_SPR_ACCESSES */
386
387 /*
388 * Generic callbacks:
389 * do nothing but store/retrieve spr value
390 */
391 static void spr_load_dump_spr(int sprn)
392 {
393 #ifdef PPC_DUMP_SPR_ACCESSES
394 TCGv_i32 t0 = tcg_const_i32(sprn);
395 gen_helper_load_dump_spr(cpu_env, t0);
396 tcg_temp_free_i32(t0);
397 #endif
398 }
399
400 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
401 {
402 gen_load_spr(cpu_gpr[gprn], sprn);
403 spr_load_dump_spr(sprn);
404 }
405
406 static void spr_store_dump_spr(int sprn)
407 {
408 #ifdef PPC_DUMP_SPR_ACCESSES
409 TCGv_i32 t0 = tcg_const_i32(sprn);
410 gen_helper_store_dump_spr(cpu_env, t0);
411 tcg_temp_free_i32(t0);
412 #endif
413 }
414
415 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
416 {
417 gen_store_spr(sprn, cpu_gpr[gprn]);
418 spr_store_dump_spr(sprn);
419 }
420
421 #if !defined(CONFIG_USER_ONLY)
422 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
423 {
424 #ifdef TARGET_PPC64
425 TCGv t0 = tcg_temp_new();
426 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
427 gen_store_spr(sprn, t0);
428 tcg_temp_free(t0);
429 spr_store_dump_spr(sprn);
430 #else
431 spr_write_generic(ctx, sprn, gprn);
432 #endif
433 }
434
435 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
436 {
437 TCGv t0 = tcg_temp_new();
438 TCGv t1 = tcg_temp_new();
439 gen_load_spr(t0, sprn);
440 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
441 tcg_gen_and_tl(t0, t0, t1);
442 gen_store_spr(sprn, t0);
443 tcg_temp_free(t0);
444 tcg_temp_free(t1);
445 }
446
447 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
448 {
449 }
450
451 #endif
452
453 /* SPR common to all PowerPC */
454 /* XER */
455 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
456 {
457 TCGv dst = cpu_gpr[gprn];
458 TCGv t0 = tcg_temp_new();
459 TCGv t1 = tcg_temp_new();
460 TCGv t2 = tcg_temp_new();
461 tcg_gen_mov_tl(dst, cpu_xer);
462 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
463 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
464 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
465 tcg_gen_or_tl(t0, t0, t1);
466 tcg_gen_or_tl(dst, dst, t2);
467 tcg_gen_or_tl(dst, dst, t0);
468 if (is_isa300(ctx)) {
469 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
470 tcg_gen_or_tl(dst, dst, t0);
471 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
472 tcg_gen_or_tl(dst, dst, t0);
473 }
474 tcg_temp_free(t0);
475 tcg_temp_free(t1);
476 tcg_temp_free(t2);
477 }
478
479 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
480 {
481 TCGv src = cpu_gpr[gprn];
482 /* Write all flags, while reading back check for isa300 */
483 tcg_gen_andi_tl(cpu_xer, src,
484 ~((1u << XER_SO) |
485 (1u << XER_OV) | (1u << XER_OV32) |
486 (1u << XER_CA) | (1u << XER_CA32)));
487 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
488 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
489 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
490 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
491 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
492 }
493
494 /* LR */
495 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
496 {
497 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
498 }
499
500 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
501 {
502 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
503 }
504
505 /* CFAR */
506 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
507 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
508 {
509 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
510 }
511
512 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
513 {
514 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
515 }
516 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
517
518 /* CTR */
519 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
520 {
521 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
522 }
523
524 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
525 {
526 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
527 }
528
529 /* User read access to SPR */
530 /* USPRx */
531 /* UMMCRx */
532 /* UPMCx */
533 /* USIA */
534 /* UDECR */
535 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
536 {
537 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
538 }
539
540 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
541 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
542 {
543 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
544 }
545 #endif
546
547 /* SPR common to all non-embedded PowerPC */
548 /* DECR */
549 #if !defined(CONFIG_USER_ONLY)
550 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
551 {
552 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
553 gen_io_start();
554 }
555 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
556 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
557 gen_stop_exception(ctx);
558 }
559 }
560
561 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
562 {
563 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
564 gen_io_start();
565 }
566 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
567 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
568 gen_stop_exception(ctx);
569 }
570 }
571 #endif
572
573 /* SPR common to all non-embedded PowerPC, except 601 */
574 /* Time base */
575 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
576 {
577 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
578 gen_io_start();
579 }
580 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
581 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
582 gen_io_end();
583 gen_stop_exception(ctx);
584 }
585 }
586
587 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
588 {
589 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
590 gen_io_start();
591 }
592 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
593 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
594 gen_io_end();
595 gen_stop_exception(ctx);
596 }
597 }
598
599 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
600 {
601 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
602 }
603
604 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
605 {
606 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
607 }
608
609 #if !defined(CONFIG_USER_ONLY)
610 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
611 {
612 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
613 gen_io_start();
614 }
615 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
616 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
617 gen_io_end();
618 gen_stop_exception(ctx);
619 }
620 }
621
622 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
623 {
624 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
625 gen_io_start();
626 }
627 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
628 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
629 gen_io_end();
630 gen_stop_exception(ctx);
631 }
632 }
633
634 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
635 {
636 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
637 }
638
639 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
640 {
641 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
642 }
643
644 #if defined(TARGET_PPC64)
645 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
646 {
647 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
648 gen_io_start();
649 }
650 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
651 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
652 gen_stop_exception(ctx);
653 }
654 }
655
656 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
657 {
658 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
659 gen_io_start();
660 }
661 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
662 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
663 gen_stop_exception(ctx);
664 }
665 }
666
667 /* HDECR */
668 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
669 {
670 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
671 gen_io_start();
672 }
673 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
674 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
675 gen_io_end();
676 gen_stop_exception(ctx);
677 }
678 }
679
680 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
681 {
682 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
683 gen_io_start();
684 }
685 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
686 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
687 gen_io_end();
688 gen_stop_exception(ctx);
689 }
690 }
691
692 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
693 {
694 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
695 gen_io_start();
696 }
697 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
698 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
699 gen_stop_exception(ctx);
700 }
701 }
702
703 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
704 {
705 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
706 gen_io_start();
707 }
708 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
709 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
710 gen_stop_exception(ctx);
711 }
712 }
713
714 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
715 {
716 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
717 gen_io_start();
718 }
719 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
720 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
721 gen_stop_exception(ctx);
722 }
723 }
724
725 #endif
726 #endif
727
728 #if !defined(CONFIG_USER_ONLY)
729 /* IBAT0U...IBAT0U */
730 /* IBAT0L...IBAT7L */
731 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
732 {
733 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
734 offsetof(CPUPPCState,
735 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
736 }
737
738 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
739 {
740 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
741 offsetof(CPUPPCState,
742 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
743 }
744
745 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
746 {
747 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
748 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
749 tcg_temp_free_i32(t0);
750 }
751
752 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
753 {
754 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
755 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
756 tcg_temp_free_i32(t0);
757 }
758
759 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
760 {
761 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
762 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
763 tcg_temp_free_i32(t0);
764 }
765
766 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
767 {
768 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
769 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
770 tcg_temp_free_i32(t0);
771 }
772
773 /* DBAT0U...DBAT7U */
774 /* DBAT0L...DBAT7L */
775 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
776 {
777 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
778 offsetof(CPUPPCState,
779 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
780 }
781
782 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
783 {
784 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
785 offsetof(CPUPPCState,
786 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
787 }
788
789 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
790 {
791 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
792 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
793 tcg_temp_free_i32(t0);
794 }
795
796 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
797 {
798 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
799 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
800 tcg_temp_free_i32(t0);
801 }
802
803 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
804 {
805 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
806 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
807 tcg_temp_free_i32(t0);
808 }
809
810 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
811 {
812 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
813 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
814 tcg_temp_free_i32(t0);
815 }
816
817 /* SDR1 */
818 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
819 {
820 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
821 }
822
823 #if defined(TARGET_PPC64)
824 /* 64 bits PowerPC specific SPRs */
825 /* PIDR */
826 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
827 {
828 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
829 }
830
831 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
832 {
833 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
834 }
835
836 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
837 {
838 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
839 }
840
841 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
842 {
843 TCGv t0 = tcg_temp_new();
844 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
845 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
846 tcg_temp_free(t0);
847 }
848 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
849 {
850 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
851 }
852
853 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
854 {
855 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
856 }
857
858 /* DPDES */
859 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
860 {
861 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
862 }
863
864 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
865 {
866 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
867 }
868 #endif
869 #endif
870
871 /* PowerPC 601 specific registers */
872 /* RTC */
873 void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
874 {
875 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
876 }
877
878 void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
879 {
880 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
881 }
882
883 #if !defined(CONFIG_USER_ONLY)
884 void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
885 {
886 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
887 }
888
889 void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
890 {
891 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
892 }
893
894 void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
895 {
896 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
897 /* Must stop the translation as endianness may have changed */
898 gen_stop_exception(ctx);
899 }
900 #endif
901
902 /* Unified bats */
903 #if !defined(CONFIG_USER_ONLY)
904 void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
905 {
906 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
907 offsetof(CPUPPCState,
908 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
909 }
910
911 void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
912 {
913 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
914 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
915 tcg_temp_free_i32(t0);
916 }
917
918 void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
919 {
920 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
921 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
922 tcg_temp_free_i32(t0);
923 }
924 #endif
925
926 /* PowerPC 40x specific registers */
927 #if !defined(CONFIG_USER_ONLY)
928 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
929 {
930 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
931 gen_io_start();
932 }
933 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
934 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
935 gen_stop_exception(ctx);
936 }
937 }
938
939 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
940 {
941 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
942 gen_io_start();
943 }
944 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
945 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
946 gen_stop_exception(ctx);
947 }
948 }
949
950 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
951 {
952 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
953 gen_io_start();
954 }
955 gen_store_spr(sprn, cpu_gpr[gprn]);
956 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
957 /* We must stop translation as we may have rebooted */
958 gen_stop_exception(ctx);
959 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
960 gen_stop_exception(ctx);
961 }
962 }
963
964 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
965 {
966 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
967 gen_io_start();
968 }
969 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
970 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
971 gen_stop_exception(ctx);
972 }
973 }
974
975 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
976 {
977 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
978 gen_io_start();
979 }
980 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
981 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
982 gen_stop_exception(ctx);
983 }
984 }
985
986 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
987 {
988 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
989 gen_io_start();
990 }
991 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
992 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
993 gen_stop_exception(ctx);
994 }
995 }
996 #endif
997
998 /* PowerPC 403 specific registers */
999 /* PBL1 / PBU1 / PBL2 / PBU2 */
1000 #if !defined(CONFIG_USER_ONLY)
1001 void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
1002 {
1003 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
1004 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
1005 }
1006
1007 void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
1008 {
1009 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
1010 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
1011 tcg_temp_free_i32(t0);
1012 }
1013
1014 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
1015 {
1016 TCGv t0 = tcg_temp_new();
1017 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
1018 gen_store_spr(SPR_PIR, t0);
1019 tcg_temp_free(t0);
1020 }
1021 #endif
1022
1023 /* SPE specific registers */
1024 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
1025 {
1026 TCGv_i32 t0 = tcg_temp_new_i32();
1027 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
1028 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
1029 tcg_temp_free_i32(t0);
1030 }
1031
1032 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
1033 {
1034 TCGv_i32 t0 = tcg_temp_new_i32();
1035 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1036 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
1037 tcg_temp_free_i32(t0);
1038 }
1039
1040 #if !defined(CONFIG_USER_ONLY)
1041 /* Callback used to write the exception vector base */
1042 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
1043 {
1044 TCGv t0 = tcg_temp_new();
1045 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
1046 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1047 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
1048 gen_store_spr(sprn, t0);
1049 tcg_temp_free(t0);
1050 }
1051
1052 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
1053 {
1054 int sprn_offs;
1055
1056 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
1057 sprn_offs = sprn - SPR_BOOKE_IVOR0;
1058 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
1059 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
1060 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
1061 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
1062 } else {
1063 printf("Trying to write an unknown exception vector %d %03x\n",
1064 sprn, sprn);
1065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
1066 return;
1067 }
1068
1069 TCGv t0 = tcg_temp_new();
1070 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
1071 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1072 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
1073 gen_store_spr(sprn, t0);
1074 tcg_temp_free(t0);
1075 }
1076 #endif
1077
1078 #ifdef TARGET_PPC64
1079 #ifndef CONFIG_USER_ONLY
1080 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1081 {
1082 TCGv t0 = tcg_temp_new();
1083 TCGv t1 = tcg_temp_new();
1084 TCGv t2 = tcg_temp_new();
1085
1086 /*
1087 * Note, the HV=1 PR=0 case is handled earlier by simply using
1088 * spr_write_generic for HV mode in the SPR table
1089 */
1090
1091 /* Build insertion mask into t1 based on context */
1092 if (ctx->pr) {
1093 gen_load_spr(t1, SPR_UAMOR);
1094 } else {
1095 gen_load_spr(t1, SPR_AMOR);
1096 }
1097
1098 /* Mask new bits into t2 */
1099 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1100
1101 /* Load AMR and clear new bits in t0 */
1102 gen_load_spr(t0, SPR_AMR);
1103 tcg_gen_andc_tl(t0, t0, t1);
1104
1105 /* Or'in new bits and write it out */
1106 tcg_gen_or_tl(t0, t0, t2);
1107 gen_store_spr(SPR_AMR, t0);
1108 spr_store_dump_spr(SPR_AMR);
1109
1110 tcg_temp_free(t0);
1111 tcg_temp_free(t1);
1112 tcg_temp_free(t2);
1113 }
1114
1115 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1116 {
1117 TCGv t0 = tcg_temp_new();
1118 TCGv t1 = tcg_temp_new();
1119 TCGv t2 = tcg_temp_new();
1120
1121 /*
1122 * Note, the HV=1 case is handled earlier by simply using
1123 * spr_write_generic for HV mode in the SPR table
1124 */
1125
1126 /* Build insertion mask into t1 based on context */
1127 gen_load_spr(t1, SPR_AMOR);
1128
1129 /* Mask new bits into t2 */
1130 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1131
1132 /* Load AMR and clear new bits in t0 */
1133 gen_load_spr(t0, SPR_UAMOR);
1134 tcg_gen_andc_tl(t0, t0, t1);
1135
1136 /* Or'in new bits and write it out */
1137 tcg_gen_or_tl(t0, t0, t2);
1138 gen_store_spr(SPR_UAMOR, t0);
1139 spr_store_dump_spr(SPR_UAMOR);
1140
1141 tcg_temp_free(t0);
1142 tcg_temp_free(t1);
1143 tcg_temp_free(t2);
1144 }
1145
1146 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1147 {
1148 TCGv t0 = tcg_temp_new();
1149 TCGv t1 = tcg_temp_new();
1150 TCGv t2 = tcg_temp_new();
1151
1152 /*
1153 * Note, the HV=1 case is handled earlier by simply using
1154 * spr_write_generic for HV mode in the SPR table
1155 */
1156
1157 /* Build insertion mask into t1 based on context */
1158 gen_load_spr(t1, SPR_AMOR);
1159
1160 /* Mask new bits into t2 */
1161 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1162
1163 /* Load AMR and clear new bits in t0 */
1164 gen_load_spr(t0, SPR_IAMR);
1165 tcg_gen_andc_tl(t0, t0, t1);
1166
1167 /* Or'in new bits and write it out */
1168 tcg_gen_or_tl(t0, t0, t2);
1169 gen_store_spr(SPR_IAMR, t0);
1170 spr_store_dump_spr(SPR_IAMR);
1171
1172 tcg_temp_free(t0);
1173 tcg_temp_free(t1);
1174 tcg_temp_free(t2);
1175 }
1176 #endif
1177 #endif
1178
1179 #ifndef CONFIG_USER_ONLY
1180 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1181 {
1182 gen_helper_fixup_thrm(cpu_env);
1183 gen_load_spr(cpu_gpr[gprn], sprn);
1184 spr_load_dump_spr(sprn);
1185 }
1186 #endif /* !CONFIG_USER_ONLY */
1187
1188 #if !defined(CONFIG_USER_ONLY)
1189 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1190 {
1191 TCGv t0 = tcg_temp_new();
1192
1193 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1194 gen_store_spr(sprn, t0);
1195 tcg_temp_free(t0);
1196 }
1197
1198 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1199 {
1200 TCGv t0 = tcg_temp_new();
1201
1202 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1203 gen_store_spr(sprn, t0);
1204 tcg_temp_free(t0);
1205 }
1206
1207 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1208 {
1209 TCGv t0 = tcg_temp_new();
1210
1211 tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1212 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1213 gen_store_spr(sprn, t0);
1214 tcg_temp_free(t0);
1215 }
1216
1217 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1218 {
1219 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1220 }
1221
1222 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1223 {
1224 TCGv_i32 t0 = tcg_const_i32(sprn);
1225 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1226 tcg_temp_free_i32(t0);
1227 }
1228 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1229 {
1230 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1231 }
1232 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1233 {
1234 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1235 }
1236
1237 #endif
1238
1239 #if !defined(CONFIG_USER_ONLY)
1240 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1241 {
1242 TCGv val = tcg_temp_new();
1243 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1244 gen_store_spr(SPR_BOOKE_MAS3, val);
1245 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1246 gen_store_spr(SPR_BOOKE_MAS7, val);
1247 tcg_temp_free(val);
1248 }
1249
1250 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1251 {
1252 TCGv mas7 = tcg_temp_new();
1253 TCGv mas3 = tcg_temp_new();
1254 gen_load_spr(mas7, SPR_BOOKE_MAS7);
1255 tcg_gen_shli_tl(mas7, mas7, 32);
1256 gen_load_spr(mas3, SPR_BOOKE_MAS3);
1257 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1258 tcg_temp_free(mas3);
1259 tcg_temp_free(mas7);
1260 }
1261
1262 #endif
1263
1264 #ifdef TARGET_PPC64
1265 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1266 int bit, int sprn, int cause)
1267 {
1268 TCGv_i32 t1 = tcg_const_i32(bit);
1269 TCGv_i32 t2 = tcg_const_i32(sprn);
1270 TCGv_i32 t3 = tcg_const_i32(cause);
1271
1272 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1273
1274 tcg_temp_free_i32(t3);
1275 tcg_temp_free_i32(t2);
1276 tcg_temp_free_i32(t1);
1277 }
1278
1279 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1280 int bit, int sprn, int cause)
1281 {
1282 TCGv_i32 t1 = tcg_const_i32(bit);
1283 TCGv_i32 t2 = tcg_const_i32(sprn);
1284 TCGv_i32 t3 = tcg_const_i32(cause);
1285
1286 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1287
1288 tcg_temp_free_i32(t3);
1289 tcg_temp_free_i32(t2);
1290 tcg_temp_free_i32(t1);
1291 }
1292
1293 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1294 {
1295 TCGv spr_up = tcg_temp_new();
1296 TCGv spr = tcg_temp_new();
1297
1298 gen_load_spr(spr, sprn - 1);
1299 tcg_gen_shri_tl(spr_up, spr, 32);
1300 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1301
1302 tcg_temp_free(spr);
1303 tcg_temp_free(spr_up);
1304 }
1305
1306 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1307 {
1308 TCGv spr = tcg_temp_new();
1309
1310 gen_load_spr(spr, sprn - 1);
1311 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1312 gen_store_spr(sprn - 1, spr);
1313
1314 tcg_temp_free(spr);
1315 }
1316
1317 #if !defined(CONFIG_USER_ONLY)
1318 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1319 {
1320 TCGv hmer = tcg_temp_new();
1321
1322 gen_load_spr(hmer, sprn);
1323 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1324 gen_store_spr(sprn, hmer);
1325 spr_store_dump_spr(sprn);
1326 tcg_temp_free(hmer);
1327 }
1328
1329 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1330 {
1331 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1332 }
1333 #endif /* !defined(CONFIG_USER_ONLY) */
1334
1335 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1336 {
1337 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1338 spr_read_generic(ctx, gprn, sprn);
1339 }
1340
1341 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1342 {
1343 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1344 spr_write_generic(ctx, sprn, gprn);
1345 }
1346
1347 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1348 {
1349 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1350 spr_read_generic(ctx, gprn, sprn);
1351 }
1352
1353 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1354 {
1355 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1356 spr_write_generic(ctx, sprn, gprn);
1357 }
1358
1359 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1360 {
1361 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1362 spr_read_prev_upper32(ctx, gprn, sprn);
1363 }
1364
1365 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1366 {
1367 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1368 spr_write_prev_upper32(ctx, sprn, gprn);
1369 }
1370
1371 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1372 {
1373 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1374 spr_read_generic(ctx, gprn, sprn);
1375 }
1376
1377 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1378 {
1379 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1380 spr_write_generic(ctx, sprn, gprn);
1381 }
1382
1383 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1384 {
1385 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1386 spr_read_prev_upper32(ctx, gprn, sprn);
1387 }
1388
1389 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1390 {
1391 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1392 spr_write_prev_upper32(ctx, sprn, gprn);
1393 }
1394 #endif
1395
1396 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
1397 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1398
1399 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
1400 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1401
1402 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
1403 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1404
1405 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
1406 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1407
1408 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
1409 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1410
1411 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1412 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1413
1414 typedef struct opcode_t {
1415 unsigned char opc1, opc2, opc3, opc4;
1416 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1417 unsigned char pad[4];
1418 #endif
1419 opc_handler_t handler;
1420 const char *oname;
1421 } opcode_t;
1422
1423 /* Helpers for priv. check */
1424 #define GEN_PRIV \
1425 do { \
1426 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
1427 } while (0)
1428
1429 #if defined(CONFIG_USER_ONLY)
1430 #define CHK_HV GEN_PRIV
1431 #define CHK_SV GEN_PRIV
1432 #define CHK_HVRM GEN_PRIV
1433 #else
1434 #define CHK_HV \
1435 do { \
1436 if (unlikely(ctx->pr || !ctx->hv)) { \
1437 GEN_PRIV; \
1438 } \
1439 } while (0)
1440 #define CHK_SV \
1441 do { \
1442 if (unlikely(ctx->pr)) { \
1443 GEN_PRIV; \
1444 } \
1445 } while (0)
1446 #define CHK_HVRM \
1447 do { \
1448 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1449 GEN_PRIV; \
1450 } \
1451 } while (0)
1452 #endif
1453
1454 #define CHK_NONE
1455
1456 /*****************************************************************************/
1457 /* PowerPC instructions table */
1458
1459 #if defined(DO_PPC_STATISTICS)
1460 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1461 { \
1462 .opc1 = op1, \
1463 .opc2 = op2, \
1464 .opc3 = op3, \
1465 .opc4 = 0xff, \
1466 .handler = { \
1467 .inval1 = invl, \
1468 .type = _typ, \
1469 .type2 = _typ2, \
1470 .handler = &gen_##name, \
1471 .oname = stringify(name), \
1472 }, \
1473 .oname = stringify(name), \
1474 }
1475 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1476 { \
1477 .opc1 = op1, \
1478 .opc2 = op2, \
1479 .opc3 = op3, \
1480 .opc4 = 0xff, \
1481 .handler = { \
1482 .inval1 = invl1, \
1483 .inval2 = invl2, \
1484 .type = _typ, \
1485 .type2 = _typ2, \
1486 .handler = &gen_##name, \
1487 .oname = stringify(name), \
1488 }, \
1489 .oname = stringify(name), \
1490 }
1491 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1492 { \
1493 .opc1 = op1, \
1494 .opc2 = op2, \
1495 .opc3 = op3, \
1496 .opc4 = 0xff, \
1497 .handler = { \
1498 .inval1 = invl, \
1499 .type = _typ, \
1500 .type2 = _typ2, \
1501 .handler = &gen_##name, \
1502 .oname = onam, \
1503 }, \
1504 .oname = onam, \
1505 }
1506 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1507 { \
1508 .opc1 = op1, \
1509 .opc2 = op2, \
1510 .opc3 = op3, \
1511 .opc4 = op4, \
1512 .handler = { \
1513 .inval1 = invl, \
1514 .type = _typ, \
1515 .type2 = _typ2, \
1516 .handler = &gen_##name, \
1517 .oname = stringify(name), \
1518 }, \
1519 .oname = stringify(name), \
1520 }
1521 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1522 { \
1523 .opc1 = op1, \
1524 .opc2 = op2, \
1525 .opc3 = op3, \
1526 .opc4 = op4, \
1527 .handler = { \
1528 .inval1 = invl, \
1529 .type = _typ, \
1530 .type2 = _typ2, \
1531 .handler = &gen_##name, \
1532 .oname = onam, \
1533 }, \
1534 .oname = onam, \
1535 }
1536 #else
1537 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1538 { \
1539 .opc1 = op1, \
1540 .opc2 = op2, \
1541 .opc3 = op3, \
1542 .opc4 = 0xff, \
1543 .handler = { \
1544 .inval1 = invl, \
1545 .type = _typ, \
1546 .type2 = _typ2, \
1547 .handler = &gen_##name, \
1548 }, \
1549 .oname = stringify(name), \
1550 }
1551 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1552 { \
1553 .opc1 = op1, \
1554 .opc2 = op2, \
1555 .opc3 = op3, \
1556 .opc4 = 0xff, \
1557 .handler = { \
1558 .inval1 = invl1, \
1559 .inval2 = invl2, \
1560 .type = _typ, \
1561 .type2 = _typ2, \
1562 .handler = &gen_##name, \
1563 }, \
1564 .oname = stringify(name), \
1565 }
1566 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1567 { \
1568 .opc1 = op1, \
1569 .opc2 = op2, \
1570 .opc3 = op3, \
1571 .opc4 = 0xff, \
1572 .handler = { \
1573 .inval1 = invl, \
1574 .type = _typ, \
1575 .type2 = _typ2, \
1576 .handler = &gen_##name, \
1577 }, \
1578 .oname = onam, \
1579 }
1580 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1581 { \
1582 .opc1 = op1, \
1583 .opc2 = op2, \
1584 .opc3 = op3, \
1585 .opc4 = op4, \
1586 .handler = { \
1587 .inval1 = invl, \
1588 .type = _typ, \
1589 .type2 = _typ2, \
1590 .handler = &gen_##name, \
1591 }, \
1592 .oname = stringify(name), \
1593 }
1594 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1595 { \
1596 .opc1 = op1, \
1597 .opc2 = op2, \
1598 .opc3 = op3, \
1599 .opc4 = op4, \
1600 .handler = { \
1601 .inval1 = invl, \
1602 .type = _typ, \
1603 .type2 = _typ2, \
1604 .handler = &gen_##name, \
1605 }, \
1606 .oname = onam, \
1607 }
1608 #endif
1609
1610 /* Invalid instruction */
1611 static void gen_invalid(DisasContext *ctx)
1612 {
1613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1614 }
1615
1616 static opc_handler_t invalid_handler = {
1617 .inval1 = 0xFFFFFFFF,
1618 .inval2 = 0xFFFFFFFF,
1619 .type = PPC_NONE,
1620 .type2 = PPC_NONE,
1621 .handler = gen_invalid,
1622 };
1623
1624 /*** Integer comparison ***/
1625
1626 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1627 {
1628 TCGv t0 = tcg_temp_new();
1629 TCGv t1 = tcg_temp_new();
1630 TCGv_i32 t = tcg_temp_new_i32();
1631
1632 tcg_gen_movi_tl(t0, CRF_EQ);
1633 tcg_gen_movi_tl(t1, CRF_LT);
1634 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1635 t0, arg0, arg1, t1, t0);
1636 tcg_gen_movi_tl(t1, CRF_GT);
1637 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1638 t0, arg0, arg1, t1, t0);
1639
1640 tcg_gen_trunc_tl_i32(t, t0);
1641 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1642 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1643
1644 tcg_temp_free(t0);
1645 tcg_temp_free(t1);
1646 tcg_temp_free_i32(t);
1647 }
1648
1649 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1650 {
1651 TCGv t0 = tcg_const_tl(arg1);
1652 gen_op_cmp(arg0, t0, s, crf);
1653 tcg_temp_free(t0);
1654 }
1655
1656 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1657 {
1658 TCGv t0, t1;
1659 t0 = tcg_temp_new();
1660 t1 = tcg_temp_new();
1661 if (s) {
1662 tcg_gen_ext32s_tl(t0, arg0);
1663 tcg_gen_ext32s_tl(t1, arg1);
1664 } else {
1665 tcg_gen_ext32u_tl(t0, arg0);
1666 tcg_gen_ext32u_tl(t1, arg1);
1667 }
1668 gen_op_cmp(t0, t1, s, crf);
1669 tcg_temp_free(t1);
1670 tcg_temp_free(t0);
1671 }
1672
1673 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1674 {
1675 TCGv t0 = tcg_const_tl(arg1);
1676 gen_op_cmp32(arg0, t0, s, crf);
1677 tcg_temp_free(t0);
1678 }
1679
1680 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1681 {
1682 if (NARROW_MODE(ctx)) {
1683 gen_op_cmpi32(reg, 0, 1, 0);
1684 } else {
1685 gen_op_cmpi(reg, 0, 1, 0);
1686 }
1687 }
1688
1689 /* cmp */
1690 static void gen_cmp(DisasContext *ctx)
1691 {
1692 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1693 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1694 1, crfD(ctx->opcode));
1695 } else {
1696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1697 1, crfD(ctx->opcode));
1698 }
1699 }
1700
1701 /* cmpi */
1702 static void gen_cmpi(DisasContext *ctx)
1703 {
1704 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1705 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1706 1, crfD(ctx->opcode));
1707 } else {
1708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1709 1, crfD(ctx->opcode));
1710 }
1711 }
1712
1713 /* cmpl */
1714 static void gen_cmpl(DisasContext *ctx)
1715 {
1716 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1717 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1718 0, crfD(ctx->opcode));
1719 } else {
1720 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1721 0, crfD(ctx->opcode));
1722 }
1723 }
1724
1725 /* cmpli */
1726 static void gen_cmpli(DisasContext *ctx)
1727 {
1728 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1729 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
1730 0, crfD(ctx->opcode));
1731 } else {
1732 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
1733 0, crfD(ctx->opcode));
1734 }
1735 }
1736
1737 /* cmprb - range comparison: isupper, isaplha, islower*/
1738 static void gen_cmprb(DisasContext *ctx)
1739 {
1740 TCGv_i32 src1 = tcg_temp_new_i32();
1741 TCGv_i32 src2 = tcg_temp_new_i32();
1742 TCGv_i32 src2lo = tcg_temp_new_i32();
1743 TCGv_i32 src2hi = tcg_temp_new_i32();
1744 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1745
1746 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1747 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1748
1749 tcg_gen_andi_i32(src1, src1, 0xFF);
1750 tcg_gen_ext8u_i32(src2lo, src2);
1751 tcg_gen_shri_i32(src2, src2, 8);
1752 tcg_gen_ext8u_i32(src2hi, src2);
1753
1754 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1755 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1756 tcg_gen_and_i32(crf, src2lo, src2hi);
1757
1758 if (ctx->opcode & 0x00200000) {
1759 tcg_gen_shri_i32(src2, src2, 8);
1760 tcg_gen_ext8u_i32(src2lo, src2);
1761 tcg_gen_shri_i32(src2, src2, 8);
1762 tcg_gen_ext8u_i32(src2hi, src2);
1763 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1764 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1765 tcg_gen_and_i32(src2lo, src2lo, src2hi);
1766 tcg_gen_or_i32(crf, crf, src2lo);
1767 }
1768 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
1769 tcg_temp_free_i32(src1);
1770 tcg_temp_free_i32(src2);
1771 tcg_temp_free_i32(src2lo);
1772 tcg_temp_free_i32(src2hi);
1773 }
1774
1775 #if defined(TARGET_PPC64)
1776 /* cmpeqb */
1777 static void gen_cmpeqb(DisasContext *ctx)
1778 {
1779 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1780 cpu_gpr[rB(ctx->opcode)]);
1781 }
1782 #endif
1783
1784 /* isel (PowerPC 2.03 specification) */
1785 static void gen_isel(DisasContext *ctx)
1786 {
1787 uint32_t bi = rC(ctx->opcode);
1788 uint32_t mask = 0x08 >> (bi & 0x03);
1789 TCGv t0 = tcg_temp_new();
1790 TCGv zr;
1791
1792 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1793 tcg_gen_andi_tl(t0, t0, mask);
1794
1795 zr = tcg_const_tl(0);
1796 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1797 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1798 cpu_gpr[rB(ctx->opcode)]);
1799 tcg_temp_free(zr);
1800 tcg_temp_free(t0);
1801 }
1802
1803 /* cmpb: PowerPC 2.05 specification */
1804 static void gen_cmpb(DisasContext *ctx)
1805 {
1806 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1807 cpu_gpr[rB(ctx->opcode)]);
1808 }
1809
1810 /*** Integer arithmetic ***/
1811
1812 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1813 TCGv arg1, TCGv arg2, int sub)
1814 {
1815 TCGv t0 = tcg_temp_new();
1816
1817 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1818 tcg_gen_xor_tl(t0, arg1, arg2);
1819 if (sub) {
1820 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1821 } else {
1822 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1823 }
1824 tcg_temp_free(t0);
1825 if (NARROW_MODE(ctx)) {
1826 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1827 if (is_isa300(ctx)) {
1828 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1829 }
1830 } else {
1831 if (is_isa300(ctx)) {
1832 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1833 }
1834 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1835 }
1836 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1837 }
1838
1839 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1840 TCGv res, TCGv arg0, TCGv arg1,
1841 TCGv ca32, int sub)
1842 {
1843 TCGv t0;
1844
1845 if (!is_isa300(ctx)) {
1846 return;
1847 }
1848
1849 t0 = tcg_temp_new();
1850 if (sub) {
1851 tcg_gen_eqv_tl(t0, arg0, arg1);
1852 } else {
1853 tcg_gen_xor_tl(t0, arg0, arg1);
1854 }
1855 tcg_gen_xor_tl(t0, t0, res);
1856 tcg_gen_extract_tl(ca32, t0, 32, 1);
1857 tcg_temp_free(t0);
1858 }
1859
1860 /* Common add function */
1861 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1862 TCGv arg2, TCGv ca, TCGv ca32,
1863 bool add_ca, bool compute_ca,
1864 bool compute_ov, bool compute_rc0)
1865 {
1866 TCGv t0 = ret;
1867
1868 if (compute_ca || compute_ov) {
1869 t0 = tcg_temp_new();
1870 }
1871
1872 if (compute_ca) {
1873 if (NARROW_MODE(ctx)) {
1874 /*
1875 * Caution: a non-obvious corner case of the spec is that
1876 * we must produce the *entire* 64-bit addition, but
1877 * produce the carry into bit 32.
1878 */
1879 TCGv t1 = tcg_temp_new();
1880 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
1881 tcg_gen_add_tl(t0, arg1, arg2);
1882 if (add_ca) {
1883 tcg_gen_add_tl(t0, t0, ca);
1884 }
1885 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
1886 tcg_temp_free(t1);
1887 tcg_gen_extract_tl(ca, ca, 32, 1);
1888 if (is_isa300(ctx)) {
1889 tcg_gen_mov_tl(ca32, ca);
1890 }
1891 } else {
1892 TCGv zero = tcg_const_tl(0);
1893 if (add_ca) {
1894 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1895 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
1896 } else {
1897 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1898 }
1899 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1900 tcg_temp_free(zero);
1901 }
1902 } else {
1903 tcg_gen_add_tl(t0, arg1, arg2);
1904 if (add_ca) {
1905 tcg_gen_add_tl(t0, t0, ca);
1906 }
1907 }
1908
1909 if (compute_ov) {
1910 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1911 }
1912 if (unlikely(compute_rc0)) {
1913 gen_set_Rc0(ctx, t0);
1914 }
1915
1916 if (t0 != ret) {
1917 tcg_gen_mov_tl(ret, t0);
1918 tcg_temp_free(t0);
1919 }
1920 }
1921 /* Add functions with two operands */
1922 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
1923 static void glue(gen_, name)(DisasContext *ctx) \
1924 { \
1925 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1926 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1927 ca, glue(ca, 32), \
1928 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1929 }
1930 /* Add functions with one operand and one immediate */
1931 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
1932 add_ca, compute_ca, compute_ov) \
1933 static void glue(gen_, name)(DisasContext *ctx) \
1934 { \
1935 TCGv t0 = tcg_const_tl(const_val); \
1936 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1937 cpu_gpr[rA(ctx->opcode)], t0, \
1938 ca, glue(ca, 32), \
1939 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1940 tcg_temp_free(t0); \
1941 }
1942
1943 /* add add. addo addo. */
1944 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1945 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
1946 /* addc addc. addco addco. */
1947 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1948 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
1949 /* adde adde. addeo addeo. */
1950 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1951 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
1952 /* addme addme. addmeo addmeo. */
1953 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1954 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1955 /* addex */
1956 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
1957 /* addze addze. addzeo addzeo.*/
1958 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1959 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
1960 /* addi */
1961 static void gen_addi(DisasContext *ctx)
1962 {
1963 target_long simm = SIMM(ctx->opcode);
1964
1965 if (rA(ctx->opcode) == 0) {
1966 /* li case */
1967 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1968 } else {
1969 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1970 cpu_gpr[rA(ctx->opcode)], simm);
1971 }
1972 }
1973 /* addic addic.*/
1974 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1975 {
1976 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1977 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1978 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
1979 tcg_temp_free(c);
1980 }
1981
1982 static void gen_addic(DisasContext *ctx)
1983 {
1984 gen_op_addic(ctx, 0);
1985 }
1986
1987 static void gen_addic_(DisasContext *ctx)
1988 {
1989 gen_op_addic(ctx, 1);
1990 }
1991
1992 /* addis */
1993 static void gen_addis(DisasContext *ctx)
1994 {
1995 target_long simm = SIMM(ctx->opcode);
1996
1997 if (rA(ctx->opcode) == 0) {
1998 /* lis case */
1999 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
2000 } else {
2001 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
2002 cpu_gpr[rA(ctx->opcode)], simm << 16);
2003 }
2004 }
2005
2006 /* addpcis */
2007 static void gen_addpcis(DisasContext *ctx)
2008 {
2009 target_long d = DX(ctx->opcode);
2010
2011 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
2012 }
2013
2014 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
2015 TCGv arg2, int sign, int compute_ov)
2016 {
2017 TCGv_i32 t0 = tcg_temp_new_i32();
2018 TCGv_i32 t1 = tcg_temp_new_i32();
2019 TCGv_i32 t2 = tcg_temp_new_i32();
2020 TCGv_i32 t3 = tcg_temp_new_i32();
2021
2022 tcg_gen_trunc_tl_i32(t0, arg1);
2023 tcg_gen_trunc_tl_i32(t1, arg2);
2024 if (sign) {
2025 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
2026 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
2027 tcg_gen_and_i32(t2, t2, t3);
2028 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
2029 tcg_gen_or_i32(t2, t2, t3);
2030 tcg_gen_movi_i32(t3, 0);
2031 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2032 tcg_gen_div_i32(t3, t0, t1);
2033 tcg_gen_extu_i32_tl(ret, t3);
2034 } else {
2035 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
2036 tcg_gen_movi_i32(t3, 0);
2037 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2038 tcg_gen_divu_i32(t3, t0, t1);
2039 tcg_gen_extu_i32_tl(ret, t3);
2040 }
2041 if (compute_ov) {
2042 tcg_gen_extu_i32_tl(cpu_ov, t2);
2043 if (is_isa300(ctx)) {
2044 tcg_gen_extu_i32_tl(cpu_ov32, t2);
2045 }
2046 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2047 }
2048 tcg_temp_free_i32(t0);
2049 tcg_temp_free_i32(t1);
2050 tcg_temp_free_i32(t2);
2051 tcg_temp_free_i32(t3);
2052
2053 if (unlikely(Rc(ctx->opcode) != 0)) {
2054 gen_set_Rc0(ctx, ret);
2055 }
2056 }
2057 /* Div functions */
2058 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
2059 static void glue(gen_, name)(DisasContext *ctx) \
2060 { \
2061 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
2062 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2063 sign, compute_ov); \
2064 }
2065 /* divwu divwu. divwuo divwuo. */
2066 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
2067 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
2068 /* divw divw. divwo divwo. */
2069 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
2070 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
2071
2072 /* div[wd]eu[o][.] */
2073 #define GEN_DIVE(name, hlpr, compute_ov) \
2074 static void gen_##name(DisasContext *ctx) \
2075 { \
2076 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
2077 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
2078 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
2079 tcg_temp_free_i32(t0); \
2080 if (unlikely(Rc(ctx->opcode) != 0)) { \
2081 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
2082 } \
2083 }
2084
2085 GEN_DIVE(divweu, divweu, 0);
2086 GEN_DIVE(divweuo, divweu, 1);
2087 GEN_DIVE(divwe, divwe, 0);
2088 GEN_DIVE(divweo, divwe, 1);
2089
2090 #if defined(TARGET_PPC64)
2091 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
2092 TCGv arg2, int sign, int compute_ov)
2093 {
2094 TCGv_i64 t0 = tcg_temp_new_i64();
2095 TCGv_i64 t1 = tcg_temp_new_i64();
2096 TCGv_i64 t2 = tcg_temp_new_i64();
2097 TCGv_i64 t3 = tcg_temp_new_i64();
2098
2099 tcg_gen_mov_i64(t0, arg1);
2100 tcg_gen_mov_i64(t1, arg2);
2101 if (sign) {
2102 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
2103 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
2104 tcg_gen_and_i64(t2, t2, t3);
2105 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
2106 tcg_gen_or_i64(t2, t2, t3);
2107 tcg_gen_movi_i64(t3, 0);
2108 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2109 tcg_gen_div_i64(ret, t0, t1);
2110 } else {
2111 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
2112 tcg_gen_movi_i64(t3, 0);
2113 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2114 tcg_gen_divu_i64(ret, t0, t1);
2115 }
2116 if (compute_ov) {
2117 tcg_gen_mov_tl(cpu_ov, t2);
2118 if (is_isa300(ctx)) {
2119 tcg_gen_mov_tl(cpu_ov32, t2);
2120 }
2121 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2122 }
2123 tcg_temp_free_i64(t0);
2124 tcg_temp_free_i64(t1);
2125 tcg_temp_free_i64(t2);
2126 tcg_temp_free_i64(t3);
2127
2128 if (unlikely(Rc(ctx->opcode) != 0)) {
2129 gen_set_Rc0(ctx, ret);
2130 }
2131 }
2132
2133 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
2134 static void glue(gen_, name)(DisasContext *ctx) \
2135 { \
2136 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
2137 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2138 sign, compute_ov); \
2139 }
2140 /* divdu divdu. divduo divduo. */
2141 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
2142 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
2143 /* divd divd. divdo divdo. */
2144 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
2145 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
2146
2147 GEN_DIVE(divdeu, divdeu, 0);
2148 GEN_DIVE(divdeuo, divdeu, 1);
2149 GEN_DIVE(divde, divde, 0);
2150 GEN_DIVE(divdeo, divde, 1);
2151 #endif
2152
2153 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
2154 TCGv arg2, int sign)
2155 {
2156 TCGv_i32 t0 = tcg_temp_new_i32();
2157 TCGv_i32 t1 = tcg_temp_new_i32();
2158
2159 tcg_gen_trunc_tl_i32(t0, arg1);
2160 tcg_gen_trunc_tl_i32(t1, arg2);
2161 if (sign) {
2162 TCGv_i32 t2 = tcg_temp_new_i32();
2163 TCGv_i32 t3 = tcg_temp_new_i32();
2164 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
2165 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
2166 tcg_gen_and_i32(t2, t2, t3);
2167 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
2168 tcg_gen_or_i32(t2, t2, t3);
2169 tcg_gen_movi_i32(t3, 0);
2170 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2171 tcg_gen_rem_i32(t3, t0, t1);
2172 tcg_gen_ext_i32_tl(ret, t3);
2173 tcg_temp_free_i32(t2);
2174 tcg_temp_free_i32(t3);
2175 } else {
2176 TCGv_i32 t2 = tcg_const_i32(1);
2177 TCGv_i32 t3 = tcg_const_i32(0);
2178 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
2179 tcg_gen_remu_i32(t3, t0, t1);
2180 tcg_gen_extu_i32_tl(ret, t3);
2181 tcg_temp_free_i32(t2);
2182 tcg_temp_free_i32(t3);
2183 }
2184 tcg_temp_free_i32(t0);
2185 tcg_temp_free_i32(t1);
2186 }
2187
2188 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
2189 static void glue(gen_, name)(DisasContext *ctx) \
2190 { \
2191 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
2192 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2193 sign); \
2194 }
2195
2196 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
2197 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
2198
2199 #if defined(TARGET_PPC64)
2200 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
2201 TCGv arg2, int sign)
2202 {
2203 TCGv_i64 t0 = tcg_temp_new_i64();
2204 TCGv_i64 t1 = tcg_temp_new_i64();
2205
2206 tcg_gen_mov_i64(t0, arg1);
2207 tcg_gen_mov_i64(t1, arg2);
2208 if (sign) {
2209 TCGv_i64 t2 = tcg_temp_new_i64();
2210 TCGv_i64 t3 = tcg_temp_new_i64();
2211 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
2212 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
2213 tcg_gen_and_i64(t2, t2, t3);
2214 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
2215 tcg_gen_or_i64(t2, t2, t3);
2216 tcg_gen_movi_i64(t3, 0);
2217 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2218 tcg_gen_rem_i64(ret, t0, t1);
2219 tcg_temp_free_i64(t2);
2220 tcg_temp_free_i64(t3);
2221 } else {
2222 TCGv_i64 t2 = tcg_const_i64(1);
2223 TCGv_i64 t3 = tcg_const_i64(0);
2224 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
2225 tcg_gen_remu_i64(ret, t0, t1);
2226 tcg_temp_free_i64(t2);
2227 tcg_temp_free_i64(t3);
2228 }
2229 tcg_temp_free_i64(t0);
2230 tcg_temp_free_i64(t1);
2231 }
2232
2233 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
2234 static void glue(gen_, name)(DisasContext *ctx) \
2235 { \
2236 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
2237 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2238 sign); \
2239 }
2240
2241 GEN_INT_ARITH_MODD(modud, 0x08, 0);
2242 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
2243 #endif
2244
2245 /* mulhw mulhw. */
2246 static void gen_mulhw(DisasContext *ctx)
2247 {
2248 TCGv_i32 t0 = tcg_temp_new_i32();
2249 TCGv_i32 t1 = tcg_temp_new_i32();
2250
2251 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2252 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2253 tcg_gen_muls2_i32(t0, t1, t0, t1);
2254 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2255 tcg_temp_free_i32(t0);
2256 tcg_temp_free_i32(t1);
2257 if (unlikely(Rc(ctx->opcode) != 0)) {
2258 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2259 }
2260 }
2261
2262 /* mulhwu mulhwu. */
2263 static void gen_mulhwu(DisasContext *ctx)
2264 {
2265 TCGv_i32 t0 = tcg_temp_new_i32();
2266 TCGv_i32 t1 = tcg_temp_new_i32();
2267
2268 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2269 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2270 tcg_gen_mulu2_i32(t0, t1, t0, t1);
2271 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2272 tcg_temp_free_i32(t0);
2273 tcg_temp_free_i32(t1);
2274 if (unlikely(Rc(ctx->opcode) != 0)) {
2275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2276 }
2277 }
2278
2279 /* mullw mullw. */
2280 static void gen_mullw(DisasContext *ctx)
2281 {
2282 #if defined(TARGET_PPC64)
2283 TCGv_i64 t0, t1;
2284 t0 = tcg_temp_new_i64();
2285 t1 = tcg_temp_new_i64();
2286 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
2287 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
2288 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2289 tcg_temp_free(t0);
2290 tcg_temp_free(t1);
2291 #else
2292 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2293 cpu_gpr[rB(ctx->opcode)]);
2294 #endif
2295 if (unlikely(Rc(ctx->opcode) != 0)) {
2296 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2297 }
2298 }
2299
2300 /* mullwo mullwo. */
2301 static void gen_mullwo(DisasContext *ctx)
2302 {
2303 TCGv_i32 t0 = tcg_temp_new_i32();
2304 TCGv_i32 t1 = tcg_temp_new_i32();
2305
2306 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2307 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2308 tcg_gen_muls2_i32(t0, t1, t0, t1);
2309 #if defined(TARGET_PPC64)
2310 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2311 #else
2312 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
2313 #endif
2314
2315 tcg_gen_sari_i32(t0, t0, 31);
2316 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
2317 tcg_gen_extu_i32_tl(cpu_ov, t0);
2318 if (is_isa300(ctx)) {
2319 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2320 }
2321 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2322
2323 tcg_temp_free_i32(t0);
2324 tcg_temp_free_i32(t1);
2325 if (unlikely(Rc(ctx->opcode) != 0)) {
2326 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2327 }
2328 }
2329
2330 /* mulli */
2331 static void gen_mulli(DisasContext *ctx)
2332 {
2333 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2334 SIMM(ctx->opcode));
2335 }
2336
2337 #if defined(TARGET_PPC64)
2338 /* mulhd mulhd. */
2339 static void gen_mulhd(DisasContext *ctx)
2340 {
2341 TCGv lo = tcg_temp_new();
2342 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2343 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2344 tcg_temp_free(lo);
2345 if (unlikely(Rc(ctx->opcode) != 0)) {
2346 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2347 }
2348 }
2349
2350 /* mulhdu mulhdu. */
2351 static void gen_mulhdu(DisasContext *ctx)
2352 {
2353 TCGv lo = tcg_temp_new();
2354 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2355 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2356 tcg_temp_free(lo);
2357 if (unlikely(Rc(ctx->opcode) != 0)) {
2358 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2359 }
2360 }
2361
2362 /* mulld mulld. */
2363 static void gen_mulld(DisasContext *ctx)
2364 {
2365 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2366 cpu_gpr[rB(ctx->opcode)]);
2367 if (unlikely(Rc(ctx->opcode) != 0)) {
2368 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2369 }
2370 }
2371
2372 /* mulldo mulldo. */
2373 static void gen_mulldo(DisasContext *ctx)
2374 {
2375 TCGv_i64 t0 = tcg_temp_new_i64();
2376 TCGv_i64 t1 = tcg_temp_new_i64();
2377
2378 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
2379 cpu_gpr[rB(ctx->opcode)]);
2380 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
2381
2382 tcg_gen_sari_i64(t0, t0, 63);
2383 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
2384 if (is_isa300(ctx)) {
2385 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2386 }
2387 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2388
2389 tcg_temp_free_i64(t0);
2390 tcg_temp_free_i64(t1);
2391
2392 if (unlikely(Rc(ctx->opcode) != 0)) {
2393 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2394 }
2395 }
2396 #endif
2397
2398 /* Common subf function */
2399 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
2400 TCGv arg2, bool add_ca, bool compute_ca,
2401 bool compute_ov, bool compute_rc0)
2402 {
2403 TCGv t0 = ret;
2404
2405 if (compute_ca || compute_ov) {
2406 t0 = tcg_temp_new();
2407 }
2408
2409 if (compute_ca) {
2410 /* dest = ~arg1 + arg2 [+ ca]. */
2411 if (NARROW_MODE(ctx)) {
2412 /*
2413 * Caution: a non-obvious corner case of the spec is that
2414 * we must produce the *entire* 64-bit addition, but
2415 * produce the carry into bit 32.
2416 */
2417 TCGv inv1 = tcg_temp_new();
2418 TCGv t1 = tcg_temp_new();
2419 tcg_gen_not_tl(inv1, arg1);
2420 if (add_ca) {
2421 tcg_gen_add_tl(t0, arg2, cpu_ca);
2422 } else {
2423 tcg_gen_addi_tl(t0, arg2, 1);
2424 }
2425 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
2426 tcg_gen_add_tl(t0, t0, inv1);
2427 tcg_temp_free(inv1);
2428 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
2429 tcg_temp_free(t1);
2430 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
2431 if (is_isa300(ctx)) {
2432 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2433 }
2434 } else if (add_ca) {
2435 TCGv zero, inv1 = tcg_temp_new();
2436 tcg_gen_not_tl(inv1, arg1);
2437 zero = tcg_const_tl(0);
2438 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
2439 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
2440 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
2441 tcg_temp_free(zero);
2442 tcg_temp_free(inv1);
2443 } else {
2444 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
2445 tcg_gen_sub_tl(t0, arg2, arg1);
2446 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
2447 }
2448 } else if (add_ca) {
2449 /*
2450 * Since we're ignoring carry-out, we can simplify the
2451 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2452 */
2453 tcg_gen_sub_tl(t0, arg2, arg1);
2454 tcg_gen_add_tl(t0, t0, cpu_ca);
2455 tcg_gen_subi_tl(t0, t0, 1);
2456 } else {
2457 tcg_gen_sub_tl(t0, arg2, arg1);
2458 }
2459
2460 if (compute_ov) {
2461 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2462 }
2463 if (unlikely(compute_rc0)) {
2464 gen_set_Rc0(ctx, t0);
2465 }
2466
2467 if (t0 != ret) {
2468 tcg_gen_mov_tl(ret, t0);
2469 tcg_temp_free(t0);
2470 }
2471 }
2472 /* Sub functions with Two operands functions */
2473 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
2474 static void glue(gen_, name)(DisasContext *ctx) \
2475 { \
2476 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2477 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2478 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2479 }
2480 /* Sub functions with one operand and one immediate */
2481 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
2482 add_ca, compute_ca, compute_ov) \
2483 static void glue(gen_, name)(DisasContext *ctx) \
2484 { \
2485 TCGv t0 = tcg_const_tl(const_val); \
2486 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2487 cpu_gpr[rA(ctx->opcode)], t0, \
2488 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2489 tcg_temp_free(t0); \
2490 }
2491 /* subf subf. subfo subfo. */
2492 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2493 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2494 /* subfc subfc. subfco subfco. */
2495 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2496 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2497 /* subfe subfe. subfeo subfo. */
2498 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2499 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2500 /* subfme subfme. subfmeo subfmeo. */
2501 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2502 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2503 /* subfze subfze. subfzeo subfzeo.*/
2504 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2505 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
2506
2507 /* subfic */
2508 static void gen_subfic(DisasContext *ctx)
2509 {
2510 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
2511 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2512 c, 0, 1, 0, 0);
2513 tcg_temp_free(c);
2514 }
2515
2516 /* neg neg. nego nego. */
2517 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2518 {
2519 TCGv zero = tcg_const_tl(0);
2520 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2521 zero, 0, 0, compute_ov, Rc(ctx->opcode));
2522 tcg_temp_free(zero);
2523 }
2524
2525 static void gen_neg(DisasContext *ctx)
2526 {
2527 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2528 if (unlikely(Rc(ctx->opcode))) {
2529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2530 }
2531 }
2532
2533 static void gen_nego(DisasContext *ctx)
2534 {
2535 gen_op_arith_neg(ctx, 1);
2536 }
2537
2538 /*** Integer logical ***/
2539 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
2540 static void glue(gen_, name)(DisasContext *ctx) \
2541 { \
2542 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
2543 cpu_gpr[rB(ctx->opcode)]); \
2544 if (unlikely(Rc(ctx->opcode) != 0)) \
2545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2546 }
2547
2548 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
2549 static void glue(gen_, name)(DisasContext *ctx) \
2550 { \
2551 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
2552 if (unlikely(Rc(ctx->opcode) != 0)) \
2553 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2554 }
2555
2556 /* and & and. */
2557 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
2558 /* andc & andc. */
2559 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
2560
2561 /* andi. */
2562 static void gen_andi_(DisasContext *ctx)
2563 {
2564 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2565 UIMM(ctx->opcode));
2566 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2567 }
2568
2569 /* andis. */
2570 static void gen_andis_(DisasContext *ctx)
2571 {
2572 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2573 UIMM(ctx->opcode) << 16);
2574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2575 }
2576
2577 /* cntlzw */
2578 static void gen_cntlzw(DisasContext *ctx)
2579 {
2580 TCGv_i32 t = tcg_temp_new_i32();
2581
2582 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2583 tcg_gen_clzi_i32(t, t, 32);
2584 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2585 tcg_temp_free_i32(t);
2586
2587 if (unlikely(Rc(ctx->opcode) != 0)) {
2588 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2589 }
2590 }
2591
2592 /* cnttzw */
2593 static void gen_cnttzw(DisasContext *ctx)
2594 {
2595 TCGv_i32 t = tcg_temp_new_i32();
2596
2597 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2598 tcg_gen_ctzi_i32(t, t, 32);
2599 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2600 tcg_temp_free_i32(t);
2601
2602 if (unlikely(Rc(ctx->opcode) != 0)) {
2603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2604 }
2605 }
2606
2607 /* eqv & eqv. */
2608 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
2609 /* extsb & extsb. */
2610 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
2611 /* extsh & extsh. */
2612 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
2613 /* nand & nand. */
2614 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
2615 /* nor & nor. */
2616 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
2617
2618 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2619 static void gen_pause(DisasContext *ctx)
2620 {
2621 TCGv_i32 t0 = tcg_const_i32(0);
2622 tcg_gen_st_i32(t0, cpu_env,
2623 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2624 tcg_temp_free_i32(t0);
2625
2626 /* Stop translation, this gives other CPUs a chance to run */
2627 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
2628 }
2629 #endif /* defined(TARGET_PPC64) */
2630
2631 /* or & or. */
2632 static void gen_or(DisasContext *ctx)
2633 {
2634 int rs, ra, rb;
2635
2636 rs = rS(ctx->opcode);
2637 ra = rA(ctx->opcode);
2638 rb = rB(ctx->opcode);
2639 /* Optimisation for mr. ri case */
2640 if (rs != ra || rs != rb) {
2641 if (rs != rb) {
2642 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
2643 } else {
2644 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
2645 }
2646 if (unlikely(Rc(ctx->opcode) != 0)) {
2647 gen_set_Rc0(ctx, cpu_gpr[ra]);
2648 }
2649 } else if (unlikely(Rc(ctx->opcode) != 0)) {
2650 gen_set_Rc0(ctx, cpu_gpr[rs]);
2651 #if defined(TARGET_PPC64)
2652 } else if (rs != 0) { /* 0 is nop */
2653 int prio = 0;
2654
2655 switch (rs) {
2656 case 1:
2657 /* Set process priority to low */
2658 prio = 2;
2659 break;
2660 case 6:
2661 /* Set process priority to medium-low */
2662 prio = 3;
2663 break;
2664 case 2:
2665 /* Set process priority to normal */
2666 prio = 4;
2667 break;
2668 #if !defined(CONFIG_USER_ONLY)
2669 case 31:
2670 if (!ctx->pr) {
2671 /* Set process priority to very low */
2672 prio = 1;
2673 }
2674 break;
2675 case 5:
2676 if (!ctx->pr) {
2677 /* Set process priority to medium-hight */
2678 prio = 5;
2679 }
2680 break;
2681 case 3:
2682 if (!ctx->pr) {
2683 /* Set process priority to high */
2684 prio = 6;
2685 }
2686 break;
2687 case 7:
2688 if (ctx->hv && !ctx->pr) {
2689 /* Set process priority to very high */
2690 prio = 7;
2691 }
2692 break;
2693 #endif
2694 default:
2695 break;
2696 }
2697 if (prio) {
2698 TCGv t0 = tcg_temp_new();
2699 gen_load_spr(t0, SPR_PPR);
2700 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2701 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
2702 gen_store_spr(SPR_PPR, t0);
2703 tcg_temp_free(t0);
2704 }
2705 #if !defined(CONFIG_USER_ONLY)
2706 /*
2707 * Pause out of TCG otherwise spin loops with smt_low eat too
2708 * much CPU and the kernel hangs. This applies to all
2709 * encodings other than no-op, e.g., miso(rs=26), yield(27),
2710 * mdoio(29), mdoom(30), and all currently undefined.
2711 */
2712 gen_pause(ctx);
2713 #endif
2714 #endif
2715 }
2716 }
2717 /* orc & orc. */
2718 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
2719
2720 /* xor & xor. */
2721 static void gen_xor(DisasContext *ctx)
2722 {
2723 /* Optimisation for "set to zero" case */
2724 if (rS(ctx->opcode) != rB(ctx->opcode)) {
2725 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2726 cpu_gpr[rB(ctx->opcode)]);
2727 } else {
2728 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2729 }
2730 if (unlikely(Rc(ctx->opcode) != 0)) {
2731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2732 }
2733 }
2734
2735 /* ori */
2736 static void gen_ori(DisasContext *ctx)
2737 {
2738 target_ulong uimm = UIMM(ctx->opcode);
2739
2740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2741 return;
2742 }
2743 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2744 }
2745
2746 /* oris */
2747 static void gen_oris(DisasContext *ctx)
2748 {
2749 target_ulong uimm = UIMM(ctx->opcode);
2750
2751 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2752 /* NOP */
2753 return;
2754 }
2755 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2756 uimm << 16);
2757 }
2758
2759 /* xori */
2760 static void gen_xori(DisasContext *ctx)
2761 {
2762 target_ulong uimm = UIMM(ctx->opcode);
2763
2764 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2765 /* NOP */
2766 return;
2767 }
2768 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2769 }
2770
2771 /* xoris */
2772 static void gen_xoris(DisasContext *ctx)
2773 {
2774 target_ulong uimm = UIMM(ctx->opcode);
2775
2776 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2777 /* NOP */
2778 return;
2779 }
2780 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2781 uimm << 16);
2782 }
2783
2784 /* popcntb : PowerPC 2.03 specification */
2785 static void gen_popcntb(DisasContext *ctx)
2786 {
2787 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2788 }
2789
2790 static void gen_popcntw(DisasContext *ctx)
2791 {
2792 #if defined(TARGET_PPC64)
2793 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2794 #else
2795 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2796 #endif
2797 }
2798
2799 #if defined(TARGET_PPC64)
2800 /* popcntd: PowerPC 2.06 specification */
2801 static void gen_popcntd(DisasContext *ctx)
2802 {
2803 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2804 }
2805 #endif
2806
2807 /* prtyw: PowerPC 2.05 specification */
2808 static void gen_prtyw(DisasContext *ctx)
2809 {
2810 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2811 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2812 TCGv t0 = tcg_temp_new();
2813 tcg_gen_shri_tl(t0, rs, 16);
2814 tcg_gen_xor_tl(ra, rs, t0);
2815 tcg_gen_shri_tl(t0, ra, 8);
2816 tcg_gen_xor_tl(ra, ra, t0);
2817 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2818 tcg_temp_free(t0);
2819 }
2820
2821 #if defined(TARGET_PPC64)
2822 /* prtyd: PowerPC 2.05 specification */
2823 static void gen_prtyd(DisasContext *ctx)
2824 {
2825 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2826 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2827 TCGv t0 = tcg_temp_new();
2828 tcg_gen_shri_tl(t0, rs, 32);
2829 tcg_gen_xor_tl(ra, rs, t0);
2830 tcg_gen_shri_tl(t0, ra, 16);
2831 tcg_gen_xor_tl(ra, ra, t0);
2832 tcg_gen_shri_tl(t0, ra, 8);
2833 tcg_gen_xor_tl(ra, ra, t0);
2834 tcg_gen_andi_tl(ra, ra, 1);
2835 tcg_temp_free(t0);
2836 }
2837 #endif
2838
2839 #if defined(TARGET_PPC64)
2840 /* bpermd */
2841 static void gen_bpermd(DisasContext *ctx)
2842 {
2843 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2844 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2845 }
2846 #endif
2847
2848 #if defined(TARGET_PPC64)
2849 /* extsw & extsw. */
2850 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
2851
2852 /* cntlzd */
2853 static void gen_cntlzd(DisasContext *ctx)
2854 {
2855 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2856 if (unlikely(Rc(ctx->opcode) != 0)) {
2857 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2858 }
2859 }
2860
2861 /* cnttzd */
2862 static void gen_cnttzd(DisasContext *ctx)
2863 {
2864 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2865 if (unlikely(Rc(ctx->opcode) != 0)) {
2866 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2867 }
2868 }
2869
2870 /* darn */
2871 static void gen_darn(DisasContext *ctx)
2872 {
2873 int l = L(ctx->opcode);
2874
2875 if (l > 2) {
2876 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
2877 } else {
2878 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
2879 gen_io_start();
2880 }
2881 if (l == 0) {
2882 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2883 } else {
2884 /* Return 64-bit random for both CRN and RRN */
2885 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2886 }
2887 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
2888 gen_stop_exception(ctx);
2889 }
2890 }
2891 }
2892 #endif
2893
2894 /*** Integer rotate ***/
2895
2896 /* rlwimi & rlwimi. */
2897 static void gen_rlwimi(DisasContext *ctx)
2898 {
2899 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2900 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2901 uint32_t sh = SH(ctx->opcode);
2902 uint32_t mb = MB(ctx->opcode);
2903 uint32_t me = ME(ctx->opcode);
2904
2905 if (sh == (31 - me) && mb <= me) {
2906 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2907 } else {
2908 target_ulong mask;
2909 bool mask_in_32b = true;
2910 TCGv t1;
2911
2912 #if defined(TARGET_PPC64)
2913 mb += 32;
2914 me += 32;
2915 #endif
2916 mask = MASK(mb, me);
2917
2918 #if defined(TARGET_PPC64)
2919 if (mask > 0xffffffffu) {
2920 mask_in_32b = false;
2921 }
2922 #endif
2923 t1 = tcg_temp_new();
2924 if (mask_in_32b) {
2925 TCGv_i32 t0 = tcg_temp_new_i32();
2926 tcg_gen_trunc_tl_i32(t0, t_rs);
2927 tcg_gen_rotli_i32(t0, t0, sh);
2928 tcg_gen_extu_i32_tl(t1, t0);
2929 tcg_temp_free_i32(t0);
2930 } else {
2931 #if defined(TARGET_PPC64)
2932 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2933 tcg_gen_rotli_i64(t1, t1, sh);
2934 #else
2935 g_assert_not_reached();
2936 #endif
2937 }
2938
2939 tcg_gen_andi_tl(t1, t1, mask);
2940 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2941 tcg_gen_or_tl(t_ra, t_ra, t1);
2942 tcg_temp_free(t1);
2943 }
2944 if (unlikely(Rc(ctx->opcode) != 0)) {
2945 gen_set_Rc0(ctx, t_ra);
2946 }
2947 }
2948
2949 /* rlwinm & rlwinm. */
2950 static void gen_rlwinm(DisasContext *ctx)
2951 {
2952 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2953 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2954 int sh = SH(ctx->opcode);
2955 int mb = MB(ctx->opcode);
2956 int me = ME(ctx->opcode);
2957 int len = me - mb + 1;
2958 int rsh = (32 - sh) & 31;
2959
2960 if (sh != 0 && len > 0 && me == (31 - sh)) {
2961 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2962 } else if (me == 31 && rsh + len <= 32) {
2963 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2964 } else {
2965 target_ulong mask;
2966 bool mask_in_32b = true;
2967 #if defined(TARGET_PPC64)
2968 mb += 32;
2969 me += 32;
2970 #endif
2971 mask = MASK(mb, me);
2972 #if defined(TARGET_PPC64)
2973 if (mask > 0xffffffffu) {
2974 mask_in_32b = false;
2975 }
2976 #endif
2977 if (mask_in_32b) {
2978 if (sh == 0) {
2979 tcg_gen_andi_tl(t_ra, t_rs, mask);
2980 } else {
2981 TCGv_i32 t0 = tcg_temp_new_i32();
2982 tcg_gen_trunc_tl_i32(t0, t_rs);
2983 tcg_gen_rotli_i32(t0, t0, sh);
2984 tcg_gen_andi_i32(t0, t0, mask);
2985 tcg_gen_extu_i32_tl(t_ra, t0);
2986 tcg_temp_free_i32(t0);
2987 }
2988 } else {
2989 #if defined(TARGET_PPC64)
2990 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2991 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2992 tcg_gen_andi_i64(t_ra, t_ra, mask);
2993 #else
2994 g_assert_not_reached();
2995 #endif
2996 }
2997 }
2998 if (unlikely(Rc(ctx->opcode) != 0)) {
2999 gen_set_Rc0(ctx, t_ra);
3000 }
3001 }
3002
3003 /* rlwnm & rlwnm. */
3004 static void gen_rlwnm(DisasContext *ctx)
3005 {
3006 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3007 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3008 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
3009 uint32_t mb = MB(ctx->opcode);
3010 uint32_t me = ME(ctx->opcode);
3011 target_ulong mask;
3012 bool mask_in_32b = true;
3013
3014 #if defined(TARGET_PPC64)
3015 mb += 32;
3016 me += 32;
3017 #endif
3018 mask = MASK(mb, me);
3019
3020 #if defined(TARGET_PPC64)
3021 if (mask > 0xffffffffu) {
3022 mask_in_32b = false;
3023 }
3024 #endif
3025 if (mask_in_32b) {
3026 TCGv_i32 t0 = tcg_temp_new_i32();
3027 TCGv_i32 t1 = tcg_temp_new_i32();
3028 tcg_gen_trunc_tl_i32(t0, t_rb);
3029 tcg_gen_trunc_tl_i32(t1, t_rs);
3030 tcg_gen_andi_i32(t0, t0, 0x1f);
3031 tcg_gen_rotl_i32(t1, t1, t0);
3032 tcg_gen_extu_i32_tl(t_ra, t1);
3033 tcg_temp_free_i32(t0);
3034 tcg_temp_free_i32(t1);
3035 } else {
3036 #if defined(TARGET_PPC64)
3037 TCGv_i64 t0 = tcg_temp_new_i64();
3038 tcg_gen_andi_i64(t0, t_rb, 0x1f);
3039 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
3040 tcg_gen_rotl_i64(t_ra, t_ra, t0);
3041 tcg_temp_free_i64(t0);
3042 #else
3043 g_assert_not_reached();
3044 #endif
3045 }
3046
3047 tcg_gen_andi_tl(t_ra, t_ra, mask);
3048
3049 if (unlikely(Rc(ctx->opcode) != 0)) {
3050 gen_set_Rc0(ctx, t_ra);
3051 }
3052 }
3053
3054 #if defined(TARGET_PPC64)
3055 #define GEN_PPC64_R2(name, opc1, opc2) \
3056 static void glue(gen_, name##0)(DisasContext *ctx) \
3057 { \
3058 gen_##name(ctx, 0); \
3059 } \
3060 \
3061 static void glue(gen_, name##1)(DisasContext *ctx) \
3062 { \
3063 gen_##name(ctx, 1); \
3064 }
3065 #define GEN_PPC64_R4(name, opc1, opc2) \
3066 static void glue(gen_, name##0)(DisasContext *ctx) \
3067 { \
3068 gen_##name(ctx, 0, 0); \
3069 } \
3070 \
3071 static void glue(gen_, name##1)(DisasContext *ctx) \
3072 { \
3073 gen_##name(ctx, 0, 1); \
3074 } \
3075 \
3076 static void glue(gen_, name##2)(DisasContext *ctx) \
3077 { \
3078 gen_##name(ctx, 1, 0); \
3079 } \
3080 \
3081 static void glue(gen_, name##3)(DisasContext *ctx) \
3082 { \
3083 gen_##name(ctx, 1, 1); \
3084 }
3085
3086 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
3087 {
3088 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3089 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3090 int len = me - mb + 1;
3091 int rsh = (64 - sh) & 63;
3092
3093 if (sh != 0 && len > 0 && me == (63 - sh)) {
3094 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
3095 } else if (me == 63 && rsh + len <= 64) {
3096 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
3097 } else {
3098 tcg_gen_rotli_tl(t_ra, t_rs, sh);
3099 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
3100 }
3101 if (unlikely(Rc(ctx->opcode) != 0)) {
3102 gen_set_Rc0(ctx, t_ra);
3103 }
3104 }
3105
3106 /* rldicl - rldicl. */
3107 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
3108 {
3109 uint32_t sh, mb;
3110
3111 sh = SH(ctx->opcode) | (shn << 5);
3112 mb = MB(ctx->opcode) | (mbn << 5);
3113 gen_rldinm(ctx, mb, 63, sh);
3114 }
3115 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
3116
3117 /* rldicr - rldicr. */
3118 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
3119 {
3120 uint32_t sh, me;
3121
3122 sh = SH(ctx->opcode) | (shn << 5);
3123 me = MB(ctx->opcode) | (men << 5);
3124 gen_rldinm(ctx, 0, me, sh);
3125 }
3126 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
3127
3128 /* rldic - rldic. */
3129 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
3130 {
3131 uint32_t sh, mb;
3132
3133 sh = SH(ctx->opcode) | (shn << 5);
3134 mb = MB(ctx->opcode) | (mbn << 5);
3135 gen_rldinm(ctx, mb, 63 - sh, sh);
3136 }
3137 GEN_PPC64_R4(rldic, 0x1E, 0x04);
3138
3139 static void gen_rldnm(DisasContext *ctx, int mb, int me)
3140 {
3141 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3142 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3143 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
3144 TCGv t0;
3145
3146 t0 = tcg_temp_new();
3147 tcg_gen_andi_tl(t0, t_rb, 0x3f);
3148 tcg_gen_rotl_tl(t_ra, t_rs, t0);
3149 tcg_temp_free(t0);
3150
3151 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
3152 if (unlikely(Rc(ctx->opcode) != 0)) {
3153 gen_set_Rc0(ctx, t_ra);
3154 }
3155 }
3156
3157 /* rldcl - rldcl. */
3158 static inline void gen_rldcl(DisasContext *ctx, int mbn)
3159 {
3160 uint32_t mb;
3161
3162 mb = MB(ctx->opcode) | (mbn << 5);
3163 gen_rldnm(ctx, mb, 63);
3164 }
3165 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
3166
3167 /* rldcr - rldcr. */
3168 static inline void gen_rldcr(DisasContext *ctx, int men)
3169 {
3170 uint32_t me;
3171
3172 me = MB(ctx->opcode) | (men << 5);
3173 gen_rldnm(ctx, 0, me);
3174 }
3175 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
3176
3177 /* rldimi - rldimi. */
3178 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
3179 {
3180 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3181 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3182 uint32_t sh = SH(ctx->opcode) | (shn << 5);
3183 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
3184 uint32_t me = 63 - sh;
3185
3186 if (mb <= me) {
3187 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
3188 } else {
3189 target_ulong mask = MASK(mb, me);
3190 TCGv t1 = tcg_temp_new();
3191
3192 tcg_gen_rotli_tl(t1, t_rs, sh);
3193 tcg_gen_andi_tl(t1, t1, mask);
3194 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
3195 tcg_gen_or_tl(t_ra, t_ra, t1);
3196 tcg_temp_free(t1);
3197 }
3198 if (unlikely(Rc(ctx->opcode) != 0)) {
3199 gen_set_Rc0(ctx, t_ra);
3200 }
3201 }
3202 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
3203 #endif
3204
3205 /*** Integer shift ***/
3206
3207 /* slw & slw. */
3208 static void gen_slw(DisasContext *ctx)
3209 {
3210 TCGv t0, t1;
3211
3212 t0 = tcg_temp_new();
3213 /* AND rS with a mask that is 0 when rB >= 0x20 */
3214 #if defined(TARGET_PPC64)
3215 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3216 tcg_gen_sari_tl(t0, t0, 0x3f);
3217 #else
3218 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3219 tcg_gen_sari_tl(t0, t0, 0x1f);
3220 #endif
3221 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3222 t1 = tcg_temp_new();
3223 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3224 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3225 tcg_temp_free(t1);
3226 tcg_temp_free(t0);
3227 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
3228 if (unlikely(Rc(ctx->opcode) != 0)) {
3229 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3230 }
3231 }
3232
3233 /* sraw & sraw. */
3234 static void gen_sraw(DisasContext *ctx)
3235 {
3236 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
3237 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3238 if (unlikely(Rc(ctx->opcode) != 0)) {
3239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3240 }
3241 }
3242
3243 /* srawi & srawi. */
3244 static void gen_srawi(DisasContext *ctx)
3245 {
3246 int sh = SH(ctx->opcode);
3247 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3248 TCGv src = cpu_gpr[rS(ctx->opcode)];
3249 if (sh == 0) {
3250 tcg_gen_ext32s_tl(dst, src);
3251 tcg_gen_movi_tl(cpu_ca, 0);
3252 if (is_isa300(ctx)) {
3253 tcg_gen_movi_tl(cpu_ca32, 0);
3254 }
3255 } else {
3256 TCGv t0;
3257 tcg_gen_ext32s_tl(dst, src);
3258 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
3259 t0 = tcg_temp_new();
3260 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
3261 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3262 tcg_temp_free(t0);
3263 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3264 if (is_isa300(ctx)) {
3265 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3266 }
3267 tcg_gen_sari_tl(dst, dst, sh);
3268 }
3269 if (unlikely(Rc(ctx->opcode) != 0)) {
3270 gen_set_Rc0(ctx, dst);
3271 }
3272 }
3273
3274 /* srw & srw. */
3275 static void gen_srw(DisasContext *ctx)
3276 {
3277 TCGv t0, t1;
3278
3279 t0 = tcg_temp_new();
3280 /* AND rS with a mask that is 0 when rB >= 0x20 */
3281 #if defined(TARGET_PPC64)
3282 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3283 tcg_gen_sari_tl(t0, t0, 0x3f);
3284 #else
3285 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3286 tcg_gen_sari_tl(t0, t0, 0x1f);
3287 #endif
3288 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3289 tcg_gen_ext32u_tl(t0, t0);
3290 t1 = tcg_temp_new();
3291 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3292 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3293 tcg_temp_free(t1);
3294 tcg_temp_free(t0);
3295 if (unlikely(Rc(ctx->opcode) != 0)) {
3296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3297 }
3298 }
3299
3300 #if defined(TARGET_PPC64)
3301 /* sld & sld. */
3302 static void gen_sld(DisasContext *ctx)
3303 {
3304 TCGv t0, t1;
3305
3306 t0 = tcg_temp_new();
3307 /* AND rS with a mask that is 0 when rB >= 0x40 */
3308 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3309 tcg_gen_sari_tl(t0, t0, 0x3f);
3310 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3311 t1 = tcg_temp_new();
3312 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3313 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3314 tcg_temp_free(t1);
3315 tcg_temp_free(t0);
3316 if (unlikely(Rc(ctx->opcode) != 0)) {
3317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3318 }
3319 }
3320
3321 /* srad & srad. */
3322 static void gen_srad(DisasContext *ctx)
3323 {
3324 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
3325 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3326 if (unlikely(Rc(ctx->opcode) != 0)) {
3327 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3328 }
3329 }
3330 /* sradi & sradi. */
3331 static inline void gen_sradi(DisasContext *ctx, int n)
3332 {
3333 int sh = SH(ctx->opcode) + (n << 5);
3334 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3335 TCGv src = cpu_gpr[rS(ctx->opcode)];
3336 if (sh == 0) {
3337 tcg_gen_mov_tl(dst, src);
3338 tcg_gen_movi_tl(cpu_ca, 0);
3339 if (is_isa300(ctx)) {
3340 tcg_gen_movi_tl(cpu_ca32, 0);
3341 }
3342 } else {
3343 TCGv t0;
3344 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
3345 t0 = tcg_temp_new();
3346 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
3347 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3348 tcg_temp_free(t0);
3349 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3350 if (is_isa300(ctx)) {
3351 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3352 }
3353 tcg_gen_sari_tl(dst, src, sh);
3354 }
3355 if (unlikely(Rc(ctx->opcode) != 0)) {
3356 gen_set_Rc0(ctx, dst);
3357 }
3358 }
3359
3360 static void gen_sradi0(DisasContext *ctx)
3361 {
3362 gen_sradi(ctx, 0);
3363 }
3364
3365 static void gen_sradi1(DisasContext *ctx)
3366 {
3367 gen_sradi(ctx, 1);
3368 }
3369
3370 /* extswsli & extswsli. */
3371 static inline void gen_extswsli(DisasContext *ctx, int n)
3372 {
3373 int sh = SH(ctx->opcode) + (n << 5);
3374 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3375 TCGv src = cpu_gpr[rS(ctx->opcode)];
3376
3377 tcg_gen_ext32s_tl(dst, src);
3378 tcg_gen_shli_tl(dst, dst, sh);
3379 if (unlikely(Rc(ctx->opcode) != 0)) {
3380 gen_set_Rc0(ctx, dst);
3381 }
3382 }
3383
3384 static void gen_extswsli0(DisasContext *ctx)
3385 {
3386 gen_extswsli(ctx, 0);
3387 }
3388
3389 static void gen_extswsli1(DisasContext *ctx)
3390 {
3391 gen_extswsli(ctx, 1);
3392 }
3393
3394 /* srd & srd. */
3395 static void gen_srd(DisasContext *ctx)
3396 {
3397 TCGv t0, t1;
3398
3399 t0 = tcg_temp_new();
3400 /* AND rS with a mask that is 0 when rB >= 0x40 */
3401 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3402 tcg_gen_sari_tl(t0, t0, 0x3f);
3403 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3404 t1 = tcg_temp_new();
3405 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3406 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3407 tcg_temp_free(t1);
3408 tcg_temp_free(t0);
3409 if (unlikely(Rc(ctx->opcode) != 0)) {
3410 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3411 }
3412 }
3413 #endif
3414
3415 /*** Addressing modes ***/
3416 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
3417 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
3418 target_long maskl)
3419 {
3420 target_long simm = SIMM(ctx->opcode);
3421
3422 simm &= ~maskl;
3423 if (rA(ctx->opcode) == 0) {
3424 if (NARROW_MODE(ctx)) {
3425 simm = (uint32_t)simm;
3426 }
3427 tcg_gen_movi_tl(EA, simm);
3428 } else if (likely(simm != 0)) {
3429 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
3430 if (NARROW_MODE(ctx)) {
3431 tcg_gen_ext32u_tl(EA, EA);
3432 }
3433 } else {
3434 if (NARROW_MODE(ctx)) {
3435 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3436 } else {
3437 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3438 }
3439 }
3440 }
3441
3442 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
3443 {
3444 if (rA(ctx->opcode) == 0) {
3445 if (NARROW_MODE(ctx)) {
3446 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3447 } else {
3448 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3449 }
3450 } else {
3451 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3452 if (NARROW_MODE(ctx)) {
3453 tcg_gen_ext32u_tl(EA, EA);
3454 }
3455 }
3456 }
3457
3458 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
3459 {
3460 if (rA(ctx->opcode) == 0) {
3461 tcg_gen_movi_tl(EA, 0);
3462 } else if (NARROW_MODE(ctx)) {
3463 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3464 } else {
3465 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3466 }
3467 }
3468
3469 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3470 target_long val)
3471 {
3472 tcg_gen_addi_tl(ret, arg1, val);
3473 if (NARROW_MODE(ctx)) {
3474 tcg_gen_ext32u_tl(ret, ret);
3475 }
3476 }
3477
3478 static inline void gen_align_no_le(DisasContext *ctx)
3479 {
3480 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3481 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3482 }
3483
3484 /*** Integer load ***/
3485 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3486 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3487
3488 #define GEN_QEMU_LOAD_TL(ldop, op) \
3489 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
3490 TCGv val, \
3491 TCGv addr) \
3492 { \
3493 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
3494 }
3495
3496 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
3497 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3498 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3499 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3500 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
3501
3502 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3503 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3504
3505 #define GEN_QEMU_LOAD_64(ldop, op) \
3506 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
3507 TCGv_i64 val, \
3508 TCGv addr) \
3509 { \
3510 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
3511 }
3512
3513 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
3514 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
3515 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3516 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
3517 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
3518
3519 #if defined(TARGET_PPC64)
3520 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
3521 #endif
3522
3523 #define GEN_QEMU_STORE_TL(stop, op) \
3524 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
3525 TCGv val, \
3526 TCGv addr) \
3527 { \
3528 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
3529 }
3530
3531 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
3532 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3533 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
3534
3535 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3536 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3537
3538 #define GEN_QEMU_STORE_64(stop, op) \
3539 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
3540 TCGv_i64 val, \
3541 TCGv addr) \
3542 { \
3543 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
3544 }
3545
3546 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
3547 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
3548 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
3549 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
3550
3551 #if defined(TARGET_PPC64)
3552 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
3553 #endif
3554
3555 #define GEN_LD(name, ldop, opc, type) \
3556 static void glue(gen_, name)(DisasContext *ctx) \
3557 { \
3558 TCGv EA; \
3559 gen_set_access_type(ctx, ACCESS_INT); \
3560 EA = tcg_temp_new(); \
3561 gen_addr_imm_index(ctx, EA, 0); \
3562 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3563 tcg_temp_free(EA); \
3564 }
3565
3566 #define GEN_LDU(name, ldop, opc, type) \
3567 static void glue(gen_, name##u)(DisasContext *ctx) \
3568 { \
3569 TCGv EA; \
3570 if (unlikely(rA(ctx->opcode) == 0 || \
3571 rA(ctx->opcode) == rD(ctx->opcode))) { \
3572 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3573 return; \
3574 } \
3575 gen_set_access_type(ctx, ACCESS_INT); \
3576 EA = tcg_temp_new(); \
3577 if (type == PPC_64B) \
3578 gen_addr_imm_index(ctx, EA, 0x03); \
3579 else \
3580 gen_addr_imm_index(ctx, EA, 0); \
3581 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3582 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3583 tcg_temp_free(EA); \
3584 }
3585
3586 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
3587 static void glue(gen_, name##ux)(DisasContext *ctx) \
3588 { \
3589 TCGv EA; \
3590 if (unlikely(rA(ctx->opcode) == 0 || \
3591 rA(ctx->opcode) == rD(ctx->opcode))) { \
3592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3593 return; \
3594 } \
3595 gen_set_access_type(ctx, ACCESS_INT); \
3596 EA = tcg_temp_new(); \
3597 gen_addr_reg_index(ctx, EA); \
3598 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3599 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3600 tcg_temp_free(EA); \
3601 }
3602
3603 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
3604 static void glue(gen_, name##x)(DisasContext *ctx) \
3605 { \
3606 TCGv EA; \
3607 chk; \
3608 gen_set_access_type(ctx, ACCESS_INT); \
3609 EA = tcg_temp_new(); \
3610 gen_addr_reg_index(ctx, EA); \
3611 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3612 tcg_temp_free(EA); \
3613 }
3614
3615 #define GEN_LDX(name, ldop, opc2, opc3, type) \
3616 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3617
3618 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3619 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3620
3621 #define GEN_LDS(name, ldop, op, type) \
3622 GEN_LD(name, ldop, op | 0x20, type); \
3623 GEN_LDU(name, ldop, op | 0x21, type); \
3624 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
3625 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
3626
3627 /* lbz lbzu lbzux lbzx */
3628 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
3629 /* lha lhau lhaux lhax */
3630 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
3631 /* lhz lhzu lhzux lhzx */
3632 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
3633 /* lwz lwzu lwzux lwzx */
3634 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
3635
3636 #define GEN_LDEPX(name, ldop, opc2, opc3) \
3637 static void glue(gen_, name##epx)(DisasContext *ctx) \
3638 { \
3639 TCGv EA; \
3640 CHK_SV; \
3641 gen_set_access_type(ctx, ACCESS_INT); \
3642 EA = tcg_temp_new(); \
3643 gen_addr_reg_index(ctx, EA); \
3644 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3645 tcg_temp_free(EA); \
3646 }
3647
3648 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3649 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3650 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3651 #if defined(TARGET_PPC64)
3652 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
3653 #endif
3654
3655 #if defined(TARGET_PPC64)
3656 /* lwaux */
3657 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
3658 /* lwax */
3659 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
3660 /* ldux */
3661 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
3662 /* ldx */
3663 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
3664
3665 /* CI load/store variants */
3666 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
3667 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3668 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3669 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3670
3671 static void gen_ld(DisasContext *ctx)
3672 {
3673 TCGv EA;
3674 if (Rc(ctx->opcode)) {
3675 if (unlikely(rA(ctx->opcode) == 0 ||
3676 rA(ctx->opcode) == rD(ctx->opcode))) {
3677 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3678 return;
3679 }
3680 }
3681 gen_set_access_type(ctx, ACCESS_INT);
3682 EA = tcg_temp_new();
3683 gen_addr_imm_index(ctx, EA, 0x03);
3684 if (ctx->opcode & 0x02) {
3685 /* lwa (lwau is undefined) */
3686 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3687 } else {
3688 /* ld - ldu */
3689 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3690 }
3691 if (Rc(ctx->opcode)) {
3692 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3693 }
3694 tcg_temp_free(EA);
3695 }
3696
3697 /* lq */
3698 static void gen_lq(DisasContext *ctx)
3699 {
3700 int ra, rd;
3701 TCGv EA, hi, lo;
3702
3703 /* lq is a legal user mode instruction starting in ISA 2.07 */
3704 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3705 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3706
3707 if (!legal_in_user_mode && ctx->pr) {
3708 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3709 return;
3710 }
3711
3712 if (!le_is_supported && ctx->le_mode) {
3713 gen_align_no_le(ctx);
3714 return;
3715 }
3716 ra = rA(ctx->opcode);
3717 rd = rD(ctx->opcode);
3718 if (unlikely((rd & 1) || rd == ra)) {
3719 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3720 return;
3721 }
3722
3723 gen_set_access_type(ctx, ACCESS_INT);
3724 EA = tcg_temp_new();
3725 gen_addr_imm_index(ctx, EA, 0x0F);
3726
3727 /* Note that the low part is always in RD+1, even in LE mode. */
3728 lo = cpu_gpr[rd + 1];
3729 hi = cpu_gpr[rd];
3730
3731 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3732 if (HAVE_ATOMIC128) {
3733 TCGv_i32 oi = tcg_temp_new_i32();
3734 if (ctx->le_mode) {
3735 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
3736 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3737 } else {
3738 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
3739 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3740 }
3741 tcg_temp_free_i32(oi);
3742 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3743 } else {
3744 /* Restart with exclusive lock. */
3745 gen_helper_exit_atomic(cpu_env);
3746 ctx->base.is_jmp = DISAS_NORETURN;
3747 }
3748 } else if (ctx->le_mode) {
3749 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
3750 gen_addr_add(ctx, EA, EA, 8);
3751 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3752 } else {
3753 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
3754 gen_addr_add(ctx, EA, EA, 8);
3755 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3756 }
3757 tcg_temp_free(EA);
3758 }
3759 #endif
3760
3761 /*** Integer store ***/
3762 #define GEN_ST(name, stop, opc, type) \
3763 static void glue(gen_, name)(DisasContext *ctx) \
3764 { \
3765 TCGv EA; \
3766 gen_set_access_type(ctx, ACCESS_INT); \
3767 EA = tcg_temp_new(); \
3768 gen_addr_imm_index(ctx, EA, 0); \
3769 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3770 tcg_temp_free(EA); \
3771 }
3772
3773 #define GEN_STU(name, stop, opc, type) \
3774 static void glue(gen_, stop##u)(DisasContext *ctx) \
3775 { \
3776 TCGv EA; \
3777 if (unlikely(rA(ctx->opcode) == 0)) { \
3778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3779 return; \
3780 } \
3781 gen_set_access_type(ctx, ACCESS_INT); \
3782 EA = tcg_temp_new(); \
3783 if (type == PPC_64B) \
3784 gen_addr_imm_index(ctx, EA, 0x03); \
3785 else \
3786 gen_addr_imm_index(ctx, EA, 0); \
3787 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3789 tcg_temp_free(EA); \
3790 }
3791
3792 #define GEN_STUX(name, stop, opc2, opc3, type) \
3793 static void glue(gen_, name##ux)(DisasContext *ctx) \
3794 { \
3795 TCGv EA; \
3796 if (unlikely(rA(ctx->opcode) == 0)) { \
3797 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3798 return; \
3799 } \
3800 gen_set_access_type(ctx, ACCESS_INT); \
3801 EA = tcg_temp_new(); \
3802 gen_addr_reg_index(ctx, EA); \
3803 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3805 tcg_temp_free(EA); \
3806 }
3807
3808 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3809 static void glue(gen_, name##x)(DisasContext *ctx) \
3810 { \
3811 TCGv EA; \
3812 chk; \
3813 gen_set_access_type(ctx, ACCESS_INT); \
3814 EA = tcg_temp_new(); \
3815 gen_addr_reg_index(ctx, EA); \
3816 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3817 tcg_temp_free(EA); \
3818 }
3819 #define GEN_STX(name, stop, opc2, opc3, type) \
3820 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3821
3822 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3823 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3824
3825 #define GEN_STS(name, stop, op, type) \
3826 GEN_ST(name, stop, op | 0x20, type); \
3827 GEN_STU(name, stop, op | 0x21, type); \
3828 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3829 GEN_STX(name, stop, 0x17, op | 0x00, type)
3830
3831 /* stb stbu stbux stbx */
3832 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3833 /* sth sthu sthux sthx */
3834 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3835 /* stw stwu stwux stwx */
3836 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3837
3838 #define GEN_STEPX(name, stop, opc2, opc3) \
3839 static void glue(gen_, name##epx)(DisasContext *ctx) \
3840 { \
3841 TCGv EA; \
3842 CHK_SV; \
3843 gen_set_access_type(ctx, ACCESS_INT); \
3844 EA = tcg_temp_new(); \
3845 gen_addr_reg_index(ctx, EA); \
3846 tcg_gen_qemu_st_tl( \
3847 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
3848 tcg_temp_free(EA); \
3849 }
3850
3851 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3852 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3853 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3854 #if defined(TARGET_PPC64)
3855 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
3856 #endif
3857
3858 #if defined(TARGET_PPC64)
3859 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
3860 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
3861 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
3862 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3863 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3864 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3865
3866 static void gen_std(DisasContext *ctx)
3867 {
3868 int rs;
3869 TCGv EA;
3870
3871 rs = rS(ctx->opcode);
3872 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3873 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3874 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3875 TCGv hi, lo;
3876
3877 if (!(ctx->insns_flags & PPC_64BX)) {
3878 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3879 }
3880
3881 if (!legal_in_user_mode && ctx->pr) {
3882 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3883 return;
3884 }
3885
3886 if (!le_is_supported && ctx->le_mode) {
3887 gen_align_no_le(ctx);
3888 return;
3889 }
3890
3891 if (unlikely(rs & 1)) {
3892 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3893 return;
3894 }
3895 gen_set_access_type(ctx, ACCESS_INT);
3896 EA = tcg_temp_new();
3897 gen_addr_imm_index(ctx, EA, 0x03);
3898
3899 /* Note that the low part is always in RS+1, even in LE mode. */
3900 lo = cpu_gpr[rs + 1];
3901 hi = cpu_gpr[rs];
3902
3903 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3904 if (HAVE_ATOMIC128) {
3905 TCGv_i32 oi = tcg_temp_new_i32();
3906 if (ctx->le_mode) {
3907 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
3908 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
3909 } else {
3910 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
3911 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
3912 }
3913 tcg_temp_free_i32(oi);
3914 } else {
3915 /* Restart with exclusive lock. */
3916 gen_helper_exit_atomic(cpu_env);
3917 ctx->base.is_jmp = DISAS_NORETURN;
3918 }
3919 } else if (ctx->le_mode) {
3920 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
3921 gen_addr_add(ctx, EA, EA, 8);
3922 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3923 } else {
3924 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
3925 gen_addr_add(ctx, EA, EA, 8);
3926 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3927 }
3928 tcg_temp_free(EA);
3929 } else {
3930 /* std / stdu */
3931 if (Rc(ctx->opcode)) {
3932 if (unlikely(rA(ctx->opcode) == 0)) {
3933 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3934 return;
3935 }
3936 }
3937 gen_set_access_type(ctx, ACCESS_INT);
3938 EA = tcg_temp_new();
3939 gen_addr_imm_index(ctx, EA, 0x03);
3940 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
3941 if (Rc(ctx->opcode)) {
3942 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3943 }
3944 tcg_temp_free(EA);
3945 }
3946 }
3947 #endif
3948 /*** Integer load and store with byte reverse ***/
3949
3950 /* lhbrx */
3951 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3952
3953 /* lwbrx */
3954 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3955
3956 #if defined(TARGET_PPC64)
3957 /* ldbrx */
3958 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3959 /* stdbrx */
3960 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3961 #endif /* TARGET_PPC64 */
3962
3963 /* sthbrx */
3964 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3965 /* stwbrx */
3966 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3967
3968 /*** Integer load and store multiple ***/
3969
3970 /* lmw */
3971 static void gen_lmw(DisasContext *ctx)
3972 {
3973 TCGv t0;
3974 TCGv_i32 t1;
3975
3976 if (ctx->le_mode) {
3977 gen_align_no_le(ctx);
3978 return;
3979 }
3980 gen_set_access_type(ctx, ACCESS_INT);
3981 t0 = tcg_temp_new();
3982 t1 = tcg_const_i32(rD(ctx->opcode));
3983 gen_addr_imm_index(ctx, t0, 0);
3984 gen_helper_lmw(cpu_env, t0, t1);
3985 tcg_temp_free(t0);
3986 tcg_temp_free_i32(t1);
3987 }
3988
3989 /* stmw */
3990 static void gen_stmw(DisasContext *ctx)
3991 {
3992 TCGv t0;
3993 TCGv_i32 t1;
3994
3995 if (ctx->le_mode) {
3996 gen_align_no_le(ctx);
3997 return;
3998 }
3999 gen_set_access_type(ctx, ACCESS_INT);
4000 t0 = tcg_temp_new();
4001 t1 = tcg_const_i32(rS(ctx->opcode));
4002 gen_addr_imm_index(ctx, t0, 0);
4003 gen_helper_stmw(cpu_env, t0, t1);
4004 tcg_temp_free(t0);
4005 tcg_temp_free_i32(t1);
4006 }
4007
4008 /*** Integer load and store strings ***/
4009
4010 /* lswi */
4011 /*
4012 * PowerPC32 specification says we must generate an exception if rA is
4013 * in the range of registers to be loaded. In an other hand, IBM says
4014 * this is valid, but rA won't be loaded. For now, I'll follow the
4015 * spec...
4016 */
4017 static void gen_lswi(DisasContext *ctx)
4018 {
4019 TCGv t0;
4020 TCGv_i32 t1, t2;
4021 int nb = NB(ctx->opcode);
4022 int start = rD(ctx->opcode);
4023 int ra = rA(ctx->opcode);
4024 int nr;
4025
4026 if (ctx->le_mode) {
4027 gen_align_no_le(ctx);
4028 return;
4029 }
4030 if (nb == 0) {
4031 nb = 32;
4032 }
4033 nr = DIV_ROUND_UP(nb, 4);
4034 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
4035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4036 return;
4037 }
4038 gen_set_access_type(ctx, ACCESS_INT);
4039 t0 = tcg_temp_new();
4040 gen_addr_register(ctx, t0);
4041 t1 = tcg_const_i32(nb);
4042 t2 = tcg_const_i32(start);
4043 gen_helper_lsw(cpu_env, t0, t1, t2);
4044 tcg_temp_free(t0);
4045 tcg_temp_free_i32(t1);
4046 tcg_temp_free_i32(t2);
4047 }
4048
4049 /* lswx */
4050 static void gen_lswx(DisasContext *ctx)
4051 {
4052 TCGv t0;
4053 TCGv_i32 t1, t2, t3;
4054
4055 if (ctx->le_mode) {
4056 gen_align_no_le(ctx);
4057 return;
4058 }
4059 gen_set_access_type(ctx, ACCESS_INT);
4060 t0 = tcg_temp_new();
4061 gen_addr_reg_index(ctx, t0);
4062 t1 = tcg_const_i32(rD(ctx->opcode));
4063 t2 = tcg_const_i32(rA(ctx->opcode));
4064 t3 = tcg_const_i32(rB(ctx->opcode));
4065 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
4066 tcg_temp_free(t0);
4067 tcg_temp_free_i32(t1);
4068 tcg_temp_free_i32(t2);
4069 tcg_temp_free_i32(t3);
4070 }
4071
4072 /* stswi */
4073 static void gen_stswi(DisasContext *ctx)
4074 {
4075 TCGv t0;
4076 TCGv_i32 t1, t2;
4077 int nb = NB(ctx->opcode);
4078
4079 if (ctx->le_mode) {
4080 gen_align_no_le(ctx);
4081 return;
4082 }
4083 gen_set_access_type(ctx, ACCESS_INT);
4084 t0 = tcg_temp_new();
4085 gen_addr_register(ctx, t0);
4086 if (nb == 0) {
4087 nb = 32;
4088 }
4089 t1 = tcg_const_i32(nb);
4090 t2 = tcg_const_i32(rS(ctx->opcode));
4091 gen_helper_stsw(cpu_env, t0, t1, t2);
4092 tcg_temp_free(t0);
4093 tcg_temp_free_i32(t1);
4094 tcg_temp_free_i32(t2);
4095 }
4096
4097 /* stswx */
4098 static void gen_stswx(DisasContext *ctx)
4099 {
4100 TCGv t0;
4101 TCGv_i32 t1, t2;
4102
4103 if (ctx->le_mode) {
4104 gen_align_no_le(ctx);
4105 return;
4106 }
4107 gen_set_access_type(ctx, ACCESS_INT);
4108 t0 = tcg_temp_new();
4109 gen_addr_reg_index(ctx, t0);
4110 t1 = tcg_temp_new_i32();
4111 tcg_gen_trunc_tl_i32(t1, cpu_xer);
4112 tcg_gen_andi_i32(t1, t1, 0x7F);
4113 t2 = tcg_const_i32(rS(ctx->opcode));
4114 gen_helper_stsw(cpu_env, t0, t1, t2);
4115 tcg_temp_free(t0);
4116 tcg_temp_free_i32(t1);
4117 tcg_temp_free_i32(t2);
4118 }
4119
4120 /*** Memory synchronisation ***/
4121 /* eieio */
4122 static void gen_eieio(DisasContext *ctx)
4123 {
4124 TCGBar bar = TCG_MO_LD_ST;
4125
4126 /*
4127 * POWER9 has a eieio instruction variant using bit 6 as a hint to
4128 * tell the CPU it is a store-forwarding barrier.
4129 */
4130 if (ctx->opcode & 0x2000000) {
4131 /*
4132 * ISA says that "Reserved fields in instructions are ignored
4133 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
4134 * as this is not an instruction software should be using,
4135 * complain to the user.
4136 */
4137 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
4138 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
4139 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
4140 } else {
4141 bar = TCG_MO_ST_LD;
4142 }
4143 }
4144
4145 tcg_gen_mb(bar | TCG_BAR_SC);
4146 }
4147
4148 #if !defined(CONFIG_USER_ONLY)
4149 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
4150 {
4151 TCGv_i32 t;
4152 TCGLabel *l;
4153
4154 if (!ctx->lazy_tlb_flush) {
4155 return;
4156 }
4157 l = gen_new_label();
4158 t = tcg_temp_new_i32();
4159 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4160 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
4161 if (global) {
4162 gen_helper_check_tlb_flush_global(cpu_env);
4163 } else {
4164 gen_helper_check_tlb_flush_local(cpu_env);
4165 }
4166 gen_set_label(l);
4167 tcg_temp_free_i32(t);
4168 }
4169 #else
4170 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
4171 #endif
4172
4173 /* isync */
4174 static void gen_isync(DisasContext *ctx)
4175 {
4176 /*
4177 * We need to check for a pending TLB flush. This can only happen in
4178 * kernel mode however so check MSR_PR
4179 */
4180 if (!ctx->pr) {
4181 gen_check_tlb_flush(ctx, false);
4182 }
4183 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
4184 gen_stop_exception(ctx);
4185 }
4186
4187 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
4188
4189 static void gen_load_locked(DisasContext *ctx, MemOp memop)
4190 {
4191 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
4192 TCGv t0 = tcg_temp_new();
4193
4194 gen_set_access_type(ctx, ACCESS_RES);
4195 gen_addr_reg_index(ctx, t0);
4196 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
4197 tcg_gen_mov_tl(cpu_reserve, t0);
4198 tcg_gen_mov_tl(cpu_reserve_val, gpr);
4199 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
4200 tcg_temp_free(t0);
4201 }
4202
4203 #define LARX(name, memop) \
4204 static void gen_##name(DisasContext *ctx) \
4205 { \
4206 gen_load_locked(ctx, memop); \
4207 }
4208
4209 /* lwarx */
4210 LARX(lbarx, DEF_MEMOP(MO_UB))
4211 LARX(lharx, DEF_MEMOP(MO_UW))
4212 LARX(lwarx, DEF_MEMOP(MO_UL))
4213
4214 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
4215 TCGv EA, TCGCond cond, int addend)
4216 {
4217 TCGv t = tcg_temp_new();
4218 TCGv t2 = tcg_temp_new();
4219 TCGv u = tcg_temp_new();
4220
4221 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
4222 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
4223 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
4224 tcg_gen_addi_tl(u, t, addend);
4225
4226 /* E.g. for fetch and increment bounded... */
4227 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
4228 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
4229 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
4230
4231 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
4232 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
4233 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
4234
4235 tcg_temp_free(t);
4236 tcg_temp_free(t2);
4237 tcg_temp_free(u);
4238 }
4239
4240 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
4241 {
4242 uint32_t gpr_FC = FC(ctx->opcode);
4243 TCGv EA = tcg_temp_new();
4244 int rt = rD(ctx->opcode);
4245 bool need_serial;
4246 TCGv src, dst;
4247
4248 gen_addr_register(ctx, EA);
4249 dst = cpu_gpr[rt];
4250 src = cpu_gpr[(rt + 1) & 31];
4251
4252 need_serial = false;
4253 memop |= MO_ALIGN;
4254 switch (gpr_FC) {
4255 case 0: /* Fetch and add */
4256 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
4257 break;
4258 case 1: /* Fetch and xor */
4259 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
4260 break;
4261 case 2: /* Fetch and or */
4262 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
4263 break;
4264 case 3: /* Fetch and 'and' */
4265 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
4266 break;
4267 case 4: /* Fetch and max unsigned */
4268 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
4269 break;
4270 case 5: /* Fetch and max signed */
4271 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
4272 break;
4273 case 6: /* Fetch and min unsigned */
4274 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
4275 break;
4276 case 7: /* Fetch and min signed */
4277 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
4278 break;
4279 case 8: /* Swap */
4280 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
4281 break;
4282
4283 case 16: /* Compare and swap not equal */
4284 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4285 need_serial = true;
4286 } else {
4287 TCGv t0 = tcg_temp_new();
4288 TCGv t1 = tcg_temp_new();
4289
4290 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
4291 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
4292 tcg_gen_mov_tl(t1, src);
4293 } else {
4294 tcg_gen_ext32u_tl(t1, src);
4295 }
4296 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
4297 cpu_gpr[(rt + 2) & 31], t0);
4298 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
4299 tcg_gen_mov_tl(dst, t0);
4300
4301 tcg_temp_free(t0);
4302 tcg_temp_free(t1);
4303 }
4304 break;
4305
4306 case 24: /* Fetch and increment bounded */
4307 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4308 need_serial = true;
4309 } else {
4310 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
4311 }
4312 break;
4313 case 25: /* Fetch and increment equal */
4314 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4315 need_serial = true;
4316 } else {
4317 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
4318 }
4319 break;
4320 case 28: /* Fetch and decrement bounded */
4321 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4322 need_serial = true;
4323 } else {
4324 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
4325 }
4326 break;
4327
4328 default:
4329 /* invoke data storage error handler */
4330 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
4331 }
4332 tcg_temp_free(EA);
4333
4334 if (need_serial) {
4335 /* Restart with exclusive lock. */
4336 gen_helper_exit_atomic(cpu_env);
4337 ctx->base.is_jmp = DISAS_NORETURN;
4338 }
4339 }
4340
4341 static void gen_lwat(DisasContext *ctx)
4342 {
4343 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
4344 }
4345
4346 #ifdef TARGET_PPC64
4347 static void gen_ldat(DisasContext *ctx)
4348 {
4349 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
4350 }
4351 #endif
4352
4353 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
4354 {
4355 uint32_t gpr_FC = FC(ctx->opcode);
4356 TCGv EA = tcg_temp_new();
4357 TCGv src, discard;
4358
4359 gen_addr_register(ctx, EA);
4360 src = cpu_gpr[rD(ctx->opcode)];
4361 discard = tcg_temp_new();
4362
4363 memop |= MO_ALIGN;
4364 switch (gpr_FC) {
4365 case 0: /* add and Store */
4366 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4367 break;
4368 case 1: /* xor and Store */
4369 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4370 break;
4371 case 2: /* Or and Store */
4372 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4373 break;
4374 case 3: /* 'and' and Store */
4375 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4376 break;
4377 case 4: /* Store max unsigned */
4378 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4379 break;
4380 case 5: /* Store max signed */
4381 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4382 break;
4383 case 6: /* Store min unsigned */
4384 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4385 break;
4386 case 7: /* Store min signed */
4387 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4388 break;
4389 case 24: /* Store twin */
4390 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4391 /* Restart with exclusive lock. */
4392 gen_helper_exit_atomic(cpu_env);
4393 ctx->base.is_jmp = DISAS_NORETURN;
4394 } else {
4395 TCGv t = tcg_temp_new();
4396 TCGv t2 = tcg_temp_new();
4397 TCGv s = tcg_temp_new();
4398 TCGv s2 = tcg_temp_new();
4399 TCGv ea_plus_s = tcg_temp_new();
4400
4401 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
4402 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
4403 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
4404 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
4405 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
4406 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
4407 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
4408
4409 tcg_temp_free(ea_plus_s);
4410 tcg_temp_free(s2);
4411 tcg_temp_free(s);
4412 tcg_temp_free(t2);
4413 tcg_temp_free(t);
4414 }
4415 break;
4416 default:
4417 /* invoke data storage error handler */
4418 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
4419 }
4420 tcg_temp_free(discard);
4421 tcg_temp_free(EA);
4422 }
4423
4424 static void gen_stwat(DisasContext *ctx)
4425 {
4426 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
4427 }
4428
4429 #ifdef TARGET_PPC64
4430 static void gen_stdat(DisasContext *ctx)
4431 {
4432 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
4433 }
4434 #endif
4435
4436 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
4437 {
4438 TCGLabel *l1 = gen_new_label();
4439 TCGLabel *l2 = gen_new_label();
4440 TCGv t0 = tcg_temp_new();
4441 int reg = rS(ctx->opcode);
4442
4443 gen_set_access_type(ctx, ACCESS_RES);
4444 gen_addr_reg_index(ctx, t0);
4445 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
4446 tcg_temp_free(t0);
4447
4448 t0 = tcg_temp_new();
4449 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
4450 cpu_gpr[reg], ctx->mem_idx,
4451 DEF_MEMOP(memop) | MO_ALIGN);
4452 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
4453 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
4454 tcg_gen_or_tl(t0, t0, cpu_so);
4455 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
4456 tcg_temp_free(t0);
4457 tcg_gen_br(l2);
4458
4459 gen_set_label(l1);
4460
4461 /*
4462 * Address mismatch implies failure. But we still need to provide
4463 * the memory barrier semantics of the instruction.
4464 */
4465 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
4466 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4467
4468 gen_set_label(l2);
4469 tcg_gen_movi_tl(cpu_reserve, -1);
4470 }
4471
4472 #define STCX(name, memop) \
4473 static void gen_##name(DisasContext *ctx) \
4474 { \
4475 gen_conditional_store(ctx, memop); \
4476 }
4477
4478 STCX(stbcx_, DEF_MEMOP(MO_UB))
4479 STCX(sthcx_, DEF_MEMOP(MO_UW))
4480 STCX(stwcx_, DEF_MEMOP(MO_UL))
4481
4482 #if defined(TARGET_PPC64)
4483 /* ldarx */
4484 LARX(ldarx, DEF_MEMOP(MO_Q))
4485 /* stdcx. */
4486 STCX(stdcx_, DEF_MEMOP(MO_Q))
4487
4488 /* lqarx */
4489 static void gen_lqarx(DisasContext *ctx)
4490 {
4491 int rd = rD(ctx->opcode);
4492 TCGv EA, hi, lo;
4493
4494 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
4495 (rd == rB(ctx->opcode)))) {
4496 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4497 return;
4498 }
4499
4500 gen_set_access_type(ctx, ACCESS_RES);
4501 EA = tcg_temp_new();
4502 gen_addr_reg_index(ctx, EA);
4503
4504 /* Note that the low part is always in RD+1, even in LE mode. */
4505 lo = cpu_gpr[rd + 1];
4506 hi = cpu_gpr[rd];
4507
4508 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4509 if (HAVE_ATOMIC128) {
4510 TCGv_i32 oi = tcg_temp_new_i32();
4511 if (ctx->le_mode) {
4512 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
4513 ctx->mem_idx));
4514 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
4515 } else {
4516 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
4517 ctx->mem_idx));
4518 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
4519 }
4520 tcg_temp_free_i32(oi);
4521 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
4522 } else {
4523 /* Restart with exclusive lock. */
4524 gen_helper_exit_atomic(cpu_env);
4525 ctx->base.is_jmp = DISAS_NORETURN;
4526 tcg_temp_free(EA);
4527 return;
4528 }
4529 } else if (ctx->le_mode) {
4530 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
4531 tcg_gen_mov_tl(cpu_reserve, EA);
4532 gen_addr_add(ctx, EA, EA, 8);
4533 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
4534 } else {
4535 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
4536 tcg_gen_mov_tl(cpu_reserve, EA);
4537 gen_addr_add(ctx, EA, EA, 8);
4538 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
4539 }
4540 tcg_temp_free(EA);
4541
4542 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
4543 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
4544 }
4545
4546 /* stqcx. */
4547 static void gen_stqcx_(DisasContext *ctx)
4548 {
4549 int rs = rS(ctx->opcode);
4550 TCGv EA, hi, lo;
4551
4552 if (unlikely(rs & 1)) {
4553 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4554 return;
4555 }
4556
4557 gen_set_access_type(ctx, ACCESS_RES);
4558 EA = tcg_temp_new();
4559 gen_addr_reg_index(ctx, EA);
4560
4561 /* Note that the low part is always in RS+1, even in LE mode. */
4562 lo = cpu_gpr[rs + 1];
4563 hi = cpu_gpr[rs];
4564
4565 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4566 if (HAVE_CMPXCHG128) {
4567 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
4568 if (ctx->le_mode) {
4569 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
4570 EA, lo, hi, oi);
4571 } else {
4572 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
4573 EA, lo, hi, oi);
4574 }
4575 tcg_temp_free_i32(oi);
4576 } else {
4577 /* Restart with exclusive lock. */
4578 gen_helper_exit_atomic(cpu_env);
4579 ctx->base.is_jmp = DISAS_NORETURN;
4580 }
4581 tcg_temp_free(EA);
4582 } else {
4583 TCGLabel *lab_fail = gen_new_label();
4584 TCGLabel *lab_over = gen_new_label();
4585 TCGv_i64 t0 = tcg_temp_new_i64();
4586 TCGv_i64 t1 = tcg_temp_new_i64();
4587
4588 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
4589 tcg_temp_free(EA);
4590
4591 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
4592 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4593 ? offsetof(CPUPPCState, reserve_val2)
4594 : offsetof(CPUPPCState, reserve_val)));
4595 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4596
4597 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4598 gen_qemu_ld64_i64(ctx, t0, t0);
4599 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4600 ? offsetof(CPUPPCState, reserve_val)
4601 : offsetof(CPUPPCState, reserve_val2)));
4602 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4603
4604 /* Success */
4605 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
4606 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4607 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
4608
4609 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4610 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4611 tcg_gen_br(lab_over);
4612
4613 gen_set_label(lab_fail);
4614 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4615
4616 gen_set_label(lab_over);
4617 tcg_gen_movi_tl(cpu_reserve, -1);
4618 tcg_temp_free_i64(t0);
4619 tcg_temp_free_i64(t1);
4620 }
4621 }
4622 #endif /* defined(TARGET_PPC64) */
4623
4624 /* sync */
4625 static void gen_sync(DisasContext *ctx)
4626 {
4627 uint32_t l = (ctx->opcode >> 21) & 3;
4628
4629 /*
4630 * We may need to check for a pending TLB flush.
4631 *
4632 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
4633 *
4634 * Additionally, this can only happen in kernel mode however so
4635 * check MSR_PR as well.
4636 */
4637 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
4638 gen_check_tlb_flush(ctx, true);
4639 }
4640 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
4641 }
4642
4643 /* wait */
4644 static void gen_wait(DisasContext *ctx)
4645 {
4646 TCGv_i32 t0 = tcg_const_i32(1);
4647 tcg_gen_st_i32(t0, cpu_env,
4648 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
4649 tcg_temp_free_i32(t0);
4650 /* Stop translation, as the CPU is supposed to sleep from now */
4651 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4652 }
4653
4654 #if defined(TARGET_PPC64)
4655 static void gen_doze(DisasContext *ctx)
4656 {
4657 #if defined(CONFIG_USER_ONLY)
4658 GEN_PRIV;
4659 #else
4660 TCGv_i32 t;
4661
4662 CHK_HV;
4663 t = tcg_const_i32(PPC_PM_DOZE);
4664 gen_helper_pminsn(cpu_env, t);
4665 tcg_temp_free_i32(t);
4666 /* Stop translation, as the CPU is supposed to sleep from now */
4667 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4668 #endif /* defined(CONFIG_USER_ONLY) */
4669 }
4670
4671 static void gen_nap(DisasContext *ctx)
4672 {
4673 #if defined(CONFIG_USER_ONLY)
4674 GEN_PRIV;
4675 #else
4676 TCGv_i32 t;
4677
4678 CHK_HV;
4679 t = tcg_const_i32(PPC_PM_NAP);
4680 gen_helper_pminsn(cpu_env, t);
4681 tcg_temp_free_i32(t);
4682 /* Stop translation, as the CPU is supposed to sleep from now */
4683 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4684 #endif /* defined(CONFIG_USER_ONLY) */
4685 }
4686
4687 static void gen_stop(DisasContext *ctx)
4688 {
4689 #if defined(CONFIG_USER_ONLY)
4690 GEN_PRIV;
4691 #else
4692 TCGv_i32 t;
4693
4694 CHK_HV;
4695 t = tcg_const_i32(PPC_PM_STOP);
4696 gen_helper_pminsn(cpu_env, t);
4697 tcg_temp_free_i32(t);
4698 /* Stop translation, as the CPU is supposed to sleep from now */
4699 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4700 #endif /* defined(CONFIG_USER_ONLY) */
4701 }
4702
4703 static void gen_sleep(DisasContext *ctx)
4704 {
4705 #if defined(CONFIG_USER_ONLY)
4706 GEN_PRIV;
4707 #else
4708 TCGv_i32 t;
4709
4710 CHK_HV;
4711 t = tcg_const_i32(PPC_PM_SLEEP);
4712 gen_helper_pminsn(cpu_env, t);
4713 tcg_temp_free_i32(t);
4714 /* Stop translation, as the CPU is supposed to sleep from now */
4715 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4716 #endif /* defined(CONFIG_USER_ONLY) */
4717 }
4718
4719 static void gen_rvwinkle(DisasContext *ctx)
4720 {
4721 #if defined(CONFIG_USER_ONLY)
4722 GEN_PRIV;
4723 #else
4724 TCGv_i32 t;
4725
4726 CHK_HV;
4727 t = tcg_const_i32(PPC_PM_RVWINKLE);
4728 gen_helper_pminsn(cpu_env, t);
4729 tcg_temp_free_i32(t);
4730 /* Stop translation, as the CPU is supposed to sleep from now */
4731 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4732 #endif /* defined(CONFIG_USER_ONLY) */
4733 }
4734 #endif /* #if defined(TARGET_PPC64) */
4735
4736 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4737 {
4738 #if defined(TARGET_PPC64)
4739 if (ctx->has_cfar) {
4740 tcg_gen_movi_tl(cpu_cfar, nip);
4741 }
4742 #endif
4743 }
4744
4745 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4746 {
4747 if (unlikely(ctx->singlestep_enabled)) {
4748 return false;
4749 }
4750
4751 #ifndef CONFIG_USER_ONLY
4752 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4753 #else
4754 return true;
4755 #endif
4756 }
4757
4758 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4759 {
4760 int sse = ctx->singlestep_enabled;
4761 if (unlikely(sse)) {
4762 if (sse & GDBSTUB_SINGLE_STEP) {
4763 gen_debug_exception(ctx);
4764 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
4765 uint32_t excp = gen_prep_dbgex(ctx);
4766 gen_exception(ctx, excp);
4767 }
4768 tcg_gen_exit_tb(NULL, 0);
4769 } else {
4770 tcg_gen_lookup_and_goto_ptr();
4771 }
4772 }
4773
4774 /*** Branch ***/
4775 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4776 {
4777 if (NARROW_MODE(ctx)) {
4778 dest = (uint32_t) dest;
4779 }
4780 if (use_goto_tb(ctx, dest)) {
4781 tcg_gen_goto_tb(n);
4782 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4783 tcg_gen_exit_tb(ctx->base.tb, n);
4784 } else {
4785 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4786 gen_lookup_and_goto_ptr(ctx);
4787 }
4788 }
4789
4790 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4791 {
4792 if (NARROW_MODE(ctx)) {
4793 nip = (uint32_t)nip;
4794 }
4795 tcg_gen_movi_tl(cpu_lr, nip);
4796 }
4797
4798 /* b ba bl bla */
4799 static void gen_b(DisasContext *ctx)
4800 {
4801 target_ulong li, target;
4802
4803 ctx->exception = POWERPC_EXCP_BRANCH;
4804 /* sign extend LI */
4805 li = LI(ctx->opcode);
4806 li = (li ^ 0x02000000) - 0x02000000;
4807 if (likely(AA(ctx->opcode) == 0)) {
4808 target = ctx->base.pc_next + li - 4;
4809 } else {
4810 target = li;
4811 }
4812 if (LK(ctx->opcode)) {
4813 gen_setlr(ctx, ctx->base.pc_next);
4814 }
4815 gen_update_cfar(ctx, ctx->base.pc_next - 4);
4816 gen_goto_tb(ctx, 0, target);
4817 }
4818
4819 #define BCOND_IM 0
4820 #define BCOND_LR 1
4821 #define BCOND_CTR 2
4822 #define BCOND_TAR 3
4823
4824 static void gen_bcond(DisasContext *ctx, int type)
4825 {
4826 uint32_t bo = BO(ctx->opcode);
4827 TCGLabel *l1;
4828 TCGv target;
4829 ctx->exception = POWERPC_EXCP_BRANCH;
4830
4831 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4832 target = tcg_temp_local_new();
4833 if (type == BCOND_CTR) {
4834 tcg_gen_mov_tl(target, cpu_ctr);
4835 } else if (type == BCOND_TAR) {
4836 gen_load_spr(target, SPR_TAR);
4837 } else {
4838 tcg_gen_mov_tl(target, cpu_lr);
4839 }
4840 } else {
4841 target = NULL;
4842 }
4843 if (LK(ctx->opcode)) {
4844 gen_setlr(ctx, ctx->base.pc_next);
4845 }
4846 l1 = gen_new_label();
4847 if ((bo & 0x4) == 0) {
4848 /* Decrement and test CTR */
4849 TCGv temp = tcg_temp_new();
4850
4851 if (type == BCOND_CTR) {
4852 /*
4853 * All ISAs up to v3 describe this form of bcctr as invalid but
4854 * some processors, ie. 64-bit server processors compliant with
4855 * arch 2.x, do implement a "test and decrement" logic instead,
4856 * as described in their respective UMs. This logic involves CTR
4857 * to act as both the branch target and a counter, which makes
4858 * it basically useless and thus never used in real code.
4859 *
4860 * This form was hence chosen to trigger extra micro-architectural
4861 * side-effect on real HW needed for the Spectre v2 workaround.
4862 * It is up to guests that implement such workaround, ie. linux, to
4863 * use this form in a way it just triggers the side-effect without
4864 * doing anything else harmful.
4865 */
4866 if (unlikely(!is_book3s_arch2x(ctx))) {
4867 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4868 tcg_temp_free(temp);
4869 tcg_temp_free(target);
4870 return;
4871 }
4872
4873 if (NARROW_MODE(ctx)) {
4874 tcg_gen_ext32u_tl(temp, cpu_ctr);
4875 } else {
4876 tcg_gen_mov_tl(temp, cpu_ctr);
4877 }
4878 if (bo & 0x2) {
4879 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4880 } else {
4881 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4882 }
4883 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4884 } else {
4885 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4886 if (NARROW_MODE(ctx)) {
4887 tcg_gen_ext32u_tl(temp, cpu_ctr);
4888 } else {
4889 tcg_gen_mov_tl(temp, cpu_ctr);
4890 }
4891 if (bo & 0x2) {
4892 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4893 } else {
4894 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4895 }
4896 }
4897 tcg_temp_free(temp);
4898 }
4899 if ((bo & 0x10) == 0) {
4900 /* Test CR */
4901 uint32_t bi = BI(ctx->opcode);
4902 uint32_t mask = 0x08 >> (bi & 0x03);
4903 TCGv_i32 temp = tcg_temp_new_i32();
4904
4905 if (bo & 0x8) {
4906 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4907 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4908 } else {
4909 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4910 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4911 }
4912 tcg_temp_free_i32(temp);
4913 }
4914 gen_update_cfar(ctx, ctx->base.pc_next - 4);
4915 if (type == BCOND_IM) {
4916 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4917 if (likely(AA(ctx->opcode) == 0)) {
4918 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
4919 } else {
4920 gen_goto_tb(ctx, 0, li);
4921 }
4922 } else {
4923 if (NARROW_MODE(ctx)) {
4924 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4925 } else {
4926 tcg_gen_andi_tl(cpu_nip, target, ~3);
4927 }
4928 gen_lookup_and_goto_ptr(ctx);
4929 tcg_temp_free(target);
4930 }
4931 if ((bo & 0x14) != 0x14) {
4932 /* fallthrough case */
4933 gen_set_label(l1);
4934 gen_goto_tb(ctx, 1, ctx->base.pc_next);
4935 }
4936 }
4937
4938 static void gen_bc(DisasContext *ctx)
4939 {
4940 gen_bcond(ctx, BCOND_IM);
4941 }
4942
4943 static void gen_bcctr(DisasContext *ctx)
4944 {
4945 gen_bcond(ctx, BCOND_CTR);
4946 }
4947
4948 static void gen_bclr(DisasContext *ctx)
4949 {
4950 gen_bcond(ctx, BCOND_LR);
4951 }
4952
4953 static void gen_bctar(DisasContext *ctx)
4954 {
4955 gen_bcond(ctx, BCOND_TAR);
4956 }
4957
4958 /*** Condition register logical ***/
4959 #define GEN_CRLOGIC(name, tcg_op, opc) \
4960 static void glue(gen_, name)(DisasContext *ctx) \
4961 { \
4962 uint8_t bitmask; \
4963 int sh; \
4964 TCGv_i32 t0, t1; \
4965 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4966 t0 = tcg_temp_new_i32(); \
4967 if (sh > 0) \
4968 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4969 else if (sh < 0) \
4970 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4971 else \
4972 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4973 t1 = tcg_temp_new_i32(); \
4974 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4975 if (sh > 0) \
4976 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4977 else if (sh < 0) \
4978 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4979 else \
4980 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4981 tcg_op(t0, t0, t1); \
4982 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4983 tcg_gen_andi_i32(t0, t0, bitmask); \
4984 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4985 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4986 tcg_temp_free_i32(t0); \
4987 tcg_temp_free_i32(t1); \
4988 }
4989
4990 /* crand */
4991 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4992 /* crandc */
4993 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4994 /* creqv */
4995 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4996 /* crnand */
4997 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4998 /* crnor */
4999 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
5000 /* cror */
5001 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
5002 /* crorc */
5003 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
5004 /* crxor */
5005 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
5006
5007 /* mcrf */
5008 static void gen_mcrf(DisasContext *ctx)
5009 {
5010 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
5011 }
5012
5013 /*** System linkage ***/
5014
5015 /* rfi (supervisor only) */
5016 static void gen_rfi(DisasContext *ctx)
5017 {
5018 #if defined(CONFIG_USER_ONLY)
5019 GEN_PRIV;
5020 #else
5021 /*
5022 * This instruction doesn't exist anymore on 64-bit server
5023 * processors compliant with arch 2.x
5024 */
5025 if (is_book3s_arch2x(ctx)) {
5026 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5027 return;
5028 }
5029 /* Restore CPU state */
5030 CHK_SV;
5031 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5032 gen_io_start();
5033 }
5034 gen_update_cfar(ctx, ctx->base.pc_next - 4);
5035 gen_helper_rfi(cpu_env);
5036 gen_sync_exception(ctx);
5037 #endif
5038 }
5039
5040 #if defined(TARGET_PPC64)
5041 static void gen_rfid(DisasContext *ctx)
5042 {
5043 #if defined(CONFIG_USER_ONLY)
5044 GEN_PRIV;
5045 #else
5046 /* Restore CPU state */
5047 CHK_SV;
5048 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5049 gen_io_start();
5050 }
5051 gen_update_cfar(ctx, ctx->base.pc_next - 4);
5052 gen_helper_rfid(cpu_env);
5053 gen_sync_exception(ctx);
5054 #endif
5055 }
5056
5057 #if !defined(CONFIG_USER_ONLY)
5058 static void gen_rfscv(DisasContext *ctx)
5059 {
5060 #if defined(CONFIG_USER_ONLY)
5061 GEN_PRIV;
5062 #else
5063 /* Restore CPU state */
5064 CHK_SV;
5065 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5066 gen_io_start();
5067 }
5068 gen_update_cfar(ctx, ctx->base.pc_next - 4);
5069 gen_helper_rfscv(cpu_env);
5070 gen_sync_exception(ctx);
5071 #endif
5072 }
5073 #endif
5074
5075 static void gen_hrfid(DisasContext *ctx)
5076 {
5077 #if defined(CONFIG_USER_ONLY)
5078 GEN_PRIV;
5079 #else
5080 /* Restore CPU state */
5081 CHK_HV;
5082 gen_helper_hrfid(cpu_env);
5083 gen_sync_exception(ctx);
5084 #endif
5085 }
5086 #endif
5087
5088 /* sc */
5089 #if defined(CONFIG_USER_ONLY)
5090 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
5091 #else
5092 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
5093 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
5094 #endif
5095 static void gen_sc(DisasContext *ctx)
5096 {
5097 uint32_t lev;
5098
5099 lev = (ctx->opcode >> 5) & 0x7F;
5100 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
5101 }
5102
5103 #if defined(TARGET_PPC64)
5104 #if !defined(CONFIG_USER_ONLY)
5105 static void gen_scv(DisasContext *ctx)
5106 {
5107 uint32_t lev = (ctx->opcode >> 5) & 0x7F;
5108
5109 /* Set the PC back to the faulting instruction. */
5110 if (ctx->exception == POWERPC_EXCP_NONE) {
5111 gen_update_nip(ctx, ctx->base.pc_next - 4);
5112 }
5113 gen_helper_scv(cpu_env, tcg_constant_i32(lev));
5114
5115 /* This need not be exact, just not POWERPC_EXCP_NONE */
5116 ctx->exception = POWERPC_SYSCALL_VECTORED;
5117 }
5118 #endif
5119 #endif
5120
5121 /*** Trap ***/
5122
5123 /* Check for unconditional traps (always or never) */
5124 static bool check_unconditional_trap(DisasContext *ctx)
5125 {
5126 /* Trap never */
5127 if (TO(ctx->opcode) == 0) {
5128 return true;
5129 }
5130 /* Trap always */
5131 if (TO(ctx->opcode) == 31) {
5132 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
5133 return true;
5134 }
5135 return false;
5136 }
5137
5138 /* tw */
5139 static void gen_tw(DisasContext *ctx)
5140 {
5141 TCGv_i32 t0;
5142
5143 if (check_unconditional_trap(ctx)) {
5144 return;
5145 }
5146 t0 = tcg_const_i32(TO(ctx->opcode));
5147 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5148 t0);
5149 tcg_temp_free_i32(t0);
5150 }
5151
5152 /* twi */
5153 static void gen_twi(DisasContext *ctx)
5154 {
5155 TCGv t0;
5156 TCGv_i32 t1;
5157
5158 if (check_unconditional_trap(ctx)) {
5159 return;
5160 }
5161 t0 = tcg_const_tl(SIMM(ctx->opcode));
5162 t1 = tcg_const_i32(TO(ctx->opcode));
5163 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
5164 tcg_temp_free(t0);
5165 tcg_temp_free_i32(t1);
5166 }
5167
5168 #if defined(TARGET_PPC64)
5169 /* td */
5170 static void gen_td(DisasContext *ctx)
5171 {
5172 TCGv_i32 t0;
5173
5174 if (check_unconditional_trap(ctx)) {
5175 return;
5176 }
5177 t0 = tcg_const_i32(TO(ctx->opcode));
5178 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5179 t0);
5180 tcg_temp_free_i32(t0);
5181 }
5182
5183 /* tdi */
5184 static void gen_tdi(DisasContext *ctx)
5185 {
5186 TCGv t0;
5187 TCGv_i32 t1;
5188
5189 if (check_unconditional_trap(ctx)) {
5190 return;
5191 }
5192 t0 = tcg_const_tl(SIMM(ctx->opcode));
5193 t1 = tcg_const_i32(TO(ctx->opcode));
5194 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
5195 tcg_temp_free(t0);
5196 tcg_temp_free_i32(t1);
5197 }
5198 #endif
5199
5200 /*** Processor control ***/
5201
5202 /* mcrxr */
5203 static void gen_mcrxr(DisasContext *ctx)
5204 {
5205 TCGv_i32 t0 = tcg_temp_new_i32();
5206 TCGv_i32 t1 = tcg_temp_new_i32();
5207 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
5208
5209 tcg_gen_trunc_tl_i32(t0, cpu_so);
5210 tcg_gen_trunc_tl_i32(t1, cpu_ov);
5211 tcg_gen_trunc_tl_i32(dst, cpu_ca);
5212 tcg_gen_shli_i32(t0, t0, 3);
5213 tcg_gen_shli_i32(t1, t1, 2);
5214 tcg_gen_shli_i32(dst, dst, 1);
5215 tcg_gen_or_i32(dst, dst, t0);
5216 tcg_gen_or_i32(dst, dst, t1);
5217 tcg_temp_free_i32(t0);
5218 tcg_temp_free_i32(t1);
5219
5220 tcg_gen_movi_tl(cpu_so, 0);
5221 tcg_gen_movi_tl(cpu_ov, 0);
5222 tcg_gen_movi_tl(cpu_ca, 0);
5223 }
5224
5225 #ifdef TARGET_PPC64
5226 /* mcrxrx */
5227 static void gen_mcrxrx(DisasContext *ctx)
5228 {
5229 TCGv t0 = tcg_temp_new();
5230 TCGv t1 = tcg_temp_new();
5231 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
5232
5233 /* copy OV and OV32 */
5234 tcg_gen_shli_tl(t0, cpu_ov, 1);
5235 tcg_gen_or_tl(t0, t0, cpu_ov32);
5236 tcg_gen_shli_tl(t0, t0, 2);
5237 /* copy CA and CA32 */
5238 tcg_gen_shli_tl(t1, cpu_ca, 1);
5239 tcg_gen_or_tl(t1, t1, cpu_ca32);
5240 tcg_gen_or_tl(t0, t0, t1);
5241 tcg_gen_trunc_tl_i32(dst, t0);
5242 tcg_temp_free(t0);
5243 tcg_temp_free(t1);
5244 }
5245 #endif
5246
5247 /* mfcr mfocrf */
5248 static void gen_mfcr(DisasContext *ctx)
5249 {
5250 uint32_t crm, crn;
5251
5252 if (likely(ctx->opcode & 0x00100000)) {
5253 crm = CRM(ctx->opcode);
5254 if (likely(crm && ((crm & (crm - 1)) == 0))) {
5255 crn = ctz32(crm);
5256 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
5257 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
5258 cpu_gpr[rD(ctx->opcode)], crn * 4);
5259 }
5260 } else {
5261 TCGv_i32 t0 = tcg_temp_new_i32();
5262 tcg_gen_mov_i32(t0, cpu_crf[0]);
5263 tcg_gen_shli_i32(t0, t0, 4);
5264 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
5265 tcg_gen_shli_i32(t0, t0, 4);
5266 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
5267 tcg_gen_shli_i32(t0, t0, 4);
5268 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
5269 tcg_gen_shli_i32(t0, t0, 4);
5270 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
5271 tcg_gen_shli_i32(t0, t0, 4);
5272 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
5273 tcg_gen_shli_i32(t0, t0, 4);
5274 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
5275 tcg_gen_shli_i32(t0, t0, 4);
5276 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
5277 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5278 tcg_temp_free_i32(t0);
5279 }
5280 }
5281
5282 /* mfmsr */
5283 static void gen_mfmsr(DisasContext *ctx)
5284 {
5285 CHK_SV;
5286 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
5287 }
5288
5289 /* mfspr */
5290 static inline void gen_op_mfspr(DisasContext *ctx)
5291 {
5292 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
5293 uint32_t sprn = SPR(ctx->opcode);
5294
5295 #if defined(CONFIG_USER_ONLY)
5296 read_cb = ctx->spr_cb[sprn].uea_read;
5297 #else
5298 if (ctx->pr) {
5299 read_cb = ctx->spr_cb[sprn].uea_read;
5300 } else if (ctx->hv) {
5301 read_cb = ctx->spr_cb[sprn].hea_read;
5302 } else {
5303 read_cb = ctx->spr_cb[sprn].oea_read;
5304 }
5305 #endif
5306 if (likely(read_cb != NULL)) {
5307 if (likely(read_cb != SPR_NOACCESS)) {
5308 (*read_cb)(ctx, rD(ctx->opcode), sprn);
5309 } else {
5310 /* Privilege exception */
5311 /*
5312 * This is a hack to avoid warnings when running Linux:
5313 * this OS breaks the PowerPC virtualisation model,
5314 * allowing userland application to read the PVR
5315 */
5316 if (sprn != SPR_PVR) {
5317 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
5318 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
5319 ctx->base.pc_next - 4);
5320 }
5321 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
5322 }
5323 } else {
5324 /* ISA 2.07 defines these as no-ops */
5325 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
5326 (sprn >= 808 && sprn <= 811)) {
5327 /* This is a nop */
5328 return;
5329 }
5330 /* Not defined */
5331 qemu_log_mask(LOG_GUEST_ERROR,
5332 "Trying to read invalid spr %d (0x%03x) at "
5333 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
5334
5335 /*
5336 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5337 * generate a priv, a hv emu or a no-op
5338 */
5339 if (sprn & 0x10) {
5340 if (ctx->pr) {
5341 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5342 }
5343 } else {
5344 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
5345 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5346 }
5347 }
5348 }
5349 }
5350
5351 static void gen_mfspr(DisasContext *ctx)
5352 {
5353 gen_op_mfspr(ctx);
5354 }
5355
5356 /* mftb */
5357 static void gen_mftb(DisasContext *ctx)
5358 {
5359 gen_op_mfspr(ctx);
5360 }
5361
5362 /* mtcrf mtocrf*/
5363 static void gen_mtcrf(DisasContext *ctx)
5364 {
5365 uint32_t crm, crn;
5366
5367 crm = CRM(ctx->opcode);
5368 if (likely((ctx->opcode & 0x00100000))) {
5369 if (crm && ((crm & (crm - 1)) == 0)) {
5370 TCGv_i32 temp = tcg_temp_new_i32();
5371 crn = ctz32(crm);
5372 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
5373 tcg_gen_shri_i32(temp, temp, crn * 4);
5374 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
5375 tcg_temp_free_i32(temp);
5376 }
5377 } else {
5378 TCGv_i32 temp = tcg_temp_new_i32();
5379 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
5380 for (crn = 0 ; crn < 8 ; crn++) {
5381 if (crm & (1 << crn)) {
5382 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
5383 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
5384 }
5385 }
5386 tcg_temp_free_i32(temp);
5387 }
5388 }
5389
5390 /* mtmsr */
5391 #if defined(TARGET_PPC64)
5392 static void gen_mtmsrd(DisasContext *ctx)
5393 {
5394 CHK_SV;
5395
5396 #if !defined(CONFIG_USER_ONLY)
5397 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5398 gen_io_start();
5399 }
5400 if (ctx->opcode & 0x00010000) {
5401 /* L=1 form only updates EE and RI */
5402 TCGv t0 = tcg_temp_new();
5403 TCGv t1 = tcg_temp_new();
5404 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
5405 (1 << MSR_RI) | (1 << MSR_EE));
5406 tcg_gen_andi_tl(t1, cpu_msr,
5407 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
5408 tcg_gen_or_tl(t1, t1, t0);
5409
5410 gen_helper_store_msr(cpu_env, t1);
5411 tcg_temp_free(t0);
5412 tcg_temp_free(t1);
5413
5414 } else {
5415 /*
5416 * XXX: we need to update nip before the store if we enter
5417 * power saving mode, we will exit the loop directly from
5418 * ppc_store_msr
5419 */
5420 gen_update_nip(ctx, ctx->base.pc_next);
5421 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
5422 }
5423 /* Must stop the translation as machine state (may have) changed */
5424 gen_stop_exception(ctx);
5425 #endif /* !defined(CONFIG_USER_ONLY) */
5426 }
5427 #endif /* defined(TARGET_PPC64) */
5428
5429 static void gen_mtmsr(DisasContext *ctx)
5430 {
5431 CHK_SV;
5432
5433 #if !defined(CONFIG_USER_ONLY)
5434 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5435 gen_io_start();
5436 }
5437 if (ctx->opcode & 0x00010000) {
5438 /* L=1 form only updates EE and RI */
5439 TCGv t0 = tcg_temp_new();
5440 TCGv t1 = tcg_temp_new();
5441 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
5442 (1 << MSR_RI) | (1 << MSR_EE));
5443 tcg_gen_andi_tl(t1, cpu_msr,
5444 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
5445 tcg_gen_or_tl(t1, t1, t0);
5446
5447 gen_helper_store_msr(cpu_env, t1);
5448 tcg_temp_free(t0);
5449 tcg_temp_free(t1);
5450
5451 } else {
5452 TCGv msr = tcg_temp_new();
5453
5454 /*
5455 * XXX: we need to update nip before the store if we enter
5456 * power saving mode, we will exit the loop directly from
5457 * ppc_store_msr
5458 */
5459 gen_update_nip(ctx, ctx->base.pc_next);
5460 #if defined(TARGET_PPC64)
5461 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
5462 #else
5463 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
5464 #endif
5465 gen_helper_store_msr(cpu_env, msr);
5466 tcg_temp_free(msr);
5467 }
5468 /* Must stop the translation as machine state (may have) changed */
5469 gen_stop_exception(ctx);
5470 #endif
5471 }
5472
5473 /* mtspr */
5474 static void gen_mtspr(DisasContext *ctx)
5475 {
5476 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
5477 uint32_t sprn = SPR(ctx->opcode);
5478
5479 #if defined(CONFIG_USER_ONLY)
5480 write_cb = ctx->spr_cb[sprn].uea_write;
5481 #else
5482 if (ctx->pr) {
5483 write_cb = ctx->spr_cb[sprn].uea_write;
5484 } else if (ctx->hv) {
5485 write_cb = ctx->spr_cb[sprn].hea_write;
5486 } else {
5487 write_cb = ctx->spr_cb[sprn].oea_write;
5488 }
5489 #endif
5490 if (likely(write_cb != NULL)) {
5491 if (likely(write_cb != SPR_NOACCESS)) {
5492 (*write_cb)(ctx, sprn, rS(ctx->opcode));
5493 } else {
5494 /* Privilege exception */
5495 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
5496 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
5497 ctx->base.pc_next - 4);
5498 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
5499 }
5500 } else {
5501 /* ISA 2.07 defines these as no-ops */
5502 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
5503 (sprn >= 808 && sprn <= 811)) {
5504 /* This is a nop */
5505 return;
5506 }
5507
5508 /* Not defined */
5509 qemu_log_mask(LOG_GUEST_ERROR,
5510 "Trying to write invalid spr %d (0x%03x) at "
5511 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
5512
5513
5514 /*
5515 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5516 * generate a priv, a hv emu or a no-op
5517 */
5518 if (sprn & 0x10) {
5519 if (ctx->pr) {
5520 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5521 }
5522 } else {
5523 if (ctx->pr || sprn == 0) {
5524 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5525 }
5526 }
5527 }
5528 }
5529
5530 #if defined(TARGET_PPC64)
5531 /* setb */
5532 static void gen_setb(DisasContext *ctx)
5533 {
5534 TCGv_i32 t0 = tcg_temp_new_i32();
5535 TCGv_i32 t8 = tcg_temp_new_i32();
5536 TCGv_i32 tm1 = tcg_temp_new_i32();
5537 int crf = crfS(ctx->opcode);
5538
5539 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
5540 tcg_gen_movi_i32(t8, 8);
5541 tcg_gen_movi_i32(tm1, -1);
5542 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
5543 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5544
5545 tcg_temp_free_i32(t0);
5546 tcg_temp_free_i32(t8);
5547 tcg_temp_free_i32(tm1);
5548 }
5549 #endif
5550
5551 /*** Cache management ***/
5552
5553 /* dcbf */
5554 static void gen_dcbf(DisasContext *ctx)
5555 {
5556 /* XXX: specification says this is treated as a load by the MMU */
5557 TCGv t0;
5558 gen_set_access_type(ctx, ACCESS_CACHE);
5559 t0 = tcg_temp_new();
5560 gen_addr_reg_index(ctx, t0);
5561 gen_qemu_ld8u(ctx, t0, t0);
5562 tcg_temp_free(t0);
5563 }
5564
5565 /* dcbfep (external PID dcbf) */
5566 static void gen_dcbfep(DisasContext *ctx)
5567 {
5568 /* XXX: specification says this is treated as a load by the MMU */
5569 TCGv t0;
5570 CHK_SV;
5571 gen_set_access_type(ctx, ACCESS_CACHE);
5572 t0 = tcg_temp_new();
5573 gen_addr_reg_index(ctx, t0);
5574 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5575 tcg_temp_free(t0);
5576 }
5577
5578 /* dcbi (Supervisor only) */
5579 static void gen_dcbi(DisasContext *ctx)
5580 {
5581 #if defined(CONFIG_USER_ONLY)
5582 GEN_PRIV;
5583 #else
5584 TCGv EA, val;
5585
5586 CHK_SV;
5587 EA = tcg_temp_new();
5588 gen_set_access_type(ctx, ACCESS_CACHE);
5589 gen_addr_reg_index(ctx, EA);
5590 val = tcg_temp_new();
5591 /* XXX: specification says this should be treated as a store by the MMU */
5592 gen_qemu_ld8u(ctx, val, EA);
5593 gen_qemu_st8(ctx, val, EA);
5594 tcg_temp_free(val);
5595 tcg_temp_free(EA);
5596 #endif /* defined(CONFIG_USER_ONLY) */
5597 }
5598
5599 /* dcdst */
5600 static void gen_dcbst(DisasContext *ctx)
5601 {
5602 /* XXX: specification say this is treated as a load by the MMU */
5603 TCGv t0;
5604 gen_set_access_type(ctx, ACCESS_CACHE);
5605 t0 = tcg_temp_new();
5606 gen_addr_reg_index(ctx, t0);
5607 gen_qemu_ld8u(ctx, t0, t0);
5608 tcg_temp_free(t0);
5609 }
5610
5611 /* dcbstep (dcbstep External PID version) */
5612 static void gen_dcbstep(DisasContext *ctx)
5613 {
5614 /* XXX: specification say this is treated as a load by the MMU */
5615 TCGv t0;
5616 gen_set_access_type(ctx, ACCESS_CACHE);
5617 t0 = tcg_temp_new();
5618 gen_addr_reg_index(ctx, t0);
5619 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5620 tcg_temp_free(t0);
5621 }
5622
5623 /* dcbt */
5624 static void gen_dcbt(DisasContext *ctx)
5625 {
5626 /*
5627 * interpreted as no-op
5628 * XXX: specification say this is treated as a load by the MMU but
5629 * does not generate any exception
5630 */
5631 }
5632
5633 /* dcbtep */
5634 static void gen_dcbtep(DisasContext *ctx)
5635 {
5636 /*
5637 * interpreted as no-op
5638 * XXX: specification say this is treated as a load by the MMU but
5639 * does not generate any exception
5640 */
5641 }
5642
5643 /* dcbtst */
5644 static void gen_dcbtst(DisasContext *ctx)
5645 {
5646 /*
5647 * interpreted as no-op
5648 * XXX: specification say this is treated as a load by the MMU but
5649 * does not generate any exception
5650 */
5651 }
5652
5653 /* dcbtstep */
5654 static void gen_dcbtstep(DisasContext *ctx)
5655 {
5656 /*
5657 * interpreted as no-op
5658 * XXX: specification say this is treated as a load by the MMU but
5659 * does not generate any exception
5660 */
5661 }
5662
5663 /* dcbtls */
5664 static void gen_dcbtls(DisasContext *ctx)
5665 {
5666 /* Always fails locking the cache */
5667 TCGv t0 = tcg_temp_new();
5668 gen_load_spr(t0, SPR_Exxx_L1CSR0);
5669 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5670 gen_store_spr(SPR_Exxx_L1CSR0, t0);
5671 tcg_temp_free(t0);
5672 }
5673
5674 /* dcbz */
5675 static void gen_dcbz(DisasContext *ctx)
5676 {
5677 TCGv tcgv_addr;
5678 TCGv_i32 tcgv_op;
5679
5680 gen_set_access_type(ctx, ACCESS_CACHE);
5681 tcgv_addr = tcg_temp_new();
5682 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5683 gen_addr_reg_index(ctx, tcgv_addr);
5684 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
5685 tcg_temp_free(tcgv_addr);
5686 tcg_temp_free_i32(tcgv_op);
5687 }
5688
5689 /* dcbzep */
5690 static void gen_dcbzep(DisasContext *ctx)
5691 {
5692 TCGv tcgv_addr;
5693 TCGv_i32 tcgv_op;
5694
5695 gen_set_access_type(ctx, ACCESS_CACHE);
5696 tcgv_addr = tcg_temp_new();
5697 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5698 gen_addr_reg_index(ctx, tcgv_addr);
5699 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5700 tcg_temp_free(tcgv_addr);
5701 tcg_temp_free_i32(tcgv_op);
5702 }
5703
5704 /* dst / dstt */
5705 static void gen_dst(DisasContext *ctx)
5706 {
5707 if (rA(ctx->opcode) == 0) {
5708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5709 } else {
5710 /* interpreted as no-op */
5711 }
5712 }
5713
5714 /* dstst /dststt */
5715 static void gen_dstst(DisasContext *ctx)
5716 {
5717 if (rA(ctx->opcode) == 0) {
5718 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5719 } else {
5720 /* interpreted as no-op */
5721 }
5722
5723 }
5724
5725 /* dss / dssall */
5726 static void gen_dss(DisasContext *ctx)
5727 {
5728 /* interpreted as no-op */
5729 }
5730
5731 /* icbi */
5732 static void gen_icbi(DisasContext *ctx)
5733 {
5734 TCGv t0;
5735 gen_set_access_type(ctx, ACCESS_CACHE);
5736 t0 = tcg_temp_new();
5737 gen_addr_reg_index(ctx, t0);
5738 gen_helper_icbi(cpu_env, t0);
5739 tcg_temp_free(t0);
5740 }
5741
5742 /* icbiep */
5743 static void gen_icbiep(DisasContext *ctx)
5744 {
5745 TCGv t0;
5746 gen_set_access_type(ctx, ACCESS_CACHE);
5747 t0 = tcg_temp_new();
5748 gen_addr_reg_index(ctx, t0);
5749 gen_helper_icbiep(cpu_env, t0);
5750 tcg_temp_free(t0);
5751 }
5752
5753 /* Optional: */
5754 /* dcba */
5755 static void gen_dcba(DisasContext *ctx)
5756 {
5757 /*
5758 * interpreted as no-op
5759 * XXX: specification say this is treated as a store by the MMU
5760 * but does not generate any exception
5761 */
5762 }
5763
5764 /*** Segment register manipulation ***/
5765 /* Supervisor only: */
5766
5767 /* mfsr */
5768 static void gen_mfsr(DisasContext *ctx)
5769 {
5770 #if defined(CONFIG_USER_ONLY)
5771 GEN_PRIV;
5772 #else
5773 TCGv t0;
5774
5775 CHK_SV;
5776 t0 = tcg_const_tl(SR(ctx->opcode));
5777 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5778 tcg_temp_free(t0);
5779 #endif /* defined(CONFIG_USER_ONLY) */
5780 }
5781
5782 /* mfsrin */
5783 static void gen_mfsrin(DisasContext *ctx)
5784 {
5785 #if defined(CONFIG_USER_ONLY)
5786 GEN_PRIV;
5787 #else
5788 TCGv t0;
5789
5790 CHK_SV;
5791 t0 = tcg_temp_new();
5792 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5793 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5794 tcg_temp_free(t0);
5795 #endif /* defined(CONFIG_USER_ONLY) */
5796 }
5797
5798 /* mtsr */
5799 static void gen_mtsr(DisasContext *ctx)
5800 {
5801 #if defined(CONFIG_USER_ONLY)
5802 GEN_PRIV;
5803 #else
5804 TCGv t0;
5805
5806 CHK_SV;
5807 t0 = tcg_const_tl(SR(ctx->opcode));
5808 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5809 tcg_temp_free(t0);
5810 #endif /* defined(CONFIG_USER_ONLY) */
5811 }
5812
5813 /* mtsrin */
5814 static void gen_mtsrin(DisasContext *ctx)
5815 {
5816 #if defined(CONFIG_USER_ONLY)
5817 GEN_PRIV;
5818 #else
5819 TCGv t0;
5820 CHK_SV;
5821
5822 t0 = tcg_temp_new();
5823 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5824 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5825 tcg_temp_free(t0);
5826 #endif /* defined(CONFIG_USER_ONLY) */
5827 }
5828
5829 #if defined(TARGET_PPC64)
5830 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5831
5832 /* mfsr */
5833 static void gen_mfsr_64b(DisasContext *ctx)
5834 {
5835 #if defined(CONFIG_USER_ONLY)
5836 GEN_PRIV;
5837 #else
5838 TCGv t0;
5839
5840 CHK_SV;
5841 t0 = tcg_const_tl(SR(ctx->opcode));
5842 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5843 tcg_temp_free(t0);
5844 #endif /* defined(CONFIG_USER_ONLY) */
5845 }
5846
5847 /* mfsrin */
5848 static void gen_mfsrin_64b(DisasContext *ctx)
5849 {
5850 #if defined(CONFIG_USER_ONLY)
5851 GEN_PRIV;
5852 #else
5853 TCGv t0;
5854
5855 CHK_SV;
5856 t0 = tcg_temp_new();
5857 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5858 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5859 tcg_temp_free(t0);
5860 #endif /* defined(CONFIG_USER_ONLY) */
5861 }
5862
5863 /* mtsr */
5864 static void gen_mtsr_64b(DisasContext *ctx)
5865 {
5866 #if defined(CONFIG_USER_ONLY)
5867 GEN_PRIV;
5868 #else
5869 TCGv t0;
5870
5871 CHK_SV;
5872 t0 = tcg_const_tl(SR(ctx->opcode));
5873 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5874 tcg_temp_free(t0);
5875 #endif /* defined(CONFIG_USER_ONLY) */
5876 }
5877
5878 /* mtsrin */
5879 static void gen_mtsrin_64b(DisasContext *ctx)
5880 {
5881 #if defined(CONFIG_USER_ONLY)
5882 GEN_PRIV;
5883 #else
5884 TCGv t0;
5885
5886 CHK_SV;
5887 t0 = tcg_temp_new();
5888 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5889 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5890 tcg_temp_free(t0);
5891 #endif /* defined(CONFIG_USER_ONLY) */
5892 }
5893
5894 /* slbmte */
5895 static void gen_slbmte(DisasContext *ctx)
5896 {
5897 #if defined(CONFIG_USER_ONLY)
5898 GEN_PRIV;
5899 #else
5900 CHK_SV;
5901
5902 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5903 cpu_gpr[rS(ctx->opcode)]);
5904 #endif /* defined(CONFIG_USER_ONLY) */
5905 }
5906
5907 static void gen_slbmfee(DisasContext *ctx)
5908 {
5909 #if defined(CONFIG_USER_ONLY)
5910 GEN_PRIV;
5911 #else
5912 CHK_SV;
5913
5914 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5915 cpu_gpr[rB(ctx->opcode)]);
5916 #endif /* defined(CONFIG_USER_ONLY) */
5917 }
5918
5919 static void gen_slbmfev(DisasContext *ctx)
5920 {
5921 #if defined(CONFIG_USER_ONLY)
5922 GEN_PRIV;
5923 #else
5924 CHK_SV;
5925
5926 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5927 cpu_gpr[rB(ctx->opcode)]);
5928 #endif /* defined(CONFIG_USER_ONLY) */
5929 }
5930
5931 static void gen_slbfee_(DisasContext *ctx)
5932 {
5933 #if defined(CONFIG_USER_ONLY)
5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5935 #else
5936 TCGLabel *l1, *l2;
5937
5938 if (unlikely(ctx->pr)) {
5939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5940 return;
5941 }
5942 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5943 cpu_gpr[rB(ctx->opcode)]);
5944 l1 = gen_new_label();
5945 l2 = gen_new_label();
5946 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5947 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5948 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
5949 tcg_gen_br(l2);
5950 gen_set_label(l1);
5951 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5952 gen_set_label(l2);
5953 #endif
5954 }
5955 #endif /* defined(TARGET_PPC64) */
5956
5957 /*** Lookaside buffer management ***/
5958 /* Optional & supervisor only: */
5959
5960 /* tlbia */
5961 static void gen_tlbia(DisasContext *ctx)
5962 {
5963 #if defined(CONFIG_USER_ONLY)
5964 GEN_PRIV;
5965 #else
5966 CHK_HV;
5967
5968 gen_helper_tlbia(cpu_env);
5969 #endif /* defined(CONFIG_USER_ONLY) */
5970 }
5971
5972 /* tlbiel */
5973 static void gen_tlbiel(DisasContext *ctx)
5974 {
5975 #if defined(CONFIG_USER_ONLY)
5976 GEN_PRIV;
5977 #else
5978 CHK_SV;
5979
5980 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5981 #endif /* defined(CONFIG_USER_ONLY) */
5982 }
5983
5984 /* tlbie */
5985 static void gen_tlbie(DisasContext *ctx)
5986 {
5987 #if defined(CONFIG_USER_ONLY)
5988 GEN_PRIV;
5989 #else
5990 TCGv_i32 t1;
5991
5992 if (ctx->gtse) {
5993 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
5994 } else {
5995 CHK_HV; /* Else hypervisor privileged */
5996 }
5997
5998 if (NARROW_MODE(ctx)) {
5999 TCGv t0 = tcg_temp_new();
6000 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
6001 gen_helper_tlbie(cpu_env, t0);
6002 tcg_temp_free(t0);
6003 } else {
6004 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6005 }
6006 t1 = tcg_temp_new_i32();
6007 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
6008 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
6009 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
6010 tcg_temp_free_i32(t1);
6011 #endif /* defined(CONFIG_USER_ONLY) */
6012 }
6013
6014 /* tlbsync */
6015 static void gen_tlbsync(DisasContext *ctx)
6016 {
6017 #if defined(CONFIG_USER_ONLY)
6018 GEN_PRIV;
6019 #else
6020
6021 if (ctx->gtse) {
6022 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
6023 } else {
6024 CHK_HV; /* Else hypervisor privileged */
6025 }
6026
6027 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
6028 if (ctx->insns_flags & PPC_BOOKE) {
6029 gen_check_tlb_flush(ctx, true);
6030 }
6031 #endif /* defined(CONFIG_USER_ONLY) */
6032 }
6033
6034 #if defined(TARGET_PPC64)
6035 /* slbia */
6036 static void gen_slbia(DisasContext *ctx)
6037 {
6038 #if defined(CONFIG_USER_ONLY)
6039 GEN_PRIV;
6040 #else
6041 uint32_t ih = (ctx->opcode >> 21) & 0x7;
6042 TCGv_i32 t0 = tcg_const_i32(ih);
6043
6044 CHK_SV;
6045
6046 gen_helper_slbia(cpu_env, t0);
6047 tcg_temp_free_i32(t0);
6048 #endif /* defined(CONFIG_USER_ONLY) */
6049 }
6050
6051 /* slbie */
6052 static void gen_slbie(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 GEN_PRIV;
6056 #else
6057 CHK_SV;
6058
6059 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6060 #endif /* defined(CONFIG_USER_ONLY) */
6061 }
6062
6063 /* slbieg */
6064 static void gen_slbieg(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 GEN_PRIV;
6068 #else
6069 CHK_SV;
6070
6071 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6072 #endif /* defined(CONFIG_USER_ONLY) */
6073 }
6074
6075 /* slbsync */
6076 static void gen_slbsync(DisasContext *ctx)
6077 {
6078 #if defined(CONFIG_USER_ONLY)
6079 GEN_PRIV;
6080 #else
6081 CHK_SV;
6082 gen_check_tlb_flush(ctx, true);
6083 #endif /* defined(CONFIG_USER_ONLY) */
6084 }
6085
6086 #endif /* defined(TARGET_PPC64) */
6087
6088 /*** External control ***/
6089 /* Optional: */
6090
6091 /* eciwx */
6092 static void gen_eciwx(DisasContext *ctx)
6093 {
6094 TCGv t0;
6095 /* Should check EAR[E] ! */
6096 gen_set_access_type(ctx, ACCESS_EXT);
6097 t0 = tcg_temp_new();
6098 gen_addr_reg_index(ctx, t0);
6099 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
6100 DEF_MEMOP(MO_UL | MO_ALIGN));
6101 tcg_temp_free(t0);
6102 }
6103
6104 /* ecowx */
6105 static void gen_ecowx(DisasContext *ctx)
6106 {
6107 TCGv t0;
6108 /* Should check EAR[E] ! */
6109 gen_set_access_type(ctx, ACCESS_EXT);
6110 t0 = tcg_temp_new();
6111 gen_addr_reg_index(ctx, t0);
6112 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
6113 DEF_MEMOP(MO_UL | MO_ALIGN));
6114 tcg_temp_free(t0);
6115 }
6116
6117 /* PowerPC 601 specific instructions */
6118
6119 /* abs - abs. */
6120 static void gen_abs(DisasContext *ctx)
6121 {
6122 TCGv d = cpu_gpr[rD(ctx->opcode)];
6123 TCGv a = cpu_gpr[rA(ctx->opcode)];
6124
6125 tcg_gen_abs_tl(d, a);
6126 if (unlikely(Rc(ctx->opcode) != 0)) {
6127 gen_set_Rc0(ctx, d);
6128 }
6129 }
6130
6131 /* abso - abso. */
6132 static void gen_abso(DisasContext *ctx)
6133 {
6134 TCGv d = cpu_gpr[rD(ctx->opcode)];
6135 TCGv a = cpu_gpr[rA(ctx->opcode)];
6136
6137 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
6138 tcg_gen_abs_tl(d, a);
6139 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
6140 if (unlikely(Rc(ctx->opcode) != 0)) {
6141 gen_set_Rc0(ctx, d);
6142 }
6143 }
6144
6145 /* clcs */
6146 static void gen_clcs(DisasContext *ctx)
6147 {
6148 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
6149 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6150 tcg_temp_free_i32(t0);
6151 /* Rc=1 sets CR0 to an undefined state */
6152 }
6153
6154 /* div - div. */
6155 static void gen_div(DisasContext *ctx)
6156 {
6157 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6158 cpu_gpr[rB(ctx->opcode)]);
6159 if (unlikely(Rc(ctx->opcode) != 0)) {
6160 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6161 }
6162 }
6163
6164 /* divo - divo. */
6165 static void gen_divo(DisasContext *ctx)
6166 {
6167 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6168 cpu_gpr[rB(ctx->opcode)]);
6169 if (unlikely(Rc(ctx->opcode) != 0)) {
6170 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6171 }
6172 }
6173
6174 /* divs - divs. */
6175 static void gen_divs(DisasContext *ctx)
6176 {
6177 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6178 cpu_gpr[rB(ctx->opcode)]);
6179 if (unlikely(Rc(ctx->opcode) != 0)) {
6180 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6181 }
6182 }
6183
6184 /* divso - divso. */
6185 static void gen_divso(DisasContext *ctx)
6186 {
6187 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
6188 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6189 if (unlikely(Rc(ctx->opcode) != 0)) {
6190 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6191 }
6192 }
6193
6194 /* doz - doz. */
6195 static void gen_doz(DisasContext *ctx)
6196 {
6197 TCGLabel *l1 = gen_new_label();
6198 TCGLabel *l2 = gen_new_label();
6199 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
6200 cpu_gpr[rA(ctx->opcode)], l1);
6201 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
6202 cpu_gpr[rA(ctx->opcode)]);
6203 tcg_gen_br(l2);
6204 gen_set_label(l1);
6205 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6206 gen_set_label(l2);
6207 if (unlikely(Rc(ctx->opcode) != 0)) {
6208 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6209 }
6210 }
6211
6212 /* dozo - dozo. */
6213 static void gen_dozo(DisasContext *ctx)
6214 {
6215 TCGLabel *l1 = gen_new_label();
6216 TCGLabel *l2 = gen_new_label();
6217 TCGv t0 = tcg_temp_new();
6218 TCGv t1 = tcg_temp_new();
6219 TCGv t2 = tcg_temp_new();
6220 /* Start with XER OV disabled, the most likely case */
6221 tcg_gen_movi_tl(cpu_ov, 0);
6222 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
6223 cpu_gpr[rA(ctx->opcode)], l1);
6224 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6225 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6226 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
6227 tcg_gen_andc_tl(t1, t1, t2);
6228 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6229 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6230 tcg_gen_movi_tl(cpu_ov, 1);
6231 tcg_gen_movi_tl(cpu_so, 1);
6232 tcg_gen_br(l2);
6233 gen_set_label(l1);
6234 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6235 gen_set_label(l2);
6236 tcg_temp_free(t0);
6237 tcg_temp_free(t1);
6238 tcg_temp_free(t2);
6239 if (unlikely(Rc(ctx->opcode) != 0)) {
6240 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6241 }
6242 }
6243
6244 /* dozi */
6245 static void gen_dozi(DisasContext *ctx)
6246 {
6247 target_long simm = SIMM(ctx->opcode);
6248 TCGLabel *l1 = gen_new_label();
6249 TCGLabel *l2 = gen_new_label();
6250 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
6251 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
6252 tcg_gen_br(l2);
6253 gen_set_label(l1);
6254 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6255 gen_set_label(l2);
6256 if (unlikely(Rc(ctx->opcode) != 0)) {
6257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6258 }
6259 }
6260
6261 /* lscbx - lscbx. */
6262 static void gen_lscbx(DisasContext *ctx)
6263 {
6264 TCGv t0 = tcg_temp_new();
6265 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
6266 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
6267 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
6268
6269 gen_addr_reg_index(ctx, t0);
6270 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
6271 tcg_temp_free_i32(t1);
6272 tcg_temp_free_i32(t2);
6273 tcg_temp_free_i32(t3);
6274 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
6275 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
6276 if (unlikely(Rc(ctx->opcode) != 0)) {
6277 gen_set_Rc0(ctx, t0);
6278 }
6279 tcg_temp_free(t0);
6280 }
6281
6282 /* maskg - maskg. */
6283 static void gen_maskg(DisasContext *ctx)
6284 {
6285 TCGLabel *l1 = gen_new_label();
6286 TCGv t0 = tcg_temp_new();
6287 TCGv t1 = tcg_temp_new();
6288 TCGv t2 = tcg_temp_new();
6289 TCGv t3 = tcg_temp_new();
6290 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
6291 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6292 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
6293 tcg_gen_addi_tl(t2, t0, 1);
6294 tcg_gen_shr_tl(t2, t3, t2);
6295 tcg_gen_shr_tl(t3, t3, t1);
6296 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
6297 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
6298 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6299 gen_set_label(l1);
6300 tcg_temp_free(t0);
6301 tcg_temp_free(t1);
6302 tcg_temp_free(t2);
6303 tcg_temp_free(t3);
6304 if (unlikely(Rc(ctx->opcode) != 0)) {
6305 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6306 }
6307 }
6308
6309 /* maskir - maskir. */
6310 static void gen_maskir(DisasContext *ctx)
6311 {
6312 TCGv t0 = tcg_temp_new();
6313 TCGv t1 = tcg_temp_new();
6314 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6315 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6316 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6317 tcg_temp_free(t0);
6318 tcg_temp_free(t1);
6319 if (unlikely(Rc(ctx->opcode) != 0)) {
6320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6321 }
6322 }
6323
6324 /* mul - mul. */
6325 static void gen_mul(DisasContext *ctx)
6326 {
6327 TCGv_i64 t0 = tcg_temp_new_i64();
6328 TCGv_i64 t1 = tcg_temp_new_i64();
6329 TCGv t2 = tcg_temp_new();
6330 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
6331 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
6332 tcg_gen_mul_i64(t0, t0, t1);
6333 tcg_gen_trunc_i64_tl(t2, t0);
6334 gen_store_spr(SPR_MQ, t2);
6335 tcg_gen_shri_i64(t1, t0, 32);
6336 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
6337 tcg_temp_free_i64(t0);
6338 tcg_temp_free_i64(t1);
6339 tcg_temp_free(t2);
6340 if (unlikely(Rc(ctx->opcode) != 0)) {
6341 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6342 }
6343 }
6344
6345 /* mulo - mulo. */
6346 static void gen_mulo(DisasContext *ctx)
6347 {
6348 TCGLabel *l1 = gen_new_label();
6349 TCGv_i64 t0 = tcg_temp_new_i64();
6350 TCGv_i64 t1 = tcg_temp_new_i64();
6351 TCGv t2 = tcg_temp_new();
6352 /* Start with XER OV disabled, the most likely case */
6353 tcg_gen_movi_tl(cpu_ov, 0);
6354 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
6355 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
6356 tcg_gen_mul_i64(t0, t0, t1);
6357 tcg_gen_trunc_i64_tl(t2, t0);
6358 gen_store_spr(SPR_MQ, t2);
6359 tcg_gen_shri_i64(t1, t0, 32);
6360 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
6361 tcg_gen_ext32s_i64(t1, t0);
6362 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
6363 tcg_gen_movi_tl(cpu_ov, 1);
6364 tcg_gen_movi_tl(cpu_so, 1);
6365 gen_set_label(l1);
6366 tcg_temp_free_i64(t0);
6367 tcg_temp_free_i64(t1);
6368 tcg_temp_free(t2);
6369 if (unlikely(Rc(ctx->opcode) != 0)) {
6370 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6371 }
6372 }
6373
6374 /* nabs - nabs. */
6375 static void gen_nabs(DisasContext *ctx)
6376 {
6377 TCGv d = cpu_gpr[rD(ctx->opcode)];
6378 TCGv a = cpu_gpr[rA(ctx->opcode)];
6379
6380 tcg_gen_abs_tl(d, a);
6381 tcg_gen_neg_tl(d, d);
6382 if (unlikely(Rc(ctx->opcode) != 0)) {
6383 gen_set_Rc0(ctx, d);
6384 }
6385 }
6386
6387 /* nabso - nabso. */
6388 static void gen_nabso(DisasContext *ctx)
6389 {
6390 TCGv d = cpu_gpr[rD(ctx->opcode)];
6391 TCGv a = cpu_gpr[rA(ctx->opcode)];
6392
6393 tcg_gen_abs_tl(d, a);
6394 tcg_gen_neg_tl(d, d);
6395 /* nabs never overflows */
6396 tcg_gen_movi_tl(cpu_ov, 0);
6397 if (unlikely(Rc(ctx->opcode) != 0)) {
6398 gen_set_Rc0(ctx, d);
6399 }
6400 }
6401
6402 /* rlmi - rlmi. */
6403 static void gen_rlmi(DisasContext *ctx)
6404 {
6405 uint32_t mb = MB(ctx->opcode);
6406 uint32_t me = ME(ctx->opcode);
6407 TCGv t0 = tcg_temp_new();
6408 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6409 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6410 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
6411 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
6412 ~MASK(mb, me));
6413 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
6414 tcg_temp_free(t0);
6415 if (unlikely(Rc(ctx->opcode) != 0)) {
6416 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6417 }
6418 }
6419
6420 /* rrib - rrib. */
6421 static void gen_rrib(DisasContext *ctx)
6422 {
6423 TCGv t0 = tcg_temp_new();
6424 TCGv t1 = tcg_temp_new();
6425 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6426 tcg_gen_movi_tl(t1, 0x80000000);
6427 tcg_gen_shr_tl(t1, t1, t0);
6428 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6429 tcg_gen_and_tl(t0, t0, t1);
6430 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
6431 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6432 tcg_temp_free(t0);
6433 tcg_temp_free(t1);
6434 if (unlikely(Rc(ctx->opcode) != 0)) {
6435 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6436 }
6437 }
6438
6439 /* sle - sle. */
6440 static void gen_sle(DisasContext *ctx)
6441 {
6442 TCGv t0 = tcg_temp_new();
6443 TCGv t1 = tcg_temp_new();
6444 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6445 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6446 tcg_gen_subfi_tl(t1, 32, t1);
6447 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6448 tcg_gen_or_tl(t1, t0, t1);
6449 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6450 gen_store_spr(SPR_MQ, t1);
6451 tcg_temp_free(t0);
6452 tcg_temp_free(t1);
6453 if (unlikely(Rc(ctx->opcode) != 0)) {
6454 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6455 }
6456 }
6457
6458 /* sleq - sleq. */
6459 static void gen_sleq(DisasContext *ctx)
6460 {
6461 TCGv t0 = tcg_temp_new();
6462 TCGv t1 = tcg_temp_new();
6463 TCGv t2 = tcg_temp_new();
6464 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6465 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
6466 tcg_gen_shl_tl(t2, t2, t0);
6467 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6468 gen_load_spr(t1, SPR_MQ);
6469 gen_store_spr(SPR_MQ, t0);
6470 tcg_gen_and_tl(t0, t0, t2);
6471 tcg_gen_andc_tl(t1, t1, t2);
6472 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6473 tcg_temp_free(t0);
6474 tcg_temp_free(t1);
6475 tcg_temp_free(t2);
6476 if (unlikely(Rc(ctx->opcode) != 0)) {
6477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6478 }
6479 }
6480
6481 /* sliq - sliq. */
6482 static void gen_sliq(DisasContext *ctx)
6483 {
6484 int sh = SH(ctx->opcode);
6485 TCGv t0 = tcg_temp_new();
6486 TCGv t1 = tcg_temp_new();
6487 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6488 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6489 tcg_gen_or_tl(t1, t0, t1);
6490 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6491 gen_store_spr(SPR_MQ, t1);
6492 tcg_temp_free(t0);
6493 tcg_temp_free(t1);
6494 if (unlikely(Rc(ctx->opcode) != 0)) {
6495 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6496 }
6497 }
6498
6499 /* slliq - slliq. */
6500 static void gen_slliq(DisasContext *ctx)
6501 {
6502 int sh = SH(ctx->opcode);
6503 TCGv t0 = tcg_temp_new();
6504 TCGv t1 = tcg_temp_new();
6505 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6506 gen_load_spr(t1, SPR_MQ);
6507 gen_store_spr(SPR_MQ, t0);
6508 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
6509 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
6510 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6511 tcg_temp_free(t0);
6512 tcg_temp_free(t1);
6513 if (unlikely(Rc(ctx->opcode) != 0)) {
6514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6515 }
6516 }
6517
6518 /* sllq - sllq. */
6519 static void gen_sllq(DisasContext *ctx)
6520 {
6521 TCGLabel *l1 = gen_new_label();
6522 TCGLabel *l2 = gen_new_label();
6523 TCGv t0 = tcg_temp_local_new();
6524 TCGv t1 = tcg_temp_local_new();
6525 TCGv t2 = tcg_temp_local_new();
6526 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6527 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6528 tcg_gen_shl_tl(t1, t1, t2);
6529 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6530 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6531 gen_load_spr(t0, SPR_MQ);
6532 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6533 tcg_gen_br(l2);
6534 gen_set_label(l1);
6535 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6536 gen_load_spr(t2, SPR_MQ);
6537 tcg_gen_andc_tl(t1, t2, t1);
6538 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6539 gen_set_label(l2);
6540 tcg_temp_free(t0);
6541 tcg_temp_free(t1);
6542 tcg_temp_free(t2);
6543 if (unlikely(Rc(ctx->opcode) != 0)) {
6544 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6545 }
6546 }
6547
6548 /* slq - slq. */
6549 static void gen_slq(DisasContext *ctx)
6550 {
6551 TCGLabel *l1 = gen_new_label();
6552 TCGv t0 = tcg_temp_new();
6553 TCGv t1 = tcg_temp_new();
6554 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6555 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6556 tcg_gen_subfi_tl(t1, 32, t1);
6557 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6558 tcg_gen_or_tl(t1, t0, t1);
6559 gen_store_spr(SPR_MQ, t1);
6560 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6561 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6562 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6563 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6564 gen_set_label(l1);
6565 tcg_temp_free(t0);
6566 tcg_temp_free(t1);
6567 if (unlikely(Rc(ctx->opcode) != 0)) {
6568 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6569 }
6570 }
6571
6572 /* sraiq - sraiq. */
6573 static void gen_sraiq(DisasContext *ctx)
6574 {
6575 int sh = SH(ctx->opcode);
6576 TCGLabel *l1 = gen_new_label();
6577 TCGv t0 = tcg_temp_new();
6578 TCGv t1 = tcg_temp_new();
6579 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6580 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6581 tcg_gen_or_tl(t0, t0, t1);
6582 gen_store_spr(SPR_MQ, t0);
6583 tcg_gen_movi_tl(cpu_ca, 0);
6584 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6585 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
6586 tcg_gen_movi_tl(cpu_ca, 1);
6587 gen_set_label(l1);
6588 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
6589 tcg_temp_free(t0);
6590 tcg_temp_free(t1);
6591 if (unlikely(Rc(ctx->opcode) != 0)) {
6592 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6593 }
6594 }
6595
6596 /* sraq - sraq. */
6597 static void gen_sraq(DisasContext *ctx)
6598 {
6599 TCGLabel *l1 = gen_new_label();
6600 TCGLabel *l2 = gen_new_label();
6601 TCGv t0 = tcg_temp_new();
6602 TCGv t1 = tcg_temp_local_new();
6603 TCGv t2 = tcg_temp_local_new();
6604 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6605 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6606 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
6607 tcg_gen_subfi_tl(t2, 32, t2);
6608 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
6609 tcg_gen_or_tl(t0, t0, t2);
6610 gen_store_spr(SPR_MQ, t0);
6611 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6612 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
6613 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
6614 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
6615 gen_set_label(l1);
6616 tcg_temp_free(t0);
6617 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
6618 tcg_gen_movi_tl(cpu_ca, 0);
6619 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6620 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
6621 tcg_gen_movi_tl(cpu_ca, 1);
6622 gen_set_label(l2);
6623 tcg_temp_free(t1);
6624 tcg_temp_free(t2);
6625 if (unlikely(Rc(ctx->opcode) != 0)) {
6626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6627 }
6628 }
6629
6630 /* sre - sre. */
6631 static void gen_sre(DisasContext *ctx)
6632 {
6633 TCGv t0 = tcg_temp_new();
6634 TCGv t1 = tcg_temp_new();
6635 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6636 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6637 tcg_gen_subfi_tl(t1, 32, t1);
6638 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6639 tcg_gen_or_tl(t1, t0, t1);
6640 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6641 gen_store_spr(SPR_MQ, t1);
6642 tcg_temp_free(t0);
6643 tcg_temp_free(t1);
6644 if (unlikely(Rc(ctx->opcode) != 0)) {
6645 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6646 }
6647 }
6648
6649 /* srea - srea. */
6650 static void gen_srea(DisasContext *ctx)
6651 {
6652 TCGv t0 = tcg_temp_new();
6653 TCGv t1 = tcg_temp_new();
6654 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6655 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6656 gen_store_spr(SPR_MQ, t0);
6657 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
6658 tcg_temp_free(t0);
6659 tcg_temp_free(t1);
6660 if (unlikely(Rc(ctx->opcode) != 0)) {
6661 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6662 }
6663 }
6664
6665 /* sreq */
6666 static void gen_sreq(DisasContext *ctx)
6667 {
6668 TCGv t0 = tcg_temp_new();
6669 TCGv t1 = tcg_temp_new();
6670 TCGv t2 = tcg_temp_new();
6671 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6672 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6673 tcg_gen_shr_tl(t1, t1, t0);
6674 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6675 gen_load_spr(t2, SPR_MQ);
6676 gen_store_spr(SPR_MQ, t0);
6677 tcg_gen_and_tl(t0, t0, t1);
6678 tcg_gen_andc_tl(t2, t2, t1);
6679 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6680 tcg_temp_free(t0);
6681 tcg_temp_free(t1);
6682 tcg_temp_free(t2);
6683 if (unlikely(Rc(ctx->opcode) != 0)) {
6684 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6685 }
6686 }
6687
6688 /* sriq */
6689 static void gen_sriq(DisasContext *ctx)
6690 {
6691 int sh = SH(ctx->opcode);
6692 TCGv t0 = tcg_temp_new();
6693 TCGv t1 = tcg_temp_new();
6694 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6695 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6696 tcg_gen_or_tl(t1, t0, t1);
6697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6698 gen_store_spr(SPR_MQ, t1);
6699 tcg_temp_free(t0);
6700 tcg_temp_free(t1);
6701 if (unlikely(Rc(ctx->opcode) != 0)) {
6702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6703 }
6704 }
6705
6706 /* srliq */
6707 static void gen_srliq(DisasContext *ctx)
6708 {
6709 int sh = SH(ctx->opcode);
6710 TCGv t0 = tcg_temp_new();
6711 TCGv t1 = tcg_temp_new();
6712 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6713 gen_load_spr(t1, SPR_MQ);
6714 gen_store_spr(SPR_MQ, t0);
6715 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
6716 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
6717 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6718 tcg_temp_free(t0);
6719 tcg_temp_free(t1);
6720 if (unlikely(Rc(ctx->opcode) != 0)) {
6721 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6722 }
6723 }
6724
6725 /* srlq */
6726 static void gen_srlq(DisasContext *ctx)
6727 {
6728 TCGLabel *l1 = gen_new_label();
6729 TCGLabel *l2 = gen_new_label();
6730 TCGv t0 = tcg_temp_local_new();
6731 TCGv t1 = tcg_temp_local_new();
6732 TCGv t2 = tcg_temp_local_new();
6733 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6734 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6735 tcg_gen_shr_tl(t2, t1, t2);
6736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6737 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6738 gen_load_spr(t0, SPR_MQ);
6739 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6740 tcg_gen_br(l2);
6741 gen_set_label(l1);
6742 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6743 tcg_gen_and_tl(t0, t0, t2);
6744 gen_load_spr(t1, SPR_MQ);
6745 tcg_gen_andc_tl(t1, t1, t2);
6746 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6747 gen_set_label(l2);
6748 tcg_temp_free(t0);
6749 tcg_temp_free(t1);
6750 tcg_temp_free(t2);
6751 if (unlikely(Rc(ctx->opcode) != 0)) {
6752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6753 }
6754 }
6755
6756 /* srq */
6757 static void gen_srq(DisasContext *ctx)
6758 {
6759 TCGLabel *l1 = gen_new_label();
6760 TCGv t0 = tcg_temp_new();
6761 TCGv t1 = tcg_temp_new();
6762 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6763 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6764 tcg_gen_subfi_tl(t1, 32, t1);
6765 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6766 tcg_gen_or_tl(t1, t0, t1);
6767 gen_store_spr(SPR_MQ, t1);
6768 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6770 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6771 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6772 gen_set_label(l1);
6773 tcg_temp_free(t0);
6774 tcg_temp_free(t1);
6775 if (unlikely(Rc(ctx->opcode) != 0)) {
6776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6777 }
6778 }
6779
6780 /* PowerPC 602 specific instructions */
6781
6782 /* dsa */
6783 static void gen_dsa(DisasContext *ctx)
6784 {
6785 /* XXX: TODO */
6786 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6787 }
6788
6789 /* esa */
6790 static void gen_esa(DisasContext *ctx)
6791 {
6792 /* XXX: TODO */
6793 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6794 }
6795
6796 /* mfrom */
6797 static void gen_mfrom(DisasContext *ctx)
6798 {
6799 #if defined(CONFIG_USER_ONLY)
6800 GEN_PRIV;
6801 #else
6802 CHK_SV;
6803 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6804 #endif /* defined(CONFIG_USER_ONLY) */
6805 }
6806
6807 /* 602 - 603 - G2 TLB management */
6808
6809 /* tlbld */
6810 static void gen_tlbld_6xx(DisasContext *ctx)
6811 {
6812 #if defined(CONFIG_USER_ONLY)
6813 GEN_PRIV;
6814 #else
6815 CHK_SV;
6816 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6817 #endif /* defined(CONFIG_USER_ONLY) */
6818 }
6819
6820 /* tlbli */
6821 static void gen_tlbli_6xx(DisasContext *ctx)
6822 {
6823 #if defined(CONFIG_USER_ONLY)
6824 GEN_PRIV;
6825 #else
6826 CHK_SV;
6827 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6828 #endif /* defined(CONFIG_USER_ONLY) */
6829 }
6830
6831 /* 74xx TLB management */
6832
6833 /* tlbld */
6834 static void gen_tlbld_74xx(DisasContext *ctx)
6835 {
6836 #if defined(CONFIG_USER_ONLY)
6837 GEN_PRIV;
6838 #else
6839 CHK_SV;
6840 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6841 #endif /* defined(CONFIG_USER_ONLY) */
6842 }
6843
6844 /* tlbli */
6845 static void gen_tlbli_74xx(DisasContext *ctx)
6846 {
6847 #if defined(CONFIG_USER_ONLY)
6848 GEN_PRIV;
6849 #else
6850 CHK_SV;
6851 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6852 #endif /* defined(CONFIG_USER_ONLY) */
6853 }
6854
6855 /* POWER instructions not in PowerPC 601 */
6856
6857 /* clf */
6858 static void gen_clf(DisasContext *ctx)
6859 {
6860 /* Cache line flush: implemented as no-op */
6861 }
6862
6863 /* cli */
6864 static void gen_cli(DisasContext *ctx)
6865 {
6866 #if defined(CONFIG_USER_ONLY)
6867 GEN_PRIV;
6868 #else
6869 /* Cache line invalidate: privileged and treated as no-op */
6870 CHK_SV;
6871 #endif /* defined(CONFIG_USER_ONLY) */
6872 }
6873
6874 /* dclst */
6875 static void gen_dclst(DisasContext *ctx)
6876 {
6877 /* Data cache line store: treated as no-op */
6878 }
6879
6880 static void gen_mfsri(DisasContext *ctx)
6881 {
6882 #if defined(CONFIG_USER_ONLY)
6883 GEN_PRIV;
6884 #else
6885 int ra = rA(ctx->opcode);
6886 int rd = rD(ctx->opcode);
6887 TCGv t0;
6888
6889 CHK_SV;
6890 t0 = tcg_temp_new();
6891 gen_addr_reg_index(ctx, t0);
6892 tcg_gen_extract_tl(t0, t0, 28, 4);
6893 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
6894 tcg_temp_free(t0);
6895 if (ra != 0 && ra != rd) {
6896 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
6897 }
6898 #endif /* defined(CONFIG_USER_ONLY) */
6899 }
6900
6901 static void gen_rac(DisasContext *ctx)
6902 {
6903 #if defined(CONFIG_USER_ONLY)
6904 GEN_PRIV;
6905 #else
6906 TCGv t0;
6907
6908 CHK_SV;
6909 t0 = tcg_temp_new();
6910 gen_addr_reg_index(ctx, t0);
6911 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6912 tcg_temp_free(t0);
6913 #endif /* defined(CONFIG_USER_ONLY) */
6914 }
6915
6916 static void gen_rfsvc(DisasContext *ctx)
6917 {
6918 #if defined(CONFIG_USER_ONLY)
6919 GEN_PRIV;
6920 #else
6921 CHK_SV;
6922
6923 gen_helper_rfsvc(cpu_env);
6924 gen_sync_exception(ctx);
6925 #endif /* defined(CONFIG_USER_ONLY) */
6926 }
6927
6928 /* svc is not implemented for now */
6929
6930 /* BookE specific instructions */
6931
6932 /* XXX: not implemented on 440 ? */
6933 static void gen_mfapidi(DisasContext *ctx)
6934 {
6935 /* XXX: TODO */
6936 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6937 }
6938
6939 /* XXX: not implemented on 440 ? */
6940 static void gen_tlbiva(DisasContext *ctx)
6941 {
6942 #if defined(CONFIG_USER_ONLY)
6943 GEN_PRIV;
6944 #else
6945 TCGv t0;
6946
6947 CHK_SV;
6948 t0 = tcg_temp_new();
6949 gen_addr_reg_index(ctx, t0);
6950 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6951 tcg_temp_free(t0);
6952 #endif /* defined(CONFIG_USER_ONLY) */
6953 }
6954
6955 /* All 405 MAC instructions are translated here */
6956 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6957 int ra, int rb, int rt, int Rc)
6958 {
6959 TCGv t0, t1;
6960
6961 t0 = tcg_temp_local_new();
6962 t1 = tcg_temp_local_new();
6963
6964 switch (opc3 & 0x0D) {
6965 case 0x05:
6966 /* macchw - macchw. - macchwo - macchwo. */
6967 /* macchws - macchws. - macchwso - macchwso. */
6968 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6969 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6970 /* mulchw - mulchw. */
6971 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6972 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6973 tcg_gen_ext16s_tl(t1, t1);
6974 break;
6975 case 0x04:
6976 /* macchwu - macchwu. - macchwuo - macchwuo. */
6977 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6978 /* mulchwu - mulchwu. */
6979 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6980 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6981 tcg_gen_ext16u_tl(t1, t1);
6982 break;
6983 case 0x01:
6984 /* machhw - machhw. - machhwo - machhwo. */
6985 /* machhws - machhws. - machhwso - machhwso. */
6986 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6987 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6988 /* mulhhw - mulhhw. */
6989 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6990 tcg_gen_ext16s_tl(t0, t0);
6991 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6992 tcg_gen_ext16s_tl(t1, t1);
6993 break;
6994 case 0x00:
6995 /* machhwu - machhwu. - machhwuo - machhwuo. */
6996 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6997 /* mulhhwu - mulhhwu. */
6998 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6999 tcg_gen_ext16u_tl(t0, t0);
7000 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
7001 tcg_gen_ext16u_tl(t1, t1);
7002 break;
7003 case 0x0D:
7004 /* maclhw - maclhw. - maclhwo - maclhwo. */
7005 /* maclhws - maclhws. - maclhwso - maclhwso. */
7006 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
7007 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
7008 /* mullhw - mullhw. */
7009 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
7010 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
7011 break;
7012 case 0x0C:
7013 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
7014 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
7015 /* mullhwu - mullhwu. */
7016 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
7017 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
7018 break;
7019 }
7020 if (opc2 & 0x04) {
7021 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
7022 tcg_gen_mul_tl(t1, t0, t1);
7023 if (opc2 & 0x02) {
7024 /* nmultiply-and-accumulate (0x0E) */
7025 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
7026 } else {
7027 /* multiply-and-accumulate (0x0C) */
7028 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
7029 }
7030
7031 if (opc3 & 0x12) {
7032 /* Check overflow and/or saturate */
7033 TCGLabel *l1 = gen_new_label();
7034
7035 if (opc3 & 0x10) {
7036 /* Start with XER OV disabled, the most likely case */
7037 tcg_gen_movi_tl(cpu_ov, 0);
7038 }
7039 if (opc3 & 0x01) {
7040 /* Signed */
7041 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
7042 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
7043 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
7044 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
7045 if (opc3 & 0x02) {
7046 /* Saturate */
7047 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
7048 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
7049 }
7050 } else {
7051 /* Unsigned */
7052 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
7053 if (opc3 & 0x02) {
7054 /* Saturate */
7055 tcg_gen_movi_tl(t0, UINT32_MAX);
7056 }
7057 }
7058 if (opc3 & 0x10) {
7059 /* Check overflow */
7060 tcg_gen_movi_tl(cpu_ov, 1);
7061 tcg_gen_movi_tl(cpu_so, 1);
7062 }
7063 gen_set_label(l1);
7064 tcg_gen_mov_tl(cpu_gpr[rt], t0);
7065 }
7066 } else {
7067 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
7068 }
7069 tcg_temp_free(t0);
7070 tcg_temp_free(t1);
7071 if (unlikely(Rc) != 0) {
7072 /* Update Rc0 */
7073 gen_set_Rc0(ctx, cpu_gpr[rt]);
7074 }
7075 }
7076
7077 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7078 static void glue(gen_, name)(DisasContext *ctx) \
7079 { \
7080 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
7081 rD(ctx->opcode), Rc(ctx->opcode)); \
7082 }
7083
7084 /* macchw - macchw. */
7085 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
7086 /* macchwo - macchwo. */
7087 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
7088 /* macchws - macchws. */
7089 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
7090 /* macchwso - macchwso. */
7091 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
7092 /* macchwsu - macchwsu. */
7093 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
7094 /* macchwsuo - macchwsuo. */
7095 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
7096 /* macchwu - macchwu. */
7097 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
7098 /* macchwuo - macchwuo. */
7099 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
7100 /* machhw - machhw. */
7101 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
7102 /* machhwo - machhwo. */
7103 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
7104 /* machhws - machhws. */
7105 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
7106 /* machhwso - machhwso. */
7107 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
7108 /* machhwsu - machhwsu. */
7109 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
7110 /* machhwsuo - machhwsuo. */
7111 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
7112 /* machhwu - machhwu. */
7113 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
7114 /* machhwuo - machhwuo. */
7115 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
7116 /* maclhw - maclhw. */
7117 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
7118 /* maclhwo - maclhwo. */
7119 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
7120 /* maclhws - maclhws. */
7121 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
7122 /* maclhwso - maclhwso. */
7123 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
7124 /* maclhwu - maclhwu. */
7125 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
7126 /* maclhwuo - maclhwuo. */
7127 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
7128 /* maclhwsu - maclhwsu. */
7129 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
7130 /* maclhwsuo - maclhwsuo. */
7131 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
7132 /* nmacchw - nmacchw. */
7133 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
7134 /* nmacchwo - nmacchwo. */
7135 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
7136 /* nmacchws - nmacchws. */
7137 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
7138 /* nmacchwso - nmacchwso. */
7139 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
7140 /* nmachhw - nmachhw. */
7141 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
7142 /* nmachhwo - nmachhwo. */
7143 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
7144 /* nmachhws - nmachhws. */
7145 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
7146 /* nmachhwso - nmachhwso. */
7147 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
7148 /* nmaclhw - nmaclhw. */
7149 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
7150 /* nmaclhwo - nmaclhwo. */
7151 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
7152 /* nmaclhws - nmaclhws. */
7153 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
7154 /* nmaclhwso - nmaclhwso. */
7155 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
7156
7157 /* mulchw - mulchw. */
7158 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
7159 /* mulchwu - mulchwu. */
7160 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
7161 /* mulhhw - mulhhw. */
7162 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
7163 /* mulhhwu - mulhhwu. */
7164 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
7165 /* mullhw - mullhw. */
7166 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
7167 /* mullhwu - mullhwu. */
7168 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
7169
7170 /* mfdcr */
7171 static void gen_mfdcr(DisasContext *ctx)
7172 {
7173 #if defined(CONFIG_USER_ONLY)
7174 GEN_PRIV;
7175 #else
7176 TCGv dcrn;
7177
7178 CHK_SV;
7179 dcrn = tcg_const_tl(SPR(ctx->opcode));
7180 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
7181 tcg_temp_free(dcrn);
7182 #endif /* defined(CONFIG_USER_ONLY) */
7183 }
7184
7185 /* mtdcr */
7186 static void gen_mtdcr(DisasContext *ctx)
7187 {
7188 #if defined(CONFIG_USER_ONLY)
7189 GEN_PRIV;
7190 #else
7191 TCGv dcrn;
7192
7193 CHK_SV;
7194 dcrn = tcg_const_tl(SPR(ctx->opcode));
7195 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
7196 tcg_temp_free(dcrn);
7197 #endif /* defined(CONFIG_USER_ONLY) */
7198 }
7199
7200 /* mfdcrx */
7201 /* XXX: not implemented on 440 ? */
7202 static void gen_mfdcrx(DisasContext *ctx)
7203 {
7204 #if defined(CONFIG_USER_ONLY)
7205 GEN_PRIV;
7206 #else
7207 CHK_SV;
7208 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
7209 cpu_gpr[rA(ctx->opcode)]);
7210 /* Note: Rc update flag set leads to undefined state of Rc0 */
7211 #endif /* defined(CONFIG_USER_ONLY) */
7212 }
7213
7214 /* mtdcrx */
7215 /* XXX: not implemented on 440 ? */
7216 static void gen_mtdcrx(DisasContext *ctx)
7217 {
7218 #if defined(CONFIG_USER_ONLY)
7219 GEN_PRIV;
7220 #else
7221 CHK_SV;
7222 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
7223 cpu_gpr[rS(ctx->opcode)]);
7224 /* Note: Rc update flag set leads to undefined state of Rc0 */
7225 #endif /* defined(CONFIG_USER_ONLY) */
7226 }
7227
7228 /* mfdcrux (PPC 460) : user-mode access to DCR */
7229 static void gen_mfdcrux(DisasContext *ctx)
7230 {
7231 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
7232 cpu_gpr[rA(ctx->opcode)]);
7233 /* Note: Rc update flag set leads to undefined state of Rc0 */
7234 }
7235
7236 /* mtdcrux (PPC 460) : user-mode access to DCR */
7237 static void gen_mtdcrux(DisasContext *ctx)
7238 {
7239 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
7240 cpu_gpr[rS(ctx->opcode)]);
7241 /* Note: Rc update flag set leads to undefined state of Rc0 */
7242 }
7243
7244 /* dccci */
7245 static void gen_dccci(DisasContext *ctx)
7246 {
7247 CHK_SV;
7248 /* interpreted as no-op */
7249 }
7250
7251 /* dcread */
7252 static void gen_dcread(DisasContext *ctx)
7253 {
7254 #if defined(CONFIG_USER_ONLY)
7255 GEN_PRIV;
7256 #else
7257 TCGv EA, val;
7258
7259 CHK_SV;
7260 gen_set_access_type(ctx, ACCESS_CACHE);
7261 EA = tcg_temp_new();
7262 gen_addr_reg_index(ctx, EA);
7263 val = tcg_temp_new();
7264 gen_qemu_ld32u(ctx, val, EA);
7265 tcg_temp_free(val);
7266 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
7267 tcg_temp_free(EA);
7268 #endif /* defined(CONFIG_USER_ONLY) */
7269 }
7270
7271 /* icbt */
7272 static void gen_icbt_40x(DisasContext *ctx)
7273 {
7274 /*
7275 * interpreted as no-op
7276 * XXX: specification say this is treated as a load by the MMU but
7277 * does not generate any exception
7278 */
7279 }
7280
7281 /* iccci */
7282 static void gen_iccci(DisasContext *ctx)
7283 {
7284 CHK_SV;
7285 /* interpreted as no-op */
7286 }
7287
7288 /* icread */
7289 static void gen_icread(DisasContext *ctx)
7290 {
7291 CHK_SV;
7292 /* interpreted as no-op */
7293 }
7294
7295 /* rfci (supervisor only) */
7296 static void gen_rfci_40x(DisasContext *ctx)
7297 {
7298 #if defined(CONFIG_USER_ONLY)
7299 GEN_PRIV;
7300 #else
7301 CHK_SV;
7302 /* Restore CPU state */
7303 gen_helper_40x_rfci(cpu_env);
7304 gen_sync_exception(ctx);
7305 #endif /* defined(CONFIG_USER_ONLY) */
7306 }
7307
7308 static void gen_rfci(DisasContext *ctx)
7309 {
7310 #if defined(CONFIG_USER_ONLY)
7311 GEN_PRIV;
7312 #else
7313 CHK_SV;
7314 /* Restore CPU state */
7315 gen_helper_rfci(cpu_env);
7316 gen_sync_exception(ctx);
7317 #endif /* defined(CONFIG_USER_ONLY) */
7318 }
7319
7320 /* BookE specific */
7321
7322 /* XXX: not implemented on 440 ? */
7323 static void gen_rfdi(DisasContext *ctx)
7324 {
7325 #if defined(CONFIG_USER_ONLY)
7326 GEN_PRIV;
7327 #else
7328 CHK_SV;
7329 /* Restore CPU state */
7330 gen_helper_rfdi(cpu_env);
7331 gen_sync_exception(ctx);
7332 #endif /* defined(CONFIG_USER_ONLY) */
7333 }
7334
7335 /* XXX: not implemented on 440 ? */
7336 static void gen_rfmci(DisasContext *ctx)
7337 {
7338 #if defined(CONFIG_USER_ONLY)
7339 GEN_PRIV;
7340 #else
7341 CHK_SV;
7342 /* Restore CPU state */
7343 gen_helper_rfmci(cpu_env);
7344 gen_sync_exception(ctx);
7345 #endif /* defined(CONFIG_USER_ONLY) */
7346 }
7347
7348 /* TLB management - PowerPC 405 implementation */
7349
7350 /* tlbre */
7351 static void gen_tlbre_40x(DisasContext *ctx)
7352 {
7353 #if defined(CONFIG_USER_ONLY)
7354 GEN_PRIV;
7355 #else
7356 CHK_SV;
7357 switch (rB(ctx->opcode)) {
7358 case 0:
7359 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
7360 cpu_gpr[rA(ctx->opcode)]);
7361 break;
7362 case 1:
7363 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
7364 cpu_gpr[rA(ctx->opcode)]);
7365 break;
7366 default:
7367 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7368 break;
7369 }
7370 #endif /* defined(CONFIG_USER_ONLY) */
7371 }
7372
7373 /* tlbsx - tlbsx. */
7374 static void gen_tlbsx_40x(DisasContext *ctx)
7375 {
7376 #if defined(CONFIG_USER_ONLY)
7377 GEN_PRIV;
7378 #else
7379 TCGv t0;
7380
7381 CHK_SV;
7382 t0 = tcg_temp_new();
7383 gen_addr_reg_index(ctx, t0);
7384 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
7385 tcg_temp_free(t0);
7386 if (Rc(ctx->opcode)) {
7387 TCGLabel *l1 = gen_new_label();
7388 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
7389 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
7390 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
7391 gen_set_label(l1);
7392 }
7393 #endif /* defined(CONFIG_USER_ONLY) */
7394 }
7395
7396 /* tlbwe */
7397 static void gen_tlbwe_40x(DisasContext *ctx)
7398 {
7399 #if defined(CONFIG_USER_ONLY)
7400 GEN_PRIV;
7401 #else
7402 CHK_SV;
7403
7404 switch (rB(ctx->opcode)) {
7405 case 0:
7406 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
7407 cpu_gpr[rS(ctx->opcode)]);
7408 break;
7409 case 1:
7410 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
7411 cpu_gpr[rS(ctx->opcode)]);
7412 break;
7413 default:
7414 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7415 break;
7416 }
7417 #endif /* defined(CONFIG_USER_ONLY) */
7418 }
7419
7420 /* TLB management - PowerPC 440 implementation */
7421
7422 /* tlbre */
7423 static void gen_tlbre_440(DisasContext *ctx)
7424 {
7425 #if defined(CONFIG_USER_ONLY)
7426 GEN_PRIV;
7427 #else
7428 CHK_SV;
7429
7430 switch (rB(ctx->opcode)) {
7431 case 0:
7432 case 1:
7433 case 2:
7434 {
7435 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
7436 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
7437 t0, cpu_gpr[rA(ctx->opcode)]);
7438 tcg_temp_free_i32(t0);
7439 }
7440 break;
7441 default:
7442 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7443 break;
7444 }
7445 #endif /* defined(CONFIG_USER_ONLY) */
7446 }
7447
7448 /* tlbsx - tlbsx. */
7449 static void gen_tlbsx_440(DisasContext *ctx)
7450 {
7451 #if defined(CONFIG_USER_ONLY)
7452 GEN_PRIV;
7453 #else
7454 TCGv t0;
7455
7456 CHK_SV;
7457 t0 = tcg_temp_new();
7458 gen_addr_reg_index(ctx, t0);
7459 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
7460 tcg_temp_free(t0);
7461 if (Rc(ctx->opcode)) {
7462 TCGLabel *l1 = gen_new_label();
7463 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
7464 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
7465 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
7466 gen_set_label(l1);
7467 }
7468 #endif /* defined(CONFIG_USER_ONLY) */
7469 }
7470
7471 /* tlbwe */
7472 static void gen_tlbwe_440(DisasContext *ctx)
7473 {
7474 #if defined(CONFIG_USER_ONLY)
7475 GEN_PRIV;
7476 #else
7477 CHK_SV;
7478 switch (rB(ctx->opcode)) {
7479 case 0:
7480 case 1:
7481 case 2:
7482 {
7483 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
7484 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
7485 cpu_gpr[rS(ctx->opcode)]);
7486 tcg_temp_free_i32(t0);
7487 }
7488 break;
7489 default:
7490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7491 break;
7492 }
7493 #endif /* defined(CONFIG_USER_ONLY) */
7494 }
7495
7496 /* TLB management - PowerPC BookE 2.06 implementation */
7497
7498 /* tlbre */
7499 static void gen_tlbre_booke206(DisasContext *ctx)
7500 {
7501 #if defined(CONFIG_USER_ONLY)
7502 GEN_PRIV;
7503 #else
7504 CHK_SV;
7505 gen_helper_booke206_tlbre(cpu_env);
7506 #endif /* defined(CONFIG_USER_ONLY) */
7507 }
7508
7509 /* tlbsx - tlbsx. */
7510 static void gen_tlbsx_booke206(DisasContext *ctx)
7511 {
7512 #if defined(CONFIG_USER_ONLY)
7513 GEN_PRIV;
7514 #else
7515 TCGv t0;
7516
7517 CHK_SV;
7518 if (rA(ctx->opcode)) {
7519 t0 = tcg_temp_new();
7520 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
7521 } else {
7522 t0 = tcg_const_tl(0);
7523 }
7524
7525 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
7526 gen_helper_booke206_tlbsx(cpu_env, t0);
7527 tcg_temp_free(t0);
7528 #endif /* defined(CONFIG_USER_ONLY) */
7529 }
7530
7531 /* tlbwe */
7532 static void gen_tlbwe_booke206(DisasContext *ctx)
7533 {
7534 #if defined(CONFIG_USER_ONLY)
7535 GEN_PRIV;
7536 #else
7537 CHK_SV;
7538 gen_helper_booke206_tlbwe(cpu_env);
7539 #endif /* defined(CONFIG_USER_ONLY) */
7540 }
7541
7542 static void gen_tlbivax_booke206(DisasContext *ctx)
7543 {
7544 #if defined(CONFIG_USER_ONLY)
7545 GEN_PRIV;
7546 #else
7547 TCGv t0;
7548
7549 CHK_SV;
7550 t0 = tcg_temp_new();
7551 gen_addr_reg_index(ctx, t0);
7552 gen_helper_booke206_tlbivax(cpu_env, t0);
7553 tcg_temp_free(t0);
7554 #endif /* defined(CONFIG_USER_ONLY) */
7555 }
7556
7557 static void gen_tlbilx_booke206(DisasContext *ctx)
7558 {
7559 #if defined(CONFIG_USER_ONLY)
7560 GEN_PRIV;
7561 #else
7562 TCGv t0;
7563
7564 CHK_SV;
7565 t0 = tcg_temp_new();
7566 gen_addr_reg_index(ctx, t0);
7567
7568 switch ((ctx->opcode >> 21) & 0x3) {
7569 case 0:
7570 gen_helper_booke206_tlbilx0(cpu_env, t0);
7571 break;
7572 case 1:
7573 gen_helper_booke206_tlbilx1(cpu_env, t0);
7574 break;
7575 case 3:
7576 gen_helper_booke206_tlbilx3(cpu_env, t0);
7577 break;
7578 default:
7579 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7580 break;
7581 }
7582
7583 tcg_temp_free(t0);
7584 #endif /* defined(CONFIG_USER_ONLY) */
7585 }
7586
7587
7588 /* wrtee */
7589 static void gen_wrtee(DisasContext *ctx)
7590 {
7591 #if defined(CONFIG_USER_ONLY)
7592 GEN_PRIV;
7593 #else
7594 TCGv t0;
7595
7596 CHK_SV;
7597 t0 = tcg_temp_new();
7598 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
7599 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7600 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
7601 tcg_temp_free(t0);
7602 /*
7603 * Stop translation to have a chance to raise an exception if we
7604 * just set msr_ee to 1
7605 */
7606 gen_stop_exception(ctx);
7607 #endif /* defined(CONFIG_USER_ONLY) */
7608 }
7609
7610 /* wrteei */
7611 static void gen_wrteei(DisasContext *ctx)
7612 {
7613 #if defined(CONFIG_USER_ONLY)
7614 GEN_PRIV;
7615 #else
7616 CHK_SV;
7617 if (ctx->opcode & 0x00008000) {
7618 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
7619 /* Stop translation to have a chance to raise an exception */
7620 gen_stop_exception(ctx);
7621 } else {
7622 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7623 }
7624 #endif /* defined(CONFIG_USER_ONLY) */
7625 }
7626
7627 /* PowerPC 440 specific instructions */
7628
7629 /* dlmzb */
7630 static void gen_dlmzb(DisasContext *ctx)
7631 {
7632 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
7633 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
7634 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
7635 tcg_temp_free_i32(t0);
7636 }
7637
7638 /* mbar replaces eieio on 440 */
7639 static void gen_mbar(DisasContext *ctx)
7640 {
7641 /* interpreted as no-op */
7642 }
7643
7644 /* msync replaces sync on 440 */
7645 static void gen_msync_4xx(DisasContext *ctx)
7646 {
7647 /* Only e500 seems to treat reserved bits as invalid */
7648 if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
7649 (ctx->opcode & 0x03FFF801)) {
7650 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7651 }
7652 /* otherwise interpreted as no-op */
7653 }
7654
7655 /* icbt */
7656 static void gen_icbt_440(DisasContext *ctx)
7657 {
7658 /*
7659 * interpreted as no-op
7660 * XXX: specification say this is treated as a load by the MMU but
7661 * does not generate any exception
7662 */
7663 }
7664
7665 /* Embedded.Processor Control */
7666
7667 static void gen_msgclr(DisasContext *ctx)
7668 {
7669 #if defined(CONFIG_USER_ONLY)
7670 GEN_PRIV;
7671 #else
7672 CHK_HV;
7673 if (is_book3s_arch2x(ctx)) {
7674 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7675 } else {
7676 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7677 }
7678 #endif /* defined(CONFIG_USER_ONLY) */
7679 }
7680
7681 static void gen_msgsnd(DisasContext *ctx)
7682 {
7683 #if defined(CONFIG_USER_ONLY)
7684 GEN_PRIV;
7685 #else
7686 CHK_HV;
7687 if (is_book3s_arch2x(ctx)) {
7688 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7689 } else {
7690 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7691 }
7692 #endif /* defined(CONFIG_USER_ONLY) */
7693 }
7694
7695 #if defined(TARGET_PPC64)
7696 static void gen_msgclrp(DisasContext *ctx)
7697 {
7698 #if defined(CONFIG_USER_ONLY)
7699 GEN_PRIV;
7700 #else
7701 CHK_SV;
7702 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7703 #endif /* defined(CONFIG_USER_ONLY) */
7704 }
7705
7706 static void gen_msgsndp(DisasContext *ctx)
7707 {
7708 #if defined(CONFIG_USER_ONLY)
7709 GEN_PRIV;
7710 #else
7711 CHK_SV;
7712 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7713 #endif /* defined(CONFIG_USER_ONLY) */
7714 }
7715 #endif
7716
7717 static void gen_msgsync(DisasContext *ctx)
7718 {
7719 #if defined(CONFIG_USER_ONLY)
7720 GEN_PRIV;
7721 #else
7722 CHK_HV;
7723 #endif /* defined(CONFIG_USER_ONLY) */
7724 /* interpreted as no-op */
7725 }
7726
7727 #if defined(TARGET_PPC64)
7728 static void gen_maddld(DisasContext *ctx)
7729 {
7730 TCGv_i64 t1 = tcg_temp_new_i64();
7731
7732 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7733 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
7734 tcg_temp_free_i64(t1);
7735 }
7736
7737 /* maddhd maddhdu */
7738 static void gen_maddhd_maddhdu(DisasContext *ctx)
7739 {
7740 TCGv_i64 lo = tcg_temp_new_i64();
7741 TCGv_i64 hi = tcg_temp_new_i64();
7742 TCGv_i64 t1 = tcg_temp_new_i64();
7743
7744 if (Rc(ctx->opcode)) {
7745 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7746 cpu_gpr[rB(ctx->opcode)]);
7747 tcg_gen_movi_i64(t1, 0);
7748 } else {
7749 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7750 cpu_gpr[rB(ctx->opcode)]);
7751 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
7752 }
7753 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
7754 cpu_gpr[rC(ctx->opcode)], t1);
7755 tcg_temp_free_i64(lo);
7756 tcg_temp_free_i64(hi);
7757 tcg_temp_free_i64(t1);
7758 }
7759 #endif /* defined(TARGET_PPC64) */
7760
7761 static void gen_tbegin(DisasContext *ctx)
7762 {
7763 if (unlikely(!ctx->tm_enabled)) {
7764 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7765 return;
7766 }
7767 gen_helper_tbegin(cpu_env);
7768 }
7769
7770 #define GEN_TM_NOOP(name) \
7771 static inline void gen_##name(DisasContext *ctx) \
7772 { \
7773 if (unlikely(!ctx->tm_enabled)) { \
7774 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7775 return; \
7776 } \
7777 /* \
7778 * Because tbegin always fails in QEMU, these user \
7779 * space instructions all have a simple implementation: \
7780 * \
7781 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7782 * = 0b0 || 0b00 || 0b0 \
7783 */ \
7784 tcg_gen_movi_i32(cpu_crf[0], 0); \
7785 }
7786
7787 GEN_TM_NOOP(tend);
7788 GEN_TM_NOOP(tabort);
7789 GEN_TM_NOOP(tabortwc);
7790 GEN_TM_NOOP(tabortwci);
7791 GEN_TM_NOOP(tabortdc);
7792 GEN_TM_NOOP(tabortdci);
7793 GEN_TM_NOOP(tsr);
7794
7795 static inline void gen_cp_abort(DisasContext *ctx)
7796 {
7797 /* Do Nothing */
7798 }
7799
7800 #define GEN_CP_PASTE_NOOP(name) \
7801 static inline void gen_##name(DisasContext *ctx) \
7802 { \
7803 /* \
7804 * Generate invalid exception until we have an \
7805 * implementation of the copy paste facility \
7806 */ \
7807 gen_invalid(ctx); \
7808 }
7809
7810 GEN_CP_PASTE_NOOP(copy)
7811 GEN_CP_PASTE_NOOP(paste)
7812
7813 static void gen_tcheck(DisasContext *ctx)
7814 {
7815 if (unlikely(!ctx->tm_enabled)) {
7816 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7817 return;
7818 }
7819 /*
7820 * Because tbegin always fails, the tcheck implementation is
7821 * simple:
7822 *
7823 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
7824 * = 0b1 || 0b00 || 0b0
7825 */
7826 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
7827 }
7828
7829 #if defined(CONFIG_USER_ONLY)
7830 #define GEN_TM_PRIV_NOOP(name) \
7831 static inline void gen_##name(DisasContext *ctx) \
7832 { \
7833 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
7834 }
7835
7836 #else
7837
7838 #define GEN_TM_PRIV_NOOP(name) \
7839 static inline void gen_##name(DisasContext *ctx) \
7840 { \
7841 CHK_SV; \
7842 if (unlikely(!ctx->tm_enabled)) { \
7843 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7844 return; \
7845 } \
7846 /* \
7847 * Because tbegin always fails, the implementation is \
7848 * simple: \
7849 * \
7850 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7851 * = 0b0 || 0b00 | 0b0 \
7852 */ \
7853 tcg_gen_movi_i32(cpu_crf[0], 0); \
7854 }
7855
7856 #endif
7857
7858 GEN_TM_PRIV_NOOP(treclaim);
7859 GEN_TM_PRIV_NOOP(trechkpt);
7860
7861 static inline void get_fpr(TCGv_i64 dst, int regno)
7862 {
7863 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
7864 }
7865
7866 static inline void set_fpr(int regno, TCGv_i64 src)
7867 {
7868 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
7869 }
7870
7871 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
7872 {
7873 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
7874 }
7875
7876 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
7877 {
7878 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
7879 }
7880
7881 #include "translate/fp-impl.c.inc"
7882
7883 #include "translate/vmx-impl.c.inc"
7884
7885 #include "translate/vsx-impl.c.inc"
7886
7887 #include "translate/dfp-impl.c.inc"
7888
7889 #include "translate/spe-impl.c.inc"
7890
7891 /* Handles lfdp, lxsd, lxssp */
7892 static void gen_dform39(DisasContext *ctx)
7893 {
7894 switch (ctx->opcode & 0x3) {
7895 case 0: /* lfdp */
7896 if (ctx->insns_flags2 & PPC2_ISA205) {
7897 return gen_lfdp(ctx);
7898 }
7899 break;
7900 case 2: /* lxsd */
7901 if (ctx->insns_flags2 & PPC2_ISA300) {
7902 return gen_lxsd(ctx);
7903 }
7904 break;
7905 case 3: /* lxssp */
7906 if (ctx->insns_flags2 & PPC2_ISA300) {
7907 return gen_lxssp(ctx);
7908 }
7909 break;
7910 }
7911 return gen_invalid(ctx);
7912 }
7913
7914 /* handles stfdp, lxv, stxsd, stxssp lxvx */
7915 static void gen_dform3D(DisasContext *ctx)
7916 {
7917 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
7918 switch (ctx->opcode & 0x7) {
7919 case 1: /* lxv */
7920 if (ctx->insns_flags2 & PPC2_ISA300) {
7921 return gen_lxv(ctx);
7922 }
7923 break;
7924 case 5: /* stxv */
7925 if (ctx->insns_flags2 & PPC2_ISA300) {
7926 return gen_stxv(ctx);
7927 }
7928 break;
7929 }
7930 } else { /* DS-FORM */
7931 switch (ctx->opcode & 0x3) {
7932 case 0: /* stfdp */
7933 if (ctx->insns_flags2 & PPC2_ISA205) {
7934 return gen_stfdp(ctx);
7935 }
7936 break;
7937 case 2: /* stxsd */
7938 if (ctx->insns_flags2 & PPC2_ISA300) {
7939 return gen_stxsd(ctx);
7940 }
7941 break;
7942 case 3: /* stxssp */
7943 if (ctx->insns_flags2 & PPC2_ISA300) {
7944 return gen_stxssp(ctx);
7945 }
7946 break;
7947 }
7948 }
7949 return gen_invalid(ctx);
7950 }
7951
7952 #if defined(TARGET_PPC64)
7953 /* brd */
7954 static void gen_brd(DisasContext *ctx)
7955 {
7956 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7957 }
7958
7959 /* brw */
7960 static void gen_brw(DisasContext *ctx)
7961 {
7962 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7963 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
7964
7965 }
7966
7967 /* brh */
7968 static void gen_brh(DisasContext *ctx)
7969 {
7970 TCGv_i64 t0 = tcg_temp_new_i64();
7971 TCGv_i64 t1 = tcg_temp_new_i64();
7972 TCGv_i64 t2 = tcg_temp_new_i64();
7973
7974 tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
7975 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
7976 tcg_gen_and_i64(t2, t1, t0);
7977 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
7978 tcg_gen_shli_i64(t1, t1, 8);
7979 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
7980
7981 tcg_temp_free_i64(t0);
7982 tcg_temp_free_i64(t1);
7983 tcg_temp_free_i64(t2);
7984 }
7985 #endif
7986
7987 static opcode_t opcodes[] = {
7988 #if defined(TARGET_PPC64)
7989 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
7990 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
7991 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
7992 #endif
7993 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
7994 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
7995 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7996 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
7997 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7998 #if defined(TARGET_PPC64)
7999 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
8000 #endif
8001 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8002 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
8003 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8004 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8005 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8006 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8007 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8008 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
8009 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8010 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8011 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8012 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8013 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8014 #if defined(TARGET_PPC64)
8015 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8016 #endif
8017 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8018 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8019 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8020 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8021 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8022 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8023 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
8024 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
8025 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8026 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
8027 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8028 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8029 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8030 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8031 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8032 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8033 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
8034 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8035 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8036 #if defined(TARGET_PPC64)
8037 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8038 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8039 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
8040 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
8041 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8042 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
8043 #endif
8044 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8045 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8046 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8047 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8048 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8049 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8050 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8051 #if defined(TARGET_PPC64)
8052 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8053 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8054 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8055 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8056 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8057 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
8058 PPC_NONE, PPC2_ISA300),
8059 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
8060 PPC_NONE, PPC2_ISA300),
8061 #endif
8062 #if defined(TARGET_PPC64)
8063 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8064 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8065 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8066 #endif
8067 /* handles lfdp, lxsd, lxssp */
8068 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
8069 /* handles stfdp, lxv, stxsd, stxssp, stxv */
8070 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
8071 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8072 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8073 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8074 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8075 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8076 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8077 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
8078 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8079 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8080 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8081 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8082 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
8083 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
8084 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8085 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8086 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8087 #if defined(TARGET_PPC64)
8088 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
8089 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
8090 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8091 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
8092 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8093 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
8094 #endif
8095 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8096 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8097 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
8098 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8099 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8100 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8101 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8102 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
8103 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8104 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8105 #if defined(TARGET_PPC64)
8106 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8107 #if !defined(CONFIG_USER_ONLY)
8108 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
8109 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
8110 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
8111 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
8112 #endif
8113 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8114 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8115 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8116 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8117 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8118 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8119 #endif
8120 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
8121 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
8122 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
8123 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8124 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8125 #if defined(TARGET_PPC64)
8126 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8127 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8128 #endif
8129 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8130 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8131 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8132 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8133 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8134 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8135 #if defined(TARGET_PPC64)
8136 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8137 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
8138 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
8139 #endif
8140 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
8141 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
8142 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8143 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
8144 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8145 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8146 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
8147 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
8148 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
8149 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
8150 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
8151 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8152 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8153 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
8154 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8155 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
8156 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8157 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8158 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
8159 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8160 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8161 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8162 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8163 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8164 #if defined(TARGET_PPC64)
8165 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8166 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8167 PPC_SEGMENT_64B),
8168 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8169 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8170 PPC_SEGMENT_64B),
8171 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8172 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8173 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8174 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
8175 #endif
8176 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8177 /*
8178 * XXX Those instructions will need to be handled differently for
8179 * different ISA versions
8180 */
8181 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
8182 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
8183 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
8184 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
8185 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8186 #if defined(TARGET_PPC64)
8187 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
8188 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8189 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
8190 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8191 #endif
8192 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8193 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8194 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8195 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8196 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8197 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8198 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8199 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8200 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8201 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8202 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8203 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8204 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8205 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8206 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8207 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8208 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8209 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8210 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8211 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8212 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8213 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8214 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8215 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8216 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8217 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8218 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8219 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8220 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8221 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8222 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8223 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8224 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8225 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8226 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8227 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8228 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8229 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8230 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8231 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8232 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8233 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8234 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8235 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8236 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8237 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8238 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8239 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8240 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8241 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8242 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8243 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8244 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8245 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8246 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8247 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8248 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8249 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8250 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8251 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8252 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8253 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8254 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8255 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8256 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8257 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8258 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8259 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8260 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8261 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8262 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8263 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8264 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8265 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8266 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8267 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8268 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8269 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8270 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8271 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8272 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8273 PPC_NONE, PPC2_BOOKE206),
8274 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8275 PPC_NONE, PPC2_BOOKE206),
8276 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8277 PPC_NONE, PPC2_BOOKE206),
8278 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8279 PPC_NONE, PPC2_BOOKE206),
8280 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8281 PPC_NONE, PPC2_BOOKE206),
8282 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8283 PPC_NONE, PPC2_PRCNTL),
8284 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8285 PPC_NONE, PPC2_PRCNTL),
8286 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
8287 PPC_NONE, PPC2_PRCNTL),
8288 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8289 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8290 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8291 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8292 PPC_BOOKE, PPC2_BOOKE206),
8293 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
8294 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8295 PPC_BOOKE, PPC2_BOOKE206),
8296 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
8297 PPC_440_SPEC),
8298 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8299 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8300 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8301 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8302 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8303 #if defined(TARGET_PPC64)
8304 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
8305 PPC2_ISA300),
8306 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
8307 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
8308 PPC_NONE, PPC2_ISA207S),
8309 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
8310 PPC_NONE, PPC2_ISA207S),
8311 #endif
8312
8313 #undef GEN_INT_ARITH_ADD
8314 #undef GEN_INT_ARITH_ADD_CONST
8315 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8316 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8317 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8318 add_ca, compute_ca, compute_ov) \
8319 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8320 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8321 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8322 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8323 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8324 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8325 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8326 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8327 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8328 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
8329 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8330 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8331
8332 #undef GEN_INT_ARITH_DIVW
8333 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8334 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8335 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8336 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8337 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8338 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8339 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8340 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8341 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8342 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8343 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
8344 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
8345
8346 #if defined(TARGET_PPC64)
8347 #undef GEN_INT_ARITH_DIVD
8348 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8349 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8350 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8351 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8352 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8353 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8354
8355 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8356 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8357 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8358 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8359 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
8360 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
8361
8362 #undef GEN_INT_ARITH_MUL_HELPER
8363 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8364 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8365 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8366 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8367 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8368 #endif
8369
8370 #undef GEN_INT_ARITH_SUBF
8371 #undef GEN_INT_ARITH_SUBF_CONST
8372 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8373 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8374 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8375 add_ca, compute_ca, compute_ov) \
8376 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8377 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8378 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8379 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8380 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8381 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8382 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8383 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8384 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8385 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8386 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8387
8388 #undef GEN_LOGICAL1
8389 #undef GEN_LOGICAL2
8390 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8391 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8392 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8393 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8394 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8395 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8396 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8397 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8398 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8399 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8400 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8401 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8402 #if defined(TARGET_PPC64)
8403 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8404 #endif
8405
8406 #if defined(TARGET_PPC64)
8407 #undef GEN_PPC64_R2
8408 #undef GEN_PPC64_R4
8409 #define GEN_PPC64_R2(name, opc1, opc2) \
8410 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8411 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8412 PPC_64B)
8413 #define GEN_PPC64_R4(name, opc1, opc2) \
8414 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8415 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8416 PPC_64B), \
8417 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8418 PPC_64B), \
8419 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8420 PPC_64B)
8421 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8422 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8423 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8424 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8425 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8426 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8427 #endif
8428
8429 #undef GEN_LD
8430 #undef GEN_LDU
8431 #undef GEN_LDUX
8432 #undef GEN_LDX_E
8433 #undef GEN_LDS
8434 #define GEN_LD(name, ldop, opc, type) \
8435 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8436 #define GEN_LDU(name, ldop, opc, type) \
8437 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8438 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8439 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8440 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
8441 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8442 #define GEN_LDS(name, ldop, op, type) \
8443 GEN_LD(name, ldop, op | 0x20, type) \
8444 GEN_LDU(name, ldop, op | 0x21, type) \
8445 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8446 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8447
8448 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8449 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8450 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8451 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8452 #if defined(TARGET_PPC64)
8453 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8454 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8455 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
8456 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
8457 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
8458
8459 /* HV/P7 and later only */
8460 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
8461 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
8462 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
8463 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
8464 #endif
8465 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8466 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8467
8468 /* External PID based load */
8469 #undef GEN_LDEPX
8470 #define GEN_LDEPX(name, ldop, opc2, opc3) \
8471 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8472 0x00000001, PPC_NONE, PPC2_BOOKE206),
8473
8474 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
8475 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
8476 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
8477 #if defined(TARGET_PPC64)
8478 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
8479 #endif
8480
8481 #undef GEN_ST
8482 #undef GEN_STU
8483 #undef GEN_STUX
8484 #undef GEN_STX_E
8485 #undef GEN_STS
8486 #define GEN_ST(name, stop, opc, type) \
8487 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8488 #define GEN_STU(name, stop, opc, type) \
8489 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8490 #define GEN_STUX(name, stop, opc2, opc3, type) \
8491 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8492 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
8493 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
8494 #define GEN_STS(name, stop, op, type) \
8495 GEN_ST(name, stop, op | 0x20, type) \
8496 GEN_STU(name, stop, op | 0x21, type) \
8497 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8498 GEN_STX(name, stop, 0x17, op | 0x00, type)
8499
8500 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8501 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8502 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8503 #if defined(TARGET_PPC64)
8504 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
8505 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
8506 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
8507 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
8508 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
8509 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
8510 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
8511 #endif
8512 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8513 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8514
8515 #undef GEN_STEPX
8516 #define GEN_STEPX(name, ldop, opc2, opc3) \
8517 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8518 0x00000001, PPC_NONE, PPC2_BOOKE206),
8519
8520 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
8521 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
8522 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
8523 #if defined(TARGET_PPC64)
8524 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
8525 #endif
8526
8527 #undef GEN_CRLOGIC
8528 #define GEN_CRLOGIC(name, tcg_op, opc) \
8529 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8530 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8531 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8532 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8533 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8534 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8535 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8536 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8537 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8538
8539 #undef GEN_MAC_HANDLER
8540 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8541 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8542 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8543 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8544 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8545 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8546 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8547 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8548 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8549 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8550 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8551 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8552 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8553 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8554 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8555 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8556 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8557 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8558 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8559 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8560 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8561 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8562 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8563 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8564 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8565 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8566 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8567 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8568 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8569 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8570 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8571 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8572 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8573 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8574 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8575 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8576 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8577 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8578 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8579 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8580 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8581 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8582 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8583 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8584
8585 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
8586 PPC_NONE, PPC2_TM),
8587 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
8588 PPC_NONE, PPC2_TM),
8589 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
8590 PPC_NONE, PPC2_TM),
8591 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
8592 PPC_NONE, PPC2_TM),
8593 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
8594 PPC_NONE, PPC2_TM),
8595 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
8596 PPC_NONE, PPC2_TM),
8597 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
8598 PPC_NONE, PPC2_TM),
8599 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
8600 PPC_NONE, PPC2_TM),
8601 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
8602 PPC_NONE, PPC2_TM),
8603 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
8604 PPC_NONE, PPC2_TM),
8605 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
8606 PPC_NONE, PPC2_TM),
8607
8608 #include "translate/fp-ops.c.inc"
8609
8610 #include "translate/vmx-ops.c.inc"
8611
8612 #include "translate/vsx-ops.c.inc"
8613
8614 #include "translate/dfp-ops.c.inc"
8615
8616 #include "translate/spe-ops.c.inc"
8617 };
8618
8619 #include "helper_regs.h"
8620 #include "translate_init.c.inc"
8621
8622 /*****************************************************************************/
8623 /* Misc PowerPC helpers */
8624 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
8625 {
8626 #define RGPL 4
8627 #define RFPL 4
8628
8629 PowerPCCPU *cpu = POWERPC_CPU(cs);
8630 CPUPPCState *env = &cpu->env;
8631 int i;
8632
8633 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
8634 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
8635 env->nip, env->lr, env->ctr, cpu_read_xer(env),
8636 cs->cpu_index);
8637 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
8638 "%08x iidx %d didx %d\n",
8639 env->msr, env->spr[SPR_HID0], env->hflags,
8640 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
8641 #if !defined(NO_TIMER_DUMP)
8642 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
8643 #if !defined(CONFIG_USER_ONLY)
8644 " DECR " TARGET_FMT_lu
8645 #endif
8646 "\n",
8647 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8648 #if !defined(CONFIG_USER_ONLY)
8649 , cpu_ppc_load_decr(env)
8650 #endif
8651 );
8652 #endif
8653 for (i = 0; i < 32; i++) {
8654 if ((i & (RGPL - 1)) == 0) {
8655 qemu_fprintf(f, "GPR%02d", i);
8656 }
8657 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
8658 if ((i & (RGPL - 1)) == (RGPL - 1)) {
8659 qemu_fprintf(f, "\n");
8660 }
8661 }
8662 qemu_fprintf(f, "CR ");
8663 for (i = 0; i < 8; i++)
8664 qemu_fprintf(f, "%01x", env->crf[i]);
8665 qemu_fprintf(f, " [");
8666 for (i = 0; i < 8; i++) {
8667 char a = '-';
8668 if (env->crf[i] & 0x08) {
8669 a = 'L';
8670 } else if (env->crf[i] & 0x04) {
8671 a = 'G';
8672 } else if (env->crf[i] & 0x02) {
8673 a = 'E';
8674 }
8675 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8676 }
8677 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
8678 env->reserve_addr);
8679
8680 if (flags & CPU_DUMP_FPU) {
8681 for (i = 0; i < 32; i++) {
8682 if ((i & (RFPL - 1)) == 0) {
8683 qemu_fprintf(f, "FPR%02d", i);
8684 }
8685 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
8686 if ((i & (RFPL - 1)) == (RFPL - 1)) {
8687 qemu_fprintf(f, "\n");
8688 }
8689 }
8690 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
8691 }
8692
8693 #if !defined(CONFIG_USER_ONLY)
8694 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
8695 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8696 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8697 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8698
8699 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8700 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8701 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8702 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8703
8704 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8705 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8706 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8707 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8708
8709 #if defined(TARGET_PPC64)
8710 if (env->excp_model == POWERPC_EXCP_POWER7 ||
8711 env->excp_model == POWERPC_EXCP_POWER8 ||
8712 env->excp_model == POWERPC_EXCP_POWER9 ||
8713 env->excp_model == POWERPC_EXCP_POWER10) {
8714 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8715 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8716 }
8717 #endif
8718 if (env->excp_model == POWERPC_EXCP_BOOKE) {
8719 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8720 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8721 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8722 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8723
8724 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8725 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8726 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8727 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8728
8729 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8730 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8731 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8732 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8733
8734 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8735 " EPR " TARGET_FMT_lx "\n",
8736 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8737 env->spr[SPR_BOOKE_EPR]);
8738
8739 /* FSL-specific */
8740 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8741 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8742 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8743 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8744
8745 /*
8746 * IVORs are left out as they are large and do not change often --
8747 * they can be read with "p $ivor0", "p $ivor1", etc.
8748 */
8749 }
8750
8751 #if defined(TARGET_PPC64)
8752 if (env->flags & POWERPC_FLAG_CFAR) {
8753 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8754 }
8755 #endif
8756
8757 if (env->spr_cb[SPR_LPCR].name) {
8758 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8759 }
8760
8761 switch (env->mmu_model) {
8762 case POWERPC_MMU_32B:
8763 case POWERPC_MMU_601:
8764 case POWERPC_MMU_SOFT_6xx:
8765 case POWERPC_MMU_SOFT_74xx:
8766 #if defined(TARGET_PPC64)
8767 case POWERPC_MMU_64B:
8768 case POWERPC_MMU_2_03:
8769 case POWERPC_MMU_2_06:
8770 case POWERPC_MMU_2_07:
8771 case POWERPC_MMU_3_00:
8772 #endif
8773 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8774 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8775 }
8776 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8777 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8778 }
8779 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8780 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8781 break;
8782 case POWERPC_MMU_BOOKE206:
8783 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8784 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8785 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8786 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8787
8788 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8789 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8790 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8791 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8792
8793 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8794 " TLB1CFG " TARGET_FMT_lx "\n",
8795 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8796 env->spr[SPR_BOOKE_TLB1CFG]);
8797 break;
8798 default:
8799 break;
8800 }
8801 #endif
8802
8803 #undef RGPL
8804 #undef RFPL
8805 }
8806
8807 /*****************************************************************************/
8808 /* Opcode types */
8809 enum {
8810 PPC_DIRECT = 0, /* Opcode routine */
8811 PPC_INDIRECT = 1, /* Indirect opcode table */
8812 };
8813
8814 #define PPC_OPCODE_MASK 0x3
8815
8816 static inline int is_indirect_opcode(void *handler)
8817 {
8818 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8819 }
8820
8821 static inline opc_handler_t **ind_table(void *handler)
8822 {
8823 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8824 }
8825
8826 /* Instruction table creation */
8827 /* Opcodes tables creation */
8828 static void fill_new_table(opc_handler_t **table, int len)
8829 {
8830 int i;
8831
8832 for (i = 0; i < len; i++) {
8833 table[i] = &invalid_handler;
8834 }
8835 }
8836
8837 static int create_new_table(opc_handler_t **table, unsigned char idx)
8838 {
8839 opc_handler_t **tmp;
8840
8841 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8842 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8843 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8844
8845 return 0;
8846 }
8847
8848 static int insert_in_table(opc_handler_t **table, unsigned char idx,
8849 opc_handler_t *handler)
8850 {
8851 if (table[idx] != &invalid_handler) {
8852 return -1;
8853 }
8854 table[idx] = handler;
8855
8856 return 0;
8857 }
8858
8859 static int register_direct_insn(opc_handler_t **ppc_opcodes,
8860 unsigned char idx, opc_handler_t *handler)
8861 {
8862 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8863 printf("*** ERROR: opcode %02x already assigned in main "
8864 "opcode table\n", idx);
8865 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8866 printf(" Registered handler '%s' - new handler '%s'\n",
8867 ppc_opcodes[idx]->oname, handler->oname);
8868 #endif
8869 return -1;
8870 }
8871
8872 return 0;
8873 }
8874
8875 static int register_ind_in_table(opc_handler_t **table,
8876 unsigned char idx1, unsigned char idx2,
8877 opc_handler_t *handler)
8878 {
8879 if (table[idx1] == &invalid_handler) {
8880 if (create_new_table(table, idx1) < 0) {
8881 printf("*** ERROR: unable to create indirect table "
8882 "idx=%02x\n", idx1);
8883 return -1;
8884 }
8885 } else {
8886 if (!is_indirect_opcode(table[idx1])) {
8887 printf("*** ERROR: idx %02x already assigned to a direct "
8888 "opcode\n", idx1);
8889 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8890 printf(" Registered handler '%s' - new handler '%s'\n",
8891 ind_table(table[idx1])[idx2]->oname, handler->oname);
8892 #endif
8893 return -1;
8894 }
8895 }
8896 if (handler != NULL &&
8897 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8898 printf("*** ERROR: opcode %02x already assigned in "
8899 "opcode table %02x\n", idx2, idx1);
8900 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8901 printf(" Registered handler '%s' - new handler '%s'\n",
8902 ind_table(table[idx1])[idx2]->oname, handler->oname);
8903 #endif
8904 return -1;
8905 }
8906
8907 return 0;
8908 }
8909
8910 static int register_ind_insn(opc_handler_t **ppc_opcodes,
8911 unsigned char idx1, unsigned char idx2,
8912 opc_handler_t *handler)
8913 {
8914 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8915 }
8916
8917 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
8918 unsigned char idx1, unsigned char idx2,
8919 unsigned char idx3, opc_handler_t *handler)
8920 {
8921 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8922 printf("*** ERROR: unable to join indirect table idx "
8923 "[%02x-%02x]\n", idx1, idx2);
8924 return -1;
8925 }
8926 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8927 handler) < 0) {
8928 printf("*** ERROR: unable to insert opcode "
8929 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8930 return -1;
8931 }
8932
8933 return 0;
8934 }
8935
8936 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
8937 unsigned char idx1, unsigned char idx2,
8938 unsigned char idx3, unsigned char idx4,
8939 opc_handler_t *handler)
8940 {
8941 opc_handler_t **table;
8942
8943 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8944 printf("*** ERROR: unable to join indirect table idx "
8945 "[%02x-%02x]\n", idx1, idx2);
8946 return -1;
8947 }
8948 table = ind_table(ppc_opcodes[idx1]);
8949 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
8950 printf("*** ERROR: unable to join 2nd-level indirect table idx "
8951 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8952 return -1;
8953 }
8954 table = ind_table(table[idx2]);
8955 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
8956 printf("*** ERROR: unable to insert opcode "
8957 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
8958 return -1;
8959 }
8960 return 0;
8961 }
8962 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
8963 {
8964 if (insn->opc2 != 0xFF) {
8965 if (insn->opc3 != 0xFF) {
8966 if (insn->opc4 != 0xFF) {
8967 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8968 insn->opc3, insn->opc4,
8969 &insn->handler) < 0) {
8970 return -1;
8971 }
8972 } else {
8973 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8974 insn->opc3, &insn->handler) < 0) {
8975 return -1;
8976 }
8977 }
8978 } else {
8979 if (register_ind_insn(ppc_opcodes, insn->opc1,
8980 insn->opc2, &insn->handler) < 0) {
8981 return -1;
8982 }
8983 }
8984 } else {
8985 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
8986 return -1;
8987 }
8988 }
8989
8990 return 0;
8991 }
8992
8993 static int test_opcode_table(opc_handler_t **table, int len)
8994 {
8995 int i, count, tmp;
8996
8997 for (i = 0, count = 0; i < len; i++) {
8998 /* Consistency fixup */
8999 if (table[i] == NULL) {
9000 table[i] = &invalid_handler;
9001 }
9002 if (table[i] != &invalid_handler) {
9003 if (is_indirect_opcode(table[i])) {
9004 tmp = test_opcode_table(ind_table(table[i]),
9005 PPC_CPU_INDIRECT_OPCODES_LEN);
9006 if (tmp == 0) {
9007 free(table[i]);
9008 table[i] = &invalid_handler;
9009 } else {
9010 count++;
9011 }
9012 } else {
9013 count++;
9014 }
9015 }
9016 }
9017
9018 return count;
9019 }
9020
9021 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9022 {
9023 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
9024 printf("*** WARNING: no opcode defined !\n");
9025 }
9026 }
9027
9028 /*****************************************************************************/
9029 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9030 {
9031 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9032 opcode_t *opc;
9033
9034 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
9035 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9036 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9037 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9038 if (register_insn(cpu->opcodes, opc) < 0) {
9039 error_setg(errp, "ERROR initializing PowerPC instruction "
9040 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9041 opc->opc3);
9042 return;
9043 }
9044 }
9045 }
9046 fix_opcode_tables(cpu->opcodes);
9047 fflush(stdout);
9048 fflush(stderr);
9049 }
9050
9051 void destroy_ppc_opcodes(PowerPCCPU *cpu)
9052 {
9053 opc_handler_t **table, **table_2;
9054 int i, j, k;
9055
9056 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9057 if (cpu->opcodes[i] == &invalid_handler) {
9058 continue;
9059 }
9060 if (is_indirect_opcode(cpu->opcodes[i])) {
9061 table = ind_table(cpu->opcodes[i]);
9062 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9063 if (table[j] == &invalid_handler) {
9064 continue;
9065 }
9066 if (is_indirect_opcode(table[j])) {
9067 table_2 = ind_table(table[j]);
9068 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
9069 if (table_2[k] != &invalid_handler &&
9070 is_indirect_opcode(table_2[k])) {
9071 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
9072 ~PPC_INDIRECT));
9073 }
9074 }
9075 g_free((opc_handler_t *)((uintptr_t)table[j] &
9076 ~PPC_INDIRECT));
9077 }
9078 }
9079 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
9080 ~PPC_INDIRECT));
9081 }
9082 }
9083 }
9084
9085 #if defined(PPC_DUMP_CPU)
9086 static void dump_ppc_insns(CPUPPCState *env)
9087 {
9088 opc_handler_t **table, *handler;
9089 const char *p, *q;
9090 uint8_t opc1, opc2, opc3, opc4;
9091
9092 printf("Instructions set:\n");
9093 /* opc1 is 6 bits long */
9094 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9095 table = env->opcodes;
9096 handler = table[opc1];
9097 if (is_indirect_opcode(handler)) {
9098 /* opc2 is 5 bits long */
9099 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9100 table = env->opcodes;
9101 handler = env->opcodes[opc1];
9102 table = ind_table(handler);
9103 handler = table[opc2];
9104 if (is_indirect_opcode(handler)) {
9105 table = ind_table(handler);
9106 /* opc3 is 5 bits long */
9107 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9108 opc3++) {
9109 handler = table[opc3];
9110 if (is_indirect_opcode(handler)) {
9111 table = ind_table(handler);
9112 /* opc4 is 5 bits long */
9113 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9114 opc4++) {
9115 handler = table[opc4];
9116 if (handler->handler != &gen_invalid) {
9117 printf("INSN: %02x %02x %02x %02x -- "
9118 "(%02d %04d %02d) : %s\n",
9119 opc1, opc2, opc3, opc4,
9120 opc1, (opc3 << 5) | opc2, opc4,
9121 handler->oname);
9122 }
9123 }
9124 } else {
9125 if (handler->handler != &gen_invalid) {
9126 /* Special hack to properly dump SPE insns */
9127 p = strchr(handler->oname, '_');
9128 if (p == NULL) {
9129 printf("INSN: %02x %02x %02x (%02d %04d) : "
9130 "%s\n",
9131 opc1, opc2, opc3, opc1,
9132 (opc3 << 5) | opc2,
9133 handler->oname);
9134 } else {
9135 q = "speundef";
9136 if ((p - handler->oname) != strlen(q)
9137 || (memcmp(handler->oname, q, strlen(q))
9138 != 0)) {
9139 /* First instruction */
9140 printf("INSN: %02x %02x %02x"
9141 "(%02d %04d) : %.*s\n",
9142 opc1, opc2 << 1, opc3, opc1,
9143 (opc3 << 6) | (opc2 << 1),
9144 (int)(p - handler->oname),
9145 handler->oname);
9146 }
9147 if (strcmp(p + 1, q) != 0) {
9148 /* Second instruction */
9149 printf("INSN: %02x %02x %02x "
9150 "(%02d %04d) : %s\n", opc1,
9151 (opc2 << 1) | 1, opc3, opc1,
9152 (opc3 << 6) | (opc2 << 1) | 1,
9153 p + 1);
9154 }
9155 }
9156 }
9157 }
9158 }
9159 } else {
9160 if (handler->handler != &gen_invalid) {
9161 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9162 opc1, opc2, opc1, opc2, handler->oname);
9163 }
9164 }
9165 }
9166 } else {
9167 if (handler->handler != &gen_invalid) {
9168 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9169 opc1, opc1, handler->oname);
9170 }
9171 }
9172 }
9173 }
9174 #endif
9175 int ppc_fixup_cpu(PowerPCCPU *cpu)
9176 {
9177 CPUPPCState *env = &cpu->env;
9178
9179 /*
9180 * TCG doesn't (yet) emulate some groups of instructions that are
9181 * implemented on some otherwise supported CPUs (e.g. VSX and
9182 * decimal floating point instructions on POWER7). We remove
9183 * unsupported instruction groups from the cpu state's instruction
9184 * masks and hope the guest can cope. For at least the pseries
9185 * machine, the unavailability of these instructions can be
9186 * advertised to the guest via the device tree.
9187 */
9188 if ((env->insns_flags & ~PPC_TCG_INSNS)
9189 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9190 warn_report("Disabling some instructions which are not "
9191 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9192 env->insns_flags & ~PPC_TCG_INSNS,
9193 env->insns_flags2 & ~PPC_TCG_INSNS2);
9194 }
9195 env->insns_flags &= PPC_TCG_INSNS;
9196 env->insns_flags2 &= PPC_TCG_INSNS2;
9197 return 0;
9198 }
9199
9200
9201 void ppc_cpu_dump_statistics(CPUState *cs, int flags)
9202 {
9203 #if defined(DO_PPC_STATISTICS)
9204 PowerPCCPU *cpu = POWERPC_CPU(cs);
9205 opc_handler_t **t1, **t2, **t3, *handler;
9206 int op1, op2, op3;
9207
9208 t1 = cpu->env.opcodes;
9209 for (op1 = 0; op1 < 64; op1++) {
9210 handler = t1[op1];
9211 if (is_indirect_opcode(handler)) {
9212 t2 = ind_table(handler);
9213 for (op2 = 0; op2 < 32; op2++) {
9214 handler = t2[op2];
9215 if (is_indirect_opcode(handler)) {
9216 t3 = ind_table(handler);
9217 for (op3 = 0; op3 < 32; op3++) {
9218 handler = t3[op3];
9219 if (handler->count == 0) {
9220 continue;
9221 }
9222 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
9223 "%016" PRIx64 " %" PRId64 "\n",
9224 op1, op2, op3, op1, (op3 << 5) | op2,
9225 handler->oname,
9226 handler->count, handler->count);
9227 }
9228 } else {
9229 if (handler->count == 0) {
9230 continue;
9231 }
9232 qemu_printf("%02x %02x (%02x %04d) %16s: "
9233 "%016" PRIx64 " %" PRId64 "\n",
9234 op1, op2, op1, op2, handler->oname,
9235 handler->count, handler->count);
9236 }
9237 }
9238 } else {
9239 if (handler->count == 0) {
9240 continue;
9241 }
9242 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
9243 " %" PRId64 "\n",
9244 op1, op1, handler->oname,
9245 handler->count, handler->count);
9246 }
9247 }
9248 #endif
9249 }
9250
9251 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
9252 {
9253 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9254 CPUPPCState *env = cs->env_ptr;
9255 uint32_t hflags = ctx->base.tb->flags;
9256 int bound;
9257
9258 ctx->exception = POWERPC_EXCP_NONE;
9259 ctx->spr_cb = env->spr_cb;
9260 ctx->pr = (hflags >> HFLAGS_PR) & 1;
9261 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
9262 ctx->dr = (hflags >> HFLAGS_DR) & 1;
9263 ctx->hv = (hflags >> HFLAGS_HV) & 1;
9264 ctx->insns_flags = env->insns_flags;
9265 ctx->insns_flags2 = env->insns_flags2;
9266 ctx->access_type = -1;
9267 ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
9268 ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
9269 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
9270 ctx->flags = env->flags;
9271 #if defined(TARGET_PPC64)
9272 ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
9273 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9274 #endif
9275 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
9276 || env->mmu_model == POWERPC_MMU_601
9277 || env->mmu_model & POWERPC_MMU_64;
9278
9279 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
9280 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
9281 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
9282 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
9283 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
9284 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
9285
9286 ctx->singlestep_enabled = 0;
9287 if ((hflags >> HFLAGS_SE) & 1) {
9288 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
9289 }
9290 if ((hflags >> HFLAGS_BE) & 1) {
9291 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
9292 }
9293 if (unlikely(ctx->base.singlestep_enabled)) {
9294 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9295 }
9296
9297 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
9298 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
9299 }
9300
9301 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
9302 {
9303 }
9304
9305 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
9306 {
9307 tcg_gen_insn_start(dcbase->pc_next);
9308 }
9309
9310 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
9311 const CPUBreakpoint *bp)
9312 {
9313 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9314
9315 gen_debug_exception(ctx);
9316 dcbase->is_jmp = DISAS_NORETURN;
9317 /*
9318 * The address covered by the breakpoint must be included in
9319 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
9320 * cleared -- thus we increment the PC here so that the logic
9321 * setting tb->size below does the right thing.
9322 */
9323 ctx->base.pc_next += 4;
9324 return true;
9325 }
9326
9327 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
9328 {
9329 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9330 PowerPCCPU *cpu = POWERPC_CPU(cs);
9331 CPUPPCState *env = cs->env_ptr;
9332 opc_handler_t **table, *handler;
9333
9334 LOG_DISAS("----------------\n");
9335 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9336 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
9337
9338 ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
9339 need_byteswap(ctx));
9340
9341 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
9342 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
9343 opc3(ctx->opcode), opc4(ctx->opcode),
9344 ctx->le_mode ? "little" : "big");
9345 ctx->base.pc_next += 4;
9346 table = cpu->opcodes;
9347 handler = table[opc1(ctx->opcode)];
9348 if (is_indirect_opcode(handler)) {
9349 table = ind_table(handler);
9350 handler = table[opc2(ctx->opcode)];
9351 if (is_indirect_opcode(handler)) {
9352 table = ind_table(handler);
9353 handler = table[opc3(ctx->opcode)];
9354 if (is_indirect_opcode(handler)) {
9355 table = ind_table(handler);
9356 handler = table[opc4(ctx->opcode)];
9357 }
9358 }
9359 }
9360 /* Is opcode *REALLY* valid ? */
9361 if (unlikely(handler->handler == &gen_invalid)) {
9362 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
9363 "%02x - %02x - %02x - %02x (%08x) "
9364 TARGET_FMT_lx " %d\n",
9365 opc1(ctx->opcode), opc2(ctx->opcode),
9366 opc3(ctx->opcode), opc4(ctx->opcode),
9367 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
9368 } else {
9369 uint32_t inval;
9370
9371 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
9372 && Rc(ctx->opcode))) {
9373 inval = handler->inval2;
9374 } else {
9375 inval = handler->inval1;
9376 }
9377
9378 if (unlikely((ctx->opcode & inval) != 0)) {
9379 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
9380 "%02x - %02x - %02x - %02x (%08x) "
9381 TARGET_FMT_lx "\n", ctx->opcode & inval,
9382 opc1(ctx->opcode), opc2(ctx->opcode),
9383 opc3(ctx->opcode), opc4(ctx->opcode),
9384 ctx->opcode, ctx->base.pc_next - 4);
9385 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9386 ctx->base.is_jmp = DISAS_NORETURN;
9387 return;
9388 }
9389 }
9390 (*(handler->handler))(ctx);
9391 #if defined(DO_PPC_STATISTICS)
9392 handler->count++;
9393 #endif
9394 /* Check trace mode exceptions */
9395 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
9396 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
9397 ctx->exception != POWERPC_SYSCALL &&
9398 ctx->exception != POWERPC_EXCP_TRAP &&
9399 ctx->exception != POWERPC_EXCP_BRANCH)) {
9400 uint32_t excp = gen_prep_dbgex(ctx);
9401 gen_exception_nip(ctx, excp, ctx->base.pc_next);
9402 }
9403
9404 if (tcg_check_temp_count()) {
9405 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
9406 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
9407 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
9408 }
9409
9410 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
9411 DISAS_NEXT : DISAS_NORETURN;
9412 }
9413
9414 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
9415 {
9416 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9417
9418 if (ctx->exception == POWERPC_EXCP_NONE) {
9419 gen_goto_tb(ctx, 0, ctx->base.pc_next);
9420 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
9421 if (unlikely(ctx->base.singlestep_enabled)) {
9422 gen_debug_exception(ctx);
9423 }
9424 /* Generate the return instruction */
9425 tcg_gen_exit_tb(NULL, 0);
9426 }
9427 }
9428
9429 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
9430 {
9431 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
9432 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
9433 }
9434
9435 static const TranslatorOps ppc_tr_ops = {
9436 .init_disas_context = ppc_tr_init_disas_context,
9437 .tb_start = ppc_tr_tb_start,
9438 .insn_start = ppc_tr_insn_start,
9439 .breakpoint_check = ppc_tr_breakpoint_check,
9440 .translate_insn = ppc_tr_translate_insn,
9441 .tb_stop = ppc_tr_tb_stop,
9442 .disas_log = ppc_tr_disas_log,
9443 };
9444
9445 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
9446 {
9447 DisasContext ctx;
9448
9449 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
9450 }
9451
9452 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
9453 target_ulong *data)
9454 {
9455 env->nip = data[0];
9456 }
AR7 emulation for QEMU