hw/watchdog/wdt_i6300esb: Convert away from old_mmio
[qemu/ar7.git] / hw / pci-host / sabre.c
blobe2f4ee480e431fb6a459e848d42ec46c4d2201c2
1 /*
2 * QEMU Ultrasparc Sabre PCI host (PBM)
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2012,2013 Artyom Tarasenko
6 * Copyright (c) 2018 Mark Cave-Ayland
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_host.h"
31 #include "hw/pci/pci_bridge.h"
32 #include "hw/pci/pci_bus.h"
33 #include "hw/pci-bridge/simba.h"
34 #include "hw/pci-host/sabre.h"
35 #include "sysemu/sysemu.h"
36 #include "exec/address-spaces.h"
37 #include "qemu/log.h"
38 #include "trace.h"
41 * Chipset docs:
42 * PBM: "UltraSPARC IIi User's Manual",
43 * http://www.sun.com/processors/manuals/805-0087.pdf
46 #define PBM_PCI_IMR_MASK 0x7fffffff
47 #define PBM_PCI_IMR_ENABLED 0x80000000
49 #define POR (1U << 31)
50 #define SOFT_POR (1U << 30)
51 #define SOFT_XIR (1U << 29)
52 #define BTN_POR (1U << 28)
53 #define BTN_XIR (1U << 27)
54 #define RESET_MASK 0xf8000000
55 #define RESET_WCMASK 0x98000000
56 #define RESET_WMASK 0x60000000
58 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
60 static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
62 trace_sabre_set_request(irq_num);
63 s->irq_request = irq_num;
64 qemu_set_irq(s->ivec_irqs[irq_num], 1);
67 static inline void sabre_check_irqs(SabreState *s)
69 unsigned int i;
71 /* Previous request is not acknowledged, resubmit */
72 if (s->irq_request != NO_IRQ_REQUEST) {
73 sabre_set_request(s, s->irq_request);
74 return;
76 /* no request pending */
77 if (s->pci_irq_in == 0ULL) {
78 return;
80 for (i = 0; i < 32; i++) {
81 if (s->pci_irq_in & (1ULL << i)) {
82 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
83 sabre_set_request(s, i);
84 return;
88 for (i = 32; i < 64; i++) {
89 if (s->pci_irq_in & (1ULL << i)) {
90 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
91 sabre_set_request(s, i);
92 break;
98 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
100 trace_sabre_clear_request(irq_num);
101 qemu_set_irq(s->ivec_irqs[irq_num], 0);
102 s->irq_request = NO_IRQ_REQUEST;
105 static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
107 IOMMUState *is = opaque;
109 return &is->iommu_as;
112 static void sabre_config_write(void *opaque, hwaddr addr,
113 uint64_t val, unsigned size)
115 SabreState *s = opaque;
117 trace_sabre_config_write(addr, val);
119 switch (addr & 0xffff) {
120 case 0x30 ... 0x4f: /* DMA error registers */
121 /* XXX: not implemented yet */
122 break;
123 case 0xc00 ... 0xc3f: /* PCI interrupt control */
124 if (addr & 4) {
125 unsigned int ino = (addr & 0x3f) >> 3;
126 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
127 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
128 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
129 sabre_clear_request(s, ino);
131 sabre_check_irqs(s);
133 break;
134 case 0x1000 ... 0x107f: /* OBIO interrupt control */
135 if (addr & 4) {
136 unsigned int ino = ((addr & 0xff) >> 3);
137 s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
138 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
139 if ((s->irq_request == (ino | 0x20))
140 && !(val & ~PBM_PCI_IMR_MASK)) {
141 sabre_clear_request(s, ino | 0x20);
143 sabre_check_irqs(s);
145 break;
146 case 0x1400 ... 0x14ff: /* PCI interrupt clear */
147 if (addr & 4) {
148 unsigned int ino = (addr & 0xff) >> 5;
149 if ((s->irq_request / 4) == ino) {
150 sabre_clear_request(s, s->irq_request);
151 sabre_check_irqs(s);
154 break;
155 case 0x1800 ... 0x1860: /* OBIO interrupt clear */
156 if (addr & 4) {
157 unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
158 if (s->irq_request == ino) {
159 sabre_clear_request(s, ino);
160 sabre_check_irqs(s);
163 break;
164 case 0x2000 ... 0x202f: /* PCI control */
165 s->pci_control[(addr & 0x3f) >> 2] = val;
166 break;
167 case 0xf020 ... 0xf027: /* Reset control */
168 if (addr & 4) {
169 val &= RESET_MASK;
170 s->reset_control &= ~(val & RESET_WCMASK);
171 s->reset_control |= val & RESET_WMASK;
172 if (val & SOFT_POR) {
173 s->nr_resets = 0;
174 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
175 } else if (val & SOFT_XIR) {
176 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
179 break;
180 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
181 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
182 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
183 case 0xf000 ... 0xf01f: /* FFB config, memory control */
184 /* we don't care */
185 default:
186 break;
190 static uint64_t sabre_config_read(void *opaque,
191 hwaddr addr, unsigned size)
193 SabreState *s = opaque;
194 uint32_t val;
196 switch (addr & 0xffff) {
197 case 0x30 ... 0x4f: /* DMA error registers */
198 val = 0;
199 /* XXX: not implemented yet */
200 break;
201 case 0xc00 ... 0xc3f: /* PCI interrupt control */
202 if (addr & 4) {
203 val = s->pci_irq_map[(addr & 0x3f) >> 3];
204 } else {
205 val = 0;
207 break;
208 case 0x1000 ... 0x107f: /* OBIO interrupt control */
209 if (addr & 4) {
210 val = s->obio_irq_map[(addr & 0xff) >> 3];
211 } else {
212 val = 0;
214 break;
215 case 0x1080 ... 0x108f: /* PCI bus error */
216 if (addr & 4) {
217 val = s->pci_err_irq_map[(addr & 0xf) >> 3];
218 } else {
219 val = 0;
221 break;
222 case 0x2000 ... 0x202f: /* PCI control */
223 val = s->pci_control[(addr & 0x3f) >> 2];
224 break;
225 case 0xf020 ... 0xf027: /* Reset control */
226 if (addr & 4) {
227 val = s->reset_control;
228 } else {
229 val = 0;
231 break;
232 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
233 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
234 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
235 case 0xf000 ... 0xf01f: /* FFB config, memory control */
236 /* we don't care */
237 default:
238 val = 0;
239 break;
241 trace_sabre_config_read(addr, val);
243 return val;
246 static const MemoryRegionOps sabre_config_ops = {
247 .read = sabre_config_read,
248 .write = sabre_config_write,
249 .endianness = DEVICE_BIG_ENDIAN,
252 static void sabre_pci_config_write(void *opaque, hwaddr addr,
253 uint64_t val, unsigned size)
255 SabreState *s = opaque;
256 PCIHostState *phb = PCI_HOST_BRIDGE(s);
258 trace_sabre_pci_config_write(addr, val);
259 pci_data_write(phb->bus, addr, val, size);
262 static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
263 unsigned size)
265 uint32_t ret;
266 SabreState *s = opaque;
267 PCIHostState *phb = PCI_HOST_BRIDGE(s);
269 ret = pci_data_read(phb->bus, addr, size);
270 trace_sabre_pci_config_read(addr, ret);
271 return ret;
274 /* The sabre host has an IRQ line for each IRQ line of each slot. */
275 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
277 /* Return the irq as swizzled by the PBM */
278 return irq_num;
281 static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num)
283 /* The on-board devices have fixed (legacy) OBIO intnos */
284 switch (PCI_SLOT(pci_dev->devfn)) {
285 case 1:
286 /* Onboard NIC */
287 return OBIO_NIC_IRQ;
288 case 3:
289 /* Onboard IDE */
290 return OBIO_HDD_IRQ;
291 default:
292 /* Normal intno, fall through */
293 break;
296 return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
299 static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
301 return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
304 static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
306 SabreState *s = opaque;
308 trace_sabre_pci_set_irq(irq_num, level);
310 /* PCI IRQ map onto the first 32 INO. */
311 if (irq_num < 32) {
312 if (level) {
313 s->pci_irq_in |= 1ULL << irq_num;
314 if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
315 sabre_set_request(s, irq_num);
317 } else {
318 s->pci_irq_in &= ~(1ULL << irq_num);
320 } else {
321 /* OBIO IRQ map onto the next 32 INO. */
322 if (level) {
323 trace_sabre_pci_set_obio_irq(irq_num, level);
324 s->pci_irq_in |= 1ULL << irq_num;
325 if ((s->irq_request == NO_IRQ_REQUEST)
326 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
327 sabre_set_request(s, irq_num);
329 } else {
330 s->pci_irq_in &= ~(1ULL << irq_num);
335 static void sabre_reset(DeviceState *d)
337 SabreState *s = SABRE_DEVICE(d);
338 PCIDevice *pci_dev;
339 unsigned int i;
340 uint16_t cmd;
342 for (i = 0; i < 8; i++) {
343 s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
345 for (i = 0; i < 32; i++) {
346 s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
349 s->irq_request = NO_IRQ_REQUEST;
350 s->pci_irq_in = 0ULL;
352 if (s->nr_resets++ == 0) {
353 /* Power on reset */
354 s->reset_control = POR;
357 /* As this is the busA PCI bridge which contains the on-board devices
358 * attached to the ebus, ensure that we initially allow IO transactions
359 * so that we get the early serial console until OpenBIOS can properly
360 * configure the PCI bridge itself */
361 pci_dev = PCI_DEVICE(s->bridgeA);
362 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
363 pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO);
364 pci_bridge_update_mappings(PCI_BRIDGE(pci_dev));
367 static const MemoryRegionOps pci_config_ops = {
368 .read = sabre_pci_config_read,
369 .write = sabre_pci_config_write,
370 .endianness = DEVICE_LITTLE_ENDIAN,
373 static void sabre_realize(DeviceState *dev, Error **errp)
375 SabreState *s = SABRE_DEVICE(dev);
376 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
377 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
378 PCIDevice *pci_dev;
380 /* sabre_config */
381 sysbus_mmio_map(sbd, 0, s->special_base);
382 /* PCI configuration space */
383 sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
384 /* pci_ioport */
385 sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
387 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
388 memory_region_add_subregion(get_system_memory(), s->mem_base,
389 &s->pci_mmio);
391 phb->bus = pci_register_root_bus(dev, "pci",
392 pci_sabre_set_irq, pci_sabre_map_irq, s,
393 &s->pci_mmio,
394 &s->pci_ioport,
395 0, 32, TYPE_PCI_BUS);
397 pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
399 /* IOMMU */
400 memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
401 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
402 pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
404 /* APB secondary busses */
405 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
406 TYPE_SIMBA_PCI_BRIDGE);
407 s->bridgeB = PCI_BRIDGE(pci_dev);
408 pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
409 qdev_init_nofail(&pci_dev->qdev);
411 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
412 TYPE_SIMBA_PCI_BRIDGE);
413 s->bridgeA = PCI_BRIDGE(pci_dev);
414 pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
415 qdev_init_nofail(&pci_dev->qdev);
418 static void sabre_init(Object *obj)
420 SabreState *s = SABRE_DEVICE(obj);
421 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
422 unsigned int i;
424 for (i = 0; i < 8; i++) {
425 s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
427 for (i = 0; i < 2; i++) {
428 s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
430 for (i = 0; i < 32; i++) {
431 s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
433 qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
434 qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
435 s->irq_request = NO_IRQ_REQUEST;
436 s->pci_irq_in = 0ULL;
438 /* IOMMU */
439 object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU,
440 (Object **) &s->iommu,
441 qdev_prop_allow_set_link_before_realize,
442 0, NULL);
444 /* sabre_config */
445 memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
446 "sabre-config", 0x10000);
447 /* at region 0 */
448 sysbus_init_mmio(sbd, &s->sabre_config);
450 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
451 "sabre-pci-config", 0x1000000);
452 /* at region 1 */
453 sysbus_init_mmio(sbd, &s->pci_config);
455 /* pci_ioport */
456 memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
457 0x1000000);
459 /* at region 2 */
460 sysbus_init_mmio(sbd, &s->pci_ioport);
463 static void sabre_pci_realize(PCIDevice *d, Error **errp)
465 pci_set_word(d->config + PCI_COMMAND,
466 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
467 pci_set_word(d->config + PCI_STATUS,
468 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
469 PCI_STATUS_DEVSEL_MEDIUM);
472 static void sabre_pci_class_init(ObjectClass *klass, void *data)
474 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
475 DeviceClass *dc = DEVICE_CLASS(klass);
477 k->realize = sabre_pci_realize;
478 k->vendor_id = PCI_VENDOR_ID_SUN;
479 k->device_id = PCI_DEVICE_ID_SUN_SABRE;
480 k->class_id = PCI_CLASS_BRIDGE_HOST;
482 * PCI-facing part of the host bridge, not usable without the
483 * host-facing part, which can't be device_add'ed, yet.
485 dc->user_creatable = false;
488 static const TypeInfo sabre_pci_info = {
489 .name = TYPE_SABRE_PCI_DEVICE,
490 .parent = TYPE_PCI_DEVICE,
491 .instance_size = sizeof(SabrePCIState),
492 .class_init = sabre_pci_class_init,
493 .interfaces = (InterfaceInfo[]) {
494 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
495 { },
499 static Property sabre_properties[] = {
500 DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
501 DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
502 DEFINE_PROP_END_OF_LIST(),
505 static void sabre_class_init(ObjectClass *klass, void *data)
507 DeviceClass *dc = DEVICE_CLASS(klass);
509 dc->realize = sabre_realize;
510 dc->reset = sabre_reset;
511 dc->props = sabre_properties;
512 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
515 static const TypeInfo sabre_info = {
516 .name = TYPE_SABRE,
517 .parent = TYPE_PCI_HOST_BRIDGE,
518 .instance_size = sizeof(SabreState),
519 .instance_init = sabre_init,
520 .class_init = sabre_class_init,
523 static void sabre_register_types(void)
525 type_register_static(&sabre_info);
526 type_register_static(&sabre_pci_info);
529 type_init(sabre_register_types)