2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011, 2016 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
23 #include "exec/cpu_ldst.h"
24 #include "tcg/tcg-op.h"
25 #include "qemu/compiler.h"
30 * Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
31 * Without assertions, the interpreter runs much faster.
33 #if defined(CONFIG_DEBUG_TCG)
34 # define tci_assert(cond) assert(cond)
36 # define tci_assert(cond) ((void)(cond))
39 __thread
uintptr_t tci_tb_ptr
;
41 static void tci_write_reg64(tcg_target_ulong
*regs
, uint32_t high_index
,
42 uint32_t low_index
, uint64_t value
)
44 regs
[low_index
] = value
;
45 regs
[high_index
] = value
>> 32;
48 /* Create a 64 bit value from two 32 bit values. */
49 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
51 return ((uint64_t)high
<< 32) + low
;
55 * Load sets of arguments all at once. The naming convention is:
56 * tci_args_<arguments>
57 * where arguments is a sequence of
59 * b = immediate (bit position)
60 * c = condition (TCGCond)
61 * i = immediate (uint32_t)
62 * I = immediate (tcg_target_ulong)
63 * l = label or pointer
64 * m = immediate (TCGMemOpIdx)
65 * n = immediate (call return length)
67 * s = signed ldst offset
70 static void tci_args_l(uint32_t insn
, const void *tb_ptr
, void **l0
)
72 int diff
= sextract32(insn
, 12, 20);
73 *l0
= diff
? (void *)tb_ptr
+ diff
: NULL
;
76 static void tci_args_r(uint32_t insn
, TCGReg
*r0
)
78 *r0
= extract32(insn
, 8, 4);
81 static void tci_args_nl(uint32_t insn
, const void *tb_ptr
,
82 uint8_t *n0
, void **l1
)
84 *n0
= extract32(insn
, 8, 4);
85 *l1
= sextract32(insn
, 12, 20) + (void *)tb_ptr
;
88 static void tci_args_rl(uint32_t insn
, const void *tb_ptr
,
89 TCGReg
*r0
, void **l1
)
91 *r0
= extract32(insn
, 8, 4);
92 *l1
= sextract32(insn
, 12, 20) + (void *)tb_ptr
;
95 static void tci_args_rr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
)
97 *r0
= extract32(insn
, 8, 4);
98 *r1
= extract32(insn
, 12, 4);
101 static void tci_args_ri(uint32_t insn
, TCGReg
*r0
, tcg_target_ulong
*i1
)
103 *r0
= extract32(insn
, 8, 4);
104 *i1
= sextract32(insn
, 12, 20);
107 static void tci_args_rrm(uint32_t insn
, TCGReg
*r0
,
108 TCGReg
*r1
, TCGMemOpIdx
*m2
)
110 *r0
= extract32(insn
, 8, 4);
111 *r1
= extract32(insn
, 12, 4);
112 *m2
= extract32(insn
, 20, 12);
115 static void tci_args_rrr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
)
117 *r0
= extract32(insn
, 8, 4);
118 *r1
= extract32(insn
, 12, 4);
119 *r2
= extract32(insn
, 16, 4);
122 static void tci_args_rrs(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
, int32_t *i2
)
124 *r0
= extract32(insn
, 8, 4);
125 *r1
= extract32(insn
, 12, 4);
126 *i2
= sextract32(insn
, 16, 16);
129 static void tci_args_rrrc(uint32_t insn
,
130 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGCond
*c3
)
132 *r0
= extract32(insn
, 8, 4);
133 *r1
= extract32(insn
, 12, 4);
134 *r2
= extract32(insn
, 16, 4);
135 *c3
= extract32(insn
, 20, 4);
138 static void tci_args_rrrm(uint32_t insn
,
139 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGMemOpIdx
*m3
)
141 *r0
= extract32(insn
, 8, 4);
142 *r1
= extract32(insn
, 12, 4);
143 *r2
= extract32(insn
, 16, 4);
144 *m3
= extract32(insn
, 20, 12);
147 static void tci_args_rrrbb(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
148 TCGReg
*r2
, uint8_t *i3
, uint8_t *i4
)
150 *r0
= extract32(insn
, 8, 4);
151 *r1
= extract32(insn
, 12, 4);
152 *r2
= extract32(insn
, 16, 4);
153 *i3
= extract32(insn
, 20, 6);
154 *i4
= extract32(insn
, 26, 6);
157 static void tci_args_rrrrr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
158 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
)
160 *r0
= extract32(insn
, 8, 4);
161 *r1
= extract32(insn
, 12, 4);
162 *r2
= extract32(insn
, 16, 4);
163 *r3
= extract32(insn
, 20, 4);
164 *r4
= extract32(insn
, 24, 4);
167 #if TCG_TARGET_REG_BITS == 32
168 static void tci_args_rrrr(uint32_t insn
,
169 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGReg
*r3
)
171 *r0
= extract32(insn
, 8, 4);
172 *r1
= extract32(insn
, 12, 4);
173 *r2
= extract32(insn
, 16, 4);
174 *r3
= extract32(insn
, 20, 4);
178 static void tci_args_rrrrrc(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
179 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
, TCGCond
*c5
)
181 *r0
= extract32(insn
, 8, 4);
182 *r1
= extract32(insn
, 12, 4);
183 *r2
= extract32(insn
, 16, 4);
184 *r3
= extract32(insn
, 20, 4);
185 *r4
= extract32(insn
, 24, 4);
186 *c5
= extract32(insn
, 28, 4);
189 #if TCG_TARGET_REG_BITS == 32
190 static void tci_args_rrrrrr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
191 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
, TCGReg
*r5
)
193 *r0
= extract32(insn
, 8, 4);
194 *r1
= extract32(insn
, 12, 4);
195 *r2
= extract32(insn
, 16, 4);
196 *r3
= extract32(insn
, 20, 4);
197 *r4
= extract32(insn
, 24, 4);
198 *r5
= extract32(insn
, 28, 4);
202 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
239 g_assert_not_reached();
244 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
281 g_assert_not_reached();
287 cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
288 #define qemu_ld_leuw \
289 cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
290 #define qemu_ld_leul \
291 cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
292 #define qemu_ld_leq \
293 cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
294 #define qemu_ld_beuw \
295 cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
296 #define qemu_ld_beul \
297 cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
298 #define qemu_ld_beq \
299 cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
300 #define qemu_st_b(X) \
301 cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
302 #define qemu_st_lew(X) \
303 cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
304 #define qemu_st_lel(X) \
305 cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
306 #define qemu_st_leq(X) \
307 cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
308 #define qemu_st_bew(X) \
309 cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
310 #define qemu_st_bel(X) \
311 cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
312 #define qemu_st_beq(X) \
313 cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
315 #if TCG_TARGET_REG_BITS == 64
316 # define CASE_32_64(x) \
317 case glue(glue(INDEX_op_, x), _i64): \
318 case glue(glue(INDEX_op_, x), _i32):
319 # define CASE_64(x) \
320 case glue(glue(INDEX_op_, x), _i64):
322 # define CASE_32_64(x) \
323 case glue(glue(INDEX_op_, x), _i32):
327 /* Interpret pseudo code in tb. */
329 * Disable CFI checks.
330 * One possible operation in the pseudo code is a call to binary code.
331 * Therefore, disable CFI checks in the interpreter function
333 uintptr_t QEMU_DISABLE_CFI
tcg_qemu_tb_exec(CPUArchState
*env
,
334 const void *v_tb_ptr
)
336 const uint32_t *tb_ptr
= v_tb_ptr
;
337 tcg_target_ulong regs
[TCG_TARGET_NB_REGS
];
338 uint64_t stack
[(TCG_STATIC_CALL_ARGS_SIZE
+ TCG_STATIC_FRAME_SIZE
)
340 void *call_slots
[TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(uint64_t)];
342 regs
[TCG_AREG0
] = (tcg_target_ulong
)env
;
343 regs
[TCG_REG_CALL_STACK
] = (uintptr_t)stack
;
344 /* Other call_slots entries initialized at first use (see below). */
345 call_slots
[0] = NULL
;
351 TCGReg r0
, r1
, r2
, r3
, r4
;
358 #if TCG_TARGET_REG_BITS == 32
367 opc
= extract32(insn
, 0, 8);
372 * Set up the ffi_avalue array once, delayed until now
373 * because many TB's do not make any calls. In tcg_gen_callN,
374 * we arranged for every real argument to be "left-aligned"
375 * in each 64-bit slot.
377 if (unlikely(call_slots
[0] == NULL
)) {
378 for (int i
= 0; i
< ARRAY_SIZE(call_slots
); ++i
) {
379 call_slots
[i
] = &stack
[i
];
383 tci_args_nl(insn
, tb_ptr
, &len
, &ptr
);
385 /* Helper functions may need to access the "return address" */
386 tci_tb_ptr
= (uintptr_t)tb_ptr
;
390 ffi_call(pptr
[1], pptr
[0], stack
, call_slots
);
393 /* Any result winds up "left-aligned" in the stack[0] slot. */
397 case 1: /* uint32_t */
399 * Note that libffi has an odd special case in that it will
400 * always widen an integral result to ffi_arg.
402 if (sizeof(ffi_arg
) == 4) {
403 regs
[TCG_REG_R0
] = *(uint32_t *)stack
;
407 case 2: /* uint64_t */
408 if (TCG_TARGET_REG_BITS
== 32) {
409 tci_write_reg64(regs
, TCG_REG_R1
, TCG_REG_R0
, stack
[0]);
411 regs
[TCG_REG_R0
] = stack
[0];
415 g_assert_not_reached();
420 tci_args_l(insn
, tb_ptr
, &ptr
);
423 case INDEX_op_setcond_i32
:
424 tci_args_rrrc(insn
, &r0
, &r1
, &r2
, &condition
);
425 regs
[r0
] = tci_compare32(regs
[r1
], regs
[r2
], condition
);
427 case INDEX_op_movcond_i32
:
428 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
429 tmp32
= tci_compare32(regs
[r1
], regs
[r2
], condition
);
430 regs
[r0
] = regs
[tmp32
? r3
: r4
];
432 #if TCG_TARGET_REG_BITS == 32
433 case INDEX_op_setcond2_i32
:
434 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
435 T1
= tci_uint64(regs
[r2
], regs
[r1
]);
436 T2
= tci_uint64(regs
[r4
], regs
[r3
]);
437 regs
[r0
] = tci_compare64(T1
, T2
, condition
);
439 #elif TCG_TARGET_REG_BITS == 64
440 case INDEX_op_setcond_i64
:
441 tci_args_rrrc(insn
, &r0
, &r1
, &r2
, &condition
);
442 regs
[r0
] = tci_compare64(regs
[r1
], regs
[r2
], condition
);
444 case INDEX_op_movcond_i64
:
445 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
446 tmp32
= tci_compare64(regs
[r1
], regs
[r2
], condition
);
447 regs
[r0
] = regs
[tmp32
? r3
: r4
];
451 tci_args_rr(insn
, &r0
, &r1
);
454 case INDEX_op_tci_movi
:
455 tci_args_ri(insn
, &r0
, &t1
);
458 case INDEX_op_tci_movl
:
459 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
460 regs
[r0
] = *(tcg_target_ulong
*)ptr
;
463 /* Load/store operations (32 bit). */
466 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
467 ptr
= (void *)(regs
[r1
] + ofs
);
468 regs
[r0
] = *(uint8_t *)ptr
;
471 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
472 ptr
= (void *)(regs
[r1
] + ofs
);
473 regs
[r0
] = *(int8_t *)ptr
;
476 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
477 ptr
= (void *)(regs
[r1
] + ofs
);
478 regs
[r0
] = *(uint16_t *)ptr
;
481 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
482 ptr
= (void *)(regs
[r1
] + ofs
);
483 regs
[r0
] = *(int16_t *)ptr
;
485 case INDEX_op_ld_i32
:
487 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
488 ptr
= (void *)(regs
[r1
] + ofs
);
489 regs
[r0
] = *(uint32_t *)ptr
;
492 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
493 ptr
= (void *)(regs
[r1
] + ofs
);
494 *(uint8_t *)ptr
= regs
[r0
];
497 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
498 ptr
= (void *)(regs
[r1
] + ofs
);
499 *(uint16_t *)ptr
= regs
[r0
];
501 case INDEX_op_st_i32
:
503 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
504 ptr
= (void *)(regs
[r1
] + ofs
);
505 *(uint32_t *)ptr
= regs
[r0
];
508 /* Arithmetic operations (mixed 32/64 bit). */
511 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
512 regs
[r0
] = regs
[r1
] + regs
[r2
];
515 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
516 regs
[r0
] = regs
[r1
] - regs
[r2
];
519 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
520 regs
[r0
] = regs
[r1
] * regs
[r2
];
523 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
524 regs
[r0
] = regs
[r1
] & regs
[r2
];
527 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
528 regs
[r0
] = regs
[r1
] | regs
[r2
];
531 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
532 regs
[r0
] = regs
[r1
] ^ regs
[r2
];
534 #if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
536 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
537 regs
[r0
] = regs
[r1
] & ~regs
[r2
];
540 #if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
542 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
543 regs
[r0
] = regs
[r1
] | ~regs
[r2
];
546 #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
548 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
549 regs
[r0
] = ~(regs
[r1
] ^ regs
[r2
]);
552 #if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
554 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
555 regs
[r0
] = ~(regs
[r1
] & regs
[r2
]);
558 #if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
560 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
561 regs
[r0
] = ~(regs
[r1
] | regs
[r2
]);
565 /* Arithmetic operations (32 bit). */
567 case INDEX_op_div_i32
:
568 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
569 regs
[r0
] = (int32_t)regs
[r1
] / (int32_t)regs
[r2
];
571 case INDEX_op_divu_i32
:
572 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
573 regs
[r0
] = (uint32_t)regs
[r1
] / (uint32_t)regs
[r2
];
575 case INDEX_op_rem_i32
:
576 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
577 regs
[r0
] = (int32_t)regs
[r1
] % (int32_t)regs
[r2
];
579 case INDEX_op_remu_i32
:
580 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
581 regs
[r0
] = (uint32_t)regs
[r1
] % (uint32_t)regs
[r2
];
584 /* Shift/rotate operations (32 bit). */
586 case INDEX_op_shl_i32
:
587 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
588 regs
[r0
] = (uint32_t)regs
[r1
] << (regs
[r2
] & 31);
590 case INDEX_op_shr_i32
:
591 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
592 regs
[r0
] = (uint32_t)regs
[r1
] >> (regs
[r2
] & 31);
594 case INDEX_op_sar_i32
:
595 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
596 regs
[r0
] = (int32_t)regs
[r1
] >> (regs
[r2
] & 31);
598 #if TCG_TARGET_HAS_rot_i32
599 case INDEX_op_rotl_i32
:
600 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
601 regs
[r0
] = rol32(regs
[r1
], regs
[r2
] & 31);
603 case INDEX_op_rotr_i32
:
604 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
605 regs
[r0
] = ror32(regs
[r1
], regs
[r2
] & 31);
608 #if TCG_TARGET_HAS_deposit_i32
609 case INDEX_op_deposit_i32
:
610 tci_args_rrrbb(insn
, &r0
, &r1
, &r2
, &pos
, &len
);
611 regs
[r0
] = deposit32(regs
[r1
], pos
, len
, regs
[r2
]);
614 case INDEX_op_brcond_i32
:
615 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
616 if ((uint32_t)regs
[r0
]) {
620 #if TCG_TARGET_REG_BITS == 32
621 case INDEX_op_add2_i32
:
622 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
623 T1
= tci_uint64(regs
[r3
], regs
[r2
]);
624 T2
= tci_uint64(regs
[r5
], regs
[r4
]);
625 tci_write_reg64(regs
, r1
, r0
, T1
+ T2
);
627 case INDEX_op_sub2_i32
:
628 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
629 T1
= tci_uint64(regs
[r3
], regs
[r2
]);
630 T2
= tci_uint64(regs
[r5
], regs
[r4
]);
631 tci_write_reg64(regs
, r1
, r0
, T1
- T2
);
633 case INDEX_op_mulu2_i32
:
634 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
635 tci_write_reg64(regs
, r1
, r0
, (uint64_t)regs
[r2
] * regs
[r3
]);
637 #endif /* TCG_TARGET_REG_BITS == 32 */
638 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
640 tci_args_rr(insn
, &r0
, &r1
);
641 regs
[r0
] = (int8_t)regs
[r1
];
644 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
646 tci_args_rr(insn
, &r0
, &r1
);
647 regs
[r0
] = (int16_t)regs
[r1
];
650 #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
652 tci_args_rr(insn
, &r0
, &r1
);
653 regs
[r0
] = (uint8_t)regs
[r1
];
656 #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
658 tci_args_rr(insn
, &r0
, &r1
);
659 regs
[r0
] = (uint16_t)regs
[r1
];
662 #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
664 tci_args_rr(insn
, &r0
, &r1
);
665 regs
[r0
] = bswap16(regs
[r1
]);
668 #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
670 tci_args_rr(insn
, &r0
, &r1
);
671 regs
[r0
] = bswap32(regs
[r1
]);
674 #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
676 tci_args_rr(insn
, &r0
, &r1
);
677 regs
[r0
] = ~regs
[r1
];
680 #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
682 tci_args_rr(insn
, &r0
, &r1
);
683 regs
[r0
] = -regs
[r1
];
686 #if TCG_TARGET_REG_BITS == 64
687 /* Load/store operations (64 bit). */
689 case INDEX_op_ld32s_i64
:
690 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
691 ptr
= (void *)(regs
[r1
] + ofs
);
692 regs
[r0
] = *(int32_t *)ptr
;
694 case INDEX_op_ld_i64
:
695 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
696 ptr
= (void *)(regs
[r1
] + ofs
);
697 regs
[r0
] = *(uint64_t *)ptr
;
699 case INDEX_op_st_i64
:
700 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
701 ptr
= (void *)(regs
[r1
] + ofs
);
702 *(uint64_t *)ptr
= regs
[r0
];
705 /* Arithmetic operations (64 bit). */
707 case INDEX_op_div_i64
:
708 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
709 regs
[r0
] = (int64_t)regs
[r1
] / (int64_t)regs
[r2
];
711 case INDEX_op_divu_i64
:
712 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
713 regs
[r0
] = (uint64_t)regs
[r1
] / (uint64_t)regs
[r2
];
715 case INDEX_op_rem_i64
:
716 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
717 regs
[r0
] = (int64_t)regs
[r1
] % (int64_t)regs
[r2
];
719 case INDEX_op_remu_i64
:
720 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
721 regs
[r0
] = (uint64_t)regs
[r1
] % (uint64_t)regs
[r2
];
724 /* Shift/rotate operations (64 bit). */
726 case INDEX_op_shl_i64
:
727 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
728 regs
[r0
] = regs
[r1
] << (regs
[r2
] & 63);
730 case INDEX_op_shr_i64
:
731 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
732 regs
[r0
] = regs
[r1
] >> (regs
[r2
] & 63);
734 case INDEX_op_sar_i64
:
735 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
736 regs
[r0
] = (int64_t)regs
[r1
] >> (regs
[r2
] & 63);
738 #if TCG_TARGET_HAS_rot_i64
739 case INDEX_op_rotl_i64
:
740 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
741 regs
[r0
] = rol64(regs
[r1
], regs
[r2
] & 63);
743 case INDEX_op_rotr_i64
:
744 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
745 regs
[r0
] = ror64(regs
[r1
], regs
[r2
] & 63);
748 #if TCG_TARGET_HAS_deposit_i64
749 case INDEX_op_deposit_i64
:
750 tci_args_rrrbb(insn
, &r0
, &r1
, &r2
, &pos
, &len
);
751 regs
[r0
] = deposit64(regs
[r1
], pos
, len
, regs
[r2
]);
754 case INDEX_op_brcond_i64
:
755 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
760 case INDEX_op_ext32s_i64
:
761 case INDEX_op_ext_i32_i64
:
762 tci_args_rr(insn
, &r0
, &r1
);
763 regs
[r0
] = (int32_t)regs
[r1
];
765 case INDEX_op_ext32u_i64
:
766 case INDEX_op_extu_i32_i64
:
767 tci_args_rr(insn
, &r0
, &r1
);
768 regs
[r0
] = (uint32_t)regs
[r1
];
770 #if TCG_TARGET_HAS_bswap64_i64
771 case INDEX_op_bswap64_i64
:
772 tci_args_rr(insn
, &r0
, &r1
);
773 regs
[r0
] = bswap64(regs
[r1
]);
776 #endif /* TCG_TARGET_REG_BITS == 64 */
778 /* QEMU specific operations. */
780 case INDEX_op_exit_tb
:
781 tci_args_l(insn
, tb_ptr
, &ptr
);
782 return (uintptr_t)ptr
;
784 case INDEX_op_goto_tb
:
785 tci_args_l(insn
, tb_ptr
, &ptr
);
786 tb_ptr
= *(void **)ptr
;
789 case INDEX_op_goto_ptr
:
790 tci_args_r(insn
, &r0
);
791 ptr
= (void *)regs
[r0
];
798 case INDEX_op_qemu_ld_i32
:
799 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
800 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
803 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
804 taddr
= tci_uint64(regs
[r2
], regs
[r1
]);
806 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
811 tmp32
= (int8_t)qemu_ld_ub
;
814 tmp32
= qemu_ld_leuw
;
817 tmp32
= (int16_t)qemu_ld_leuw
;
820 tmp32
= qemu_ld_leul
;
823 tmp32
= qemu_ld_beuw
;
826 tmp32
= (int16_t)qemu_ld_beuw
;
829 tmp32
= qemu_ld_beul
;
832 g_assert_not_reached();
837 case INDEX_op_qemu_ld_i64
:
838 if (TCG_TARGET_REG_BITS
== 64) {
839 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
841 } else if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
842 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
845 tci_args_rrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
);
846 taddr
= tci_uint64(regs
[r3
], regs
[r2
]);
849 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
854 tmp64
= (int8_t)qemu_ld_ub
;
857 tmp64
= qemu_ld_leuw
;
860 tmp64
= (int16_t)qemu_ld_leuw
;
863 tmp64
= qemu_ld_leul
;
866 tmp64
= (int32_t)qemu_ld_leul
;
872 tmp64
= qemu_ld_beuw
;
875 tmp64
= (int16_t)qemu_ld_beuw
;
878 tmp64
= qemu_ld_beul
;
881 tmp64
= (int32_t)qemu_ld_beul
;
887 g_assert_not_reached();
889 if (TCG_TARGET_REG_BITS
== 32) {
890 tci_write_reg64(regs
, r1
, r0
, tmp64
);
896 case INDEX_op_qemu_st_i32
:
897 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
898 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
901 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
902 taddr
= tci_uint64(regs
[r2
], regs
[r1
]);
905 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
922 g_assert_not_reached();
926 case INDEX_op_qemu_st_i64
:
927 if (TCG_TARGET_REG_BITS
== 64) {
928 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
932 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
933 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
936 tci_args_rrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
);
937 taddr
= tci_uint64(regs
[r3
], regs
[r2
]);
940 tmp64
= tci_uint64(regs
[r1
], regs
[r0
]);
942 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
965 g_assert_not_reached();
970 /* Ensure ordering for all kinds */
974 g_assert_not_reached();
980 * Disassembler that matches the interpreter
983 static const char *str_r(TCGReg r
)
985 static const char regs
[TCG_TARGET_NB_REGS
][4] = {
986 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
987 "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
990 QEMU_BUILD_BUG_ON(TCG_AREG0
!= TCG_REG_R14
);
991 QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK
!= TCG_REG_R15
);
993 assert((unsigned)r
< TCG_TARGET_NB_REGS
);
997 static const char *str_c(TCGCond c
)
999 static const char cond
[16][8] = {
1000 [TCG_COND_NEVER
] = "never",
1001 [TCG_COND_ALWAYS
] = "always",
1002 [TCG_COND_EQ
] = "eq",
1003 [TCG_COND_NE
] = "ne",
1004 [TCG_COND_LT
] = "lt",
1005 [TCG_COND_GE
] = "ge",
1006 [TCG_COND_LE
] = "le",
1007 [TCG_COND_GT
] = "gt",
1008 [TCG_COND_LTU
] = "ltu",
1009 [TCG_COND_GEU
] = "geu",
1010 [TCG_COND_LEU
] = "leu",
1011 [TCG_COND_GTU
] = "gtu",
1014 assert((unsigned)c
< ARRAY_SIZE(cond
));
1015 assert(cond
[c
][0] != 0);
1019 /* Disassemble TCI bytecode. */
1020 int print_insn_tci(bfd_vma addr
, disassemble_info
*info
)
1022 const uint32_t *tb_ptr
= (const void *)(uintptr_t)addr
;
1023 const TCGOpDef
*def
;
1024 const char *op_name
;
1027 TCGReg r0
, r1
, r2
, r3
, r4
;
1028 #if TCG_TARGET_REG_BITS == 32
1031 tcg_target_ulong i1
;
1038 /* TCI is always the host, so we don't need to load indirect. */
1041 info
->fprintf_func(info
->stream
, "%08x ", insn
);
1043 op
= extract32(insn
, 0, 8);
1044 def
= &tcg_op_defs
[op
];
1045 op_name
= def
->name
;
1049 case INDEX_op_exit_tb
:
1050 case INDEX_op_goto_tb
:
1051 tci_args_l(insn
, tb_ptr
, &ptr
);
1052 info
->fprintf_func(info
->stream
, "%-12s %p", op_name
, ptr
);
1055 case INDEX_op_goto_ptr
:
1056 tci_args_r(insn
, &r0
);
1057 info
->fprintf_func(info
->stream
, "%-12s %s", op_name
, str_r(r0
));
1061 tci_args_nl(insn
, tb_ptr
, &len
, &ptr
);
1062 info
->fprintf_func(info
->stream
, "%-12s %d, %p", op_name
, len
, ptr
);
1065 case INDEX_op_brcond_i32
:
1066 case INDEX_op_brcond_i64
:
1067 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
1068 info
->fprintf_func(info
->stream
, "%-12s %s, 0, ne, %p",
1069 op_name
, str_r(r0
), ptr
);
1072 case INDEX_op_setcond_i32
:
1073 case INDEX_op_setcond_i64
:
1074 tci_args_rrrc(insn
, &r0
, &r1
, &r2
, &c
);
1075 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s",
1076 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), str_c(c
));
1079 case INDEX_op_tci_movi
:
1080 tci_args_ri(insn
, &r0
, &i1
);
1081 info
->fprintf_func(info
->stream
, "%-12s %s, 0x%" TCG_PRIlx
,
1082 op_name
, str_r(r0
), i1
);
1085 case INDEX_op_tci_movl
:
1086 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
1087 info
->fprintf_func(info
->stream
, "%-12s %s, %p",
1088 op_name
, str_r(r0
), ptr
);
1091 case INDEX_op_ld8u_i32
:
1092 case INDEX_op_ld8u_i64
:
1093 case INDEX_op_ld8s_i32
:
1094 case INDEX_op_ld8s_i64
:
1095 case INDEX_op_ld16u_i32
:
1096 case INDEX_op_ld16u_i64
:
1097 case INDEX_op_ld16s_i32
:
1098 case INDEX_op_ld16s_i64
:
1099 case INDEX_op_ld32u_i64
:
1100 case INDEX_op_ld32s_i64
:
1101 case INDEX_op_ld_i32
:
1102 case INDEX_op_ld_i64
:
1103 case INDEX_op_st8_i32
:
1104 case INDEX_op_st8_i64
:
1105 case INDEX_op_st16_i32
:
1106 case INDEX_op_st16_i64
:
1107 case INDEX_op_st32_i64
:
1108 case INDEX_op_st_i32
:
1109 case INDEX_op_st_i64
:
1110 tci_args_rrs(insn
, &r0
, &r1
, &s2
);
1111 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %d",
1112 op_name
, str_r(r0
), str_r(r1
), s2
);
1115 case INDEX_op_mov_i32
:
1116 case INDEX_op_mov_i64
:
1117 case INDEX_op_ext8s_i32
:
1118 case INDEX_op_ext8s_i64
:
1119 case INDEX_op_ext8u_i32
:
1120 case INDEX_op_ext8u_i64
:
1121 case INDEX_op_ext16s_i32
:
1122 case INDEX_op_ext16s_i64
:
1123 case INDEX_op_ext16u_i32
:
1124 case INDEX_op_ext32s_i64
:
1125 case INDEX_op_ext32u_i64
:
1126 case INDEX_op_ext_i32_i64
:
1127 case INDEX_op_extu_i32_i64
:
1128 case INDEX_op_bswap16_i32
:
1129 case INDEX_op_bswap16_i64
:
1130 case INDEX_op_bswap32_i32
:
1131 case INDEX_op_bswap32_i64
:
1132 case INDEX_op_bswap64_i64
:
1133 case INDEX_op_not_i32
:
1134 case INDEX_op_not_i64
:
1135 case INDEX_op_neg_i32
:
1136 case INDEX_op_neg_i64
:
1137 tci_args_rr(insn
, &r0
, &r1
);
1138 info
->fprintf_func(info
->stream
, "%-12s %s, %s",
1139 op_name
, str_r(r0
), str_r(r1
));
1142 case INDEX_op_add_i32
:
1143 case INDEX_op_add_i64
:
1144 case INDEX_op_sub_i32
:
1145 case INDEX_op_sub_i64
:
1146 case INDEX_op_mul_i32
:
1147 case INDEX_op_mul_i64
:
1148 case INDEX_op_and_i32
:
1149 case INDEX_op_and_i64
:
1150 case INDEX_op_or_i32
:
1151 case INDEX_op_or_i64
:
1152 case INDEX_op_xor_i32
:
1153 case INDEX_op_xor_i64
:
1154 case INDEX_op_andc_i32
:
1155 case INDEX_op_andc_i64
:
1156 case INDEX_op_orc_i32
:
1157 case INDEX_op_orc_i64
:
1158 case INDEX_op_eqv_i32
:
1159 case INDEX_op_eqv_i64
:
1160 case INDEX_op_nand_i32
:
1161 case INDEX_op_nand_i64
:
1162 case INDEX_op_nor_i32
:
1163 case INDEX_op_nor_i64
:
1164 case INDEX_op_div_i32
:
1165 case INDEX_op_div_i64
:
1166 case INDEX_op_rem_i32
:
1167 case INDEX_op_rem_i64
:
1168 case INDEX_op_divu_i32
:
1169 case INDEX_op_divu_i64
:
1170 case INDEX_op_remu_i32
:
1171 case INDEX_op_remu_i64
:
1172 case INDEX_op_shl_i32
:
1173 case INDEX_op_shl_i64
:
1174 case INDEX_op_shr_i32
:
1175 case INDEX_op_shr_i64
:
1176 case INDEX_op_sar_i32
:
1177 case INDEX_op_sar_i64
:
1178 case INDEX_op_rotl_i32
:
1179 case INDEX_op_rotl_i64
:
1180 case INDEX_op_rotr_i32
:
1181 case INDEX_op_rotr_i64
:
1182 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
1183 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s",
1184 op_name
, str_r(r0
), str_r(r1
), str_r(r2
));
1187 case INDEX_op_deposit_i32
:
1188 case INDEX_op_deposit_i64
:
1189 tci_args_rrrbb(insn
, &r0
, &r1
, &r2
, &pos
, &len
);
1190 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %d, %d",
1191 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), pos
, len
);
1194 case INDEX_op_movcond_i32
:
1195 case INDEX_op_movcond_i64
:
1196 case INDEX_op_setcond2_i32
:
1197 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &c
);
1198 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %s",
1199 op_name
, str_r(r0
), str_r(r1
), str_r(r2
),
1200 str_r(r3
), str_r(r4
), str_c(c
));
1203 #if TCG_TARGET_REG_BITS == 32
1204 case INDEX_op_mulu2_i32
:
1205 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
1206 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s",
1207 op_name
, str_r(r0
), str_r(r1
),
1208 str_r(r2
), str_r(r3
));
1211 case INDEX_op_add2_i32
:
1212 case INDEX_op_sub2_i32
:
1213 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
1214 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %s",
1215 op_name
, str_r(r0
), str_r(r1
), str_r(r2
),
1216 str_r(r3
), str_r(r4
), str_r(r5
));
1220 case INDEX_op_qemu_ld_i64
:
1221 case INDEX_op_qemu_st_i64
:
1222 len
= DIV_ROUND_UP(64, TCG_TARGET_REG_BITS
);
1224 case INDEX_op_qemu_ld_i32
:
1225 case INDEX_op_qemu_st_i32
:
1228 len
+= DIV_ROUND_UP(TARGET_LONG_BITS
, TCG_TARGET_REG_BITS
);
1231 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
1232 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %x",
1233 op_name
, str_r(r0
), str_r(r1
), oi
);
1236 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
1237 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %x",
1238 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), oi
);
1241 tci_args_rrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
);
1242 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s",
1243 op_name
, str_r(r0
), str_r(r1
),
1244 str_r(r2
), str_r(r3
), str_r(r4
));
1247 g_assert_not_reached();
1252 /* tcg_out_nop_fill uses zeros */
1254 info
->fprintf_func(info
->stream
, "align");
1260 info
->fprintf_func(info
->stream
, "illegal opcode %d", op
);
1264 return sizeof(insn
);