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ppc: Fix emulated INFINITY and NAN conversions
[qemu/ar7.git] / target / ppc / fpu_helper.c
blob52bcda27a62d4ade6b775443e435e5b3a90d8283
1 /*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "internal.h"
24 #include "fpu/softfloat.h"
25
26 static inline float128 float128_snan_to_qnan(float128 x)
27 {
28 float128 r;
29
30 r.high = x.high | 0x0000800000000000;
31 r.low = x.low;
32 return r;
33 }
34
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
38
39 static inline bool fp_exceptions_enabled(CPUPPCState *env)
40 {
41 #ifdef CONFIG_USER_ONLY
42 return true;
43 #else
44 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
45 #endif
46 }
47
48 /*****************************************************************************/
49 /* Floating point operations helpers */
50
51 /*
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
54 */
55 uint64_t helper_todouble(uint32_t arg)
56 {
57 uint32_t abs_arg = arg & 0x7fffffff;
58 uint64_t ret;
59
60 if (likely(abs_arg >= 0x00800000)) {
61 if (unlikely(extract32(arg, 23, 8) == 0xff)) {
62 /* Inf or NAN. */
63 ret = (uint64_t)extract32(arg, 31, 1) << 63;
64 ret |= (uint64_t)0x7ff << 52;
65 ret |= (uint64_t)extract32(arg, 0, 23) << 29;
66 } else {
67 /* Normalized operand. */
68 ret = (uint64_t)extract32(arg, 30, 2) << 62;
69 ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
70 ret |= (uint64_t)extract32(arg, 0, 30) << 29;
71 }
72 } else {
73 /* Zero or Denormalized operand. */
74 ret = (uint64_t)extract32(arg, 31, 1) << 63;
75 if (unlikely(abs_arg != 0)) {
76 /* Denormalized operand. */
77 int shift = clz32(abs_arg) - 9;
78 int exp = -126 - shift + 1023;
79 ret |= (uint64_t)exp << 52;
80 ret |= abs_arg << (shift + 29);
81 }
82 }
83 return ret;
84 }
85
86 /*
87 * This is the non-arithmatic conversion that happens e.g. on stores.
88 * In the Power ISA pseudocode, this is called SINGLE.
89 */
90 uint32_t helper_tosingle(uint64_t arg)
91 {
92 int exp = extract64(arg, 52, 11);
93 uint32_t ret;
94
95 if (likely(exp > 896)) {
96 /* No denormalization required (includes Inf, NaN). */
97 ret = extract64(arg, 62, 2) << 30;
98 ret |= extract64(arg, 29, 30);
99 } else {
100 /*
101 * Zero or Denormal result. If the exponent is in bounds for
102 * a single-precision denormal result, extract the proper
103 * bits. If the input is not zero, and the exponent is out of
104 * bounds, then the result is undefined; this underflows to
105 * zero.
106 */
107 ret = extract64(arg, 63, 1) << 31;
108 if (unlikely(exp >= 874)) {
109 /* Denormal result. */
110 ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
111 }
112 }
113 return ret;
114 }
115
116 static inline int ppc_float32_get_unbiased_exp(float32 f)
117 {
118 return ((f >> 23) & 0xFF) - 127;
119 }
120
121 static inline int ppc_float64_get_unbiased_exp(float64 f)
122 {
123 return ((f >> 52) & 0x7FF) - 1023;
124 }
125
126 /* Classify a floating-point number. */
127 enum {
128 is_normal = 1,
129 is_zero = 2,
130 is_denormal = 4,
131 is_inf = 8,
132 is_qnan = 16,
133 is_snan = 32,
134 is_neg = 64,
135 };
136
137 #define COMPUTE_CLASS(tp) \
138 static int tp##_classify(tp arg) \
139 { \
140 int ret = tp##_is_neg(arg) * is_neg; \
141 if (unlikely(tp##_is_any_nan(arg))) { \
142 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
143 ret |= (tp##_is_signaling_nan(arg, &dummy) \
144 ? is_snan : is_qnan); \
145 } else if (unlikely(tp##_is_infinity(arg))) { \
146 ret |= is_inf; \
147 } else if (tp##_is_zero(arg)) { \
148 ret |= is_zero; \
149 } else if (tp##_is_zero_or_denormal(arg)) { \
150 ret |= is_denormal; \
151 } else { \
152 ret |= is_normal; \
153 } \
154 return ret; \
155 }
156
157 COMPUTE_CLASS(float16)
158 COMPUTE_CLASS(float32)
159 COMPUTE_CLASS(float64)
160 COMPUTE_CLASS(float128)
161
162 static void set_fprf_from_class(CPUPPCState *env, int class)
163 {
164 static const uint8_t fprf[6][2] = {
165 { 0x04, 0x08 }, /* normalized */
166 { 0x02, 0x12 }, /* zero */
167 { 0x14, 0x18 }, /* denormalized */
168 { 0x05, 0x09 }, /* infinity */
169 { 0x11, 0x11 }, /* qnan */
170 { 0x00, 0x00 }, /* snan -- flags are undefined */
171 };
172 bool isneg = class & is_neg;
173
174 env->fpscr &= ~(0x1F << FPSCR_FPRF);
175 env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF;
176 }
177
178 #define COMPUTE_FPRF(tp) \
179 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
180 { \
181 set_fprf_from_class(env, tp##_classify(arg)); \
182 }
183
184 COMPUTE_FPRF(float16)
185 COMPUTE_FPRF(float32)
186 COMPUTE_FPRF(float64)
187 COMPUTE_FPRF(float128)
188
189 /* Floating-point invalid operations exception */
190 static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
191 {
192 /* Update the floating-point invalid operation summary */
193 env->fpscr |= 1 << FPSCR_VX;
194 /* Update the floating-point exception summary */
195 env->fpscr |= FP_FX;
196 if (fpscr_ve != 0) {
197 /* Update the floating-point enabled exception summary */
198 env->fpscr |= 1 << FPSCR_FEX;
199 if (fp_exceptions_enabled(env)) {
200 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
201 POWERPC_EXCP_FP | op, retaddr);
202 }
203 }
204 }
205
206 static void finish_invalid_op_arith(CPUPPCState *env, int op,
207 bool set_fpcc, uintptr_t retaddr)
208 {
209 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
210 if (fpscr_ve == 0) {
211 if (set_fpcc) {
212 env->fpscr &= ~(0xF << FPSCR_FPCC);
213 env->fpscr |= 0x11 << FPSCR_FPCC;
214 }
215 }
216 finish_invalid_op_excp(env, op, retaddr);
217 }
218
219 /* Signalling NaN */
220 static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
221 {
222 env->fpscr |= 1 << FPSCR_VXSNAN;
223 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
224 }
225
226 /* Magnitude subtraction of infinities */
227 static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
228 uintptr_t retaddr)
229 {
230 env->fpscr |= 1 << FPSCR_VXISI;
231 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
232 }
233
234 /* Division of infinity by infinity */
235 static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
236 uintptr_t retaddr)
237 {
238 env->fpscr |= 1 << FPSCR_VXIDI;
239 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
240 }
241
242 /* Division of zero by zero */
243 static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
244 uintptr_t retaddr)
245 {
246 env->fpscr |= 1 << FPSCR_VXZDZ;
247 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
248 }
249
250 /* Multiplication of zero by infinity */
251 static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
252 uintptr_t retaddr)
253 {
254 env->fpscr |= 1 << FPSCR_VXIMZ;
255 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
256 }
257
258 /* Square root of a negative number */
259 static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
260 uintptr_t retaddr)
261 {
262 env->fpscr |= 1 << FPSCR_VXSQRT;
263 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
264 }
265
266 /* Ordered comparison of NaN */
267 static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
268 uintptr_t retaddr)
269 {
270 env->fpscr |= 1 << FPSCR_VXVC;
271 if (set_fpcc) {
272 env->fpscr &= ~(0xF << FPSCR_FPCC);
273 env->fpscr |= 0x11 << FPSCR_FPCC;
274 }
275 /* Update the floating-point invalid operation summary */
276 env->fpscr |= 1 << FPSCR_VX;
277 /* Update the floating-point exception summary */
278 env->fpscr |= FP_FX;
279 /* We must update the target FPR before raising the exception */
280 if (fpscr_ve != 0) {
281 CPUState *cs = env_cpu(env);
282
283 cs->exception_index = POWERPC_EXCP_PROGRAM;
284 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
285 /* Update the floating-point enabled exception summary */
286 env->fpscr |= 1 << FPSCR_FEX;
287 /* Exception is differed */
288 }
289 }
290
291 /* Invalid conversion */
292 static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
293 uintptr_t retaddr)
294 {
295 env->fpscr |= 1 << FPSCR_VXCVI;
296 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
297 if (fpscr_ve == 0) {
298 if (set_fpcc) {
299 env->fpscr &= ~(0xF << FPSCR_FPCC);
300 env->fpscr |= 0x11 << FPSCR_FPCC;
301 }
302 }
303 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
304 }
305
306 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
307 {
308 env->fpscr |= 1 << FPSCR_ZX;
309 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
310 /* Update the floating-point exception summary */
311 env->fpscr |= FP_FX;
312 if (fpscr_ze != 0) {
313 /* Update the floating-point enabled exception summary */
314 env->fpscr |= 1 << FPSCR_FEX;
315 if (fp_exceptions_enabled(env)) {
316 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
317 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
318 raddr);
319 }
320 }
321 }
322
323 static inline void float_overflow_excp(CPUPPCState *env)
324 {
325 CPUState *cs = env_cpu(env);
326
327 env->fpscr |= 1 << FPSCR_OX;
328 /* Update the floating-point exception summary */
329 env->fpscr |= FP_FX;
330 if (fpscr_oe != 0) {
331 /* XXX: should adjust the result */
332 /* Update the floating-point enabled exception summary */
333 env->fpscr |= 1 << FPSCR_FEX;
334 /* We must update the target FPR before raising the exception */
335 cs->exception_index = POWERPC_EXCP_PROGRAM;
336 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
337 } else {
338 env->fpscr |= 1 << FPSCR_XX;
339 env->fpscr |= 1 << FPSCR_FI;
340 }
341 }
342
343 static inline void float_underflow_excp(CPUPPCState *env)
344 {
345 CPUState *cs = env_cpu(env);
346
347 env->fpscr |= 1 << FPSCR_UX;
348 /* Update the floating-point exception summary */
349 env->fpscr |= FP_FX;
350 if (fpscr_ue != 0) {
351 /* XXX: should adjust the result */
352 /* Update the floating-point enabled exception summary */
353 env->fpscr |= 1 << FPSCR_FEX;
354 /* We must update the target FPR before raising the exception */
355 cs->exception_index = POWERPC_EXCP_PROGRAM;
356 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
357 }
358 }
359
360 static inline void float_inexact_excp(CPUPPCState *env)
361 {
362 CPUState *cs = env_cpu(env);
363
364 env->fpscr |= 1 << FPSCR_FI;
365 env->fpscr |= 1 << FPSCR_XX;
366 /* Update the floating-point exception summary */
367 env->fpscr |= FP_FX;
368 if (fpscr_xe != 0) {
369 /* Update the floating-point enabled exception summary */
370 env->fpscr |= 1 << FPSCR_FEX;
371 /* We must update the target FPR before raising the exception */
372 cs->exception_index = POWERPC_EXCP_PROGRAM;
373 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
374 }
375 }
376
377 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
378 {
379 int rnd_type;
380
381 /* Set rounding mode */
382 switch (fpscr_rn) {
383 case 0:
384 /* Best approximation (round to nearest) */
385 rnd_type = float_round_nearest_even;
386 break;
387 case 1:
388 /* Smaller magnitude (round toward zero) */
389 rnd_type = float_round_to_zero;
390 break;
391 case 2:
392 /* Round toward +infinite */
393 rnd_type = float_round_up;
394 break;
395 default:
396 case 3:
397 /* Round toward -infinite */
398 rnd_type = float_round_down;
399 break;
400 }
401 set_float_rounding_mode(rnd_type, &env->fp_status);
402 }
403
404 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
405 {
406 int prev;
407
408 prev = (env->fpscr >> bit) & 1;
409 env->fpscr &= ~(1 << bit);
410 if (prev == 1) {
411 switch (bit) {
412 case FPSCR_RN1:
413 case FPSCR_RN0:
414 fpscr_set_rounding_mode(env);
415 break;
416 case FPSCR_VXSNAN:
417 case FPSCR_VXISI:
418 case FPSCR_VXIDI:
419 case FPSCR_VXZDZ:
420 case FPSCR_VXIMZ:
421 case FPSCR_VXVC:
422 case FPSCR_VXSOFT:
423 case FPSCR_VXSQRT:
424 case FPSCR_VXCVI:
425 if (!fpscr_ix) {
426 /* Set VX bit to zero */
427 env->fpscr &= ~(1 << FPSCR_VX);
428 }
429 break;
430 case FPSCR_OX:
431 case FPSCR_UX:
432 case FPSCR_ZX:
433 case FPSCR_XX:
434 case FPSCR_VE:
435 case FPSCR_OE:
436 case FPSCR_UE:
437 case FPSCR_ZE:
438 case FPSCR_XE:
439 if (!fpscr_eex) {
440 /* Set the FEX bit */
441 env->fpscr &= ~(1 << FPSCR_FEX);
442 }
443 break;
444 default:
445 break;
446 }
447 }
448 }
449
450 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
451 {
452 CPUState *cs = env_cpu(env);
453 int prev;
454
455 prev = (env->fpscr >> bit) & 1;
456 env->fpscr |= 1 << bit;
457 if (prev == 0) {
458 switch (bit) {
459 case FPSCR_VX:
460 env->fpscr |= FP_FX;
461 if (fpscr_ve) {
462 goto raise_ve;
463 }
464 break;
465 case FPSCR_OX:
466 env->fpscr |= FP_FX;
467 if (fpscr_oe) {
468 goto raise_oe;
469 }
470 break;
471 case FPSCR_UX:
472 env->fpscr |= FP_FX;
473 if (fpscr_ue) {
474 goto raise_ue;
475 }
476 break;
477 case FPSCR_ZX:
478 env->fpscr |= FP_FX;
479 if (fpscr_ze) {
480 goto raise_ze;
481 }
482 break;
483 case FPSCR_XX:
484 env->fpscr |= FP_FX;
485 if (fpscr_xe) {
486 goto raise_xe;
487 }
488 break;
489 case FPSCR_VXSNAN:
490 case FPSCR_VXISI:
491 case FPSCR_VXIDI:
492 case FPSCR_VXZDZ:
493 case FPSCR_VXIMZ:
494 case FPSCR_VXVC:
495 case FPSCR_VXSOFT:
496 case FPSCR_VXSQRT:
497 case FPSCR_VXCVI:
498 env->fpscr |= 1 << FPSCR_VX;
499 env->fpscr |= FP_FX;
500 if (fpscr_ve != 0) {
501 goto raise_ve;
502 }
503 break;
504 case FPSCR_VE:
505 if (fpscr_vx != 0) {
506 raise_ve:
507 env->error_code = POWERPC_EXCP_FP;
508 if (fpscr_vxsnan) {
509 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
510 }
511 if (fpscr_vxisi) {
512 env->error_code |= POWERPC_EXCP_FP_VXISI;
513 }
514 if (fpscr_vxidi) {
515 env->error_code |= POWERPC_EXCP_FP_VXIDI;
516 }
517 if (fpscr_vxzdz) {
518 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
519 }
520 if (fpscr_vximz) {
521 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
522 }
523 if (fpscr_vxvc) {
524 env->error_code |= POWERPC_EXCP_FP_VXVC;
525 }
526 if (fpscr_vxsoft) {
527 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
528 }
529 if (fpscr_vxsqrt) {
530 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
531 }
532 if (fpscr_vxcvi) {
533 env->error_code |= POWERPC_EXCP_FP_VXCVI;
534 }
535 goto raise_excp;
536 }
537 break;
538 case FPSCR_OE:
539 if (fpscr_ox != 0) {
540 raise_oe:
541 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
542 goto raise_excp;
543 }
544 break;
545 case FPSCR_UE:
546 if (fpscr_ux != 0) {
547 raise_ue:
548 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
549 goto raise_excp;
550 }
551 break;
552 case FPSCR_ZE:
553 if (fpscr_zx != 0) {
554 raise_ze:
555 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
556 goto raise_excp;
557 }
558 break;
559 case FPSCR_XE:
560 if (fpscr_xx != 0) {
561 raise_xe:
562 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
563 goto raise_excp;
564 }
565 break;
566 case FPSCR_RN1:
567 case FPSCR_RN0:
568 fpscr_set_rounding_mode(env);
569 break;
570 default:
571 break;
572 raise_excp:
573 /* Update the floating-point enabled exception summary */
574 env->fpscr |= 1 << FPSCR_FEX;
575 /* We have to update Rc1 before raising the exception */
576 cs->exception_index = POWERPC_EXCP_PROGRAM;
577 break;
578 }
579 }
580 }
581
582 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
583 {
584 CPUState *cs = env_cpu(env);
585 target_ulong prev, new;
586 int i;
587
588 prev = env->fpscr;
589 new = (target_ulong)arg;
590 new &= ~0x60000000LL;
591 new |= prev & 0x60000000LL;
592 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
593 if (mask & (1 << i)) {
594 env->fpscr &= ~(0xFLL << (4 * i));
595 env->fpscr |= new & (0xFLL << (4 * i));
596 }
597 }
598 /* Update VX and FEX */
599 if (fpscr_ix != 0) {
600 env->fpscr |= 1 << FPSCR_VX;
601 } else {
602 env->fpscr &= ~(1 << FPSCR_VX);
603 }
604 if ((fpscr_ex & fpscr_eex) != 0) {
605 env->fpscr |= 1 << FPSCR_FEX;
606 cs->exception_index = POWERPC_EXCP_PROGRAM;
607 /* XXX: we should compute it properly */
608 env->error_code = POWERPC_EXCP_FP;
609 } else {
610 env->fpscr &= ~(1 << FPSCR_FEX);
611 }
612 fpscr_set_rounding_mode(env);
613 }
614
615 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
616 {
617 helper_store_fpscr(env, arg, mask);
618 }
619
620 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
621 {
622 CPUState *cs = env_cpu(env);
623 int status = get_float_exception_flags(&env->fp_status);
624 bool inexact_happened = false;
625
626 if (status & float_flag_overflow) {
627 float_overflow_excp(env);
628 } else if (status & float_flag_underflow) {
629 float_underflow_excp(env);
630 } else if (status & float_flag_inexact) {
631 float_inexact_excp(env);
632 inexact_happened = true;
633 }
634
635 /* if the inexact flag was not set */
636 if (inexact_happened == false) {
637 env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
638 }
639
640 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
641 (env->error_code & POWERPC_EXCP_FP)) {
642 /* Differred floating-point exception after target FPR update */
643 if (fp_exceptions_enabled(env)) {
644 raise_exception_err_ra(env, cs->exception_index,
645 env->error_code, raddr);
646 }
647 }
648 }
649
650 void helper_float_check_status(CPUPPCState *env)
651 {
652 do_float_check_status(env, GETPC());
653 }
654
655 void helper_reset_fpstatus(CPUPPCState *env)
656 {
657 set_float_exception_flags(0, &env->fp_status);
658 }
659
660 static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
661 uintptr_t retaddr, int classes)
662 {
663 if ((classes & ~is_neg) == is_inf) {
664 /* Magnitude subtraction of infinities */
665 float_invalid_op_vxisi(env, set_fpcc, retaddr);
666 } else if (classes & is_snan) {
667 float_invalid_op_vxsnan(env, retaddr);
668 }
669 }
670
671 /* fadd - fadd. */
672 float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
673 {
674 float64 ret = float64_add(arg1, arg2, &env->fp_status);
675 int status = get_float_exception_flags(&env->fp_status);
676
677 if (unlikely(status & float_flag_invalid)) {
678 float_invalid_op_addsub(env, 1, GETPC(),
679 float64_classify(arg1) |
680 float64_classify(arg2));
681 }
682
683 return ret;
684 }
685
686 /* fsub - fsub. */
687 float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
688 {
689 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
690 int status = get_float_exception_flags(&env->fp_status);
691
692 if (unlikely(status & float_flag_invalid)) {
693 float_invalid_op_addsub(env, 1, GETPC(),
694 float64_classify(arg1) |
695 float64_classify(arg2));
696 }
697
698 return ret;
699 }
700
701 static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc,
702 uintptr_t retaddr, int classes)
703 {
704 if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) {
705 /* Multiplication of zero by infinity */
706 float_invalid_op_vximz(env, set_fprc, retaddr);
707 } else if (classes & is_snan) {
708 float_invalid_op_vxsnan(env, retaddr);
709 }
710 }
711
712 /* fmul - fmul. */
713 float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
714 {
715 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
716 int status = get_float_exception_flags(&env->fp_status);
717
718 if (unlikely(status & float_flag_invalid)) {
719 float_invalid_op_mul(env, 1, GETPC(),
720 float64_classify(arg1) |
721 float64_classify(arg2));
722 }
723
724 return ret;
725 }
726
727 static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
728 uintptr_t retaddr, int classes)
729 {
730 classes &= ~is_neg;
731 if (classes == is_inf) {
732 /* Division of infinity by infinity */
733 float_invalid_op_vxidi(env, set_fprc, retaddr);
734 } else if (classes == is_zero) {
735 /* Division of zero by zero */
736 float_invalid_op_vxzdz(env, set_fprc, retaddr);
737 } else if (classes & is_snan) {
738 float_invalid_op_vxsnan(env, retaddr);
739 }
740 }
741
742 /* fdiv - fdiv. */
743 float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
744 {
745 float64 ret = float64_div(arg1, arg2, &env->fp_status);
746 int status = get_float_exception_flags(&env->fp_status);
747
748 if (unlikely(status)) {
749 if (status & float_flag_invalid) {
750 float_invalid_op_div(env, 1, GETPC(),
751 float64_classify(arg1) |
752 float64_classify(arg2));
753 }
754 if (status & float_flag_divbyzero) {
755 float_zero_divide_excp(env, GETPC());
756 }
757 }
758
759 return ret;
760 }
761
762 static void float_invalid_cvt(CPUPPCState *env, bool set_fprc,
763 uintptr_t retaddr, int class1)
764 {
765 float_invalid_op_vxcvi(env, set_fprc, retaddr);
766 if (class1 & is_snan) {
767 float_invalid_op_vxsnan(env, retaddr);
768 }
769 }
770
771 #define FPU_FCTI(op, cvt, nanval) \
772 uint64_t helper_##op(CPUPPCState *env, float64 arg) \
773 { \
774 uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
775 int status = get_float_exception_flags(&env->fp_status); \
776 \
777 if (unlikely(status)) { \
778 if (status & float_flag_invalid) { \
779 float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
780 ret = nanval; \
781 } \
782 do_float_check_status(env, GETPC()); \
783 } \
784 return ret; \
785 }
786
787 FPU_FCTI(fctiw, int32, 0x80000000U)
788 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
789 FPU_FCTI(fctiwu, uint32, 0x00000000U)
790 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
791 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
792 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
793 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
794 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
795
796 #define FPU_FCFI(op, cvtr, is_single) \
797 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
798 { \
799 CPU_DoubleU farg; \
800 \
801 if (is_single) { \
802 float32 tmp = cvtr(arg, &env->fp_status); \
803 farg.d = float32_to_float64(tmp, &env->fp_status); \
804 } else { \
805 farg.d = cvtr(arg, &env->fp_status); \
806 } \
807 do_float_check_status(env, GETPC()); \
808 return farg.ll; \
809 }
810
811 FPU_FCFI(fcfid, int64_to_float64, 0)
812 FPU_FCFI(fcfids, int64_to_float32, 1)
813 FPU_FCFI(fcfidu, uint64_to_float64, 0)
814 FPU_FCFI(fcfidus, uint64_to_float32, 1)
815
816 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
817 int rounding_mode)
818 {
819 CPU_DoubleU farg;
820
821 farg.ll = arg;
822
823 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
824 /* sNaN round */
825 float_invalid_op_vxsnan(env, GETPC());
826 farg.ll = arg | 0x0008000000000000ULL;
827 } else {
828 int inexact = get_float_exception_flags(&env->fp_status) &
829 float_flag_inexact;
830 set_float_rounding_mode(rounding_mode, &env->fp_status);
831 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
832 /* Restore rounding mode from FPSCR */
833 fpscr_set_rounding_mode(env);
834
835 /* fri* does not set FPSCR[XX] */
836 if (!inexact) {
837 env->fp_status.float_exception_flags &= ~float_flag_inexact;
838 }
839 }
840 do_float_check_status(env, GETPC());
841 return farg.ll;
842 }
843
844 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
845 {
846 return do_fri(env, arg, float_round_ties_away);
847 }
848
849 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
850 {
851 return do_fri(env, arg, float_round_to_zero);
852 }
853
854 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
855 {
856 return do_fri(env, arg, float_round_up);
857 }
858
859 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
860 {
861 return do_fri(env, arg, float_round_down);
862 }
863
864 #define FPU_MADDSUB_UPDATE(NAME, TP) \
865 static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
866 unsigned int madd_flags, uintptr_t retaddr) \
867 { \
868 if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
869 TP##_is_signaling_nan(arg2, &env->fp_status) || \
870 TP##_is_signaling_nan(arg3, &env->fp_status)) { \
871 /* sNaN operation */ \
872 float_invalid_op_vxsnan(env, retaddr); \
873 } \
874 if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
875 (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
876 /* Multiplication of zero by infinity */ \
877 float_invalid_op_vximz(env, 1, retaddr); \
878 } \
879 if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
880 TP##_is_infinity(arg3)) { \
881 uint8_t aSign, bSign, cSign; \
882 \
883 aSign = TP##_is_neg(arg1); \
884 bSign = TP##_is_neg(arg2); \
885 cSign = TP##_is_neg(arg3); \
886 if (madd_flags & float_muladd_negate_c) { \
887 cSign ^= 1; \
888 } \
889 if (aSign ^ bSign ^ cSign) { \
890 float_invalid_op_vxisi(env, 1, retaddr); \
891 } \
892 } \
893 }
894 FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32)
895 FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
896
897 #define FPU_FMADD(op, madd_flags) \
898 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
899 uint64_t arg2, uint64_t arg3) \
900 { \
901 uint32_t flags; \
902 float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
903 &env->fp_status); \
904 flags = get_float_exception_flags(&env->fp_status); \
905 if (flags) { \
906 if (flags & float_flag_invalid) { \
907 float64_maddsub_update_excp(env, arg1, arg2, arg3, \
908 madd_flags, GETPC()); \
909 } \
910 do_float_check_status(env, GETPC()); \
911 } \
912 return ret; \
913 }
914
915 #define MADD_FLGS 0
916 #define MSUB_FLGS float_muladd_negate_c
917 #define NMADD_FLGS float_muladd_negate_result
918 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
919
920 FPU_FMADD(fmadd, MADD_FLGS)
921 FPU_FMADD(fnmadd, NMADD_FLGS)
922 FPU_FMADD(fmsub, MSUB_FLGS)
923 FPU_FMADD(fnmsub, NMSUB_FLGS)
924
925 /* frsp - frsp. */
926 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
927 {
928 CPU_DoubleU farg;
929 float32 f32;
930
931 farg.ll = arg;
932
933 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
934 float_invalid_op_vxsnan(env, GETPC());
935 }
936 f32 = float64_to_float32(farg.d, &env->fp_status);
937 farg.d = float32_to_float64(f32, &env->fp_status);
938
939 return farg.ll;
940 }
941
942 /* fsqrt - fsqrt. */
943 float64 helper_fsqrt(CPUPPCState *env, float64 arg)
944 {
945 float64 ret = float64_sqrt(arg, &env->fp_status);
946 int status = get_float_exception_flags(&env->fp_status);
947
948 if (unlikely(status & float_flag_invalid)) {
949 if (unlikely(float64_is_any_nan(arg))) {
950 if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) {
951 /* sNaN square root */
952 float_invalid_op_vxsnan(env, GETPC());
953 }
954 } else {
955 /* Square root of a negative nonzero number */
956 float_invalid_op_vxsqrt(env, 1, GETPC());
957 }
958 }
959
960 return ret;
961 }
962
963 /* fre - fre. */
964 float64 helper_fre(CPUPPCState *env, float64 arg)
965 {
966 /* "Estimate" the reciprocal with actual division. */
967 float64 ret = float64_div(float64_one, arg, &env->fp_status);
968 int status = get_float_exception_flags(&env->fp_status);
969
970 if (unlikely(status)) {
971 if (status & float_flag_invalid) {
972 if (float64_is_signaling_nan(arg, &env->fp_status)) {
973 /* sNaN reciprocal */
974 float_invalid_op_vxsnan(env, GETPC());
975 }
976 }
977 if (status & float_flag_divbyzero) {
978 float_zero_divide_excp(env, GETPC());
979 /* For FPSCR.ZE == 0, the result is 1/2. */
980 ret = float64_set_sign(float64_half, float64_is_neg(arg));
981 }
982 }
983
984 return ret;
985 }
986
987 /* fres - fres. */
988 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
989 {
990 CPU_DoubleU farg;
991 float32 f32;
992
993 farg.ll = arg;
994
995 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
996 /* sNaN reciprocal */
997 float_invalid_op_vxsnan(env, GETPC());
998 }
999 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1000 f32 = float64_to_float32(farg.d, &env->fp_status);
1001 farg.d = float32_to_float64(f32, &env->fp_status);
1002
1003 return farg.ll;
1004 }
1005
1006 /* frsqrte - frsqrte. */
1007 float64 helper_frsqrte(CPUPPCState *env, float64 arg)
1008 {
1009 /* "Estimate" the reciprocal with actual division. */
1010 float64 rets = float64_sqrt(arg, &env->fp_status);
1011 float64 retd = float64_div(float64_one, rets, &env->fp_status);
1012 int status = get_float_exception_flags(&env->fp_status);
1013
1014 if (unlikely(status)) {
1015 if (status & float_flag_invalid) {
1016 if (float64_is_signaling_nan(arg, &env->fp_status)) {
1017 /* sNaN reciprocal */
1018 float_invalid_op_vxsnan(env, GETPC());
1019 } else {
1020 /* Square root of a negative nonzero number */
1021 float_invalid_op_vxsqrt(env, 1, GETPC());
1022 }
1023 }
1024 if (status & float_flag_divbyzero) {
1025 /* Reciprocal of (square root of) zero. */
1026 float_zero_divide_excp(env, GETPC());
1027 }
1028 }
1029
1030 return retd;
1031 }
1032
1033 /* fsel - fsel. */
1034 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1035 uint64_t arg3)
1036 {
1037 CPU_DoubleU farg1;
1038
1039 farg1.ll = arg1;
1040
1041 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1042 !float64_is_any_nan(farg1.d)) {
1043 return arg2;
1044 } else {
1045 return arg3;
1046 }
1047 }
1048
1049 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
1050 {
1051 int fe_flag = 0;
1052 int fg_flag = 0;
1053
1054 if (unlikely(float64_is_infinity(fra) ||
1055 float64_is_infinity(frb) ||
1056 float64_is_zero(frb))) {
1057 fe_flag = 1;
1058 fg_flag = 1;
1059 } else {
1060 int e_a = ppc_float64_get_unbiased_exp(fra);
1061 int e_b = ppc_float64_get_unbiased_exp(frb);
1062
1063 if (unlikely(float64_is_any_nan(fra) ||
1064 float64_is_any_nan(frb))) {
1065 fe_flag = 1;
1066 } else if ((e_b <= -1022) || (e_b >= 1021)) {
1067 fe_flag = 1;
1068 } else if (!float64_is_zero(fra) &&
1069 (((e_a - e_b) >= 1023) ||
1070 ((e_a - e_b) <= -1021) ||
1071 (e_a <= -970))) {
1072 fe_flag = 1;
1073 }
1074
1075 if (unlikely(float64_is_zero_or_denormal(frb))) {
1076 /* XB is not zero because of the above check and */
1077 /* so must be denormalized. */
1078 fg_flag = 1;
1079 }
1080 }
1081
1082 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1083 }
1084
1085 uint32_t helper_ftsqrt(uint64_t frb)
1086 {
1087 int fe_flag = 0;
1088 int fg_flag = 0;
1089
1090 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
1091 fe_flag = 1;
1092 fg_flag = 1;
1093 } else {
1094 int e_b = ppc_float64_get_unbiased_exp(frb);
1095
1096 if (unlikely(float64_is_any_nan(frb))) {
1097 fe_flag = 1;
1098 } else if (unlikely(float64_is_zero(frb))) {
1099 fe_flag = 1;
1100 } else if (unlikely(float64_is_neg(frb))) {
1101 fe_flag = 1;
1102 } else if (!float64_is_zero(frb) && (e_b <= (-1022 + 52))) {
1103 fe_flag = 1;
1104 }
1105
1106 if (unlikely(float64_is_zero_or_denormal(frb))) {
1107 /* XB is not zero because of the above check and */
1108 /* therefore must be denormalized. */
1109 fg_flag = 1;
1110 }
1111 }
1112
1113 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1114 }
1115
1116 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1117 uint32_t crfD)
1118 {
1119 CPU_DoubleU farg1, farg2;
1120 uint32_t ret = 0;
1121
1122 farg1.ll = arg1;
1123 farg2.ll = arg2;
1124
1125 if (unlikely(float64_is_any_nan(farg1.d) ||
1126 float64_is_any_nan(farg2.d))) {
1127 ret = 0x01UL;
1128 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1129 ret = 0x08UL;
1130 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1131 ret = 0x04UL;
1132 } else {
1133 ret = 0x02UL;
1134 }
1135
1136 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1137 env->fpscr |= ret << FPSCR_FPRF;
1138 env->crf[crfD] = ret;
1139 if (unlikely(ret == 0x01UL
1140 && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1141 float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
1142 /* sNaN comparison */
1143 float_invalid_op_vxsnan(env, GETPC());
1144 }
1145 }
1146
1147 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1148 uint32_t crfD)
1149 {
1150 CPU_DoubleU farg1, farg2;
1151 uint32_t ret = 0;
1152
1153 farg1.ll = arg1;
1154 farg2.ll = arg2;
1155
1156 if (unlikely(float64_is_any_nan(farg1.d) ||
1157 float64_is_any_nan(farg2.d))) {
1158 ret = 0x01UL;
1159 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1160 ret = 0x08UL;
1161 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1162 ret = 0x04UL;
1163 } else {
1164 ret = 0x02UL;
1165 }
1166
1167 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1168 env->fpscr |= ret << FPSCR_FPRF;
1169 env->crf[crfD] = ret;
1170 if (unlikely(ret == 0x01UL)) {
1171 float_invalid_op_vxvc(env, 1, GETPC());
1172 if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1173 float64_is_signaling_nan(farg2.d, &env->fp_status)) {
1174 /* sNaN comparison */
1175 float_invalid_op_vxsnan(env, GETPC());
1176 }
1177 }
1178 }
1179
1180 /* Single-precision floating-point conversions */
1181 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1182 {
1183 CPU_FloatU u;
1184
1185 u.f = int32_to_float32(val, &env->vec_status);
1186
1187 return u.l;
1188 }
1189
1190 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1191 {
1192 CPU_FloatU u;
1193
1194 u.f = uint32_to_float32(val, &env->vec_status);
1195
1196 return u.l;
1197 }
1198
1199 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1200 {
1201 CPU_FloatU u;
1202
1203 u.l = val;
1204 /* NaN are not treated the same way IEEE 754 does */
1205 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1206 return 0;
1207 }
1208
1209 return float32_to_int32(u.f, &env->vec_status);
1210 }
1211
1212 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1213 {
1214 CPU_FloatU u;
1215
1216 u.l = val;
1217 /* NaN are not treated the same way IEEE 754 does */
1218 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1219 return 0;
1220 }
1221
1222 return float32_to_uint32(u.f, &env->vec_status);
1223 }
1224
1225 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1226 {
1227 CPU_FloatU u;
1228
1229 u.l = val;
1230 /* NaN are not treated the same way IEEE 754 does */
1231 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1232 return 0;
1233 }
1234
1235 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1236 }
1237
1238 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1239 {
1240 CPU_FloatU u;
1241
1242 u.l = val;
1243 /* NaN are not treated the same way IEEE 754 does */
1244 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1245 return 0;
1246 }
1247
1248 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1249 }
1250
1251 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1252 {
1253 CPU_FloatU u;
1254 float32 tmp;
1255
1256 u.f = int32_to_float32(val, &env->vec_status);
1257 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1258 u.f = float32_div(u.f, tmp, &env->vec_status);
1259
1260 return u.l;
1261 }
1262
1263 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1264 {
1265 CPU_FloatU u;
1266 float32 tmp;
1267
1268 u.f = uint32_to_float32(val, &env->vec_status);
1269 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1270 u.f = float32_div(u.f, tmp, &env->vec_status);
1271
1272 return u.l;
1273 }
1274
1275 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1276 {
1277 CPU_FloatU u;
1278 float32 tmp;
1279
1280 u.l = val;
1281 /* NaN are not treated the same way IEEE 754 does */
1282 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1283 return 0;
1284 }
1285 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1286 u.f = float32_mul(u.f, tmp, &env->vec_status);
1287
1288 return float32_to_int32(u.f, &env->vec_status);
1289 }
1290
1291 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1292 {
1293 CPU_FloatU u;
1294 float32 tmp;
1295
1296 u.l = val;
1297 /* NaN are not treated the same way IEEE 754 does */
1298 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1299 return 0;
1300 }
1301 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1302 u.f = float32_mul(u.f, tmp, &env->vec_status);
1303
1304 return float32_to_uint32(u.f, &env->vec_status);
1305 }
1306
1307 #define HELPER_SPE_SINGLE_CONV(name) \
1308 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1309 { \
1310 return e##name(env, val); \
1311 }
1312 /* efscfsi */
1313 HELPER_SPE_SINGLE_CONV(fscfsi);
1314 /* efscfui */
1315 HELPER_SPE_SINGLE_CONV(fscfui);
1316 /* efscfuf */
1317 HELPER_SPE_SINGLE_CONV(fscfuf);
1318 /* efscfsf */
1319 HELPER_SPE_SINGLE_CONV(fscfsf);
1320 /* efsctsi */
1321 HELPER_SPE_SINGLE_CONV(fsctsi);
1322 /* efsctui */
1323 HELPER_SPE_SINGLE_CONV(fsctui);
1324 /* efsctsiz */
1325 HELPER_SPE_SINGLE_CONV(fsctsiz);
1326 /* efsctuiz */
1327 HELPER_SPE_SINGLE_CONV(fsctuiz);
1328 /* efsctsf */
1329 HELPER_SPE_SINGLE_CONV(fsctsf);
1330 /* efsctuf */
1331 HELPER_SPE_SINGLE_CONV(fsctuf);
1332
1333 #define HELPER_SPE_VECTOR_CONV(name) \
1334 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1335 { \
1336 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1337 (uint64_t)e##name(env, val); \
1338 }
1339 /* evfscfsi */
1340 HELPER_SPE_VECTOR_CONV(fscfsi);
1341 /* evfscfui */
1342 HELPER_SPE_VECTOR_CONV(fscfui);
1343 /* evfscfuf */
1344 HELPER_SPE_VECTOR_CONV(fscfuf);
1345 /* evfscfsf */
1346 HELPER_SPE_VECTOR_CONV(fscfsf);
1347 /* evfsctsi */
1348 HELPER_SPE_VECTOR_CONV(fsctsi);
1349 /* evfsctui */
1350 HELPER_SPE_VECTOR_CONV(fsctui);
1351 /* evfsctsiz */
1352 HELPER_SPE_VECTOR_CONV(fsctsiz);
1353 /* evfsctuiz */
1354 HELPER_SPE_VECTOR_CONV(fsctuiz);
1355 /* evfsctsf */
1356 HELPER_SPE_VECTOR_CONV(fsctsf);
1357 /* evfsctuf */
1358 HELPER_SPE_VECTOR_CONV(fsctuf);
1359
1360 /* Single-precision floating-point arithmetic */
1361 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1362 {
1363 CPU_FloatU u1, u2;
1364
1365 u1.l = op1;
1366 u2.l = op2;
1367 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1368 return u1.l;
1369 }
1370
1371 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1372 {
1373 CPU_FloatU u1, u2;
1374
1375 u1.l = op1;
1376 u2.l = op2;
1377 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1378 return u1.l;
1379 }
1380
1381 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1382 {
1383 CPU_FloatU u1, u2;
1384
1385 u1.l = op1;
1386 u2.l = op2;
1387 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1388 return u1.l;
1389 }
1390
1391 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1392 {
1393 CPU_FloatU u1, u2;
1394
1395 u1.l = op1;
1396 u2.l = op2;
1397 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1398 return u1.l;
1399 }
1400
1401 #define HELPER_SPE_SINGLE_ARITH(name) \
1402 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1403 { \
1404 return e##name(env, op1, op2); \
1405 }
1406 /* efsadd */
1407 HELPER_SPE_SINGLE_ARITH(fsadd);
1408 /* efssub */
1409 HELPER_SPE_SINGLE_ARITH(fssub);
1410 /* efsmul */
1411 HELPER_SPE_SINGLE_ARITH(fsmul);
1412 /* efsdiv */
1413 HELPER_SPE_SINGLE_ARITH(fsdiv);
1414
1415 #define HELPER_SPE_VECTOR_ARITH(name) \
1416 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1417 { \
1418 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1419 (uint64_t)e##name(env, op1, op2); \
1420 }
1421 /* evfsadd */
1422 HELPER_SPE_VECTOR_ARITH(fsadd);
1423 /* evfssub */
1424 HELPER_SPE_VECTOR_ARITH(fssub);
1425 /* evfsmul */
1426 HELPER_SPE_VECTOR_ARITH(fsmul);
1427 /* evfsdiv */
1428 HELPER_SPE_VECTOR_ARITH(fsdiv);
1429
1430 /* Single-precision floating-point comparisons */
1431 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1432 {
1433 CPU_FloatU u1, u2;
1434
1435 u1.l = op1;
1436 u2.l = op2;
1437 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1438 }
1439
1440 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1441 {
1442 CPU_FloatU u1, u2;
1443
1444 u1.l = op1;
1445 u2.l = op2;
1446 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1447 }
1448
1449 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1450 {
1451 CPU_FloatU u1, u2;
1452
1453 u1.l = op1;
1454 u2.l = op2;
1455 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1456 }
1457
1458 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1459 {
1460 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1461 return efscmplt(env, op1, op2);
1462 }
1463
1464 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1465 {
1466 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1467 return efscmpgt(env, op1, op2);
1468 }
1469
1470 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1471 {
1472 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1473 return efscmpeq(env, op1, op2);
1474 }
1475
1476 #define HELPER_SINGLE_SPE_CMP(name) \
1477 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1478 { \
1479 return e##name(env, op1, op2); \
1480 }
1481 /* efststlt */
1482 HELPER_SINGLE_SPE_CMP(fststlt);
1483 /* efststgt */
1484 HELPER_SINGLE_SPE_CMP(fststgt);
1485 /* efststeq */
1486 HELPER_SINGLE_SPE_CMP(fststeq);
1487 /* efscmplt */
1488 HELPER_SINGLE_SPE_CMP(fscmplt);
1489 /* efscmpgt */
1490 HELPER_SINGLE_SPE_CMP(fscmpgt);
1491 /* efscmpeq */
1492 HELPER_SINGLE_SPE_CMP(fscmpeq);
1493
1494 static inline uint32_t evcmp_merge(int t0, int t1)
1495 {
1496 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1497 }
1498
1499 #define HELPER_VECTOR_SPE_CMP(name) \
1500 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1501 { \
1502 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1503 e##name(env, op1, op2)); \
1504 }
1505 /* evfststlt */
1506 HELPER_VECTOR_SPE_CMP(fststlt);
1507 /* evfststgt */
1508 HELPER_VECTOR_SPE_CMP(fststgt);
1509 /* evfststeq */
1510 HELPER_VECTOR_SPE_CMP(fststeq);
1511 /* evfscmplt */
1512 HELPER_VECTOR_SPE_CMP(fscmplt);
1513 /* evfscmpgt */
1514 HELPER_VECTOR_SPE_CMP(fscmpgt);
1515 /* evfscmpeq */
1516 HELPER_VECTOR_SPE_CMP(fscmpeq);
1517
1518 /* Double-precision floating-point conversion */
1519 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1520 {
1521 CPU_DoubleU u;
1522
1523 u.d = int32_to_float64(val, &env->vec_status);
1524
1525 return u.ll;
1526 }
1527
1528 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1529 {
1530 CPU_DoubleU u;
1531
1532 u.d = int64_to_float64(val, &env->vec_status);
1533
1534 return u.ll;
1535 }
1536
1537 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1538 {
1539 CPU_DoubleU u;
1540
1541 u.d = uint32_to_float64(val, &env->vec_status);
1542
1543 return u.ll;
1544 }
1545
1546 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1547 {
1548 CPU_DoubleU u;
1549
1550 u.d = uint64_to_float64(val, &env->vec_status);
1551
1552 return u.ll;
1553 }
1554
1555 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1556 {
1557 CPU_DoubleU u;
1558
1559 u.ll = val;
1560 /* NaN are not treated the same way IEEE 754 does */
1561 if (unlikely(float64_is_any_nan(u.d))) {
1562 return 0;
1563 }
1564
1565 return float64_to_int32(u.d, &env->vec_status);
1566 }
1567
1568 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1569 {
1570 CPU_DoubleU u;
1571
1572 u.ll = val;
1573 /* NaN are not treated the same way IEEE 754 does */
1574 if (unlikely(float64_is_any_nan(u.d))) {
1575 return 0;
1576 }
1577
1578 return float64_to_uint32(u.d, &env->vec_status);
1579 }
1580
1581 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1582 {
1583 CPU_DoubleU u;
1584
1585 u.ll = val;
1586 /* NaN are not treated the same way IEEE 754 does */
1587 if (unlikely(float64_is_any_nan(u.d))) {
1588 return 0;
1589 }
1590
1591 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1592 }
1593
1594 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1595 {
1596 CPU_DoubleU u;
1597
1598 u.ll = val;
1599 /* NaN are not treated the same way IEEE 754 does */
1600 if (unlikely(float64_is_any_nan(u.d))) {
1601 return 0;
1602 }
1603
1604 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1605 }
1606
1607 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1608 {
1609 CPU_DoubleU u;
1610
1611 u.ll = val;
1612 /* NaN are not treated the same way IEEE 754 does */
1613 if (unlikely(float64_is_any_nan(u.d))) {
1614 return 0;
1615 }
1616
1617 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1618 }
1619
1620 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1621 {
1622 CPU_DoubleU u;
1623
1624 u.ll = val;
1625 /* NaN are not treated the same way IEEE 754 does */
1626 if (unlikely(float64_is_any_nan(u.d))) {
1627 return 0;
1628 }
1629
1630 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1631 }
1632
1633 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1634 {
1635 CPU_DoubleU u;
1636 float64 tmp;
1637
1638 u.d = int32_to_float64(val, &env->vec_status);
1639 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1640 u.d = float64_div(u.d, tmp, &env->vec_status);
1641
1642 return u.ll;
1643 }
1644
1645 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1646 {
1647 CPU_DoubleU u;
1648 float64 tmp;
1649
1650 u.d = uint32_to_float64(val, &env->vec_status);
1651 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1652 u.d = float64_div(u.d, tmp, &env->vec_status);
1653
1654 return u.ll;
1655 }
1656
1657 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1658 {
1659 CPU_DoubleU u;
1660 float64 tmp;
1661
1662 u.ll = val;
1663 /* NaN are not treated the same way IEEE 754 does */
1664 if (unlikely(float64_is_any_nan(u.d))) {
1665 return 0;
1666 }
1667 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1668 u.d = float64_mul(u.d, tmp, &env->vec_status);
1669
1670 return float64_to_int32(u.d, &env->vec_status);
1671 }
1672
1673 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1674 {
1675 CPU_DoubleU u;
1676 float64 tmp;
1677
1678 u.ll = val;
1679 /* NaN are not treated the same way IEEE 754 does */
1680 if (unlikely(float64_is_any_nan(u.d))) {
1681 return 0;
1682 }
1683 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1684 u.d = float64_mul(u.d, tmp, &env->vec_status);
1685
1686 return float64_to_uint32(u.d, &env->vec_status);
1687 }
1688
1689 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1690 {
1691 CPU_DoubleU u1;
1692 CPU_FloatU u2;
1693
1694 u1.ll = val;
1695 u2.f = float64_to_float32(u1.d, &env->vec_status);
1696
1697 return u2.l;
1698 }
1699
1700 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1701 {
1702 CPU_DoubleU u2;
1703 CPU_FloatU u1;
1704
1705 u1.l = val;
1706 u2.d = float32_to_float64(u1.f, &env->vec_status);
1707
1708 return u2.ll;
1709 }
1710
1711 /* Double precision fixed-point arithmetic */
1712 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1713 {
1714 CPU_DoubleU u1, u2;
1715
1716 u1.ll = op1;
1717 u2.ll = op2;
1718 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1719 return u1.ll;
1720 }
1721
1722 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1723 {
1724 CPU_DoubleU u1, u2;
1725
1726 u1.ll = op1;
1727 u2.ll = op2;
1728 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1729 return u1.ll;
1730 }
1731
1732 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1733 {
1734 CPU_DoubleU u1, u2;
1735
1736 u1.ll = op1;
1737 u2.ll = op2;
1738 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1739 return u1.ll;
1740 }
1741
1742 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1743 {
1744 CPU_DoubleU u1, u2;
1745
1746 u1.ll = op1;
1747 u2.ll = op2;
1748 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1749 return u1.ll;
1750 }
1751
1752 /* Double precision floating point helpers */
1753 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1754 {
1755 CPU_DoubleU u1, u2;
1756
1757 u1.ll = op1;
1758 u2.ll = op2;
1759 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1760 }
1761
1762 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1763 {
1764 CPU_DoubleU u1, u2;
1765
1766 u1.ll = op1;
1767 u2.ll = op2;
1768 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1769 }
1770
1771 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1772 {
1773 CPU_DoubleU u1, u2;
1774
1775 u1.ll = op1;
1776 u2.ll = op2;
1777 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1778 }
1779
1780 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1781 {
1782 /* XXX: TODO: test special values (NaN, infinites, ...) */
1783 return helper_efdtstlt(env, op1, op2);
1784 }
1785
1786 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1787 {
1788 /* XXX: TODO: test special values (NaN, infinites, ...) */
1789 return helper_efdtstgt(env, op1, op2);
1790 }
1791
1792 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1793 {
1794 /* XXX: TODO: test special values (NaN, infinites, ...) */
1795 return helper_efdtsteq(env, op1, op2);
1796 }
1797
1798 #define float64_to_float64(x, env) x
1799
1800
1801 /*
1802 * VSX_ADD_SUB - VSX floating point add/subract
1803 * name - instruction mnemonic
1804 * op - operation (add or sub)
1805 * nels - number of elements (1, 2 or 4)
1806 * tp - type (float32 or float64)
1807 * fld - vsr_t field (VsrD(*) or VsrW(*))
1808 * sfprf - set FPRF
1809 */
1810 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1811 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
1812 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1813 { \
1814 ppc_vsr_t t = *xt; \
1815 int i; \
1816 \
1817 helper_reset_fpstatus(env); \
1818 \
1819 for (i = 0; i < nels; i++) { \
1820 float_status tstat = env->fp_status; \
1821 set_float_exception_flags(0, &tstat); \
1822 t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
1823 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1824 \
1825 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1826 float_invalid_op_addsub(env, sfprf, GETPC(), \
1827 tp##_classify(xa->fld) | \
1828 tp##_classify(xb->fld)); \
1829 } \
1830 \
1831 if (r2sp) { \
1832 t.fld = helper_frsp(env, t.fld); \
1833 } \
1834 \
1835 if (sfprf) { \
1836 helper_compute_fprf_float64(env, t.fld); \
1837 } \
1838 } \
1839 *xt = t; \
1840 do_float_check_status(env, GETPC()); \
1841 }
1842
1843 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1844 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1845 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1846 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1847 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1848 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1849 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1850 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1851
1852 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
1853 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1854 {
1855 ppc_vsr_t t = *xt;
1856 float_status tstat;
1857
1858 helper_reset_fpstatus(env);
1859
1860 tstat = env->fp_status;
1861 if (unlikely(Rc(opcode) != 0)) {
1862 tstat.float_rounding_mode = float_round_to_odd;
1863 }
1864
1865 set_float_exception_flags(0, &tstat);
1866 t.f128 = float128_add(xa->f128, xb->f128, &tstat);
1867 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1868
1869 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1870 float_invalid_op_addsub(env, 1, GETPC(),
1871 float128_classify(xa->f128) |
1872 float128_classify(xb->f128));
1873 }
1874
1875 helper_compute_fprf_float128(env, t.f128);
1876
1877 *xt = t;
1878 do_float_check_status(env, GETPC());
1879 }
1880
1881 /*
1882 * VSX_MUL - VSX floating point multiply
1883 * op - instruction mnemonic
1884 * nels - number of elements (1, 2 or 4)
1885 * tp - type (float32 or float64)
1886 * fld - vsr_t field (VsrD(*) or VsrW(*))
1887 * sfprf - set FPRF
1888 */
1889 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1890 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1891 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1892 { \
1893 ppc_vsr_t t = *xt; \
1894 int i; \
1895 \
1896 helper_reset_fpstatus(env); \
1897 \
1898 for (i = 0; i < nels; i++) { \
1899 float_status tstat = env->fp_status; \
1900 set_float_exception_flags(0, &tstat); \
1901 t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
1902 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1903 \
1904 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1905 float_invalid_op_mul(env, sfprf, GETPC(), \
1906 tp##_classify(xa->fld) | \
1907 tp##_classify(xb->fld)); \
1908 } \
1909 \
1910 if (r2sp) { \
1911 t.fld = helper_frsp(env, t.fld); \
1912 } \
1913 \
1914 if (sfprf) { \
1915 helper_compute_fprf_float64(env, t.fld); \
1916 } \
1917 } \
1918 \
1919 *xt = t; \
1920 do_float_check_status(env, GETPC()); \
1921 }
1922
1923 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1924 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1925 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1926 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1927
1928 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
1929 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1930 {
1931 ppc_vsr_t t = *xt;
1932 float_status tstat;
1933
1934 helper_reset_fpstatus(env);
1935 tstat = env->fp_status;
1936 if (unlikely(Rc(opcode) != 0)) {
1937 tstat.float_rounding_mode = float_round_to_odd;
1938 }
1939
1940 set_float_exception_flags(0, &tstat);
1941 t.f128 = float128_mul(xa->f128, xb->f128, &tstat);
1942 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1943
1944 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1945 float_invalid_op_mul(env, 1, GETPC(),
1946 float128_classify(xa->f128) |
1947 float128_classify(xb->f128));
1948 }
1949 helper_compute_fprf_float128(env, t.f128);
1950
1951 *xt = t;
1952 do_float_check_status(env, GETPC());
1953 }
1954
1955 /*
1956 * VSX_DIV - VSX floating point divide
1957 * op - instruction mnemonic
1958 * nels - number of elements (1, 2 or 4)
1959 * tp - type (float32 or float64)
1960 * fld - vsr_t field (VsrD(*) or VsrW(*))
1961 * sfprf - set FPRF
1962 */
1963 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1964 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1965 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1966 { \
1967 ppc_vsr_t t = *xt; \
1968 int i; \
1969 \
1970 helper_reset_fpstatus(env); \
1971 \
1972 for (i = 0; i < nels; i++) { \
1973 float_status tstat = env->fp_status; \
1974 set_float_exception_flags(0, &tstat); \
1975 t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
1976 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1977 \
1978 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1979 float_invalid_op_div(env, sfprf, GETPC(), \
1980 tp##_classify(xa->fld) | \
1981 tp##_classify(xb->fld)); \
1982 } \
1983 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1984 float_zero_divide_excp(env, GETPC()); \
1985 } \
1986 \
1987 if (r2sp) { \
1988 t.fld = helper_frsp(env, t.fld); \
1989 } \
1990 \
1991 if (sfprf) { \
1992 helper_compute_fprf_float64(env, t.fld); \
1993 } \
1994 } \
1995 \
1996 *xt = t; \
1997 do_float_check_status(env, GETPC()); \
1998 }
1999
2000 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
2001 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
2002 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
2003 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
2004
2005 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
2006 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
2007 {
2008 ppc_vsr_t t = *xt;
2009 float_status tstat;
2010
2011 helper_reset_fpstatus(env);
2012 tstat = env->fp_status;
2013 if (unlikely(Rc(opcode) != 0)) {
2014 tstat.float_rounding_mode = float_round_to_odd;
2015 }
2016
2017 set_float_exception_flags(0, &tstat);
2018 t.f128 = float128_div(xa->f128, xb->f128, &tstat);
2019 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2020
2021 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
2022 float_invalid_op_div(env, 1, GETPC(),
2023 float128_classify(xa->f128) |
2024 float128_classify(xb->f128));
2025 }
2026 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
2027 float_zero_divide_excp(env, GETPC());
2028 }
2029
2030 helper_compute_fprf_float128(env, t.f128);
2031 *xt = t;
2032 do_float_check_status(env, GETPC());
2033 }
2034
2035 /*
2036 * VSX_RE - VSX floating point reciprocal estimate
2037 * op - instruction mnemonic
2038 * nels - number of elements (1, 2 or 4)
2039 * tp - type (float32 or float64)
2040 * fld - vsr_t field (VsrD(*) or VsrW(*))
2041 * sfprf - set FPRF
2042 */
2043 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
2044 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2045 { \
2046 ppc_vsr_t t = *xt; \
2047 int i; \
2048 \
2049 helper_reset_fpstatus(env); \
2050 \
2051 for (i = 0; i < nels; i++) { \
2052 if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2053 float_invalid_op_vxsnan(env, GETPC()); \
2054 } \
2055 t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
2056 \
2057 if (r2sp) { \
2058 t.fld = helper_frsp(env, t.fld); \
2059 } \
2060 \
2061 if (sfprf) { \
2062 helper_compute_fprf_float64(env, t.fld); \
2063 } \
2064 } \
2065 \
2066 *xt = t; \
2067 do_float_check_status(env, GETPC()); \
2068 }
2069
2070 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
2071 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
2072 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
2073 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
2074
2075 /*
2076 * VSX_SQRT - VSX floating point square root
2077 * op - instruction mnemonic
2078 * nels - number of elements (1, 2 or 4)
2079 * tp - type (float32 or float64)
2080 * fld - vsr_t field (VsrD(*) or VsrW(*))
2081 * sfprf - set FPRF
2082 */
2083 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
2084 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2085 { \
2086 ppc_vsr_t t = *xt; \
2087 int i; \
2088 \
2089 helper_reset_fpstatus(env); \
2090 \
2091 for (i = 0; i < nels; i++) { \
2092 float_status tstat = env->fp_status; \
2093 set_float_exception_flags(0, &tstat); \
2094 t.fld = tp##_sqrt(xb->fld, &tstat); \
2095 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2096 \
2097 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2098 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
2099 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
2100 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
2101 float_invalid_op_vxsnan(env, GETPC()); \
2102 } \
2103 } \
2104 \
2105 if (r2sp) { \
2106 t.fld = helper_frsp(env, t.fld); \
2107 } \
2108 \
2109 if (sfprf) { \
2110 helper_compute_fprf_float64(env, t.fld); \
2111 } \
2112 } \
2113 \
2114 *xt = t; \
2115 do_float_check_status(env, GETPC()); \
2116 }
2117
2118 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
2119 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
2120 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
2121 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
2122
2123 /*
2124 *VSX_RSQRTE - VSX floating point reciprocal square root estimate
2125 * op - instruction mnemonic
2126 * nels - number of elements (1, 2 or 4)
2127 * tp - type (float32 or float64)
2128 * fld - vsr_t field (VsrD(*) or VsrW(*))
2129 * sfprf - set FPRF
2130 */
2131 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
2132 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2133 { \
2134 ppc_vsr_t t = *xt; \
2135 int i; \
2136 \
2137 helper_reset_fpstatus(env); \
2138 \
2139 for (i = 0; i < nels; i++) { \
2140 float_status tstat = env->fp_status; \
2141 set_float_exception_flags(0, &tstat); \
2142 t.fld = tp##_sqrt(xb->fld, &tstat); \
2143 t.fld = tp##_div(tp##_one, t.fld, &tstat); \
2144 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2145 \
2146 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2147 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
2148 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
2149 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
2150 float_invalid_op_vxsnan(env, GETPC()); \
2151 } \
2152 } \
2153 \
2154 if (r2sp) { \
2155 t.fld = helper_frsp(env, t.fld); \
2156 } \
2157 \
2158 if (sfprf) { \
2159 helper_compute_fprf_float64(env, t.fld); \
2160 } \
2161 } \
2162 \
2163 *xt = t; \
2164 do_float_check_status(env, GETPC()); \
2165 }
2166
2167 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
2168 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
2169 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
2170 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
2171
2172 /*
2173 * VSX_TDIV - VSX floating point test for divide
2174 * op - instruction mnemonic
2175 * nels - number of elements (1, 2 or 4)
2176 * tp - type (float32 or float64)
2177 * fld - vsr_t field (VsrD(*) or VsrW(*))
2178 * emin - minimum unbiased exponent
2179 * emax - maximum unbiased exponent
2180 * nbits - number of fraction bits
2181 */
2182 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
2183 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2184 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2185 { \
2186 int i; \
2187 int fe_flag = 0; \
2188 int fg_flag = 0; \
2189 \
2190 for (i = 0; i < nels; i++) { \
2191 if (unlikely(tp##_is_infinity(xa->fld) || \
2192 tp##_is_infinity(xb->fld) || \
2193 tp##_is_zero(xb->fld))) { \
2194 fe_flag = 1; \
2195 fg_flag = 1; \
2196 } else { \
2197 int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
2198 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2199 \
2200 if (unlikely(tp##_is_any_nan(xa->fld) || \
2201 tp##_is_any_nan(xb->fld))) { \
2202 fe_flag = 1; \
2203 } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
2204 fe_flag = 1; \
2205 } else if (!tp##_is_zero(xa->fld) && \
2206 (((e_a - e_b) >= emax) || \
2207 ((e_a - e_b) <= (emin + 1)) || \
2208 (e_a <= (emin + nbits)))) { \
2209 fe_flag = 1; \
2210 } \
2211 \
2212 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2213 /* \
2214 * XB is not zero because of the above check and so \
2215 * must be denormalized. \
2216 */ \
2217 fg_flag = 1; \
2218 } \
2219 } \
2220 } \
2221 \
2222 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2223 }
2224
2225 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2226 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2227 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2228
2229 /*
2230 * VSX_TSQRT - VSX floating point test for square root
2231 * op - instruction mnemonic
2232 * nels - number of elements (1, 2 or 4)
2233 * tp - type (float32 or float64)
2234 * fld - vsr_t field (VsrD(*) or VsrW(*))
2235 * emin - minimum unbiased exponent
2236 * emax - maximum unbiased exponent
2237 * nbits - number of fraction bits
2238 */
2239 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2240 void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
2241 { \
2242 int i; \
2243 int fe_flag = 0; \
2244 int fg_flag = 0; \
2245 \
2246 for (i = 0; i < nels; i++) { \
2247 if (unlikely(tp##_is_infinity(xb->fld) || \
2248 tp##_is_zero(xb->fld))) { \
2249 fe_flag = 1; \
2250 fg_flag = 1; \
2251 } else { \
2252 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2253 \
2254 if (unlikely(tp##_is_any_nan(xb->fld))) { \
2255 fe_flag = 1; \
2256 } else if (unlikely(tp##_is_zero(xb->fld))) { \
2257 fe_flag = 1; \
2258 } else if (unlikely(tp##_is_neg(xb->fld))) { \
2259 fe_flag = 1; \
2260 } else if (!tp##_is_zero(xb->fld) && \
2261 (e_b <= (emin + nbits))) { \
2262 fe_flag = 1; \
2263 } \
2264 \
2265 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2266 /* \
2267 * XB is not zero because of the above check and \
2268 * therefore must be denormalized. \
2269 */ \
2270 fg_flag = 1; \
2271 } \
2272 } \
2273 } \
2274 \
2275 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2276 }
2277
2278 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2279 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2280 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2281
2282 /*
2283 * VSX_MADD - VSX floating point muliply/add variations
2284 * op - instruction mnemonic
2285 * nels - number of elements (1, 2 or 4)
2286 * tp - type (float32 or float64)
2287 * fld - vsr_t field (VsrD(*) or VsrW(*))
2288 * maddflgs - flags for the float*muladd routine that control the
2289 * various forms (madd, msub, nmadd, nmsub)
2290 * sfprf - set FPRF
2291 */
2292 #define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
2293 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2294 ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
2295 { \
2296 ppc_vsr_t t = *xt; \
2297 int i; \
2298 \
2299 helper_reset_fpstatus(env); \
2300 \
2301 for (i = 0; i < nels; i++) { \
2302 float_status tstat = env->fp_status; \
2303 set_float_exception_flags(0, &tstat); \
2304 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2305 /* \
2306 * Avoid double rounding errors by rounding the intermediate \
2307 * result to odd. \
2308 */ \
2309 set_float_rounding_mode(float_round_to_zero, &tstat); \
2310 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2311 maddflgs, &tstat); \
2312 t.fld |= (get_float_exception_flags(&tstat) & \
2313 float_flag_inexact) != 0; \
2314 } else { \
2315 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2316 maddflgs, &tstat); \
2317 } \
2318 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2319 \
2320 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2321 tp##_maddsub_update_excp(env, xa->fld, b->fld, \
2322 c->fld, maddflgs, GETPC()); \
2323 } \
2324 \
2325 if (r2sp) { \
2326 t.fld = helper_frsp(env, t.fld); \
2327 } \
2328 \
2329 if (sfprf) { \
2330 helper_compute_fprf_float64(env, t.fld); \
2331 } \
2332 } \
2333 *xt = t; \
2334 do_float_check_status(env, GETPC()); \
2335 }
2336
2337 VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
2338 VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
2339 VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
2340 VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
2341 VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
2342 VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
2343 VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
2344 VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
2345
2346 VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
2347 VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
2348 VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0)
2349 VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0)
2350
2351 VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0)
2352 VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
2353 VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
2354 VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
2355
2356 /*
2357 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2358 * op - instruction mnemonic
2359 * cmp - comparison operation
2360 * exp - expected result of comparison
2361 * svxvc - set VXVC bit
2362 */
2363 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
2364 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2365 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2366 { \
2367 ppc_vsr_t t = *xt; \
2368 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2369 \
2370 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2371 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2372 vxsnan_flag = true; \
2373 if (fpscr_ve == 0 && svxvc) { \
2374 vxvc_flag = true; \
2375 } \
2376 } else if (svxvc) { \
2377 vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2378 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
2379 } \
2380 if (vxsnan_flag) { \
2381 float_invalid_op_vxsnan(env, GETPC()); \
2382 } \
2383 if (vxvc_flag) { \
2384 float_invalid_op_vxvc(env, 0, GETPC()); \
2385 } \
2386 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2387 \
2388 if (!vex_flag) { \
2389 if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
2390 &env->fp_status) == exp) { \
2391 t.VsrD(0) = -1; \
2392 t.VsrD(1) = 0; \
2393 } else { \
2394 t.VsrD(0) = 0; \
2395 t.VsrD(1) = 0; \
2396 } \
2397 } \
2398 *xt = t; \
2399 do_float_check_status(env, GETPC()); \
2400 }
2401
2402 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2403 VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2404 VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2405 VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2406
2407 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
2408 ppc_vsr_t *xa, ppc_vsr_t *xb)
2409 {
2410 int64_t exp_a, exp_b;
2411 uint32_t cc;
2412
2413 exp_a = extract64(xa->VsrD(0), 52, 11);
2414 exp_b = extract64(xb->VsrD(0), 52, 11);
2415
2416 if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||
2417 float64_is_any_nan(xb->VsrD(0)))) {
2418 cc = CRF_SO;
2419 } else {
2420 if (exp_a < exp_b) {
2421 cc = CRF_LT;
2422 } else if (exp_a > exp_b) {
2423 cc = CRF_GT;
2424 } else {
2425 cc = CRF_EQ;
2426 }
2427 }
2428
2429 env->fpscr &= ~(0x0F << FPSCR_FPRF);
2430 env->fpscr |= cc << FPSCR_FPRF;
2431 env->crf[BF(opcode)] = cc;
2432
2433 do_float_check_status(env, GETPC());
2434 }
2435
2436 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,
2437 ppc_vsr_t *xa, ppc_vsr_t *xb)
2438 {
2439 int64_t exp_a, exp_b;
2440 uint32_t cc;
2441
2442 exp_a = extract64(xa->VsrD(0), 48, 15);
2443 exp_b = extract64(xb->VsrD(0), 48, 15);
2444
2445 if (unlikely(float128_is_any_nan(xa->f128) ||
2446 float128_is_any_nan(xb->f128))) {
2447 cc = CRF_SO;
2448 } else {
2449 if (exp_a < exp_b) {
2450 cc = CRF_LT;
2451 } else if (exp_a > exp_b) {
2452 cc = CRF_GT;
2453 } else {
2454 cc = CRF_EQ;
2455 }
2456 }
2457
2458 env->fpscr &= ~(0x0F << FPSCR_FPRF);
2459 env->fpscr |= cc << FPSCR_FPRF;
2460 env->crf[BF(opcode)] = cc;
2461
2462 do_float_check_status(env, GETPC());
2463 }
2464
2465 #define VSX_SCALAR_CMP(op, ordered) \
2466 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2467 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2468 { \
2469 uint32_t cc = 0; \
2470 bool vxsnan_flag = false, vxvc_flag = false; \
2471 \
2472 helper_reset_fpstatus(env); \
2473 \
2474 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2475 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2476 vxsnan_flag = true; \
2477 cc = CRF_SO; \
2478 if (fpscr_ve == 0 && ordered) { \
2479 vxvc_flag = true; \
2480 } \
2481 } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2482 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \
2483 cc = CRF_SO; \
2484 if (ordered) { \
2485 vxvc_flag = true; \
2486 } \
2487 } \
2488 if (vxsnan_flag) { \
2489 float_invalid_op_vxsnan(env, GETPC()); \
2490 } \
2491 if (vxvc_flag) { \
2492 float_invalid_op_vxvc(env, 0, GETPC()); \
2493 } \
2494 \
2495 if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \
2496 cc |= CRF_LT; \
2497 } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \
2498 cc |= CRF_GT; \
2499 } else { \
2500 cc |= CRF_EQ; \
2501 } \
2502 \
2503 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2504 env->fpscr |= cc << FPSCR_FPRF; \
2505 env->crf[BF(opcode)] = cc; \
2506 \
2507 do_float_check_status(env, GETPC()); \
2508 }
2509
2510 VSX_SCALAR_CMP(xscmpodp, 1)
2511 VSX_SCALAR_CMP(xscmpudp, 0)
2512
2513 #define VSX_SCALAR_CMPQ(op, ordered) \
2514 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2515 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2516 { \
2517 uint32_t cc = 0; \
2518 bool vxsnan_flag = false, vxvc_flag = false; \
2519 \
2520 helper_reset_fpstatus(env); \
2521 \
2522 if (float128_is_signaling_nan(xa->f128, &env->fp_status) || \
2523 float128_is_signaling_nan(xb->f128, &env->fp_status)) { \
2524 vxsnan_flag = true; \
2525 cc = CRF_SO; \
2526 if (fpscr_ve == 0 && ordered) { \
2527 vxvc_flag = true; \
2528 } \
2529 } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) || \
2530 float128_is_quiet_nan(xb->f128, &env->fp_status)) { \
2531 cc = CRF_SO; \
2532 if (ordered) { \
2533 vxvc_flag = true; \
2534 } \
2535 } \
2536 if (vxsnan_flag) { \
2537 float_invalid_op_vxsnan(env, GETPC()); \
2538 } \
2539 if (vxvc_flag) { \
2540 float_invalid_op_vxvc(env, 0, GETPC()); \
2541 } \
2542 \
2543 if (float128_lt(xa->f128, xb->f128, &env->fp_status)) { \
2544 cc |= CRF_LT; \
2545 } else if (!float128_le(xa->f128, xb->f128, &env->fp_status)) { \
2546 cc |= CRF_GT; \
2547 } else { \
2548 cc |= CRF_EQ; \
2549 } \
2550 \
2551 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2552 env->fpscr |= cc << FPSCR_FPRF; \
2553 env->crf[BF(opcode)] = cc; \
2554 \
2555 do_float_check_status(env, GETPC()); \
2556 }
2557
2558 VSX_SCALAR_CMPQ(xscmpoqp, 1)
2559 VSX_SCALAR_CMPQ(xscmpuqp, 0)
2560
2561 /*
2562 * VSX_MAX_MIN - VSX floating point maximum/minimum
2563 * name - instruction mnemonic
2564 * op - operation (max or min)
2565 * nels - number of elements (1, 2 or 4)
2566 * tp - type (float32 or float64)
2567 * fld - vsr_t field (VsrD(*) or VsrW(*))
2568 */
2569 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2570 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
2571 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2572 { \
2573 ppc_vsr_t t = *xt; \
2574 int i; \
2575 \
2576 for (i = 0; i < nels; i++) { \
2577 t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2578 if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2579 tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2580 float_invalid_op_vxsnan(env, GETPC()); \
2581 } \
2582 } \
2583 \
2584 *xt = t; \
2585 do_float_check_status(env, GETPC()); \
2586 }
2587
2588 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2589 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2590 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2591 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2592 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2593 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2594
2595 #define VSX_MAX_MINC(name, max) \
2596 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2597 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2598 { \
2599 ppc_vsr_t t = *xt; \
2600 bool vxsnan_flag = false, vex_flag = false; \
2601 \
2602 if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
2603 float64_is_any_nan(xb->VsrD(0)))) { \
2604 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2605 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2606 vxsnan_flag = true; \
2607 } \
2608 t.VsrD(0) = xb->VsrD(0); \
2609 } else if ((max && \
2610 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2611 (!max && \
2612 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2613 t.VsrD(0) = xa->VsrD(0); \
2614 } else { \
2615 t.VsrD(0) = xb->VsrD(0); \
2616 } \
2617 \
2618 vex_flag = fpscr_ve & vxsnan_flag; \
2619 if (vxsnan_flag) { \
2620 float_invalid_op_vxsnan(env, GETPC()); \
2621 } \
2622 if (!vex_flag) { \
2623 *xt = t; \
2624 } \
2625 } \
2626
2627 VSX_MAX_MINC(xsmaxcdp, 1);
2628 VSX_MAX_MINC(xsmincdp, 0);
2629
2630 #define VSX_MAX_MINJ(name, max) \
2631 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2632 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2633 { \
2634 ppc_vsr_t t = *xt; \
2635 bool vxsnan_flag = false, vex_flag = false; \
2636 \
2637 if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2638 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
2639 vxsnan_flag = true; \
2640 } \
2641 t.VsrD(0) = xa->VsrD(0); \
2642 } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2643 if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2644 vxsnan_flag = true; \
2645 } \
2646 t.VsrD(0) = xb->VsrD(0); \
2647 } else if (float64_is_zero(xa->VsrD(0)) && \
2648 float64_is_zero(xb->VsrD(0))) { \
2649 if (max) { \
2650 if (!float64_is_neg(xa->VsrD(0)) || \
2651 !float64_is_neg(xb->VsrD(0))) { \
2652 t.VsrD(0) = 0ULL; \
2653 } else { \
2654 t.VsrD(0) = 0x8000000000000000ULL; \
2655 } \
2656 } else { \
2657 if (float64_is_neg(xa->VsrD(0)) || \
2658 float64_is_neg(xb->VsrD(0))) { \
2659 t.VsrD(0) = 0x8000000000000000ULL; \
2660 } else { \
2661 t.VsrD(0) = 0ULL; \
2662 } \
2663 } \
2664 } else if ((max && \
2665 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2666 (!max && \
2667 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2668 t.VsrD(0) = xa->VsrD(0); \
2669 } else { \
2670 t.VsrD(0) = xb->VsrD(0); \
2671 } \
2672 \
2673 vex_flag = fpscr_ve & vxsnan_flag; \
2674 if (vxsnan_flag) { \
2675 float_invalid_op_vxsnan(env, GETPC()); \
2676 } \
2677 if (!vex_flag) { \
2678 *xt = t; \
2679 } \
2680 } \
2681
2682 VSX_MAX_MINJ(xsmaxjdp, 1);
2683 VSX_MAX_MINJ(xsminjdp, 0);
2684
2685 /*
2686 * VSX_CMP - VSX floating point compare
2687 * op - instruction mnemonic
2688 * nels - number of elements (1, 2 or 4)
2689 * tp - type (float32 or float64)
2690 * fld - vsr_t field (VsrD(*) or VsrW(*))
2691 * cmp - comparison operation
2692 * svxvc - set VXVC bit
2693 * exp - expected result of comparison
2694 */
2695 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
2696 uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2697 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2698 { \
2699 ppc_vsr_t t = *xt; \
2700 uint32_t crf6 = 0; \
2701 int i; \
2702 int all_true = 1; \
2703 int all_false = 1; \
2704 \
2705 for (i = 0; i < nels; i++) { \
2706 if (unlikely(tp##_is_any_nan(xa->fld) || \
2707 tp##_is_any_nan(xb->fld))) { \
2708 if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2709 tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
2710 float_invalid_op_vxsnan(env, GETPC()); \
2711 } \
2712 if (svxvc) { \
2713 float_invalid_op_vxvc(env, 0, GETPC()); \
2714 } \
2715 t.fld = 0; \
2716 all_true = 0; \
2717 } else { \
2718 if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2719 t.fld = -1; \
2720 all_false = 0; \
2721 } else { \
2722 t.fld = 0; \
2723 all_true = 0; \
2724 } \
2725 } \
2726 } \
2727 \
2728 *xt = t; \
2729 crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2730 return crf6; \
2731 }
2732
2733 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2734 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2735 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2736 VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2737 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2738 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2739 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2740 VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
2741
2742 /*
2743 * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2744 * op - instruction mnemonic
2745 * nels - number of elements (1, 2 or 4)
2746 * stp - source type (float32 or float64)
2747 * ttp - target type (float32 or float64)
2748 * sfld - source vsr_t field
2749 * tfld - target vsr_t field (f32 or f64)
2750 * sfprf - set FPRF
2751 */
2752 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2753 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2754 { \
2755 ppc_vsr_t t = *xt; \
2756 int i; \
2757 \
2758 for (i = 0; i < nels; i++) { \
2759 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2760 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2761 &env->fp_status))) { \
2762 float_invalid_op_vxsnan(env, GETPC()); \
2763 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2764 } \
2765 if (sfprf) { \
2766 helper_compute_fprf_##ttp(env, t.tfld); \
2767 } \
2768 } \
2769 \
2770 *xt = t; \
2771 do_float_check_status(env, GETPC()); \
2772 }
2773
2774 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2775 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2776 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
2777 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
2778
2779 /*
2780 * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2781 * op - instruction mnemonic
2782 * nels - number of elements (1, 2 or 4)
2783 * stp - source type (float32 or float64)
2784 * ttp - target type (float32 or float64)
2785 * sfld - source vsr_t field
2786 * tfld - target vsr_t field (f32 or f64)
2787 * sfprf - set FPRF
2788 */
2789 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
2790 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2791 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2792 { \
2793 ppc_vsr_t t = *xt; \
2794 int i; \
2795 \
2796 for (i = 0; i < nels; i++) { \
2797 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2798 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2799 &env->fp_status))) { \
2800 float_invalid_op_vxsnan(env, GETPC()); \
2801 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2802 } \
2803 if (sfprf) { \
2804 helper_compute_fprf_##ttp(env, t.tfld); \
2805 } \
2806 } \
2807 \
2808 *xt = t; \
2809 do_float_check_status(env, GETPC()); \
2810 }
2811
2812 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2813
2814 /*
2815 * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2816 * involving one half precision value
2817 * op - instruction mnemonic
2818 * nels - number of elements (1, 2 or 4)
2819 * stp - source type
2820 * ttp - target type
2821 * sfld - source vsr_t field
2822 * tfld - target vsr_t field
2823 * sfprf - set FPRF
2824 */
2825 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2826 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2827 { \
2828 ppc_vsr_t t = { }; \
2829 int i; \
2830 \
2831 for (i = 0; i < nels; i++) { \
2832 t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2833 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2834 &env->fp_status))) { \
2835 float_invalid_op_vxsnan(env, GETPC()); \
2836 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2837 } \
2838 if (sfprf) { \
2839 helper_compute_fprf_##ttp(env, t.tfld); \
2840 } \
2841 } \
2842 \
2843 *xt = t; \
2844 do_float_check_status(env, GETPC()); \
2845 }
2846
2847 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2848 VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2849 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
2850 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2851
2852 /*
2853 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2854 * added to this later.
2855 */
2856 void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
2857 ppc_vsr_t *xt, ppc_vsr_t *xb)
2858 {
2859 ppc_vsr_t t = { };
2860 float_status tstat;
2861
2862 tstat = env->fp_status;
2863 if (unlikely(Rc(opcode) != 0)) {
2864 tstat.float_rounding_mode = float_round_to_odd;
2865 }
2866
2867 t.VsrD(0) = float128_to_float64(xb->f128, &tstat);
2868 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2869 if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) {
2870 float_invalid_op_vxsnan(env, GETPC());
2871 t.VsrD(0) = float64_snan_to_qnan(t.VsrD(0));
2872 }
2873 helper_compute_fprf_float64(env, t.VsrD(0));
2874
2875 *xt = t;
2876 do_float_check_status(env, GETPC());
2877 }
2878
2879 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2880 {
2881 uint64_t result;
2882
2883 float_status tstat = env->fp_status;
2884 set_float_exception_flags(0, &tstat);
2885
2886 result = (uint64_t)float64_to_float32(xb, &tstat);
2887 /* hardware replicates result to both words of the doubleword result. */
2888 return (result << 32) | result;
2889 }
2890
2891 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2892 {
2893 float_status tstat = env->fp_status;
2894 set_float_exception_flags(0, &tstat);
2895
2896 return float32_to_float64(xb >> 32, &tstat);
2897 }
2898
2899 /*
2900 * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2901 * op - instruction mnemonic
2902 * nels - number of elements (1, 2 or 4)
2903 * stp - source type (float32 or float64)
2904 * ttp - target type (int32, uint32, int64 or uint64)
2905 * sfld - source vsr_t field
2906 * tfld - target vsr_t field
2907 * rnan - resulting NaN
2908 */
2909 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2910 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2911 { \
2912 int all_flags = env->fp_status.float_exception_flags, flags; \
2913 ppc_vsr_t t = *xt; \
2914 int i; \
2915 \
2916 for (i = 0; i < nels; i++) { \
2917 env->fp_status.float_exception_flags = 0; \
2918 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2919 flags = env->fp_status.float_exception_flags; \
2920 if (unlikely(flags & float_flag_invalid)) { \
2921 float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
2922 t.tfld = rnan; \
2923 } \
2924 all_flags |= flags; \
2925 } \
2926 \
2927 *xt = t; \
2928 env->fp_status.float_exception_flags = all_flags; \
2929 do_float_check_status(env, GETPC()); \
2930 }
2931
2932 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2933 0x8000000000000000ULL)
2934 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2935 0x80000000U)
2936 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2937 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2938 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2939 0x8000000000000000ULL)
2940 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
2941 0x80000000U)
2942 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2943 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
2944 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
2945 0x8000000000000000ULL)
2946 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2947 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
2948 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2949
2950 /*
2951 * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
2952 * op - instruction mnemonic
2953 * stp - source type (float32 or float64)
2954 * ttp - target type (int32, uint32, int64 or uint64)
2955 * sfld - source vsr_t field
2956 * tfld - target vsr_t field
2957 * rnan - resulting NaN
2958 */
2959 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
2960 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2961 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2962 { \
2963 ppc_vsr_t t = { }; \
2964 \
2965 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2966 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2967 float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
2968 t.tfld = rnan; \
2969 } \
2970 \
2971 *xt = t; \
2972 do_float_check_status(env, GETPC()); \
2973 }
2974
2975 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
2976 0x8000000000000000ULL)
2977
2978 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
2979 0xffffffff80000000ULL)
2980 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2981 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
2982
2983 /*
2984 * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2985 * op - instruction mnemonic
2986 * nels - number of elements (1, 2 or 4)
2987 * stp - source type (int32, uint32, int64 or uint64)
2988 * ttp - target type (float32 or float64)
2989 * sfld - source vsr_t field
2990 * tfld - target vsr_t field
2991 * jdef - definition of the j index (i or 2*i)
2992 * sfprf - set FPRF
2993 */
2994 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
2995 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2996 { \
2997 ppc_vsr_t t = *xt; \
2998 int i; \
2999 \
3000 for (i = 0; i < nels; i++) { \
3001 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
3002 if (r2sp) { \
3003 t.tfld = helper_frsp(env, t.tfld); \
3004 } \
3005 if (sfprf) { \
3006 helper_compute_fprf_float64(env, t.tfld); \
3007 } \
3008 } \
3009 \
3010 *xt = t; \
3011 do_float_check_status(env, GETPC()); \
3012 }
3013
3014 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
3015 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
3016 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
3017 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
3018 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
3019 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
3020 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
3021 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
3022 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
3023 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
3024 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
3025 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
3026
3027 /*
3028 * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
3029 * op - instruction mnemonic
3030 * stp - source type (int32, uint32, int64 or uint64)
3031 * ttp - target type (float32 or float64)
3032 * sfld - source vsr_t field
3033 * tfld - target vsr_t field
3034 */
3035 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
3036 void helper_##op(CPUPPCState *env, uint32_t opcode, \
3037 ppc_vsr_t *xt, ppc_vsr_t *xb) \
3038 { \
3039 ppc_vsr_t t = *xt; \
3040 \
3041 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
3042 helper_compute_fprf_##ttp(env, t.tfld); \
3043 \
3044 *xt = t; \
3045 do_float_check_status(env, GETPC()); \
3046 }
3047
3048 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
3049 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
3050
3051 /*
3052 * For "use current rounding mode", define a value that will not be
3053 * one of the existing rounding model enums.
3054 */
3055 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
3056 float_round_up + float_round_to_zero)
3057
3058 /*
3059 * VSX_ROUND - VSX floating point round
3060 * op - instruction mnemonic
3061 * nels - number of elements (1, 2 or 4)
3062 * tp - type (float32 or float64)
3063 * fld - vsr_t field (VsrD(*) or VsrW(*))
3064 * rmode - rounding mode
3065 * sfprf - set FPRF
3066 */
3067 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
3068 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
3069 { \
3070 ppc_vsr_t t = *xt; \
3071 int i; \
3072 \
3073 if (rmode != FLOAT_ROUND_CURRENT) { \
3074 set_float_rounding_mode(rmode, &env->fp_status); \
3075 } \
3076 \
3077 for (i = 0; i < nels; i++) { \
3078 if (unlikely(tp##_is_signaling_nan(xb->fld, \
3079 &env->fp_status))) { \
3080 float_invalid_op_vxsnan(env, GETPC()); \
3081 t.fld = tp##_snan_to_qnan(xb->fld); \
3082 } else { \
3083 t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
3084 } \
3085 if (sfprf) { \
3086 helper_compute_fprf_float64(env, t.fld); \
3087 } \
3088 } \
3089 \
3090 /* \
3091 * If this is not a "use current rounding mode" instruction, \
3092 * then inhibit setting of the XX bit and restore rounding \
3093 * mode from FPSCR \
3094 */ \
3095 if (rmode != FLOAT_ROUND_CURRENT) { \
3096 fpscr_set_rounding_mode(env); \
3097 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
3098 } \
3099 \
3100 *xt = t; \
3101 do_float_check_status(env, GETPC()); \
3102 }
3103
3104 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
3105 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
3106 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
3107 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
3108 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
3109
3110 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
3111 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
3112 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
3113 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
3114 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
3115
3116 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
3117 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
3118 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
3119 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
3120 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
3121
3122 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
3123 {
3124 helper_reset_fpstatus(env);
3125
3126 uint64_t xt = helper_frsp(env, xb);
3127
3128 helper_compute_fprf_float64(env, xt);
3129 do_float_check_status(env, GETPC());
3130 return xt;
3131 }
3132
3133 #define VSX_XXPERM(op, indexed) \
3134 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
3135 ppc_vsr_t *xa, ppc_vsr_t *pcv) \
3136 { \
3137 ppc_vsr_t t = *xt; \
3138 int i, idx; \
3139 \
3140 for (i = 0; i < 16; i++) { \
3141 idx = pcv->VsrB(i) & 0x1F; \
3142 if (indexed) { \
3143 idx = 31 - idx; \
3144 } \
3145 t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
3146 : xt->VsrB(idx - 16); \
3147 } \
3148 *xt = t; \
3149 }
3150
3151 VSX_XXPERM(xxperm, 0)
3152 VSX_XXPERM(xxpermr, 1)
3153
3154 void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
3155 {
3156 ppc_vsr_t t = { };
3157 uint32_t exp, i, fraction;
3158
3159 for (i = 0; i < 4; i++) {
3160 exp = (xb->VsrW(i) >> 23) & 0xFF;
3161 fraction = xb->VsrW(i) & 0x7FFFFF;
3162 if (exp != 0 && exp != 255) {
3163 t.VsrW(i) = fraction | 0x00800000;
3164 } else {
3165 t.VsrW(i) = fraction;
3166 }
3167 }
3168 *xt = t;
3169 }
3170
3171 /*
3172 * VSX_TEST_DC - VSX floating point test data class
3173 * op - instruction mnemonic
3174 * nels - number of elements (1, 2 or 4)
3175 * xbn - VSR register number
3176 * tp - type (float32 or float64)
3177 * fld - vsr_t field (VsrD(*) or VsrW(*))
3178 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3179 * fld_max - target field max
3180 * scrf - set result in CR and FPCC
3181 */
3182 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
3183 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3184 { \
3185 ppc_vsr_t *xt = &env->vsr[xT(opcode)]; \
3186 ppc_vsr_t *xb = &env->vsr[xbn]; \
3187 ppc_vsr_t t = { }; \
3188 uint32_t i, sign, dcmx; \
3189 uint32_t cc, match = 0; \
3190 \
3191 if (!scrf) { \
3192 dcmx = DCMX_XV(opcode); \
3193 } else { \
3194 t = *xt; \
3195 dcmx = DCMX(opcode); \
3196 } \
3197 \
3198 for (i = 0; i < nels; i++) { \
3199 sign = tp##_is_neg(xb->fld); \
3200 if (tp##_is_any_nan(xb->fld)) { \
3201 match = extract32(dcmx, 6, 1); \
3202 } else if (tp##_is_infinity(xb->fld)) { \
3203 match = extract32(dcmx, 4 + !sign, 1); \
3204 } else if (tp##_is_zero(xb->fld)) { \
3205 match = extract32(dcmx, 2 + !sign, 1); \
3206 } else if (tp##_is_zero_or_denormal(xb->fld)) { \
3207 match = extract32(dcmx, 0 + !sign, 1); \
3208 } \
3209 \
3210 if (scrf) { \
3211 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3212 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
3213 env->fpscr |= cc << FPSCR_FPRF; \
3214 env->crf[BF(opcode)] = cc; \
3215 } else { \
3216 t.tfld = match ? fld_max : 0; \
3217 } \
3218 match = 0; \
3219 } \
3220 if (!scrf) { \
3221 *xt = t; \
3222 } \
3223 }
3224
3225 VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3226 VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3227 VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3228 VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3229
3230 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
3231 {
3232 uint32_t dcmx, sign, exp;
3233 uint32_t cc, match = 0, not_sp = 0;
3234
3235 dcmx = DCMX(opcode);
3236 exp = (xb->VsrD(0) >> 52) & 0x7FF;
3237
3238 sign = float64_is_neg(xb->VsrD(0));
3239 if (float64_is_any_nan(xb->VsrD(0))) {
3240 match = extract32(dcmx, 6, 1);
3241 } else if (float64_is_infinity(xb->VsrD(0))) {
3242 match = extract32(dcmx, 4 + !sign, 1);
3243 } else if (float64_is_zero(xb->VsrD(0))) {
3244 match = extract32(dcmx, 2 + !sign, 1);
3245 } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
3246 (exp > 0 && exp < 0x381)) {
3247 match = extract32(dcmx, 0 + !sign, 1);
3248 }
3249
3250 not_sp = !float64_eq(xb->VsrD(0),
3251 float32_to_float64(
3252 float64_to_float32(xb->VsrD(0), &env->fp_status),
3253 &env->fp_status), &env->fp_status);
3254
3255 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
3256 env->fpscr &= ~(0x0F << FPSCR_FPRF);
3257 env->fpscr |= cc << FPSCR_FPRF;
3258 env->crf[BF(opcode)] = cc;
3259 }
3260
3261 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
3262 ppc_vsr_t *xt, ppc_vsr_t *xb)
3263 {
3264 ppc_vsr_t t = { };
3265 uint8_t r = Rrm(opcode);
3266 uint8_t ex = Rc(opcode);
3267 uint8_t rmc = RMC(opcode);
3268 uint8_t rmode = 0;
3269 float_status tstat;
3270
3271 helper_reset_fpstatus(env);
3272
3273 if (r == 0 && rmc == 0) {
3274 rmode = float_round_ties_away;
3275 } else if (r == 0 && rmc == 0x3) {
3276 rmode = fpscr_rn;
3277 } else if (r == 1) {
3278 switch (rmc) {
3279 case 0:
3280 rmode = float_round_nearest_even;
3281 break;
3282 case 1:
3283 rmode = float_round_to_zero;
3284 break;
3285 case 2:
3286 rmode = float_round_up;
3287 break;
3288 case 3:
3289 rmode = float_round_down;
3290 break;
3291 default:
3292 abort();
3293 }
3294 }
3295
3296 tstat = env->fp_status;
3297 set_float_exception_flags(0, &tstat);
3298 set_float_rounding_mode(rmode, &tstat);
3299 t.f128 = float128_round_to_int(xb->f128, &tstat);
3300 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3301
3302 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3303 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3304 float_invalid_op_vxsnan(env, GETPC());
3305 t.f128 = float128_snan_to_qnan(t.f128);
3306 }
3307 }
3308
3309 if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3310 env->fp_status.float_exception_flags &= ~float_flag_inexact;
3311 }
3312
3313 helper_compute_fprf_float128(env, t.f128);
3314 do_float_check_status(env, GETPC());
3315 *xt = t;
3316 }
3317
3318 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
3319 ppc_vsr_t *xt, ppc_vsr_t *xb)
3320 {
3321 ppc_vsr_t t = { };
3322 uint8_t r = Rrm(opcode);
3323 uint8_t rmc = RMC(opcode);
3324 uint8_t rmode = 0;
3325 floatx80 round_res;
3326 float_status tstat;
3327
3328 helper_reset_fpstatus(env);
3329
3330 if (r == 0 && rmc == 0) {
3331 rmode = float_round_ties_away;
3332 } else if (r == 0 && rmc == 0x3) {
3333 rmode = fpscr_rn;
3334 } else if (r == 1) {
3335 switch (rmc) {
3336 case 0:
3337 rmode = float_round_nearest_even;
3338 break;
3339 case 1:
3340 rmode = float_round_to_zero;
3341 break;
3342 case 2:
3343 rmode = float_round_up;
3344 break;
3345 case 3:
3346 rmode = float_round_down;
3347 break;
3348 default:
3349 abort();
3350 }
3351 }
3352
3353 tstat = env->fp_status;
3354 set_float_exception_flags(0, &tstat);
3355 set_float_rounding_mode(rmode, &tstat);
3356 round_res = float128_to_floatx80(xb->f128, &tstat);
3357 t.f128 = floatx80_to_float128(round_res, &tstat);
3358 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3359
3360 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3361 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3362 float_invalid_op_vxsnan(env, GETPC());
3363 t.f128 = float128_snan_to_qnan(t.f128);
3364 }
3365 }
3366
3367 helper_compute_fprf_float128(env, t.f128);
3368 *xt = t;
3369 do_float_check_status(env, GETPC());
3370 }
3371
3372 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
3373 ppc_vsr_t *xt, ppc_vsr_t *xb)
3374 {
3375 ppc_vsr_t t = { };
3376 float_status tstat;
3377
3378 helper_reset_fpstatus(env);
3379
3380 tstat = env->fp_status;
3381 if (unlikely(Rc(opcode) != 0)) {
3382 tstat.float_rounding_mode = float_round_to_odd;
3383 }
3384
3385 set_float_exception_flags(0, &tstat);
3386 t.f128 = float128_sqrt(xb->f128, &tstat);
3387 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3388
3389 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3390 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3391 float_invalid_op_vxsnan(env, GETPC());
3392 t.f128 = float128_snan_to_qnan(xb->f128);
3393 } else if (float128_is_quiet_nan(xb->f128, &tstat)) {
3394 t.f128 = xb->f128;
3395 } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128)) {
3396 float_invalid_op_vxsqrt(env, 1, GETPC());
3397 t.f128 = float128_default_nan(&env->fp_status);
3398 }
3399 }
3400
3401 helper_compute_fprf_float128(env, t.f128);
3402 *xt = t;
3403 do_float_check_status(env, GETPC());
3404 }
3405
3406 void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
3407 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
3408 {
3409 ppc_vsr_t t = *xt;
3410 float_status tstat;
3411
3412 helper_reset_fpstatus(env);
3413
3414 tstat = env->fp_status;
3415 if (unlikely(Rc(opcode) != 0)) {
3416 tstat.float_rounding_mode = float_round_to_odd;
3417 }
3418
3419 set_float_exception_flags(0, &tstat);
3420 t.f128 = float128_sub(xa->f128, xb->f128, &tstat);
3421 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3422
3423 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3424 float_invalid_op_addsub(env, 1, GETPC(),
3425 float128_classify(xa->f128) |
3426 float128_classify(xb->f128));
3427 }
3428
3429 helper_compute_fprf_float128(env, t.f128);
3430 *xt = t;
3431 do_float_check_status(env, GETPC());
3432 }
AR7 emulation for QEMU