include/exec/cpu_ldst.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2.1 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 /*
  20  * Generate inline load/store functions for all MMU modes (typically
  21  * at least _user and _kernel) as well as _data versions, for all data
  22  * sizes.
  23  *
  24  * Used by target op helpers.
  25  *
  26  * The syntax for the accessors is:
  27  *
  28  * load:  cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
  29  *        cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
  30  *        cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
  31  *
  32  * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
  33  *        cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
  34  *        cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
  35  *
  36  * sign is:
  37  * (empty): for 32 and 64 bit sizes
  38  *   u    : unsigned
  39  *   s    : signed
  40  *
  41  * size is:
  42  *   b: 8 bits
  43  *   w: 16 bits
  44  *   l: 32 bits
  45  *   q: 64 bits
  46  *
  47  * end is:
  48  * (empty): for target native endian, or for 8 bit access
  49  *     _be: for forced big endian
  50  *     _le: for forced little endian
  51  *
  52  * mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
  53  * The "mmuidx" suffix carries an extra mmu_idx argument that specifies
  54  * the index to use; the "data" and "code" suffixes take the index from
  55  * cpu_mmu_index().
  56  */
  57 #ifndef CPU_LDST_H
  58 #define CPU_LDST_H
  59
  60 #if defined(CONFIG_USER_ONLY)
  61 /* sparc32plus has 64bit long but 32bit space address
  62  * this can make bad result with g2h() and h2g()
  63  */
  64 #if TARGET_VIRT_ADDR_SPACE_BITS <= 32
  65 typedef uint32_t abi_ptr;
  66 #define TARGET_ABI_FMT_ptr "%x"
  67 #else
  68 typedef uint64_t abi_ptr;
  69 #define TARGET_ABI_FMT_ptr "%"PRIx64
  70 #endif
  71
  72 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
  73 #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base))
  74
  75 static inline bool guest_addr_valid(abi_ulong x)
  76 {
  77     return x <= GUEST_ADDR_MAX;
  78 }
  79
  80 static inline bool guest_range_valid(abi_ulong start, abi_ulong len)
  81 {
  82     return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1;
  83 }
  84
  85 #define h2g_valid(x) \
  86     (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \
  87      (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX)
  88
  89 #define h2g_nocheck(x) ({ \
  90     uintptr_t __ret = (uintptr_t)(x) - guest_base; \
  91     (abi_ptr)__ret; \
  92 })
  93
  94 #define h2g(x) ({ \
  95     /* Check if given address fits target address space */ \
  96     assert(h2g_valid(x)); \
  97     h2g_nocheck(x); \
  98 })
  99 #else
 100 typedef target_ulong abi_ptr;
 101 #define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
 102 #endif
 103
 104 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
 105 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
 106
 107 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
 108 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
 109 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
 110 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
 111
 112 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
 113 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
 114 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
 115 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
 116
 117 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 118 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 119
 120 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 121 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 122 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 123 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 124
 125 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 126 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 127 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 128 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 129
 130 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 131
 132 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 133 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 134 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 135
 136 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 137 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 138 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 139
 140 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
 141                      uint32_t val, uintptr_t ra);
 142
 143 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
 144                         uint32_t val, uintptr_t ra);
 145 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
 146                         uint32_t val, uintptr_t ra);
 147 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
 148                         uint64_t val, uintptr_t ra);
 149
 150 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
 151                         uint32_t val, uintptr_t ra);
 152 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
 153                         uint32_t val, uintptr_t ra);
 154 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
 155                         uint64_t val, uintptr_t ra);
 156
 157 #if defined(CONFIG_USER_ONLY)
 158
 159 extern __thread uintptr_t helper_retaddr;
 160
 161 static inline void set_helper_retaddr(uintptr_t ra)
 162 {
 163     helper_retaddr = ra;
 164     /*
 165      * Ensure that this write is visible to the SIGSEGV handler that
 166      * may be invoked due to a subsequent invalid memory operation.
 167      */
 168     signal_barrier();
 169 }
 170
 171 static inline void clear_helper_retaddr(void)
 172 {
 173     /*
 174      * Ensure that previous memory operations have succeeded before
 175      * removing the data visible to the signal handler.
 176      */
 177     signal_barrier();
 178     helper_retaddr = 0;
 179 }
 180
 181 /*
 182  * Provide the same *_mmuidx_ra interface as for softmmu.
 183  * The mmu_idx argument is ignored.
 184  */
 185
 186 static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 187                                           int mmu_idx, uintptr_t ra)
 188 {
 189     return cpu_ldub_data_ra(env, addr, ra);
 190 }
 191
 192 static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 193                                      int mmu_idx, uintptr_t ra)
 194 {
 195     return cpu_ldsb_data_ra(env, addr, ra);
 196 }
 197
 198 static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 199                                              int mmu_idx, uintptr_t ra)
 200 {
 201     return cpu_lduw_be_data_ra(env, addr, ra);
 202 }
 203
 204 static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 205                                         int mmu_idx, uintptr_t ra)
 206 {
 207     return cpu_ldsw_be_data_ra(env, addr, ra);
 208 }
 209
 210 static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 211                                             int mmu_idx, uintptr_t ra)
 212 {
 213     return cpu_ldl_be_data_ra(env, addr, ra);
 214 }
 215
 216 static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 217                                             int mmu_idx, uintptr_t ra)
 218 {
 219     return cpu_ldq_be_data_ra(env, addr, ra);
 220 }
 221
 222 static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 223                                              int mmu_idx, uintptr_t ra)
 224 {
 225     return cpu_lduw_le_data_ra(env, addr, ra);
 226 }
 227
 228 static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 229                                         int mmu_idx, uintptr_t ra)
 230 {
 231     return cpu_ldsw_le_data_ra(env, addr, ra);
 232 }
 233
 234 static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 235                                             int mmu_idx, uintptr_t ra)
 236 {
 237     return cpu_ldl_le_data_ra(env, addr, ra);
 238 }
 239
 240 static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 241                                             int mmu_idx, uintptr_t ra)
 242 {
 243     return cpu_ldq_le_data_ra(env, addr, ra);
 244 }
 245
 246 static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 247                                      uint32_t val, int mmu_idx, uintptr_t ra)
 248 {
 249     cpu_stb_data_ra(env, addr, val, ra);
 250 }
 251
 252 static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 253                                         uint32_t val, int mmu_idx,
 254                                         uintptr_t ra)
 255 {
 256     cpu_stw_be_data_ra(env, addr, val, ra);
 257 }
 258
 259 static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 260                                         uint32_t val, int mmu_idx,
 261                                         uintptr_t ra)
 262 {
 263     cpu_stl_be_data_ra(env, addr, val, ra);
 264 }
 265
 266 static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 267                                         uint64_t val, int mmu_idx,
 268                                         uintptr_t ra)
 269 {
 270     cpu_stq_be_data_ra(env, addr, val, ra);
 271 }
 272
 273 static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 274                                         uint32_t val, int mmu_idx,
 275                                         uintptr_t ra)
 276 {
 277     cpu_stw_le_data_ra(env, addr, val, ra);
 278 }
 279
 280 static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 281                                         uint32_t val, int mmu_idx,
 282                                         uintptr_t ra)
 283 {
 284     cpu_stl_le_data_ra(env, addr, val, ra);
 285 }
 286
 287 static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 288                                         uint64_t val, int mmu_idx,
 289                                         uintptr_t ra)
 290 {
 291     cpu_stq_le_data_ra(env, addr, val, ra);
 292 }
 293
 294 #else
 295
 296 /* Needed for TCG_OVERSIZED_GUEST */
 297 #include "tcg/tcg.h"
 298
 299 static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
 300 {
 301 #if TCG_OVERSIZED_GUEST
 302     return entry->addr_write;
 303 #else
 304     return qatomic_read(&entry->addr_write);
 305 #endif
 306 }
 307
 308 /* Find the TLB index corresponding to the mmu_idx + address pair.  */
 309 static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
 310                                   target_ulong addr)
 311 {
 312     uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
 313
 314     return (addr >> TARGET_PAGE_BITS) & size_mask;
 315 }
 316
 317 /* Find the TLB entry corresponding to the mmu_idx + address pair.  */
 318 static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
 319                                      target_ulong addr)
 320 {
 321     return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
 322 }
 323
 324 uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 325                             int mmu_idx, uintptr_t ra);
 326 int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 327                        int mmu_idx, uintptr_t ra);
 328
 329 uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 330                                int mmu_idx, uintptr_t ra);
 331 int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 332                           int mmu_idx, uintptr_t ra);
 333 uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 334                               int mmu_idx, uintptr_t ra);
 335 uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 336                               int mmu_idx, uintptr_t ra);
 337
 338 uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 339                                int mmu_idx, uintptr_t ra);
 340 int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 341                           int mmu_idx, uintptr_t ra);
 342 uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 343                               int mmu_idx, uintptr_t ra);
 344 uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 345                               int mmu_idx, uintptr_t ra);
 346
 347 void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 348                        int mmu_idx, uintptr_t retaddr);
 349
 350 void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 351                           int mmu_idx, uintptr_t retaddr);
 352 void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 353                           int mmu_idx, uintptr_t retaddr);
 354 void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 355                           int mmu_idx, uintptr_t retaddr);
 356
 357 void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 358                           int mmu_idx, uintptr_t retaddr);
 359 void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 360                           int mmu_idx, uintptr_t retaddr);
 361 void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 362                           int mmu_idx, uintptr_t retaddr);
 363
 364 #endif /* defined(CONFIG_USER_ONLY) */
 365
 366 #ifdef TARGET_WORDS_BIGENDIAN
 367 # define cpu_lduw_data        cpu_lduw_be_data
 368 # define cpu_ldsw_data        cpu_ldsw_be_data
 369 # define cpu_ldl_data         cpu_ldl_be_data
 370 # define cpu_ldq_data         cpu_ldq_be_data
 371 # define cpu_lduw_data_ra     cpu_lduw_be_data_ra
 372 # define cpu_ldsw_data_ra     cpu_ldsw_be_data_ra
 373 # define cpu_ldl_data_ra      cpu_ldl_be_data_ra
 374 # define cpu_ldq_data_ra      cpu_ldq_be_data_ra
 375 # define cpu_lduw_mmuidx_ra   cpu_lduw_be_mmuidx_ra
 376 # define cpu_ldsw_mmuidx_ra   cpu_ldsw_be_mmuidx_ra
 377 # define cpu_ldl_mmuidx_ra    cpu_ldl_be_mmuidx_ra
 378 # define cpu_ldq_mmuidx_ra    cpu_ldq_be_mmuidx_ra
 379 # define cpu_stw_data         cpu_stw_be_data
 380 # define cpu_stl_data         cpu_stl_be_data
 381 # define cpu_stq_data         cpu_stq_be_data
 382 # define cpu_stw_data_ra      cpu_stw_be_data_ra
 383 # define cpu_stl_data_ra      cpu_stl_be_data_ra
 384 # define cpu_stq_data_ra      cpu_stq_be_data_ra
 385 # define cpu_stw_mmuidx_ra    cpu_stw_be_mmuidx_ra
 386 # define cpu_stl_mmuidx_ra    cpu_stl_be_mmuidx_ra
 387 # define cpu_stq_mmuidx_ra    cpu_stq_be_mmuidx_ra
 388 #else
 389 # define cpu_lduw_data        cpu_lduw_le_data
 390 # define cpu_ldsw_data        cpu_ldsw_le_data
 391 # define cpu_ldl_data         cpu_ldl_le_data
 392 # define cpu_ldq_data         cpu_ldq_le_data
 393 # define cpu_lduw_data_ra     cpu_lduw_le_data_ra
 394 # define cpu_ldsw_data_ra     cpu_ldsw_le_data_ra
 395 # define cpu_ldl_data_ra      cpu_ldl_le_data_ra
 396 # define cpu_ldq_data_ra      cpu_ldq_le_data_ra
 397 # define cpu_lduw_mmuidx_ra   cpu_lduw_le_mmuidx_ra
 398 # define cpu_ldsw_mmuidx_ra   cpu_ldsw_le_mmuidx_ra
 399 # define cpu_ldl_mmuidx_ra    cpu_ldl_le_mmuidx_ra
 400 # define cpu_ldq_mmuidx_ra    cpu_ldq_le_mmuidx_ra
 401 # define cpu_stw_data         cpu_stw_le_data
 402 # define cpu_stl_data         cpu_stl_le_data
 403 # define cpu_stq_data         cpu_stq_le_data
 404 # define cpu_stw_data_ra      cpu_stw_le_data_ra
 405 # define cpu_stl_data_ra      cpu_stl_le_data_ra
 406 # define cpu_stq_data_ra      cpu_stq_le_data_ra
 407 # define cpu_stw_mmuidx_ra    cpu_stw_le_mmuidx_ra
 408 # define cpu_stl_mmuidx_ra    cpu_stl_le_mmuidx_ra
 409 # define cpu_stq_mmuidx_ra    cpu_stq_le_mmuidx_ra
 410 #endif
 411
 412 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
 413 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
 414 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
 415 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
 416
 417 static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
 418 {
 419     return (int8_t)cpu_ldub_code(env, addr);
 420 }
 421
 422 static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
 423 {
 424     return (int16_t)cpu_lduw_code(env, addr);
 425 }
 426
 427 /**
 428  * tlb_vaddr_to_host:
 429  * @env: CPUArchState
 430  * @addr: guest virtual address to look up
 431  * @access_type: 0 for read, 1 for write, 2 for execute
 432  * @mmu_idx: MMU index to use for lookup
 433  *
 434  * Look up the specified guest virtual index in the TCG softmmu TLB.
 435  * If we can translate a host virtual address suitable for direct RAM
 436  * access, without causing a guest exception, then return it.
 437  * Otherwise (TLB entry is for an I/O access, guest software
 438  * TLB fill required, etc) return NULL.
 439  */
 440 #ifdef CONFIG_USER_ONLY
 441 static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 442                                       MMUAccessType access_type, int mmu_idx)
 443 {
 444     return g2h(addr);
 445 }
 446 #else
 447 void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 448                         MMUAccessType access_type, int mmu_idx);
 449 #endif
 450
 451 #endif /* CPU_LDST_H */