include/hw/intc/armv7m_nvic.h

   1 /*
   2  * ARMv7M NVIC object
   3  *
   4  * Copyright (c) 2017 Linaro Ltd
   5  * Written by Peter Maydell <peter.maydell@linaro.org>
   6  *
   7  * This code is licensed under the GPL version 2 or later.
   8  */
   9
  10 #ifndef HW_ARM_ARMV7M_NVIC_H
  11 #define HW_ARM_ARMV7M_NVIC_H
  12
  13 #include "target/arm/cpu.h"
  14 #include "hw/sysbus.h"
  15 #include "hw/timer/armv7m_systick.h"
  16 #include "qom/object.h"
  17
  18 #define TYPE_NVIC "armv7m_nvic"
  19
  20 typedef struct NVICState NVICState;
  21 DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
  22                          TYPE_NVIC)
  23
  24 /* Highest permitted number of exceptions (architectural limit) */
  25 #define NVIC_MAX_VECTORS 512
  26 /* Number of internal exceptions */
  27 #define NVIC_INTERNAL_VECTORS 16
  28
  29 typedef struct VecInfo {
  30     /* Exception priorities can range from -3 to 255; only the unmodifiable
  31      * priority values for RESET, NMI and HardFault can be negative.
  32      */
  33     int16_t prio;
  34     uint8_t enabled;
  35     uint8_t pending;
  36     uint8_t active;
  37     uint8_t level; /* exceptions <=15 never set level */
  38 } VecInfo;
  39
  40 struct NVICState {
  41     /*< private >*/
  42     SysBusDevice parent_obj;
  43     /*< public >*/
  44
  45     ARMCPU *cpu;
  46
  47     VecInfo vectors[NVIC_MAX_VECTORS];
  48     /* If the v8M security extension is implemented, some of the internal
  49      * exceptions are banked between security states (ie there exists both
  50      * a Secure and a NonSecure version of the exception and its state):
  51      *  HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
  52      * The rest (including all the external exceptions) are not banked, though
  53      * they may be configurable to target either Secure or NonSecure state.
  54      * We store the secure exception state in sec_vectors[] for the banked
  55      * exceptions, and otherwise use only vectors[] (including for exceptions
  56      * like SecureFault that unconditionally target Secure state).
  57      * Entries in sec_vectors[] for non-banked exception numbers are unused.
  58      */
  59     VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
  60     /* The PRIGROUP field in AIRCR is banked */
  61     uint32_t prigroup[M_REG_NUM_BANKS];
  62     uint8_t num_prio_bits;
  63
  64     /* v8M NVIC_ITNS state (stored as a bool per bit) */
  65     bool itns[NVIC_MAX_VECTORS];
  66
  67     /* The following fields are all cached state that can be recalculated
  68      * from the vectors[] and sec_vectors[] arrays and the prigroup field:
  69      *  - vectpending
  70      *  - vectpending_is_secure
  71      *  - exception_prio
  72      *  - vectpending_prio
  73      */
  74     unsigned int vectpending; /* highest prio pending enabled exception */
  75     /* true if vectpending is a banked secure exception, ie it is in
  76      * sec_vectors[] rather than vectors[]
  77      */
  78     bool vectpending_is_s_banked;
  79     int exception_prio; /* group prio of the highest prio active exception */
  80     int vectpending_prio; /* group prio of the exeception in vectpending */
  81
  82     MemoryRegion sysregmem;
  83     MemoryRegion sysreg_ns_mem;
  84     MemoryRegion systickmem;
  85     MemoryRegion systick_ns_mem;
  86     MemoryRegion container;
  87     MemoryRegion defaultmem;
  88
  89     uint32_t num_irq;
  90     qemu_irq excpout;
  91     qemu_irq sysresetreq;
  92
  93     SysTickState systick[M_REG_NUM_BANKS];
  94 };
  95
  96 #endif