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hw/scsi/spapr_vscsi: Convert debug fprintf() to trace event
[qemu/ar7.git] / hw / scsi / megasas.c
blobaf18c88b656e7f5fa299c5f0dda1158ad66472e9
1 /*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "hw/pci/pci.h"
24 #include "hw/qdev-properties.h"
25 #include "sysemu/dma.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "qemu/iov.h"
30 #include "qemu/module.h"
31 #include "hw/scsi/scsi.h"
32 #include "scsi/constants.h"
33 #include "trace.h"
34 #include "qapi/error.h"
35 #include "mfi.h"
36 #include "migration/vmstate.h"
37
38 #define MEGASAS_VERSION_GEN1 "1.70"
39 #define MEGASAS_VERSION_GEN2 "1.80"
40 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
41 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
42 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
43 #define MEGASAS_MAX_SGE 128 /* Firmware limit */
44 #define MEGASAS_DEFAULT_SGE 80
45 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
46 #define MEGASAS_MAX_ARRAYS 128
47
48 #define MEGASAS_HBA_SERIAL "QEMU123456"
49 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
50 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
51
52 #define MEGASAS_FLAG_USE_JBOD 0
53 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
54 #define MEGASAS_FLAG_USE_QUEUE64 1
55 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
56
57 static const char *mfi_frame_desc[] = {
58 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
59 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
60
61 typedef struct MegasasCmd {
62 uint32_t index;
63 uint16_t flags;
64 uint16_t count;
65 uint64_t context;
66
67 hwaddr pa;
68 hwaddr pa_size;
69 uint32_t dcmd_opcode;
70 union mfi_frame *frame;
71 SCSIRequest *req;
72 QEMUSGList qsg;
73 void *iov_buf;
74 size_t iov_size;
75 size_t iov_offset;
76 struct MegasasState *state;
77 } MegasasCmd;
78
79 typedef struct MegasasState {
80 /*< private >*/
81 PCIDevice parent_obj;
82 /*< public >*/
83
84 MemoryRegion mmio_io;
85 MemoryRegion port_io;
86 MemoryRegion queue_io;
87 uint32_t frame_hi;
88
89 int fw_state;
90 uint32_t fw_sge;
91 uint32_t fw_cmds;
92 uint32_t flags;
93 int fw_luns;
94 int intr_mask;
95 int doorbell;
96 int busy;
97 int diag;
98 int adp_reset;
99 OnOffAuto msi;
100 OnOffAuto msix;
101
102 MegasasCmd *event_cmd;
103 int event_locale;
104 int event_class;
105 int event_count;
106 int shutdown_event;
107 int boot_event;
108
109 uint64_t sas_addr;
110 char *hba_serial;
111
112 uint64_t reply_queue_pa;
113 void *reply_queue;
114 int reply_queue_len;
115 int reply_queue_head;
116 int reply_queue_tail;
117 uint64_t consumer_pa;
118 uint64_t producer_pa;
119
120 MegasasCmd frames[MEGASAS_MAX_FRAMES];
121 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
122 SCSIBus bus;
123 } MegasasState;
124
125 typedef struct MegasasBaseClass {
126 PCIDeviceClass parent_class;
127 const char *product_name;
128 const char *product_version;
129 int mmio_bar;
130 int ioport_bar;
131 int osts;
132 } MegasasBaseClass;
133
134 #define TYPE_MEGASAS_BASE "megasas-base"
135 #define TYPE_MEGASAS_GEN1 "megasas"
136 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
137
138 #define MEGASAS(obj) \
139 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
140
141 #define MEGASAS_DEVICE_CLASS(oc) \
142 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
143 #define MEGASAS_DEVICE_GET_CLASS(oc) \
144 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
145
146 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
147
148 static bool megasas_intr_enabled(MegasasState *s)
149 {
150 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
151 MEGASAS_INTR_DISABLED_MASK) {
152 return true;
153 }
154 return false;
155 }
156
157 static bool megasas_use_queue64(MegasasState *s)
158 {
159 return s->flags & MEGASAS_MASK_USE_QUEUE64;
160 }
161
162 static bool megasas_use_msix(MegasasState *s)
163 {
164 return s->msix != ON_OFF_AUTO_OFF;
165 }
166
167 static bool megasas_is_jbod(MegasasState *s)
168 {
169 return s->flags & MEGASAS_MASK_USE_JBOD;
170 }
171
172 static void megasas_frame_set_cmd_status(MegasasState *s,
173 unsigned long frame, uint8_t v)
174 {
175 PCIDevice *pci = &s->parent_obj;
176 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
177 }
178
179 static void megasas_frame_set_scsi_status(MegasasState *s,
180 unsigned long frame, uint8_t v)
181 {
182 PCIDevice *pci = &s->parent_obj;
183 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
184 }
185
186 /*
187 * Context is considered opaque, but the HBA firmware is running
188 * in little endian mode. So convert it to little endian, too.
189 */
190 static uint64_t megasas_frame_get_context(MegasasState *s,
191 unsigned long frame)
192 {
193 PCIDevice *pci = &s->parent_obj;
194 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
195 }
196
197 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
198 {
199 return cmd->flags & MFI_FRAME_IEEE_SGL;
200 }
201
202 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
203 {
204 return cmd->flags & MFI_FRAME_SGL64;
205 }
206
207 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
208 {
209 return cmd->flags & MFI_FRAME_SENSE64;
210 }
211
212 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
213 union mfi_sgl *sgl)
214 {
215 uint64_t addr;
216
217 if (megasas_frame_is_ieee_sgl(cmd)) {
218 addr = le64_to_cpu(sgl->sg_skinny->addr);
219 } else if (megasas_frame_is_sgl64(cmd)) {
220 addr = le64_to_cpu(sgl->sg64->addr);
221 } else {
222 addr = le32_to_cpu(sgl->sg32->addr);
223 }
224 return addr;
225 }
226
227 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
228 union mfi_sgl *sgl)
229 {
230 uint32_t len;
231
232 if (megasas_frame_is_ieee_sgl(cmd)) {
233 len = le32_to_cpu(sgl->sg_skinny->len);
234 } else if (megasas_frame_is_sgl64(cmd)) {
235 len = le32_to_cpu(sgl->sg64->len);
236 } else {
237 len = le32_to_cpu(sgl->sg32->len);
238 }
239 return len;
240 }
241
242 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
243 union mfi_sgl *sgl)
244 {
245 uint8_t *next = (uint8_t *)sgl;
246
247 if (megasas_frame_is_ieee_sgl(cmd)) {
248 next += sizeof(struct mfi_sg_skinny);
249 } else if (megasas_frame_is_sgl64(cmd)) {
250 next += sizeof(struct mfi_sg64);
251 } else {
252 next += sizeof(struct mfi_sg32);
253 }
254
255 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
256 return NULL;
257 }
258 return (union mfi_sgl *)next;
259 }
260
261 static void megasas_soft_reset(MegasasState *s);
262
263 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
264 {
265 int i;
266 int iov_count = 0;
267 size_t iov_size = 0;
268
269 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
270 iov_count = cmd->frame->header.sge_count;
271 if (iov_count > MEGASAS_MAX_SGE) {
272 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
273 MEGASAS_MAX_SGE);
274 return iov_count;
275 }
276 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
277 for (i = 0; i < iov_count; i++) {
278 dma_addr_t iov_pa, iov_size_p;
279
280 if (!sgl) {
281 trace_megasas_iovec_sgl_underflow(cmd->index, i);
282 goto unmap;
283 }
284 iov_pa = megasas_sgl_get_addr(cmd, sgl);
285 iov_size_p = megasas_sgl_get_len(cmd, sgl);
286 if (!iov_pa || !iov_size_p) {
287 trace_megasas_iovec_sgl_invalid(cmd->index, i,
288 iov_pa, iov_size_p);
289 goto unmap;
290 }
291 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
292 sgl = megasas_sgl_next(cmd, sgl);
293 iov_size += (size_t)iov_size_p;
294 }
295 if (cmd->iov_size > iov_size) {
296 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
297 } else if (cmd->iov_size < iov_size) {
298 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
299 }
300 cmd->iov_offset = 0;
301 return 0;
302 unmap:
303 qemu_sglist_destroy(&cmd->qsg);
304 return iov_count - i;
305 }
306
307 /*
308 * passthrough sense and io sense are at the same offset
309 */
310 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
311 uint8_t sense_len)
312 {
313 PCIDevice *pcid = PCI_DEVICE(cmd->state);
314 uint32_t pa_hi = 0, pa_lo;
315 hwaddr pa;
316 int frame_sense_len;
317
318 frame_sense_len = cmd->frame->header.sense_len;
319 if (sense_len > frame_sense_len) {
320 sense_len = frame_sense_len;
321 }
322 if (sense_len) {
323 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
324 if (megasas_frame_is_sense64(cmd)) {
325 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
326 }
327 pa = ((uint64_t) pa_hi << 32) | pa_lo;
328 pci_dma_write(pcid, pa, sense_ptr, sense_len);
329 cmd->frame->header.sense_len = sense_len;
330 }
331 return sense_len;
332 }
333
334 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
335 {
336 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
337 uint8_t sense_len = 18;
338
339 memset(sense_buf, 0, sense_len);
340 sense_buf[0] = 0xf0;
341 sense_buf[2] = sense.key;
342 sense_buf[7] = 10;
343 sense_buf[12] = sense.asc;
344 sense_buf[13] = sense.ascq;
345 megasas_build_sense(cmd, sense_buf, sense_len);
346 }
347
348 static void megasas_copy_sense(MegasasCmd *cmd)
349 {
350 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
351 uint8_t sense_len;
352
353 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
354 SCSI_SENSE_BUF_SIZE);
355 megasas_build_sense(cmd, sense_buf, sense_len);
356 }
357
358 /*
359 * Format an INQUIRY CDB
360 */
361 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
362 {
363 memset(cdb, 0, 6);
364 cdb[0] = INQUIRY;
365 if (pg > 0) {
366 cdb[1] = 0x1;
367 cdb[2] = pg;
368 }
369 cdb[3] = (len >> 8) & 0xff;
370 cdb[4] = (len & 0xff);
371 return len;
372 }
373
374 /*
375 * Encode lba and len into a READ_16/WRITE_16 CDB
376 */
377 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
378 uint32_t len, bool is_write)
379 {
380 memset(cdb, 0x0, 16);
381 if (is_write) {
382 cdb[0] = WRITE_16;
383 } else {
384 cdb[0] = READ_16;
385 }
386 cdb[2] = (lba >> 56) & 0xff;
387 cdb[3] = (lba >> 48) & 0xff;
388 cdb[4] = (lba >> 40) & 0xff;
389 cdb[5] = (lba >> 32) & 0xff;
390 cdb[6] = (lba >> 24) & 0xff;
391 cdb[7] = (lba >> 16) & 0xff;
392 cdb[8] = (lba >> 8) & 0xff;
393 cdb[9] = (lba) & 0xff;
394 cdb[10] = (len >> 24) & 0xff;
395 cdb[11] = (len >> 16) & 0xff;
396 cdb[12] = (len >> 8) & 0xff;
397 cdb[13] = (len) & 0xff;
398 }
399
400 /*
401 * Utility functions
402 */
403 static uint64_t megasas_fw_time(void)
404 {
405 struct tm curtime;
406
407 qemu_get_timedate(&curtime, 0);
408 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
409 ((uint64_t)curtime.tm_min & 0xff) << 40 |
410 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
411 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
412 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
413 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
414 }
415
416 /*
417 * Default disk sata address
418 * 0x1221 is the magic number as
419 * present in real hardware,
420 * so use it here, too.
421 */
422 static uint64_t megasas_get_sata_addr(uint16_t id)
423 {
424 uint64_t addr = (0x1221ULL << 48);
425 return addr | ((uint64_t)id << 24);
426 }
427
428 /*
429 * Frame handling
430 */
431 static int megasas_next_index(MegasasState *s, int index, int limit)
432 {
433 index++;
434 if (index == limit) {
435 index = 0;
436 }
437 return index;
438 }
439
440 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
441 hwaddr frame)
442 {
443 MegasasCmd *cmd = NULL;
444 int num = 0, index;
445
446 index = s->reply_queue_head;
447
448 while (num < s->fw_cmds) {
449 if (s->frames[index].pa && s->frames[index].pa == frame) {
450 cmd = &s->frames[index];
451 break;
452 }
453 index = megasas_next_index(s, index, s->fw_cmds);
454 num++;
455 }
456
457 return cmd;
458 }
459
460 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
461 {
462 PCIDevice *p = PCI_DEVICE(s);
463
464 if (cmd->pa_size) {
465 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
466 }
467 cmd->frame = NULL;
468 cmd->pa = 0;
469 cmd->pa_size = 0;
470 qemu_sglist_destroy(&cmd->qsg);
471 clear_bit(cmd->index, s->frame_map);
472 }
473
474 /*
475 * This absolutely needs to be locked if
476 * qemu ever goes multithreaded.
477 */
478 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
479 hwaddr frame, uint64_t context, int count)
480 {
481 PCIDevice *pcid = PCI_DEVICE(s);
482 MegasasCmd *cmd = NULL;
483 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
484 hwaddr frame_size_p = frame_size;
485 unsigned long index;
486
487 index = 0;
488 while (index < s->fw_cmds) {
489 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
490 if (!s->frames[index].pa)
491 break;
492 /* Busy frame found */
493 trace_megasas_qf_mapped(index);
494 }
495 if (index >= s->fw_cmds) {
496 /* All frames busy */
497 trace_megasas_qf_busy(frame);
498 return NULL;
499 }
500 cmd = &s->frames[index];
501 set_bit(index, s->frame_map);
502 trace_megasas_qf_new(index, frame);
503
504 cmd->pa = frame;
505 /* Map all possible frames */
506 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
507 if (frame_size_p != frame_size) {
508 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
509 if (cmd->frame) {
510 megasas_unmap_frame(s, cmd);
511 }
512 s->event_count++;
513 return NULL;
514 }
515 cmd->pa_size = frame_size_p;
516 cmd->context = context;
517 if (!megasas_use_queue64(s)) {
518 cmd->context &= (uint64_t)0xFFFFFFFF;
519 }
520 cmd->count = count;
521 cmd->dcmd_opcode = -1;
522 s->busy++;
523
524 if (s->consumer_pa) {
525 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
526 }
527 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
528 s->reply_queue_head, s->reply_queue_tail, s->busy);
529
530 return cmd;
531 }
532
533 static void megasas_complete_frame(MegasasState *s, uint64_t context)
534 {
535 PCIDevice *pci_dev = PCI_DEVICE(s);
536 int tail, queue_offset;
537
538 /* Decrement busy count */
539 s->busy--;
540 if (s->reply_queue_pa) {
541 /*
542 * Put command on the reply queue.
543 * Context is opaque, but emulation is running in
544 * little endian. So convert it.
545 */
546 if (megasas_use_queue64(s)) {
547 queue_offset = s->reply_queue_head * sizeof(uint64_t);
548 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
549 } else {
550 queue_offset = s->reply_queue_head * sizeof(uint32_t);
551 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
552 }
553 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
554 trace_megasas_qf_complete(context, s->reply_queue_head,
555 s->reply_queue_tail, s->busy);
556 }
557
558 if (megasas_intr_enabled(s)) {
559 /* Update reply queue pointer */
560 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
561 tail = s->reply_queue_head;
562 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
563 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
564 s->busy);
565 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
566 /* Notify HBA */
567 if (msix_enabled(pci_dev)) {
568 trace_megasas_msix_raise(0);
569 msix_notify(pci_dev, 0);
570 } else if (msi_enabled(pci_dev)) {
571 trace_megasas_msi_raise(0);
572 msi_notify(pci_dev, 0);
573 } else {
574 s->doorbell++;
575 if (s->doorbell == 1) {
576 trace_megasas_irq_raise();
577 pci_irq_assert(pci_dev);
578 }
579 }
580 } else {
581 trace_megasas_qf_complete_noirq(context);
582 }
583 }
584
585 static void megasas_complete_command(MegasasCmd *cmd)
586 {
587 cmd->iov_size = 0;
588 cmd->iov_offset = 0;
589
590 cmd->req->hba_private = NULL;
591 scsi_req_unref(cmd->req);
592 cmd->req = NULL;
593
594 megasas_unmap_frame(cmd->state, cmd);
595 megasas_complete_frame(cmd->state, cmd->context);
596 }
597
598 static void megasas_reset_frames(MegasasState *s)
599 {
600 int i;
601 MegasasCmd *cmd;
602
603 for (i = 0; i < s->fw_cmds; i++) {
604 cmd = &s->frames[i];
605 if (cmd->pa) {
606 megasas_unmap_frame(s, cmd);
607 }
608 }
609 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
610 }
611
612 static void megasas_abort_command(MegasasCmd *cmd)
613 {
614 /* Never abort internal commands. */
615 if (cmd->dcmd_opcode != -1) {
616 return;
617 }
618 if (cmd->req != NULL) {
619 scsi_req_cancel(cmd->req);
620 }
621 }
622
623 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
624 {
625 PCIDevice *pcid = PCI_DEVICE(s);
626 uint32_t pa_hi, pa_lo;
627 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
628 struct mfi_init_qinfo *initq = NULL;
629 uint32_t flags;
630 int ret = MFI_STAT_OK;
631
632 if (s->reply_queue_pa) {
633 trace_megasas_initq_mapped(s->reply_queue_pa);
634 goto out;
635 }
636 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
637 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
638 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
639 trace_megasas_init_firmware((uint64_t)iq_pa);
640 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
641 if (!initq || initq_size != sizeof(*initq)) {
642 trace_megasas_initq_map_failed(cmd->index);
643 s->event_count++;
644 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
645 goto out;
646 }
647 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
648 if (s->reply_queue_len > s->fw_cmds) {
649 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
650 s->event_count++;
651 ret = MFI_STAT_INVALID_PARAMETER;
652 goto out;
653 }
654 pa_lo = le32_to_cpu(initq->rq_addr_lo);
655 pa_hi = le32_to_cpu(initq->rq_addr_hi);
656 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
657 pa_lo = le32_to_cpu(initq->ci_addr_lo);
658 pa_hi = le32_to_cpu(initq->ci_addr_hi);
659 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
660 pa_lo = le32_to_cpu(initq->pi_addr_lo);
661 pa_hi = le32_to_cpu(initq->pi_addr_hi);
662 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
663 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
664 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
665 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
666 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
667 flags = le32_to_cpu(initq->flags);
668 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
669 s->flags |= MEGASAS_MASK_USE_QUEUE64;
670 }
671 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
672 s->reply_queue_len, s->reply_queue_head,
673 s->reply_queue_tail, flags);
674 megasas_reset_frames(s);
675 s->fw_state = MFI_FWSTATE_OPERATIONAL;
676 out:
677 if (initq) {
678 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
679 }
680 return ret;
681 }
682
683 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
684 {
685 dma_addr_t iov_pa, iov_size;
686 int iov_count;
687
688 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
689 iov_count = cmd->frame->header.sge_count;
690 if (!iov_count) {
691 trace_megasas_dcmd_zero_sge(cmd->index);
692 cmd->iov_size = 0;
693 return 0;
694 } else if (iov_count > 1) {
695 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
696 cmd->iov_size = 0;
697 return -EINVAL;
698 }
699 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
700 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
701 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
702 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
703 cmd->iov_size = iov_size;
704 return 0;
705 }
706
707 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
708 {
709 trace_megasas_finish_dcmd(cmd->index, iov_size);
710
711 if (iov_size > cmd->iov_size) {
712 if (megasas_frame_is_ieee_sgl(cmd)) {
713 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
714 } else if (megasas_frame_is_sgl64(cmd)) {
715 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
716 } else {
717 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
718 }
719 }
720 }
721
722 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
723 {
724 PCIDevice *pci_dev = PCI_DEVICE(s);
725 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
726 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
727 struct mfi_ctrl_info info;
728 size_t dcmd_size = sizeof(info);
729 BusChild *kid;
730 int num_pd_disks = 0;
731
732 memset(&info, 0x0, dcmd_size);
733 if (cmd->iov_size < dcmd_size) {
734 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
735 dcmd_size);
736 return MFI_STAT_INVALID_PARAMETER;
737 }
738
739 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
740 info.pci.device = cpu_to_le16(pci_class->device_id);
741 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
742 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
743
744 /*
745 * For some reason the firmware supports
746 * only up to 8 device ports.
747 * Despite supporting a far larger number
748 * of devices for the physical devices.
749 * So just display the first 8 devices
750 * in the device port list, independent
751 * of how many logical devices are actually
752 * present.
753 */
754 info.host.type = MFI_INFO_HOST_PCIE;
755 info.device.type = MFI_INFO_DEV_SAS3G;
756 info.device.port_count = 8;
757 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
758 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
759 uint16_t pd_id;
760
761 if (num_pd_disks < 8) {
762 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
763 info.device.port_addr[num_pd_disks] =
764 cpu_to_le64(megasas_get_sata_addr(pd_id));
765 }
766 num_pd_disks++;
767 }
768
769 memcpy(info.product_name, base_class->product_name, 24);
770 snprintf(info.serial_number, 32, "%s", s->hba_serial);
771 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
772 memcpy(info.image_component[0].name, "APP", 3);
773 snprintf(info.image_component[0].version, 10, "%s-QEMU",
774 base_class->product_version);
775 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
776 memcpy(info.image_component[0].build_time, "12:34:56", 8);
777 info.image_component_count = 1;
778 if (pci_dev->has_rom) {
779 uint8_t biosver[32];
780 uint8_t *ptr;
781
782 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
783 memcpy(biosver, ptr + 0x41, 31);
784 biosver[31] = 0;
785 memcpy(info.image_component[1].name, "BIOS", 4);
786 memcpy(info.image_component[1].version, biosver,
787 strlen((const char *)biosver));
788 info.image_component_count++;
789 }
790 info.current_fw_time = cpu_to_le32(megasas_fw_time());
791 info.max_arms = 32;
792 info.max_spans = 8;
793 info.max_arrays = MEGASAS_MAX_ARRAYS;
794 info.max_lds = MFI_MAX_LD;
795 info.max_cmds = cpu_to_le16(s->fw_cmds);
796 info.max_sg_elements = cpu_to_le16(s->fw_sge);
797 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
798 if (!megasas_is_jbod(s))
799 info.lds_present = cpu_to_le16(num_pd_disks);
800 info.pd_present = cpu_to_le16(num_pd_disks);
801 info.pd_disks_present = cpu_to_le16(num_pd_disks);
802 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
803 MFI_INFO_HW_MEM |
804 MFI_INFO_HW_FLASH);
805 info.memory_size = cpu_to_le16(512);
806 info.nvram_size = cpu_to_le16(32);
807 info.flash_size = cpu_to_le16(16);
808 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
809 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
810 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
811 MFI_INFO_AOPS_MIXED_ARRAY);
812 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
813 MFI_INFO_LDOPS_ACCESS_POLICY |
814 MFI_INFO_LDOPS_IO_POLICY |
815 MFI_INFO_LDOPS_WRITE_POLICY |
816 MFI_INFO_LDOPS_READ_POLICY);
817 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
818 info.stripe_sz_ops.min = 3;
819 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
820 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
821 info.properties.intr_throttle_cnt = cpu_to_le16(16);
822 info.properties.intr_throttle_timeout = cpu_to_le16(50);
823 info.properties.rebuild_rate = 30;
824 info.properties.patrol_read_rate = 30;
825 info.properties.bgi_rate = 30;
826 info.properties.cc_rate = 30;
827 info.properties.recon_rate = 30;
828 info.properties.cache_flush_interval = 4;
829 info.properties.spinup_drv_cnt = 2;
830 info.properties.spinup_delay = 6;
831 info.properties.ecc_bucket_size = 15;
832 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
833 info.properties.expose_encl_devices = 1;
834 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
835 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
836 MFI_INFO_PDOPS_FORCE_OFFLINE);
837 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
838 MFI_INFO_PDMIX_SATA |
839 MFI_INFO_PDMIX_LD);
840
841 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
842 return MFI_STAT_OK;
843 }
844
845 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
846 {
847 struct mfi_defaults info;
848 size_t dcmd_size = sizeof(struct mfi_defaults);
849
850 memset(&info, 0x0, dcmd_size);
851 if (cmd->iov_size < dcmd_size) {
852 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
853 dcmd_size);
854 return MFI_STAT_INVALID_PARAMETER;
855 }
856
857 info.sas_addr = cpu_to_le64(s->sas_addr);
858 info.stripe_size = 3;
859 info.flush_time = 4;
860 info.background_rate = 30;
861 info.allow_mix_in_enclosure = 1;
862 info.allow_mix_in_ld = 1;
863 info.direct_pd_mapping = 1;
864 /* Enable for BIOS support */
865 info.bios_enumerate_lds = 1;
866 info.disable_ctrl_r = 1;
867 info.expose_enclosure_devices = 1;
868 info.disable_preboot_cli = 1;
869 info.cluster_disable = 1;
870
871 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
872 return MFI_STAT_OK;
873 }
874
875 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
876 {
877 struct mfi_bios_data info;
878 size_t dcmd_size = sizeof(info);
879
880 memset(&info, 0x0, dcmd_size);
881 if (cmd->iov_size < dcmd_size) {
882 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
883 dcmd_size);
884 return MFI_STAT_INVALID_PARAMETER;
885 }
886 info.continue_on_error = 1;
887 info.verbose = 1;
888 if (megasas_is_jbod(s)) {
889 info.expose_all_drives = 1;
890 }
891
892 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
893 return MFI_STAT_OK;
894 }
895
896 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
897 {
898 uint64_t fw_time;
899 size_t dcmd_size = sizeof(fw_time);
900
901 fw_time = cpu_to_le64(megasas_fw_time());
902
903 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
904 return MFI_STAT_OK;
905 }
906
907 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
908 {
909 uint64_t fw_time;
910
911 /* This is a dummy; setting of firmware time is not allowed */
912 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
913
914 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
915 fw_time = cpu_to_le64(megasas_fw_time());
916 return MFI_STAT_OK;
917 }
918
919 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
920 {
921 struct mfi_evt_log_state info;
922 size_t dcmd_size = sizeof(info);
923
924 memset(&info, 0, dcmd_size);
925
926 info.newest_seq_num = cpu_to_le32(s->event_count);
927 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
928 info.boot_seq_num = cpu_to_le32(s->boot_event);
929
930 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
931 return MFI_STAT_OK;
932 }
933
934 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
935 {
936 union mfi_evt event;
937
938 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
939 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
940 sizeof(struct mfi_evt_detail));
941 return MFI_STAT_INVALID_PARAMETER;
942 }
943 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
944 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
945 s->event_locale = event.members.locale;
946 s->event_class = event.members.class;
947 s->event_cmd = cmd;
948 /* Decrease busy count; event frame doesn't count here */
949 s->busy--;
950 cmd->iov_size = sizeof(struct mfi_evt_detail);
951 return MFI_STAT_INVALID_STATUS;
952 }
953
954 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
955 {
956 struct mfi_pd_list info;
957 size_t dcmd_size = sizeof(info);
958 BusChild *kid;
959 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
960
961 memset(&info, 0, dcmd_size);
962 offset = 8;
963 dcmd_limit = offset + sizeof(struct mfi_pd_address);
964 if (cmd->iov_size < dcmd_limit) {
965 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
966 dcmd_limit);
967 return MFI_STAT_INVALID_PARAMETER;
968 }
969
970 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
971 if (max_pd_disks > MFI_MAX_SYS_PDS) {
972 max_pd_disks = MFI_MAX_SYS_PDS;
973 }
974 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
975 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
976 uint16_t pd_id;
977
978 if (num_pd_disks >= max_pd_disks)
979 break;
980
981 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
982 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
983 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
984 info.addr[num_pd_disks].encl_index = 0;
985 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
986 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
987 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
988 info.addr[num_pd_disks].sas_addr[0] =
989 cpu_to_le64(megasas_get_sata_addr(pd_id));
990 num_pd_disks++;
991 offset += sizeof(struct mfi_pd_address);
992 }
993 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
994 max_pd_disks, offset);
995
996 info.size = cpu_to_le32(offset);
997 info.count = cpu_to_le32(num_pd_disks);
998
999 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
1000 return MFI_STAT_OK;
1001 }
1002
1003 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1004 {
1005 uint16_t flags;
1006
1007 /* mbox0 contains flags */
1008 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1009 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1010 if (flags == MR_PD_QUERY_TYPE_ALL ||
1011 megasas_is_jbod(s)) {
1012 return megasas_dcmd_pd_get_list(s, cmd);
1013 }
1014
1015 return MFI_STAT_OK;
1016 }
1017
1018 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1019 MegasasCmd *cmd)
1020 {
1021 struct mfi_pd_info *info = cmd->iov_buf;
1022 size_t dcmd_size = sizeof(struct mfi_pd_info);
1023 uint64_t pd_size;
1024 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1025 uint8_t cmdbuf[6];
1026 size_t len, resid;
1027
1028 if (!cmd->iov_buf) {
1029 cmd->iov_buf = g_malloc0(dcmd_size);
1030 info = cmd->iov_buf;
1031 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1032 info->vpd_page83[0] = 0x7f;
1033 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1034 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1035 if (!cmd->req) {
1036 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1037 "PD get info std inquiry");
1038 g_free(cmd->iov_buf);
1039 cmd->iov_buf = NULL;
1040 return MFI_STAT_FLASH_ALLOC_FAIL;
1041 }
1042 trace_megasas_dcmd_internal_submit(cmd->index,
1043 "PD get info std inquiry", lun);
1044 len = scsi_req_enqueue(cmd->req);
1045 if (len > 0) {
1046 cmd->iov_size = len;
1047 scsi_req_continue(cmd->req);
1048 }
1049 return MFI_STAT_INVALID_STATUS;
1050 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1051 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1052 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1053 if (!cmd->req) {
1054 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1055 "PD get info vpd inquiry");
1056 return MFI_STAT_FLASH_ALLOC_FAIL;
1057 }
1058 trace_megasas_dcmd_internal_submit(cmd->index,
1059 "PD get info vpd inquiry", lun);
1060 len = scsi_req_enqueue(cmd->req);
1061 if (len > 0) {
1062 cmd->iov_size = len;
1063 scsi_req_continue(cmd->req);
1064 }
1065 return MFI_STAT_INVALID_STATUS;
1066 }
1067 /* Finished, set FW state */
1068 if ((info->inquiry_data[0] >> 5) == 0) {
1069 if (megasas_is_jbod(cmd->state)) {
1070 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1071 } else {
1072 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1073 }
1074 } else {
1075 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1076 }
1077
1078 info->ref.v.device_id = cpu_to_le16(pd_id);
1079 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1080 MFI_PD_DDF_TYPE_INTF_SAS);
1081 blk_get_geometry(sdev->conf.blk, &pd_size);
1082 info->raw_size = cpu_to_le64(pd_size);
1083 info->non_coerced_size = cpu_to_le64(pd_size);
1084 info->coerced_size = cpu_to_le64(pd_size);
1085 info->encl_device_id = 0xFFFF;
1086 info->slot_number = (sdev->id & 0xFF);
1087 info->path_info.count = 1;
1088 info->path_info.sas_addr[0] =
1089 cpu_to_le64(megasas_get_sata_addr(pd_id));
1090 info->connected_port_bitmap = 0x1;
1091 info->device_speed = 1;
1092 info->link_speed = 1;
1093 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1094 g_free(cmd->iov_buf);
1095 cmd->iov_size = dcmd_size - resid;
1096 cmd->iov_buf = NULL;
1097 return MFI_STAT_OK;
1098 }
1099
1100 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1101 {
1102 size_t dcmd_size = sizeof(struct mfi_pd_info);
1103 uint16_t pd_id;
1104 uint8_t target_id, lun_id;
1105 SCSIDevice *sdev = NULL;
1106 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1107
1108 if (cmd->iov_size < dcmd_size) {
1109 return MFI_STAT_INVALID_PARAMETER;
1110 }
1111
1112 /* mbox0 has the ID */
1113 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1114 target_id = (pd_id >> 8) & 0xFF;
1115 lun_id = pd_id & 0xFF;
1116 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1117 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1118
1119 if (sdev) {
1120 /* Submit inquiry */
1121 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1122 }
1123
1124 return retval;
1125 }
1126
1127 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1128 {
1129 struct mfi_ld_list info;
1130 size_t dcmd_size = sizeof(info), resid;
1131 uint32_t num_ld_disks = 0, max_ld_disks;
1132 uint64_t ld_size;
1133 BusChild *kid;
1134
1135 memset(&info, 0, dcmd_size);
1136 if (cmd->iov_size > dcmd_size) {
1137 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1138 dcmd_size);
1139 return MFI_STAT_INVALID_PARAMETER;
1140 }
1141
1142 max_ld_disks = (cmd->iov_size - 8) / 16;
1143 if (megasas_is_jbod(s)) {
1144 max_ld_disks = 0;
1145 }
1146 if (max_ld_disks > MFI_MAX_LD) {
1147 max_ld_disks = MFI_MAX_LD;
1148 }
1149 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1150 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1151
1152 if (num_ld_disks >= max_ld_disks) {
1153 break;
1154 }
1155 /* Logical device size is in blocks */
1156 blk_get_geometry(sdev->conf.blk, &ld_size);
1157 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1158 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1159 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1160 num_ld_disks++;
1161 }
1162 info.ld_count = cpu_to_le32(num_ld_disks);
1163 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1164
1165 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1166 cmd->iov_size = dcmd_size - resid;
1167 return MFI_STAT_OK;
1168 }
1169
1170 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1171 {
1172 uint16_t flags;
1173 struct mfi_ld_targetid_list info;
1174 size_t dcmd_size = sizeof(info), resid;
1175 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1176 BusChild *kid;
1177
1178 /* mbox0 contains flags */
1179 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1180 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1181 if (flags != MR_LD_QUERY_TYPE_ALL &&
1182 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1183 max_ld_disks = 0;
1184 }
1185
1186 memset(&info, 0, dcmd_size);
1187 if (cmd->iov_size < 12) {
1188 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1189 dcmd_size);
1190 return MFI_STAT_INVALID_PARAMETER;
1191 }
1192 dcmd_size = sizeof(uint32_t) * 2 + 3;
1193 max_ld_disks = cmd->iov_size - dcmd_size;
1194 if (megasas_is_jbod(s)) {
1195 max_ld_disks = 0;
1196 }
1197 if (max_ld_disks > MFI_MAX_LD) {
1198 max_ld_disks = MFI_MAX_LD;
1199 }
1200 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1201 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1202
1203 if (num_ld_disks >= max_ld_disks) {
1204 break;
1205 }
1206 info.targetid[num_ld_disks] = sdev->lun;
1207 num_ld_disks++;
1208 dcmd_size++;
1209 }
1210 info.ld_count = cpu_to_le32(num_ld_disks);
1211 info.size = dcmd_size;
1212 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1213
1214 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1215 cmd->iov_size = dcmd_size - resid;
1216 return MFI_STAT_OK;
1217 }
1218
1219 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1220 MegasasCmd *cmd)
1221 {
1222 struct mfi_ld_info *info = cmd->iov_buf;
1223 size_t dcmd_size = sizeof(struct mfi_ld_info);
1224 uint8_t cdb[6];
1225 ssize_t len, resid;
1226 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1227 uint64_t ld_size;
1228
1229 if (!cmd->iov_buf) {
1230 cmd->iov_buf = g_malloc0(dcmd_size);
1231 info = cmd->iov_buf;
1232 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1233 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1234 if (!cmd->req) {
1235 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1236 "LD get info vpd inquiry");
1237 g_free(cmd->iov_buf);
1238 cmd->iov_buf = NULL;
1239 return MFI_STAT_FLASH_ALLOC_FAIL;
1240 }
1241 trace_megasas_dcmd_internal_submit(cmd->index,
1242 "LD get info vpd inquiry", lun);
1243 len = scsi_req_enqueue(cmd->req);
1244 if (len > 0) {
1245 cmd->iov_size = len;
1246 scsi_req_continue(cmd->req);
1247 }
1248 return MFI_STAT_INVALID_STATUS;
1249 }
1250
1251 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1252 info->ld_config.properties.ld.v.target_id = lun;
1253 info->ld_config.params.stripe_size = 3;
1254 info->ld_config.params.num_drives = 1;
1255 info->ld_config.params.is_consistent = 1;
1256 /* Logical device size is in blocks */
1257 blk_get_geometry(sdev->conf.blk, &ld_size);
1258 info->size = cpu_to_le64(ld_size);
1259 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1260 info->ld_config.span[0].start_block = 0;
1261 info->ld_config.span[0].num_blocks = info->size;
1262 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1263
1264 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1265 g_free(cmd->iov_buf);
1266 cmd->iov_size = dcmd_size - resid;
1267 cmd->iov_buf = NULL;
1268 return MFI_STAT_OK;
1269 }
1270
1271 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1272 {
1273 struct mfi_ld_info info;
1274 size_t dcmd_size = sizeof(info);
1275 uint16_t ld_id;
1276 uint32_t max_ld_disks = s->fw_luns;
1277 SCSIDevice *sdev = NULL;
1278 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1279
1280 if (cmd->iov_size < dcmd_size) {
1281 return MFI_STAT_INVALID_PARAMETER;
1282 }
1283
1284 /* mbox0 has the ID */
1285 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1286 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1287
1288 if (megasas_is_jbod(s)) {
1289 return MFI_STAT_DEVICE_NOT_FOUND;
1290 }
1291
1292 if (ld_id < max_ld_disks) {
1293 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1294 }
1295
1296 if (sdev) {
1297 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1298 }
1299
1300 return retval;
1301 }
1302
1303 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1304 {
1305 uint8_t data[4096] = { 0 };
1306 struct mfi_config_data *info;
1307 int num_pd_disks = 0, array_offset, ld_offset;
1308 BusChild *kid;
1309
1310 if (cmd->iov_size > 4096) {
1311 return MFI_STAT_INVALID_PARAMETER;
1312 }
1313
1314 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1315 num_pd_disks++;
1316 }
1317 info = (struct mfi_config_data *)&data;
1318 /*
1319 * Array mapping:
1320 * - One array per SCSI device
1321 * - One logical drive per SCSI device
1322 * spanning the entire device
1323 */
1324 info->array_count = num_pd_disks;
1325 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1326 info->log_drv_count = num_pd_disks;
1327 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1328 info->spares_count = 0;
1329 info->spares_size = sizeof(struct mfi_spare);
1330 info->size = sizeof(struct mfi_config_data) + info->array_size +
1331 info->log_drv_size;
1332 if (info->size > 4096) {
1333 return MFI_STAT_INVALID_PARAMETER;
1334 }
1335
1336 array_offset = sizeof(struct mfi_config_data);
1337 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1338
1339 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1340 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1341 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1342 struct mfi_array *array;
1343 struct mfi_ld_config *ld;
1344 uint64_t pd_size;
1345 int i;
1346
1347 array = (struct mfi_array *)(data + array_offset);
1348 blk_get_geometry(sdev->conf.blk, &pd_size);
1349 array->size = cpu_to_le64(pd_size);
1350 array->num_drives = 1;
1351 array->array_ref = cpu_to_le16(sdev_id);
1352 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1353 array->pd[0].ref.v.seq_num = 0;
1354 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1355 array->pd[0].encl.pd = 0xFF;
1356 array->pd[0].encl.slot = (sdev->id & 0xFF);
1357 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1358 array->pd[i].ref.v.device_id = 0xFFFF;
1359 array->pd[i].ref.v.seq_num = 0;
1360 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1361 array->pd[i].encl.pd = 0xFF;
1362 array->pd[i].encl.slot = 0xFF;
1363 }
1364 array_offset += sizeof(struct mfi_array);
1365 ld = (struct mfi_ld_config *)(data + ld_offset);
1366 memset(ld, 0, sizeof(struct mfi_ld_config));
1367 ld->properties.ld.v.target_id = sdev->id;
1368 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1369 MR_LD_CACHE_READ_ADAPTIVE;
1370 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1371 MR_LD_CACHE_READ_ADAPTIVE;
1372 ld->params.state = MFI_LD_STATE_OPTIMAL;
1373 ld->params.stripe_size = 3;
1374 ld->params.num_drives = 1;
1375 ld->params.span_depth = 1;
1376 ld->params.is_consistent = 1;
1377 ld->span[0].start_block = 0;
1378 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1379 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1380 ld_offset += sizeof(struct mfi_ld_config);
1381 }
1382
1383 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1384 return MFI_STAT_OK;
1385 }
1386
1387 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1388 {
1389 struct mfi_ctrl_props info;
1390 size_t dcmd_size = sizeof(info);
1391
1392 memset(&info, 0x0, dcmd_size);
1393 if (cmd->iov_size < dcmd_size) {
1394 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1395 dcmd_size);
1396 return MFI_STAT_INVALID_PARAMETER;
1397 }
1398 info.pred_fail_poll_interval = cpu_to_le16(300);
1399 info.intr_throttle_cnt = cpu_to_le16(16);
1400 info.intr_throttle_timeout = cpu_to_le16(50);
1401 info.rebuild_rate = 30;
1402 info.patrol_read_rate = 30;
1403 info.bgi_rate = 30;
1404 info.cc_rate = 30;
1405 info.recon_rate = 30;
1406 info.cache_flush_interval = 4;
1407 info.spinup_drv_cnt = 2;
1408 info.spinup_delay = 6;
1409 info.ecc_bucket_size = 15;
1410 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1411 info.expose_encl_devices = 1;
1412
1413 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1414 return MFI_STAT_OK;
1415 }
1416
1417 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1418 {
1419 blk_drain_all();
1420 return MFI_STAT_OK;
1421 }
1422
1423 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1424 {
1425 s->fw_state = MFI_FWSTATE_READY;
1426 return MFI_STAT_OK;
1427 }
1428
1429 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
1430 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1431 {
1432 uint16_t target_id;
1433 int i;
1434
1435 /* mbox0 contains the device index */
1436 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1437 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1438 for (i = 0; i < s->fw_cmds; i++) {
1439 MegasasCmd *tmp_cmd = &s->frames[i];
1440 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1441 SCSIDevice *d = tmp_cmd->req->dev;
1442 qdev_reset_all(&d->qdev);
1443 }
1444 }
1445 return MFI_STAT_OK;
1446 }
1447
1448 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1449 {
1450 struct mfi_ctrl_props info;
1451 size_t dcmd_size = sizeof(info);
1452
1453 if (cmd->iov_size < dcmd_size) {
1454 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1455 dcmd_size);
1456 return MFI_STAT_INVALID_PARAMETER;
1457 }
1458 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1459 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1460 return MFI_STAT_OK;
1461 }
1462
1463 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1464 {
1465 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1466 return MFI_STAT_OK;
1467 }
1468
1469 static const struct dcmd_cmd_tbl_t {
1470 int opcode;
1471 const char *desc;
1472 int (*func)(MegasasState *s, MegasasCmd *cmd);
1473 } dcmd_cmd_tbl[] = {
1474 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1475 megasas_dcmd_dummy },
1476 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1477 megasas_ctrl_get_info },
1478 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1479 megasas_dcmd_get_properties },
1480 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1481 megasas_dcmd_set_properties },
1482 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1483 megasas_dcmd_dummy },
1484 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1485 megasas_dcmd_dummy },
1486 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1487 megasas_dcmd_dummy },
1488 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1489 megasas_dcmd_dummy },
1490 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1491 megasas_dcmd_dummy },
1492 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1493 megasas_event_info },
1494 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1495 megasas_dcmd_dummy },
1496 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1497 megasas_event_wait },
1498 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1499 megasas_ctrl_shutdown },
1500 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1501 megasas_dcmd_dummy },
1502 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1503 megasas_dcmd_get_fw_time },
1504 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1505 megasas_dcmd_set_fw_time },
1506 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1507 megasas_dcmd_get_bios_info },
1508 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1509 megasas_dcmd_dummy },
1510 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1511 megasas_mfc_get_defaults },
1512 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1513 megasas_dcmd_dummy },
1514 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1515 megasas_cache_flush },
1516 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1517 megasas_dcmd_pd_get_list },
1518 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1519 megasas_dcmd_pd_list_query },
1520 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1521 megasas_dcmd_pd_get_info },
1522 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1523 megasas_dcmd_dummy },
1524 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1525 megasas_dcmd_dummy },
1526 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1527 megasas_dcmd_dummy },
1528 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1529 megasas_dcmd_dummy },
1530 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1531 megasas_dcmd_ld_get_list},
1532 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1533 megasas_dcmd_ld_list_query },
1534 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1535 megasas_dcmd_ld_get_info },
1536 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1537 megasas_dcmd_dummy },
1538 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1539 megasas_dcmd_dummy },
1540 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1541 megasas_dcmd_dummy },
1542 { MFI_DCMD_CFG_READ, "CFG_READ",
1543 megasas_dcmd_cfg_read },
1544 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1545 megasas_dcmd_dummy },
1546 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1553 megasas_dcmd_dummy },
1554 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1555 megasas_dcmd_dummy },
1556 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1557 megasas_dcmd_dummy },
1558 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1559 megasas_dcmd_dummy },
1560 { MFI_DCMD_CLUSTER, "CLUSTER",
1561 megasas_dcmd_dummy },
1562 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1563 megasas_dcmd_dummy },
1564 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1565 megasas_cluster_reset_ld },
1566 { -1, NULL, NULL }
1567 };
1568
1569 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1570 {
1571 int retval = 0;
1572 size_t len;
1573 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1574
1575 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1576 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
1577 if (megasas_map_dcmd(s, cmd) < 0) {
1578 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1579 }
1580 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
1581 cmdptr++;
1582 }
1583 len = cmd->iov_size;
1584 if (cmdptr->opcode == -1) {
1585 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
1586 retval = megasas_dcmd_dummy(s, cmd);
1587 } else {
1588 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1589 retval = cmdptr->func(s, cmd);
1590 }
1591 if (retval != MFI_STAT_INVALID_STATUS) {
1592 megasas_finish_dcmd(cmd, len);
1593 }
1594 return retval;
1595 }
1596
1597 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1598 SCSIRequest *req, size_t resid)
1599 {
1600 int retval = MFI_STAT_OK;
1601 int lun = req->lun;
1602
1603 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
1604 cmd->iov_size -= resid;
1605 switch (cmd->dcmd_opcode) {
1606 case MFI_DCMD_PD_GET_INFO:
1607 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1608 break;
1609 case MFI_DCMD_LD_GET_INFO:
1610 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1611 break;
1612 default:
1613 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
1614 retval = MFI_STAT_INVALID_DCMD;
1615 break;
1616 }
1617 if (retval != MFI_STAT_INVALID_STATUS) {
1618 megasas_finish_dcmd(cmd, cmd->iov_size);
1619 }
1620 return retval;
1621 }
1622
1623 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1624 {
1625 int len;
1626
1627 len = scsi_req_enqueue(cmd->req);
1628 if (len < 0) {
1629 len = -len;
1630 }
1631 if (len > 0) {
1632 if (len > cmd->iov_size) {
1633 if (is_write) {
1634 trace_megasas_iov_write_overflow(cmd->index, len,
1635 cmd->iov_size);
1636 } else {
1637 trace_megasas_iov_read_overflow(cmd->index, len,
1638 cmd->iov_size);
1639 }
1640 }
1641 if (len < cmd->iov_size) {
1642 if (is_write) {
1643 trace_megasas_iov_write_underflow(cmd->index, len,
1644 cmd->iov_size);
1645 } else {
1646 trace_megasas_iov_read_underflow(cmd->index, len,
1647 cmd->iov_size);
1648 }
1649 cmd->iov_size = len;
1650 }
1651 scsi_req_continue(cmd->req);
1652 }
1653 return len;
1654 }
1655
1656 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1657 int frame_cmd)
1658 {
1659 uint8_t *cdb;
1660 int target_id, lun_id, cdb_len;
1661 bool is_write;
1662 struct SCSIDevice *sdev = NULL;
1663 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
1664
1665 cdb = cmd->frame->pass.cdb;
1666 target_id = cmd->frame->header.target_id;
1667 lun_id = cmd->frame->header.lun_id;
1668 cdb_len = cmd->frame->header.cdb_len;
1669
1670 if (is_logical) {
1671 if (target_id >= MFI_MAX_LD || lun_id != 0) {
1672 trace_megasas_scsi_target_not_present(
1673 mfi_frame_desc[frame_cmd], is_logical, target_id, lun_id);
1674 return MFI_STAT_DEVICE_NOT_FOUND;
1675 }
1676 }
1677 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1678
1679 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1680 trace_megasas_handle_scsi(mfi_frame_desc[frame_cmd], is_logical,
1681 target_id, lun_id, sdev, cmd->iov_size);
1682
1683 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1684 trace_megasas_scsi_target_not_present(
1685 mfi_frame_desc[frame_cmd], is_logical, target_id, lun_id);
1686 return MFI_STAT_DEVICE_NOT_FOUND;
1687 }
1688
1689 if (cdb_len > 16) {
1690 trace_megasas_scsi_invalid_cdb_len(
1691 mfi_frame_desc[frame_cmd], is_logical,
1692 target_id, lun_id, cdb_len);
1693 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1694 cmd->frame->header.scsi_status = CHECK_CONDITION;
1695 s->event_count++;
1696 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1697 }
1698
1699 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1700 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1701 cmd->frame->header.scsi_status = CHECK_CONDITION;
1702 s->event_count++;
1703 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1704 }
1705
1706 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cmd);
1707 if (!cmd->req) {
1708 trace_megasas_scsi_req_alloc_failed(
1709 mfi_frame_desc[frame_cmd], target_id, lun_id);
1710 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1711 cmd->frame->header.scsi_status = BUSY;
1712 s->event_count++;
1713 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1714 }
1715
1716 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1717 if (cmd->iov_size) {
1718 if (is_write) {
1719 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1720 } else {
1721 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1722 }
1723 } else {
1724 trace_megasas_scsi_nodata(cmd->index);
1725 }
1726 megasas_enqueue_req(cmd, is_write);
1727 return MFI_STAT_INVALID_STATUS;
1728 }
1729
1730 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
1731 {
1732 uint32_t lba_count, lba_start_hi, lba_start_lo;
1733 uint64_t lba_start;
1734 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
1735 uint8_t cdb[16];
1736 int len;
1737 struct SCSIDevice *sdev = NULL;
1738 int target_id, lun_id, cdb_len;
1739
1740 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1741 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1742 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1743 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1744
1745 target_id = cmd->frame->header.target_id;
1746 lun_id = cmd->frame->header.lun_id;
1747 cdb_len = cmd->frame->header.cdb_len;
1748
1749 if (target_id < MFI_MAX_LD && lun_id == 0) {
1750 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1751 }
1752
1753 trace_megasas_handle_io(cmd->index,
1754 mfi_frame_desc[frame_cmd], target_id, lun_id,
1755 (unsigned long)lba_start, (unsigned long)lba_count);
1756 if (!sdev) {
1757 trace_megasas_io_target_not_present(cmd->index,
1758 mfi_frame_desc[frame_cmd], target_id, lun_id);
1759 return MFI_STAT_DEVICE_NOT_FOUND;
1760 }
1761
1762 if (cdb_len > 16) {
1763 trace_megasas_scsi_invalid_cdb_len(
1764 mfi_frame_desc[frame_cmd], 1, target_id, lun_id, cdb_len);
1765 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1766 cmd->frame->header.scsi_status = CHECK_CONDITION;
1767 s->event_count++;
1768 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1769 }
1770
1771 cmd->iov_size = lba_count * sdev->blocksize;
1772 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1773 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1774 cmd->frame->header.scsi_status = CHECK_CONDITION;
1775 s->event_count++;
1776 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1777 }
1778
1779 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1780 cmd->req = scsi_req_new(sdev, cmd->index,
1781 lun_id, cdb, cmd);
1782 if (!cmd->req) {
1783 trace_megasas_scsi_req_alloc_failed(
1784 mfi_frame_desc[frame_cmd], target_id, lun_id);
1785 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1786 cmd->frame->header.scsi_status = BUSY;
1787 s->event_count++;
1788 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1789 }
1790 len = megasas_enqueue_req(cmd, is_write);
1791 if (len > 0) {
1792 if (is_write) {
1793 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1794 } else {
1795 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1796 }
1797 }
1798 return MFI_STAT_INVALID_STATUS;
1799 }
1800
1801 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1802 {
1803 MegasasCmd *cmd = req->hba_private;
1804
1805 if (cmd->dcmd_opcode != -1) {
1806 return NULL;
1807 } else {
1808 return &cmd->qsg;
1809 }
1810 }
1811
1812 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1813 {
1814 MegasasCmd *cmd = req->hba_private;
1815 uint8_t *buf;
1816
1817 trace_megasas_io_complete(cmd->index, len);
1818
1819 if (cmd->dcmd_opcode != -1) {
1820 scsi_req_continue(req);
1821 return;
1822 }
1823
1824 buf = scsi_req_get_buf(req);
1825 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1826 struct mfi_pd_info *info = cmd->iov_buf;
1827
1828 if (info->inquiry_data[0] == 0x7f) {
1829 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1830 memcpy(info->inquiry_data, buf, len);
1831 } else if (info->vpd_page83[0] == 0x7f) {
1832 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1833 memcpy(info->vpd_page83, buf, len);
1834 }
1835 scsi_req_continue(req);
1836 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
1837 struct mfi_ld_info *info = cmd->iov_buf;
1838
1839 if (cmd->iov_buf) {
1840 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1841 scsi_req_continue(req);
1842 }
1843 }
1844 }
1845
1846 static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1847 size_t resid)
1848 {
1849 MegasasCmd *cmd = req->hba_private;
1850 uint8_t cmd_status = MFI_STAT_OK;
1851
1852 trace_megasas_command_complete(cmd->index, status, resid);
1853
1854 if (req->io_canceled) {
1855 return;
1856 }
1857
1858 if (cmd->dcmd_opcode != -1) {
1859 /*
1860 * Internal command complete
1861 */
1862 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
1863 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1864 return;
1865 }
1866 } else {
1867 req->status = status;
1868 trace_megasas_scsi_complete(cmd->index, req->status,
1869 cmd->iov_size, req->cmd.xfer);
1870 if (req->status != GOOD) {
1871 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1872 }
1873 if (req->status == CHECK_CONDITION) {
1874 megasas_copy_sense(cmd);
1875 }
1876
1877 cmd->frame->header.scsi_status = req->status;
1878 }
1879 cmd->frame->header.cmd_status = cmd_status;
1880 megasas_complete_command(cmd);
1881 }
1882
1883 static void megasas_command_cancelled(SCSIRequest *req)
1884 {
1885 MegasasCmd *cmd = req->hba_private;
1886
1887 if (!cmd) {
1888 return;
1889 }
1890 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1891 megasas_complete_command(cmd);
1892 }
1893
1894 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1895 {
1896 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1897 hwaddr abort_addr, addr_hi, addr_lo;
1898 MegasasCmd *abort_cmd;
1899
1900 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1901 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1902 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1903
1904 abort_cmd = megasas_lookup_frame(s, abort_addr);
1905 if (!abort_cmd) {
1906 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1907 s->event_count++;
1908 return MFI_STAT_OK;
1909 }
1910 if (!megasas_use_queue64(s)) {
1911 abort_ctx &= (uint64_t)0xFFFFFFFF;
1912 }
1913 if (abort_cmd->context != abort_ctx) {
1914 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1915 abort_cmd->index);
1916 s->event_count++;
1917 return MFI_STAT_ABORT_NOT_POSSIBLE;
1918 }
1919 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1920 megasas_abort_command(abort_cmd);
1921 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1922 s->event_cmd = NULL;
1923 }
1924 s->event_count++;
1925 return MFI_STAT_OK;
1926 }
1927
1928 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1929 uint32_t frame_count)
1930 {
1931 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1932 uint64_t frame_context;
1933 int frame_cmd;
1934 MegasasCmd *cmd;
1935
1936 /*
1937 * Always read 64bit context, top bits will be
1938 * masked out if required in megasas_enqueue_frame()
1939 */
1940 frame_context = megasas_frame_get_context(s, frame_addr);
1941
1942 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1943 if (!cmd) {
1944 /* reply queue full */
1945 trace_megasas_frame_busy(frame_addr);
1946 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1947 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1948 megasas_complete_frame(s, frame_context);
1949 s->event_count++;
1950 return;
1951 }
1952 frame_cmd = cmd->frame->header.frame_cmd;
1953 switch (frame_cmd) {
1954 case MFI_CMD_INIT:
1955 frame_status = megasas_init_firmware(s, cmd);
1956 break;
1957 case MFI_CMD_DCMD:
1958 frame_status = megasas_handle_dcmd(s, cmd);
1959 break;
1960 case MFI_CMD_ABORT:
1961 frame_status = megasas_handle_abort(s, cmd);
1962 break;
1963 case MFI_CMD_PD_SCSI_IO:
1964 case MFI_CMD_LD_SCSI_IO:
1965 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
1966 break;
1967 case MFI_CMD_LD_READ:
1968 case MFI_CMD_LD_WRITE:
1969 frame_status = megasas_handle_io(s, cmd, frame_cmd);
1970 break;
1971 default:
1972 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
1973 s->event_count++;
1974 break;
1975 }
1976 if (frame_status != MFI_STAT_INVALID_STATUS) {
1977 if (cmd->frame) {
1978 cmd->frame->header.cmd_status = frame_status;
1979 } else {
1980 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1981 }
1982 megasas_unmap_frame(s, cmd);
1983 megasas_complete_frame(s, cmd->context);
1984 }
1985 }
1986
1987 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
1988 unsigned size)
1989 {
1990 MegasasState *s = opaque;
1991 PCIDevice *pci_dev = PCI_DEVICE(s);
1992 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
1993 uint32_t retval = 0;
1994
1995 switch (addr) {
1996 case MFI_IDB:
1997 retval = 0;
1998 trace_megasas_mmio_readl("MFI_IDB", retval);
1999 break;
2000 case MFI_OMSG0:
2001 case MFI_OSP0:
2002 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2003 (s->fw_state & MFI_FWSTATE_MASK) |
2004 ((s->fw_sge & 0xff) << 16) |
2005 (s->fw_cmds & 0xFFFF);
2006 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2007 retval);
2008 break;
2009 case MFI_OSTS:
2010 if (megasas_intr_enabled(s) && s->doorbell) {
2011 retval = base_class->osts;
2012 }
2013 trace_megasas_mmio_readl("MFI_OSTS", retval);
2014 break;
2015 case MFI_OMSK:
2016 retval = s->intr_mask;
2017 trace_megasas_mmio_readl("MFI_OMSK", retval);
2018 break;
2019 case MFI_ODCR0:
2020 retval = s->doorbell ? 1 : 0;
2021 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2022 break;
2023 case MFI_DIAG:
2024 retval = s->diag;
2025 trace_megasas_mmio_readl("MFI_DIAG", retval);
2026 break;
2027 case MFI_OSP1:
2028 retval = 15;
2029 trace_megasas_mmio_readl("MFI_OSP1", retval);
2030 break;
2031 default:
2032 trace_megasas_mmio_invalid_readl(addr);
2033 break;
2034 }
2035 return retval;
2036 }
2037
2038 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2039
2040 static void megasas_mmio_write(void *opaque, hwaddr addr,
2041 uint64_t val, unsigned size)
2042 {
2043 MegasasState *s = opaque;
2044 PCIDevice *pci_dev = PCI_DEVICE(s);
2045 uint64_t frame_addr;
2046 uint32_t frame_count;
2047 int i;
2048
2049 switch (addr) {
2050 case MFI_IDB:
2051 trace_megasas_mmio_writel("MFI_IDB", val);
2052 if (val & MFI_FWINIT_ABORT) {
2053 /* Abort all pending cmds */
2054 for (i = 0; i < s->fw_cmds; i++) {
2055 megasas_abort_command(&s->frames[i]);
2056 }
2057 }
2058 if (val & MFI_FWINIT_READY) {
2059 /* move to FW READY */
2060 megasas_soft_reset(s);
2061 }
2062 if (val & MFI_FWINIT_MFIMODE) {
2063 /* discard MFIs */
2064 }
2065 if (val & MFI_FWINIT_STOP_ADP) {
2066 /* Terminal error, stop processing */
2067 s->fw_state = MFI_FWSTATE_FAULT;
2068 }
2069 break;
2070 case MFI_OMSK:
2071 trace_megasas_mmio_writel("MFI_OMSK", val);
2072 s->intr_mask = val;
2073 if (!megasas_intr_enabled(s) &&
2074 !msi_enabled(pci_dev) &&
2075 !msix_enabled(pci_dev)) {
2076 trace_megasas_irq_lower();
2077 pci_irq_deassert(pci_dev);
2078 }
2079 if (megasas_intr_enabled(s)) {
2080 if (msix_enabled(pci_dev)) {
2081 trace_megasas_msix_enabled(0);
2082 } else if (msi_enabled(pci_dev)) {
2083 trace_megasas_msi_enabled(0);
2084 } else {
2085 trace_megasas_intr_enabled();
2086 }
2087 } else {
2088 trace_megasas_intr_disabled();
2089 megasas_soft_reset(s);
2090 }
2091 break;
2092 case MFI_ODCR0:
2093 trace_megasas_mmio_writel("MFI_ODCR0", val);
2094 s->doorbell = 0;
2095 if (megasas_intr_enabled(s)) {
2096 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2097 trace_megasas_irq_lower();
2098 pci_irq_deassert(pci_dev);
2099 }
2100 }
2101 break;
2102 case MFI_IQPH:
2103 trace_megasas_mmio_writel("MFI_IQPH", val);
2104 /* Received high 32 bits of a 64 bit MFI frame address */
2105 s->frame_hi = val;
2106 break;
2107 case MFI_IQPL:
2108 trace_megasas_mmio_writel("MFI_IQPL", val);
2109 /* Received low 32 bits of a 64 bit MFI frame address */
2110 /* Fallthrough */
2111 case MFI_IQP:
2112 if (addr == MFI_IQP) {
2113 trace_megasas_mmio_writel("MFI_IQP", val);
2114 /* Received 64 bit MFI frame address */
2115 s->frame_hi = 0;
2116 }
2117 frame_addr = (val & ~0x1F);
2118 /* Add possible 64 bit offset */
2119 frame_addr |= ((uint64_t)s->frame_hi << 32);
2120 s->frame_hi = 0;
2121 frame_count = (val >> 1) & 0xF;
2122 megasas_handle_frame(s, frame_addr, frame_count);
2123 break;
2124 case MFI_SEQ:
2125 trace_megasas_mmio_writel("MFI_SEQ", val);
2126 /* Magic sequence to start ADP reset */
2127 if (adp_reset_seq[s->adp_reset++] == val) {
2128 if (s->adp_reset == 6) {
2129 s->adp_reset = 0;
2130 s->diag = MFI_DIAG_WRITE_ENABLE;
2131 }
2132 } else {
2133 s->adp_reset = 0;
2134 s->diag = 0;
2135 }
2136 break;
2137 case MFI_DIAG:
2138 trace_megasas_mmio_writel("MFI_DIAG", val);
2139 /* ADP reset */
2140 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2141 (val & MFI_DIAG_RESET_ADP)) {
2142 s->diag |= MFI_DIAG_RESET_ADP;
2143 megasas_soft_reset(s);
2144 s->adp_reset = 0;
2145 s->diag = 0;
2146 }
2147 break;
2148 default:
2149 trace_megasas_mmio_invalid_writel(addr, val);
2150 break;
2151 }
2152 }
2153
2154 static const MemoryRegionOps megasas_mmio_ops = {
2155 .read = megasas_mmio_read,
2156 .write = megasas_mmio_write,
2157 .endianness = DEVICE_LITTLE_ENDIAN,
2158 .impl = {
2159 .min_access_size = 8,
2160 .max_access_size = 8,
2161 }
2162 };
2163
2164 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2165 unsigned size)
2166 {
2167 return megasas_mmio_read(opaque, addr & 0xff, size);
2168 }
2169
2170 static void megasas_port_write(void *opaque, hwaddr addr,
2171 uint64_t val, unsigned size)
2172 {
2173 megasas_mmio_write(opaque, addr & 0xff, val, size);
2174 }
2175
2176 static const MemoryRegionOps megasas_port_ops = {
2177 .read = megasas_port_read,
2178 .write = megasas_port_write,
2179 .endianness = DEVICE_LITTLE_ENDIAN,
2180 .impl = {
2181 .min_access_size = 4,
2182 .max_access_size = 4,
2183 }
2184 };
2185
2186 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2187 unsigned size)
2188 {
2189 return 0;
2190 }
2191
2192 static void megasas_queue_write(void *opaque, hwaddr addr,
2193 uint64_t val, unsigned size)
2194 {
2195 return;
2196 }
2197
2198 static const MemoryRegionOps megasas_queue_ops = {
2199 .read = megasas_queue_read,
2200 .write = megasas_queue_write,
2201 .endianness = DEVICE_LITTLE_ENDIAN,
2202 .impl = {
2203 .min_access_size = 8,
2204 .max_access_size = 8,
2205 }
2206 };
2207
2208 static void megasas_soft_reset(MegasasState *s)
2209 {
2210 int i;
2211 MegasasCmd *cmd;
2212
2213 trace_megasas_reset(s->fw_state);
2214 for (i = 0; i < s->fw_cmds; i++) {
2215 cmd = &s->frames[i];
2216 megasas_abort_command(cmd);
2217 }
2218 if (s->fw_state == MFI_FWSTATE_READY) {
2219 BusChild *kid;
2220
2221 /*
2222 * The EFI firmware doesn't handle UA,
2223 * so we need to clear the Power On/Reset UA
2224 * after the initial reset.
2225 */
2226 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2227 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2228
2229 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2230 scsi_device_unit_attention_reported(sdev);
2231 }
2232 }
2233 megasas_reset_frames(s);
2234 s->reply_queue_len = s->fw_cmds;
2235 s->reply_queue_pa = 0;
2236 s->consumer_pa = 0;
2237 s->producer_pa = 0;
2238 s->fw_state = MFI_FWSTATE_READY;
2239 s->doorbell = 0;
2240 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2241 s->frame_hi = 0;
2242 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2243 s->event_count++;
2244 s->boot_event = s->event_count;
2245 }
2246
2247 static void megasas_scsi_reset(DeviceState *dev)
2248 {
2249 MegasasState *s = MEGASAS(dev);
2250
2251 megasas_soft_reset(s);
2252 }
2253
2254 static const VMStateDescription vmstate_megasas_gen1 = {
2255 .name = "megasas",
2256 .version_id = 0,
2257 .minimum_version_id = 0,
2258 .fields = (VMStateField[]) {
2259 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2260 VMSTATE_MSIX(parent_obj, MegasasState),
2261
2262 VMSTATE_INT32(fw_state, MegasasState),
2263 VMSTATE_INT32(intr_mask, MegasasState),
2264 VMSTATE_INT32(doorbell, MegasasState),
2265 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2266 VMSTATE_UINT64(consumer_pa, MegasasState),
2267 VMSTATE_UINT64(producer_pa, MegasasState),
2268 VMSTATE_END_OF_LIST()
2269 }
2270 };
2271
2272 static const VMStateDescription vmstate_megasas_gen2 = {
2273 .name = "megasas-gen2",
2274 .version_id = 0,
2275 .minimum_version_id = 0,
2276 .minimum_version_id_old = 0,
2277 .fields = (VMStateField[]) {
2278 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2279 VMSTATE_MSIX(parent_obj, MegasasState),
2280
2281 VMSTATE_INT32(fw_state, MegasasState),
2282 VMSTATE_INT32(intr_mask, MegasasState),
2283 VMSTATE_INT32(doorbell, MegasasState),
2284 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2285 VMSTATE_UINT64(consumer_pa, MegasasState),
2286 VMSTATE_UINT64(producer_pa, MegasasState),
2287 VMSTATE_END_OF_LIST()
2288 }
2289 };
2290
2291 static void megasas_scsi_uninit(PCIDevice *d)
2292 {
2293 MegasasState *s = MEGASAS(d);
2294
2295 if (megasas_use_msix(s)) {
2296 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2297 }
2298 msi_uninit(d);
2299 }
2300
2301 static const struct SCSIBusInfo megasas_scsi_info = {
2302 .tcq = true,
2303 .max_target = MFI_MAX_LD,
2304 .max_lun = 255,
2305
2306 .transfer_data = megasas_xfer_complete,
2307 .get_sg_list = megasas_get_sg_list,
2308 .complete = megasas_command_complete,
2309 .cancel = megasas_command_cancelled,
2310 };
2311
2312 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2313 {
2314 MegasasState *s = MEGASAS(dev);
2315 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
2316 uint8_t *pci_conf;
2317 int i, bar_type;
2318 Error *err = NULL;
2319 int ret;
2320
2321 pci_conf = dev->config;
2322
2323 /* PCI latency timer = 0 */
2324 pci_conf[PCI_LATENCY_TIMER] = 0;
2325 /* Interrupt pin 1 */
2326 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2327
2328 if (s->msi != ON_OFF_AUTO_OFF) {
2329 ret = msi_init(dev, 0x50, 1, true, false, &err);
2330 /* Any error other than -ENOTSUP(board's MSI support is broken)
2331 * is a programming error */
2332 assert(!ret || ret == -ENOTSUP);
2333 if (ret && s->msi == ON_OFF_AUTO_ON) {
2334 /* Can't satisfy user's explicit msi=on request, fail */
2335 error_append_hint(&err, "You have to use msi=auto (default) or "
2336 "msi=off with this machine type.\n");
2337 error_propagate(errp, err);
2338 return;
2339 } else if (ret) {
2340 /* With msi=auto, we fall back to MSI off silently */
2341 s->msi = ON_OFF_AUTO_OFF;
2342 error_free(err);
2343 }
2344 }
2345
2346 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2347 "megasas-mmio", 0x4000);
2348 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2349 "megasas-io", 256);
2350 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2351 "megasas-queue", 0x40000);
2352
2353 if (megasas_use_msix(s) &&
2354 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2355 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2356 /* TODO: check msix_init's error, and should fail on msix=on */
2357 s->msix = ON_OFF_AUTO_OFF;
2358 }
2359
2360 if (pci_is_express(dev)) {
2361 pcie_endpoint_cap_init(dev, 0xa0);
2362 }
2363
2364 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2365 pci_register_bar(dev, b->ioport_bar,
2366 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2367 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2368 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2369
2370 if (megasas_use_msix(s)) {
2371 msix_vector_use(dev, 0);
2372 }
2373
2374 s->fw_state = MFI_FWSTATE_READY;
2375 if (!s->sas_addr) {
2376 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2377 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2378 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
2379 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2380 s->sas_addr |= PCI_FUNC(dev->devfn);
2381 }
2382 if (!s->hba_serial) {
2383 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2384 }
2385 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2386 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2387 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2388 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2389 } else {
2390 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2391 }
2392 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2393 s->fw_cmds = MEGASAS_MAX_FRAMES;
2394 }
2395 trace_megasas_init(s->fw_sge, s->fw_cmds,
2396 megasas_is_jbod(s) ? "jbod" : "raid");
2397
2398 if (megasas_is_jbod(s)) {
2399 s->fw_luns = MFI_MAX_SYS_PDS;
2400 } else {
2401 s->fw_luns = MFI_MAX_LD;
2402 }
2403 s->producer_pa = 0;
2404 s->consumer_pa = 0;
2405 for (i = 0; i < s->fw_cmds; i++) {
2406 s->frames[i].index = i;
2407 s->frames[i].context = -1;
2408 s->frames[i].pa = 0;
2409 s->frames[i].state = s;
2410 }
2411
2412 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2413 &megasas_scsi_info, NULL);
2414 }
2415
2416 static Property megasas_properties_gen1[] = {
2417 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2418 MEGASAS_DEFAULT_SGE),
2419 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2420 MEGASAS_DEFAULT_FRAMES),
2421 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2422 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2423 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2424 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2425 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2426 MEGASAS_FLAG_USE_JBOD, false),
2427 DEFINE_PROP_END_OF_LIST(),
2428 };
2429
2430 static Property megasas_properties_gen2[] = {
2431 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2432 MEGASAS_DEFAULT_SGE),
2433 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2434 MEGASAS_GEN2_DEFAULT_FRAMES),
2435 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2436 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2437 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2438 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2439 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2440 MEGASAS_FLAG_USE_JBOD, false),
2441 DEFINE_PROP_END_OF_LIST(),
2442 };
2443
2444 typedef struct MegasasInfo {
2445 const char *name;
2446 const char *desc;
2447 const char *product_name;
2448 const char *product_version;
2449 uint16_t device_id;
2450 uint16_t subsystem_id;
2451 int ioport_bar;
2452 int mmio_bar;
2453 int osts;
2454 const VMStateDescription *vmsd;
2455 Property *props;
2456 InterfaceInfo *interfaces;
2457 } MegasasInfo;
2458
2459 static struct MegasasInfo megasas_devices[] = {
2460 {
2461 .name = TYPE_MEGASAS_GEN1,
2462 .desc = "LSI MegaRAID SAS 1078",
2463 .product_name = "LSI MegaRAID SAS 8708EM2",
2464 .product_version = MEGASAS_VERSION_GEN1,
2465 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2466 .subsystem_id = 0x1013,
2467 .ioport_bar = 2,
2468 .mmio_bar = 0,
2469 .osts = MFI_1078_RM | 1,
2470 .vmsd = &vmstate_megasas_gen1,
2471 .props = megasas_properties_gen1,
2472 .interfaces = (InterfaceInfo[]) {
2473 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2474 { },
2475 },
2476 },{
2477 .name = TYPE_MEGASAS_GEN2,
2478 .desc = "LSI MegaRAID SAS 2108",
2479 .product_name = "LSI MegaRAID SAS 9260-8i",
2480 .product_version = MEGASAS_VERSION_GEN2,
2481 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2482 .subsystem_id = 0x9261,
2483 .ioport_bar = 0,
2484 .mmio_bar = 1,
2485 .osts = MFI_GEN2_RM,
2486 .vmsd = &vmstate_megasas_gen2,
2487 .props = megasas_properties_gen2,
2488 .interfaces = (InterfaceInfo[]) {
2489 { INTERFACE_PCIE_DEVICE },
2490 { }
2491 },
2492 }
2493 };
2494
2495 static void megasas_class_init(ObjectClass *oc, void *data)
2496 {
2497 DeviceClass *dc = DEVICE_CLASS(oc);
2498 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2499 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2500 const MegasasInfo *info = data;
2501
2502 pc->realize = megasas_scsi_realize;
2503 pc->exit = megasas_scsi_uninit;
2504 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2505 pc->device_id = info->device_id;
2506 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2507 pc->subsystem_id = info->subsystem_id;
2508 pc->class_id = PCI_CLASS_STORAGE_RAID;
2509 e->mmio_bar = info->mmio_bar;
2510 e->ioport_bar = info->ioport_bar;
2511 e->osts = info->osts;
2512 e->product_name = info->product_name;
2513 e->product_version = info->product_version;
2514 device_class_set_props(dc, info->props);
2515 dc->reset = megasas_scsi_reset;
2516 dc->vmsd = info->vmsd;
2517 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2518 dc->desc = info->desc;
2519 }
2520
2521 static const TypeInfo megasas_info = {
2522 .name = TYPE_MEGASAS_BASE,
2523 .parent = TYPE_PCI_DEVICE,
2524 .instance_size = sizeof(MegasasState),
2525 .class_size = sizeof(MegasasBaseClass),
2526 .abstract = true,
2527 };
2528
2529 static void megasas_register_types(void)
2530 {
2531 int i;
2532
2533 type_register_static(&megasas_info);
2534 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2535 const MegasasInfo *info = &megasas_devices[i];
2536 TypeInfo type_info = {};
2537
2538 type_info.name = info->name;
2539 type_info.parent = TYPE_MEGASAS_BASE;
2540 type_info.class_data = (void *)info;
2541 type_info.class_init = megasas_class_init;
2542 type_info.interfaces = info->interfaces;
2543
2544 type_register(&type_info);
2545 }
2546 }
2547
2548 type_init(megasas_register_types)
AR7 emulation for QEMU