include/hw/core/tcg-cpu-ops.h

   1 /*
   2  * TCG CPU-specific operations
   3  *
   4  * Copyright 2021 SUSE LLC
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef TCG_CPU_OPS_H
  11 #define TCG_CPU_OPS_H
  12
  13 #include "hw/core/cpu.h"
  14
  15 struct TCGCPUOps {
  16     /**
  17      * @initialize: Initalize TCG state
  18      *
  19      * Called when the first CPU is realized.
  20      */
  21     void (*initialize)(void);
  22     /**
  23      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
  24      *
  25      * This is called when we abandon execution of a TB before starting it,
  26      * and must set all parts of the CPU state which the previous TB in the
  27      * chain may not have updated.
  28      * By default, when this is NULL, a call is made to @set_pc(tb->pc).
  29      *
  30      * If more state needs to be restored, the target must implement a
  31      * function to restore all the state, and register it here.
  32      */
  33     void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
  34     /** @cpu_exec_enter: Callback for cpu_exec preparation */
  35     void (*cpu_exec_enter)(CPUState *cpu);
  36     /** @cpu_exec_exit: Callback for cpu_exec cleanup */
  37     void (*cpu_exec_exit)(CPUState *cpu);
  38     /** @debug_excp_handler: Callback for handling debug exceptions */
  39     void (*debug_excp_handler)(CPUState *cpu);
  40
  41 #ifdef NEED_CPU_H
  42 #if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
  43     /**
  44      * @fake_user_interrupt: Callback for 'fake exception' handling.
  45      *
  46      * Simulate 'fake exception' which will be handled outside the
  47      * cpu execution loop (hack for x86 user mode).
  48      */
  49     void (*fake_user_interrupt)(CPUState *cpu);
  50 #else
  51     /**
  52      * @do_interrupt: Callback for interrupt handling.
  53      */
  54     void (*do_interrupt)(CPUState *cpu);
  55 #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
  56 #ifdef CONFIG_SOFTMMU
  57     /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
  58     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
  59     /**
  60      * @tlb_fill: Handle a softmmu tlb miss
  61      *
  62      * If the access is valid, call tlb_set_page and return true;
  63      * if the access is invalid and probe is true, return false;
  64      * otherwise raise an exception and do not return.
  65      */
  66     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
  67                      MMUAccessType access_type, int mmu_idx,
  68                      bool probe, uintptr_t retaddr);
  69     /**
  70      * @do_transaction_failed: Callback for handling failed memory transactions
  71      * (ie bus faults or external aborts; not MMU faults)
  72      */
  73     void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
  74                                   unsigned size, MMUAccessType access_type,
  75                                   int mmu_idx, MemTxAttrs attrs,
  76                                   MemTxResult response, uintptr_t retaddr);
  77     /**
  78      * @do_unaligned_access: Callback for unaligned access handling
  79      * The callback must exit via raising an exception.
  80      */
  81     G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
  82                                            MMUAccessType access_type,
  83                                            int mmu_idx, uintptr_t retaddr);
  84
  85     /**
  86      * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
  87      */
  88     vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
  89
  90     /**
  91      * @debug_check_watchpoint: return true if the architectural
  92      * watchpoint whose address has matched should really fire, used by ARM
  93      * and RISC-V
  94      */
  95     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
  96
  97     /**
  98      * @debug_check_breakpoint: return true if the architectural
  99      * breakpoint whose PC has matched should really fire.
 100      */
 101     bool (*debug_check_breakpoint)(CPUState *cpu);
 102
 103     /**
 104      * @io_recompile_replay_branch: Callback for cpu_io_recompile.
 105      *
 106      * The cpu has been stopped, and cpu_restore_state_from_tb has been
 107      * called.  If the faulting instruction is in a delay slot, and the
 108      * target architecture requires re-execution of the branch, then
 109      * adjust the cpu state as required and return true.
 110      */
 111     bool (*io_recompile_replay_branch)(CPUState *cpu,
 112                                        const TranslationBlock *tb);
 113 #else
 114     /**
 115      * record_sigsegv:
 116      * @cpu: cpu context
 117      * @addr: faulting guest address
 118      * @access_type: access was read/write/execute
 119      * @maperr: true for invalid page, false for permission fault
 120      * @ra: host pc for unwinding
 121      *
 122      * We are about to raise SIGSEGV with si_code set for @maperr,
 123      * and si_addr set for @addr.  Record anything further needed
 124      * for the signal ucontext_t.
 125      *
 126      * If the emulated kernel does not provide anything to the signal
 127      * handler with anything besides the user context registers, and
 128      * the siginfo_t, then this hook need do nothing and may be omitted.
 129      * Otherwise, record the data and return; the caller will raise
 130      * the signal, unwind the cpu state, and return to the main loop.
 131      *
 132      * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
 133      * so that a "normal" cpu exception can be raised.  In this case,
 134      * the signal must be raised by the architecture cpu_loop.
 135      */
 136     void (*record_sigsegv)(CPUState *cpu, vaddr addr,
 137                            MMUAccessType access_type,
 138                            bool maperr, uintptr_t ra);
 139     /**
 140      * record_sigbus:
 141      * @cpu: cpu context
 142      * @addr: misaligned guest address
 143      * @access_type: access was read/write/execute
 144      * @ra: host pc for unwinding
 145      *
 146      * We are about to raise SIGBUS with si_code BUS_ADRALN,
 147      * and si_addr set for @addr.  Record anything further needed
 148      * for the signal ucontext_t.
 149      *
 150      * If the emulated kernel does not provide the signal handler with
 151      * anything besides the user context registers, and the siginfo_t,
 152      * then this hook need do nothing and may be omitted.
 153      * Otherwise, record the data and return; the caller will raise
 154      * the signal, unwind the cpu state, and return to the main loop.
 155      *
 156      * If it is simpler to re-use the sysemu do_unaligned_access code,
 157      * @ra is provided so that a "normal" cpu exception can be raised.
 158      * In this case, the signal must be raised by the architecture cpu_loop.
 159      */
 160     void (*record_sigbus)(CPUState *cpu, vaddr addr,
 161                           MMUAccessType access_type, uintptr_t ra);
 162 #endif /* CONFIG_SOFTMMU */
 163 #endif /* NEED_CPU_H */
 164
 165 };
 166
 167 #endif /* TCG_CPU_OPS_H */