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vfio: simplify the conditional statements in vfio_msi_enable
[qemu/ar7.git] / hw / usb / hcd-ohci.c
blob895b29fb8657916d482c9106f4c675e583a5f2aa
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o BIOS work to boot from USB storage
26 */
27
28 #include "qemu/osdep.h"
29 #include "hw/irq.h"
30 #include "qapi/error.h"
31 #include "qemu/module.h"
32 #include "qemu/timer.h"
33 #include "hw/usb.h"
34 #include "migration/vmstate.h"
35 #include "hw/sysbus.h"
36 #include "hw/qdev-dma.h"
37 #include "hw/qdev-properties.h"
38 #include "trace.h"
39 #include "hcd-ohci.h"
40
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #define ED_LINK_LIMIT 32
45
46 static int64_t usb_frame_time;
47 static int64_t usb_bit_time;
48
49 /* Host Controller Communications Area */
50 struct ohci_hcca {
51 uint32_t intr[32];
52 uint16_t frame, pad;
53 uint32_t done;
54 };
55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
57
58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
59 #define ED_WBACK_SIZE 4
60
61 /* Bitfields for the first word of an Endpoint Desciptor. */
62 #define OHCI_ED_FA_SHIFT 0
63 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
64 #define OHCI_ED_EN_SHIFT 7
65 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
66 #define OHCI_ED_D_SHIFT 11
67 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
68 #define OHCI_ED_S (1<<13)
69 #define OHCI_ED_K (1<<14)
70 #define OHCI_ED_F (1<<15)
71 #define OHCI_ED_MPS_SHIFT 16
72 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
73
74 /* Flags in the head field of an Endpoint Desciptor. */
75 #define OHCI_ED_H 1
76 #define OHCI_ED_C 2
77
78 /* Bitfields for the first word of a Transfer Desciptor. */
79 #define OHCI_TD_R (1<<18)
80 #define OHCI_TD_DP_SHIFT 19
81 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
82 #define OHCI_TD_DI_SHIFT 21
83 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
84 #define OHCI_TD_T0 (1<<24)
85 #define OHCI_TD_T1 (1<<25)
86 #define OHCI_TD_EC_SHIFT 26
87 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
88 #define OHCI_TD_CC_SHIFT 28
89 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
90
91 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
92 /* CC & DI - same as in the General Transfer Desciptor */
93 #define OHCI_TD_SF_SHIFT 0
94 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
95 #define OHCI_TD_FC_SHIFT 24
96 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
97
98 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
99 #define OHCI_TD_PSW_CC_SHIFT 12
100 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
101 #define OHCI_TD_PSW_SIZE_SHIFT 0
102 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
103
104 #define OHCI_PAGE_MASK 0xfffff000
105 #define OHCI_OFFSET_MASK 0xfff
106
107 #define OHCI_DPTR_MASK 0xfffffff0
108
109 #define OHCI_BM(val, field) \
110 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
111
112 #define OHCI_SET_BM(val, field, newval) do { \
113 val &= ~OHCI_##field##_MASK; \
114 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
115 } while(0)
116
117 /* endpoint descriptor */
118 struct ohci_ed {
119 uint32_t flags;
120 uint32_t tail;
121 uint32_t head;
122 uint32_t next;
123 };
124
125 /* General transfer descriptor */
126 struct ohci_td {
127 uint32_t flags;
128 uint32_t cbp;
129 uint32_t next;
130 uint32_t be;
131 };
132
133 /* Isochronous transfer descriptor */
134 struct ohci_iso_td {
135 uint32_t flags;
136 uint32_t bp;
137 uint32_t next;
138 uint32_t be;
139 uint16_t offset[8];
140 };
141
142 #define USB_HZ 12000000
143
144 /* OHCI Local stuff */
145 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
146 #define OHCI_CTL_PLE (1<<2)
147 #define OHCI_CTL_IE (1<<3)
148 #define OHCI_CTL_CLE (1<<4)
149 #define OHCI_CTL_BLE (1<<5)
150 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
151 #define OHCI_USB_RESET 0x00
152 #define OHCI_USB_RESUME 0x40
153 #define OHCI_USB_OPERATIONAL 0x80
154 #define OHCI_USB_SUSPEND 0xc0
155 #define OHCI_CTL_IR (1<<8)
156 #define OHCI_CTL_RWC (1<<9)
157 #define OHCI_CTL_RWE (1<<10)
158
159 #define OHCI_STATUS_HCR (1<<0)
160 #define OHCI_STATUS_CLF (1<<1)
161 #define OHCI_STATUS_BLF (1<<2)
162 #define OHCI_STATUS_OCR (1<<3)
163 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
164
165 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
166 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
167 #define OHCI_INTR_SF (1U<<2) /* Start of frame */
168 #define OHCI_INTR_RD (1U<<3) /* Resume detect */
169 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
170 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
171 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
172 #define OHCI_INTR_OC (1U<<30) /* Ownership change */
173 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
174
175 #define OHCI_HCCA_SIZE 0x100
176 #define OHCI_HCCA_MASK 0xffffff00
177
178 #define OHCI_EDPTR_MASK 0xfffffff0
179
180 #define OHCI_FMI_FI 0x00003fff
181 #define OHCI_FMI_FSMPS 0xffff0000
182 #define OHCI_FMI_FIT 0x80000000
183
184 #define OHCI_FR_RT (1U<<31)
185
186 #define OHCI_LS_THRESH 0x628
187
188 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
189 #define OHCI_RHA_PSM (1<<8)
190 #define OHCI_RHA_NPS (1<<9)
191 #define OHCI_RHA_DT (1<<10)
192 #define OHCI_RHA_OCPM (1<<11)
193 #define OHCI_RHA_NOCP (1<<12)
194 #define OHCI_RHA_POTPGT_MASK 0xff000000
195
196 #define OHCI_RHS_LPS (1U<<0)
197 #define OHCI_RHS_OCI (1U<<1)
198 #define OHCI_RHS_DRWE (1U<<15)
199 #define OHCI_RHS_LPSC (1U<<16)
200 #define OHCI_RHS_OCIC (1U<<17)
201 #define OHCI_RHS_CRWE (1U<<31)
202
203 #define OHCI_PORT_CCS (1<<0)
204 #define OHCI_PORT_PES (1<<1)
205 #define OHCI_PORT_PSS (1<<2)
206 #define OHCI_PORT_POCI (1<<3)
207 #define OHCI_PORT_PRS (1<<4)
208 #define OHCI_PORT_PPS (1<<8)
209 #define OHCI_PORT_LSDA (1<<9)
210 #define OHCI_PORT_CSC (1<<16)
211 #define OHCI_PORT_PESC (1<<17)
212 #define OHCI_PORT_PSSC (1<<18)
213 #define OHCI_PORT_OCIC (1<<19)
214 #define OHCI_PORT_PRSC (1<<20)
215 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
216 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
217
218 #define OHCI_TD_DIR_SETUP 0x0
219 #define OHCI_TD_DIR_OUT 0x1
220 #define OHCI_TD_DIR_IN 0x2
221 #define OHCI_TD_DIR_RESERVED 0x3
222
223 #define OHCI_CC_NOERROR 0x0
224 #define OHCI_CC_CRC 0x1
225 #define OHCI_CC_BITSTUFFING 0x2
226 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
227 #define OHCI_CC_STALL 0x4
228 #define OHCI_CC_DEVICENOTRESPONDING 0x5
229 #define OHCI_CC_PIDCHECKFAILURE 0x6
230 #define OHCI_CC_UNDEXPETEDPID 0x7
231 #define OHCI_CC_DATAOVERRUN 0x8
232 #define OHCI_CC_DATAUNDERRUN 0x9
233 #define OHCI_CC_BUFFEROVERRUN 0xc
234 #define OHCI_CC_BUFFERUNDERRUN 0xd
235
236 #define OHCI_HRESET_FSBIR (1 << 0)
237
238 static void ohci_die(OHCIState *ohci)
239 {
240 ohci->ohci_die(ohci);
241 }
242
243 /* Update IRQ levels */
244 static inline void ohci_intr_update(OHCIState *ohci)
245 {
246 int level = 0;
247
248 if ((ohci->intr & OHCI_INTR_MIE) &&
249 (ohci->intr_status & ohci->intr))
250 level = 1;
251
252 qemu_set_irq(ohci->irq, level);
253 }
254
255 /* Set an interrupt */
256 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
257 {
258 ohci->intr_status |= intr;
259 ohci_intr_update(ohci);
260 }
261
262 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr)
263 {
264 USBDevice *dev;
265 int i;
266
267 for (i = 0; i < ohci->num_ports; i++) {
268 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) {
269 continue;
270 }
271 dev = usb_find_device(&ohci->rhport[i].port, addr);
272 if (dev != NULL) {
273 return dev;
274 }
275 }
276 return NULL;
277 }
278
279 void ohci_stop_endpoints(OHCIState *ohci)
280 {
281 USBDevice *dev;
282 int i, j;
283
284 if (ohci->async_td) {
285 usb_cancel_packet(&ohci->usb_packet);
286 ohci->async_td = 0;
287 }
288 for (i = 0; i < ohci->num_ports; i++) {
289 dev = ohci->rhport[i].port.dev;
290 if (dev && dev->attached) {
291 usb_device_ep_stopped(dev, &dev->ep_ctl);
292 for (j = 0; j < USB_MAX_ENDPOINTS; j++) {
293 usb_device_ep_stopped(dev, &dev->ep_in[j]);
294 usb_device_ep_stopped(dev, &dev->ep_out[j]);
295 }
296 }
297 }
298 }
299
300 static void ohci_roothub_reset(OHCIState *ohci)
301 {
302 OHCIPort *port;
303 int i;
304
305 ohci_bus_stop(ohci);
306 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
307 ohci->rhdesc_b = 0x0; /* Impl. specific */
308 ohci->rhstatus = 0;
309
310 for (i = 0; i < ohci->num_ports; i++) {
311 port = &ohci->rhport[i];
312 port->ctrl = 0;
313 if (port->port.dev && port->port.dev->attached) {
314 usb_port_reset(&port->port);
315 }
316 }
317 ohci_stop_endpoints(ohci);
318 }
319
320 /* Reset the controller */
321 static void ohci_soft_reset(OHCIState *ohci)
322 {
323 trace_usb_ohci_reset(ohci->name);
324
325 ohci_bus_stop(ohci);
326 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND;
327 ohci->old_ctl = 0;
328 ohci->status = 0;
329 ohci->intr_status = 0;
330 ohci->intr = OHCI_INTR_MIE;
331
332 ohci->hcca = 0;
333 ohci->ctrl_head = ohci->ctrl_cur = 0;
334 ohci->bulk_head = ohci->bulk_cur = 0;
335 ohci->per_cur = 0;
336 ohci->done = 0;
337 ohci->done_count = 7;
338
339 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
340 * I took the value linux sets ...
341 */
342 ohci->fsmps = 0x2778;
343 ohci->fi = 0x2edf;
344 ohci->fit = 0;
345 ohci->frt = 0;
346 ohci->frame_number = 0;
347 ohci->pstart = 0;
348 ohci->lst = OHCI_LS_THRESH;
349 }
350
351 void ohci_hard_reset(OHCIState *ohci)
352 {
353 ohci_soft_reset(ohci);
354 ohci->ctl = 0;
355 ohci_roothub_reset(ohci);
356 }
357
358 /* Get an array of dwords from main memory */
359 static inline int get_dwords(OHCIState *ohci,
360 dma_addr_t addr, uint32_t *buf, int num)
361 {
362 int i;
363
364 addr += ohci->localmem_base;
365
366 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
367 if (dma_memory_read(ohci->as, addr,
368 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
369 return -1;
370 }
371 *buf = le32_to_cpu(*buf);
372 }
373
374 return 0;
375 }
376
377 /* Put an array of dwords in to main memory */
378 static inline int put_dwords(OHCIState *ohci,
379 dma_addr_t addr, uint32_t *buf, int num)
380 {
381 int i;
382
383 addr += ohci->localmem_base;
384
385 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
386 uint32_t tmp = cpu_to_le32(*buf);
387 if (dma_memory_write(ohci->as, addr,
388 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
389 return -1;
390 }
391 }
392
393 return 0;
394 }
395
396 /* Get an array of words from main memory */
397 static inline int get_words(OHCIState *ohci,
398 dma_addr_t addr, uint16_t *buf, int num)
399 {
400 int i;
401
402 addr += ohci->localmem_base;
403
404 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
405 if (dma_memory_read(ohci->as, addr,
406 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
407 return -1;
408 }
409 *buf = le16_to_cpu(*buf);
410 }
411
412 return 0;
413 }
414
415 /* Put an array of words in to main memory */
416 static inline int put_words(OHCIState *ohci,
417 dma_addr_t addr, uint16_t *buf, int num)
418 {
419 int i;
420
421 addr += ohci->localmem_base;
422
423 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
424 uint16_t tmp = cpu_to_le16(*buf);
425 if (dma_memory_write(ohci->as, addr,
426 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
427 return -1;
428 }
429 }
430
431 return 0;
432 }
433
434 static inline int ohci_read_ed(OHCIState *ohci,
435 dma_addr_t addr, struct ohci_ed *ed)
436 {
437 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
438 }
439
440 static inline int ohci_read_td(OHCIState *ohci,
441 dma_addr_t addr, struct ohci_td *td)
442 {
443 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
444 }
445
446 static inline int ohci_read_iso_td(OHCIState *ohci,
447 dma_addr_t addr, struct ohci_iso_td *td)
448 {
449 return get_dwords(ohci, addr, (uint32_t *)td, 4) ||
450 get_words(ohci, addr + 16, td->offset, 8);
451 }
452
453 static inline int ohci_read_hcca(OHCIState *ohci,
454 dma_addr_t addr, struct ohci_hcca *hcca)
455 {
456 return dma_memory_read(ohci->as, addr + ohci->localmem_base, hcca,
457 sizeof(*hcca), MEMTXATTRS_UNSPECIFIED);
458 }
459
460 static inline int ohci_put_ed(OHCIState *ohci,
461 dma_addr_t addr, struct ohci_ed *ed)
462 {
463 /* ed->tail is under control of the HCD.
464 * Since just ed->head is changed by HC, just write back this
465 */
466
467 return put_dwords(ohci, addr + ED_WBACK_OFFSET,
468 (uint32_t *)((char *)ed + ED_WBACK_OFFSET),
469 ED_WBACK_SIZE >> 2);
470 }
471
472 static inline int ohci_put_td(OHCIState *ohci,
473 dma_addr_t addr, struct ohci_td *td)
474 {
475 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
476 }
477
478 static inline int ohci_put_iso_td(OHCIState *ohci,
479 dma_addr_t addr, struct ohci_iso_td *td)
480 {
481 return put_dwords(ohci, addr, (uint32_t *)td, 4) ||
482 put_words(ohci, addr + 16, td->offset, 8);
483 }
484
485 static inline int ohci_put_hcca(OHCIState *ohci,
486 dma_addr_t addr, struct ohci_hcca *hcca)
487 {
488 return dma_memory_write(ohci->as,
489 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET,
490 (char *)hcca + HCCA_WRITEBACK_OFFSET,
491 HCCA_WRITEBACK_SIZE, MEMTXATTRS_UNSPECIFIED);
492 }
493
494 /* Read/Write the contents of a TD from/to main memory. */
495 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
496 uint8_t *buf, int len, DMADirection dir)
497 {
498 dma_addr_t ptr, n;
499
500 ptr = td->cbp;
501 n = 0x1000 - (ptr & 0xfff);
502 if (n > len)
503 n = len;
504
505 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
506 n, dir, MEMTXATTRS_UNSPECIFIED)) {
507 return -1;
508 }
509 if (n == len) {
510 return 0;
511 }
512 ptr = td->be & ~0xfffu;
513 buf += n;
514 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
515 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
516 return -1;
517 }
518 return 0;
519 }
520
521 /* Read/Write the contents of an ISO TD from/to main memory. */
522 static int ohci_copy_iso_td(OHCIState *ohci,
523 uint32_t start_addr, uint32_t end_addr,
524 uint8_t *buf, int len, DMADirection dir)
525 {
526 dma_addr_t ptr, n;
527
528 ptr = start_addr;
529 n = 0x1000 - (ptr & 0xfff);
530 if (n > len)
531 n = len;
532
533 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
534 n, dir, MEMTXATTRS_UNSPECIFIED)) {
535 return -1;
536 }
537 if (n == len) {
538 return 0;
539 }
540 ptr = end_addr & ~0xfffu;
541 buf += n;
542 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
543 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
544 return -1;
545 }
546 return 0;
547 }
548
549 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
550
551 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
552 {
553 int dir;
554 size_t len = 0;
555 const char *str = NULL;
556 int pid;
557 int ret;
558 int i;
559 USBDevice *dev;
560 USBEndpoint *ep;
561 USBPacket *pkt;
562 uint8_t buf[8192];
563 bool int_req;
564 struct ohci_iso_td iso_td;
565 uint32_t addr;
566 uint16_t starting_frame;
567 int16_t relative_frame_number;
568 int frame_count;
569 uint32_t start_offset, next_offset, end_offset = 0;
570 uint32_t start_addr, end_addr;
571
572 addr = ed->head & OHCI_DPTR_MASK;
573
574 if (ohci_read_iso_td(ohci, addr, &iso_td)) {
575 trace_usb_ohci_iso_td_read_failed(addr);
576 ohci_die(ohci);
577 return 1;
578 }
579
580 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
581 frame_count = OHCI_BM(iso_td.flags, TD_FC);
582 relative_frame_number = USUB(ohci->frame_number, starting_frame);
583
584 trace_usb_ohci_iso_td_head(
585 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
586 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
587 ohci->frame_number, starting_frame,
588 frame_count, relative_frame_number);
589 trace_usb_ohci_iso_td_head_offset(
590 iso_td.offset[0], iso_td.offset[1],
591 iso_td.offset[2], iso_td.offset[3],
592 iso_td.offset[4], iso_td.offset[5],
593 iso_td.offset[6], iso_td.offset[7]);
594
595 if (relative_frame_number < 0) {
596 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number);
597 return 1;
598 } else if (relative_frame_number > frame_count) {
599 /* ISO TD expired - retire the TD to the Done Queue and continue with
600 the next ISO TD of the same ED */
601 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number,
602 frame_count);
603 if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) {
604 /* avoid infinite loop */
605 return 1;
606 }
607 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
608 ed->head &= ~OHCI_DPTR_MASK;
609 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
610 iso_td.next = ohci->done;
611 ohci->done = addr;
612 i = OHCI_BM(iso_td.flags, TD_DI);
613 if (i < ohci->done_count)
614 ohci->done_count = i;
615 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
616 ohci_die(ohci);
617 return 1;
618 }
619 return 0;
620 }
621
622 dir = OHCI_BM(ed->flags, ED_D);
623 switch (dir) {
624 case OHCI_TD_DIR_IN:
625 str = "in";
626 pid = USB_TOKEN_IN;
627 break;
628 case OHCI_TD_DIR_OUT:
629 str = "out";
630 pid = USB_TOKEN_OUT;
631 break;
632 case OHCI_TD_DIR_SETUP:
633 str = "setup";
634 pid = USB_TOKEN_SETUP;
635 break;
636 default:
637 trace_usb_ohci_iso_td_bad_direction(dir);
638 return 1;
639 }
640
641 if (!iso_td.bp || !iso_td.be) {
642 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be);
643 return 1;
644 }
645
646 start_offset = iso_td.offset[relative_frame_number];
647 if (relative_frame_number < frame_count) {
648 next_offset = iso_td.offset[relative_frame_number + 1];
649 } else {
650 next_offset = iso_td.be;
651 }
652
653 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
654 ((relative_frame_number < frame_count) &&
655 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
656 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset);
657 return 1;
658 }
659
660 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
661 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset);
662 return 1;
663 }
664
665 if ((start_offset & 0x1000) == 0) {
666 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
667 (start_offset & OHCI_OFFSET_MASK);
668 } else {
669 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
670 (start_offset & OHCI_OFFSET_MASK);
671 }
672
673 if (relative_frame_number < frame_count) {
674 end_offset = next_offset - 1;
675 if ((end_offset & 0x1000) == 0) {
676 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
677 (end_offset & OHCI_OFFSET_MASK);
678 } else {
679 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
680 (end_offset & OHCI_OFFSET_MASK);
681 }
682 } else {
683 /* Last packet in the ISO TD */
684 end_addr = next_offset;
685 }
686
687 if (start_addr > end_addr) {
688 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr);
689 return 1;
690 }
691
692 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
693 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
694 - (start_addr & OHCI_OFFSET_MASK);
695 } else {
696 len = end_addr - start_addr + 1;
697 }
698 if (len > sizeof(buf)) {
699 len = sizeof(buf);
700 }
701
702 if (len && dir != OHCI_TD_DIR_IN) {
703 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, len,
704 DMA_DIRECTION_TO_DEVICE)) {
705 ohci_die(ohci);
706 return 1;
707 }
708 }
709
710 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
711 if (dev == NULL) {
712 trace_usb_ohci_td_dev_error();
713 return 1;
714 }
715 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
716 pkt = g_new0(USBPacket, 1);
717 usb_packet_init(pkt);
718 int_req = relative_frame_number == frame_count &&
719 OHCI_BM(iso_td.flags, TD_DI) == 0;
720 usb_packet_setup(pkt, pid, ep, 0, addr, false, int_req);
721 usb_packet_addbuf(pkt, buf, len);
722 usb_handle_packet(dev, pkt);
723 if (pkt->status == USB_RET_ASYNC) {
724 usb_device_flush_ep_queue(dev, ep);
725 g_free(pkt);
726 return 1;
727 }
728 if (pkt->status == USB_RET_SUCCESS) {
729 ret = pkt->actual_length;
730 } else {
731 ret = pkt->status;
732 }
733 g_free(pkt);
734
735 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr,
736 str, len, ret);
737
738 /* Writeback */
739 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
740 /* IN transfer succeeded */
741 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, ret,
742 DMA_DIRECTION_FROM_DEVICE)) {
743 ohci_die(ohci);
744 return 1;
745 }
746 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
747 OHCI_CC_NOERROR);
748 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
749 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
750 /* OUT transfer succeeded */
751 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
752 OHCI_CC_NOERROR);
753 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
754 } else {
755 if (ret > (ssize_t) len) {
756 trace_usb_ohci_iso_td_data_overrun(ret, len);
757 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
758 OHCI_CC_DATAOVERRUN);
759 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
760 len);
761 } else if (ret >= 0) {
762 trace_usb_ohci_iso_td_data_underrun(ret);
763 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
764 OHCI_CC_DATAUNDERRUN);
765 } else {
766 switch (ret) {
767 case USB_RET_IOERROR:
768 case USB_RET_NODEV:
769 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
770 OHCI_CC_DEVICENOTRESPONDING);
771 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
772 0);
773 break;
774 case USB_RET_NAK:
775 case USB_RET_STALL:
776 trace_usb_ohci_iso_td_nak(ret);
777 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
778 OHCI_CC_STALL);
779 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
780 0);
781 break;
782 default:
783 trace_usb_ohci_iso_td_bad_response(ret);
784 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
785 OHCI_CC_UNDEXPETEDPID);
786 break;
787 }
788 }
789 }
790
791 if (relative_frame_number == frame_count) {
792 /* Last data packet of ISO TD - retire the TD to the Done Queue */
793 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
794 ed->head &= ~OHCI_DPTR_MASK;
795 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
796 iso_td.next = ohci->done;
797 ohci->done = addr;
798 i = OHCI_BM(iso_td.flags, TD_DI);
799 if (i < ohci->done_count)
800 ohci->done_count = i;
801 }
802 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
803 ohci_die(ohci);
804 }
805 return 1;
806 }
807
808 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
809 {
810 bool print16;
811 bool printall;
812 const int width = 16;
813 int i;
814 char tmp[3 * width + 1];
815 char *p = tmp;
816
817 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
818 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL);
819
820 if (!printall && !print16) {
821 return;
822 }
823
824 for (i = 0; ; i++) {
825 if (i && (!(i % width) || (i == len))) {
826 if (!printall) {
827 trace_usb_ohci_td_pkt_short(msg, tmp);
828 break;
829 }
830 trace_usb_ohci_td_pkt_full(msg, tmp);
831 p = tmp;
832 *p = 0;
833 }
834 if (i == len) {
835 break;
836 }
837
838 p += sprintf(p, " %.2x", buf[i]);
839 }
840 }
841
842 /* Service a transport descriptor.
843 Returns nonzero to terminate processing of this endpoint. */
844
845 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
846 {
847 int dir;
848 size_t len = 0, pktlen = 0;
849 const char *str = NULL;
850 int pid;
851 int ret;
852 int i;
853 USBDevice *dev;
854 USBEndpoint *ep;
855 struct ohci_td td;
856 uint32_t addr;
857 int flag_r;
858 int completion;
859
860 addr = ed->head & OHCI_DPTR_MASK;
861 /* See if this TD has already been submitted to the device. */
862 completion = (addr == ohci->async_td);
863 if (completion && !ohci->async_complete) {
864 trace_usb_ohci_td_skip_async();
865 return 1;
866 }
867 if (ohci_read_td(ohci, addr, &td)) {
868 trace_usb_ohci_td_read_error(addr);
869 ohci_die(ohci);
870 return 1;
871 }
872
873 dir = OHCI_BM(ed->flags, ED_D);
874 switch (dir) {
875 case OHCI_TD_DIR_OUT:
876 case OHCI_TD_DIR_IN:
877 /* Same value. */
878 break;
879 default:
880 dir = OHCI_BM(td.flags, TD_DP);
881 break;
882 }
883
884 switch (dir) {
885 case OHCI_TD_DIR_IN:
886 str = "in";
887 pid = USB_TOKEN_IN;
888 break;
889 case OHCI_TD_DIR_OUT:
890 str = "out";
891 pid = USB_TOKEN_OUT;
892 break;
893 case OHCI_TD_DIR_SETUP:
894 str = "setup";
895 pid = USB_TOKEN_SETUP;
896 break;
897 default:
898 trace_usb_ohci_td_bad_direction(dir);
899 return 1;
900 }
901 if (td.cbp && td.be) {
902 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
903 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
904 } else {
905 if (td.cbp > td.be) {
906 trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be);
907 ohci_die(ohci);
908 return 1;
909 }
910 len = (td.be - td.cbp) + 1;
911 }
912 if (len > sizeof(ohci->usb_buf)) {
913 len = sizeof(ohci->usb_buf);
914 }
915
916 pktlen = len;
917 if (len && dir != OHCI_TD_DIR_IN) {
918 /* The endpoint may not allow us to transfer it all now */
919 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
920 if (pktlen > len) {
921 pktlen = len;
922 }
923 if (!completion) {
924 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen,
925 DMA_DIRECTION_TO_DEVICE)) {
926 ohci_die(ohci);
927 }
928 }
929 }
930 }
931
932 flag_r = (td.flags & OHCI_TD_R) != 0;
933 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str,
934 flag_r, td.cbp, td.be);
935 ohci_td_pkt("OUT", ohci->usb_buf, pktlen);
936
937 if (completion) {
938 ohci->async_td = 0;
939 ohci->async_complete = false;
940 } else {
941 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
942 if (dev == NULL) {
943 trace_usb_ohci_td_dev_error();
944 return 1;
945 }
946 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
947 if (ohci->async_td) {
948 /* ??? The hardware should allow one active packet per
949 endpoint. We only allow one active packet per controller.
950 This should be sufficient as long as devices respond in a
951 timely manner.
952 */
953 trace_usb_ohci_td_too_many_pending(ep->nr);
954 return 1;
955 }
956 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r,
957 OHCI_BM(td.flags, TD_DI) == 0);
958 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen);
959 usb_handle_packet(dev, &ohci->usb_packet);
960 trace_usb_ohci_td_packet_status(ohci->usb_packet.status);
961
962 if (ohci->usb_packet.status == USB_RET_ASYNC) {
963 usb_device_flush_ep_queue(dev, ep);
964 ohci->async_td = addr;
965 return 1;
966 }
967 }
968 if (ohci->usb_packet.status == USB_RET_SUCCESS) {
969 ret = ohci->usb_packet.actual_length;
970 } else {
971 ret = ohci->usb_packet.status;
972 }
973
974 if (ret >= 0) {
975 if (dir == OHCI_TD_DIR_IN) {
976 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret,
977 DMA_DIRECTION_FROM_DEVICE)) {
978 ohci_die(ohci);
979 }
980 ohci_td_pkt("IN", ohci->usb_buf, pktlen);
981 } else {
982 ret = pktlen;
983 }
984 }
985
986 /* Writeback */
987 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
988 /* Transmission succeeded. */
989 if (ret == len) {
990 td.cbp = 0;
991 } else {
992 if ((td.cbp & 0xfff) + ret > 0xfff) {
993 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff);
994 } else {
995 td.cbp += ret;
996 }
997 }
998 td.flags |= OHCI_TD_T1;
999 td.flags ^= OHCI_TD_T0;
1000 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1001 OHCI_SET_BM(td.flags, TD_EC, 0);
1002
1003 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
1004 /* Partial packet transfer: TD not ready to retire yet */
1005 goto exit_no_retire;
1006 }
1007
1008 /* Setting ED_C is part of the TD retirement process */
1009 ed->head &= ~OHCI_ED_C;
1010 if (td.flags & OHCI_TD_T0)
1011 ed->head |= OHCI_ED_C;
1012 } else {
1013 if (ret >= 0) {
1014 trace_usb_ohci_td_underrun();
1015 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1016 } else {
1017 switch (ret) {
1018 case USB_RET_IOERROR:
1019 case USB_RET_NODEV:
1020 trace_usb_ohci_td_dev_error();
1021 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1022 break;
1023 case USB_RET_NAK:
1024 trace_usb_ohci_td_nak();
1025 return 1;
1026 case USB_RET_STALL:
1027 trace_usb_ohci_td_stall();
1028 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1029 break;
1030 case USB_RET_BABBLE:
1031 trace_usb_ohci_td_babble();
1032 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1033 break;
1034 default:
1035 trace_usb_ohci_td_bad_device_response(ret);
1036 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1037 OHCI_SET_BM(td.flags, TD_EC, 3);
1038 break;
1039 }
1040 /* An error occurred so we have to clear the interrupt counter. See
1041 * spec at 6.4.4 on page 104 */
1042 ohci->done_count = 0;
1043 }
1044 ed->head |= OHCI_ED_H;
1045 }
1046
1047 /* Retire this TD */
1048 ed->head &= ~OHCI_DPTR_MASK;
1049 ed->head |= td.next & OHCI_DPTR_MASK;
1050 td.next = ohci->done;
1051 ohci->done = addr;
1052 i = OHCI_BM(td.flags, TD_DI);
1053 if (i < ohci->done_count)
1054 ohci->done_count = i;
1055 exit_no_retire:
1056 if (ohci_put_td(ohci, addr, &td)) {
1057 ohci_die(ohci);
1058 return 1;
1059 }
1060 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1061 }
1062
1063 /* Service an endpoint list. Returns nonzero if active TD were found. */
1064 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
1065 {
1066 struct ohci_ed ed;
1067 uint32_t next_ed;
1068 uint32_t cur;
1069 int active;
1070 uint32_t link_cnt = 0;
1071 active = 0;
1072
1073 if (head == 0)
1074 return 0;
1075
1076 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) {
1077 if (ohci_read_ed(ohci, cur, &ed)) {
1078 trace_usb_ohci_ed_read_error(cur);
1079 ohci_die(ohci);
1080 return 0;
1081 }
1082
1083 next_ed = ed.next & OHCI_DPTR_MASK;
1084
1085 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1086 uint32_t addr;
1087 /* Cancel pending packets for ED that have been paused. */
1088 addr = ed.head & OHCI_DPTR_MASK;
1089 if (ohci->async_td && addr == ohci->async_td) {
1090 usb_cancel_packet(&ohci->usb_packet);
1091 ohci->async_td = 0;
1092 usb_device_ep_stopped(ohci->usb_packet.ep->dev,
1093 ohci->usb_packet.ep);
1094 }
1095 continue;
1096 }
1097
1098 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1099 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0,
1100 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1101 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1102 trace_usb_ohci_ed_pkt_flags(
1103 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1104 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1105 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1106 OHCI_BM(ed.flags, ED_MPS));
1107
1108 active = 1;
1109
1110 if ((ed.flags & OHCI_ED_F) == 0) {
1111 if (ohci_service_td(ohci, &ed))
1112 break;
1113 } else {
1114 /* Handle isochronous endpoints */
1115 if (ohci_service_iso_td(ohci, &ed)) {
1116 break;
1117 }
1118 }
1119 }
1120
1121 if (ohci_put_ed(ohci, cur, &ed)) {
1122 ohci_die(ohci);
1123 return 0;
1124 }
1125 }
1126
1127 return active;
1128 }
1129
1130 /* set a timer for EOF */
1131 static void ohci_eof_timer(OHCIState *ohci)
1132 {
1133 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1134 }
1135 /* Set a timer for EOF and generate a SOF event */
1136 static void ohci_sof(OHCIState *ohci)
1137 {
1138 ohci->sof_time += usb_frame_time;
1139 ohci_eof_timer(ohci);
1140 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1141 }
1142
1143 /* Process Control and Bulk lists. */
1144 static void ohci_process_lists(OHCIState *ohci)
1145 {
1146 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1147 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1148 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur);
1149 }
1150 if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
1151 ohci->ctrl_cur = 0;
1152 ohci->status &= ~OHCI_STATUS_CLF;
1153 }
1154 }
1155
1156 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1157 if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
1158 ohci->bulk_cur = 0;
1159 ohci->status &= ~OHCI_STATUS_BLF;
1160 }
1161 }
1162 }
1163
1164 /* Do frame processing on frame boundary */
1165 static void ohci_frame_boundary(void *opaque)
1166 {
1167 OHCIState *ohci = opaque;
1168 struct ohci_hcca hcca;
1169
1170 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) {
1171 trace_usb_ohci_hcca_read_error(ohci->hcca);
1172 ohci_die(ohci);
1173 return;
1174 }
1175
1176 /* Process all the lists at the end of the frame */
1177 if (ohci->ctl & OHCI_CTL_PLE) {
1178 int n;
1179
1180 n = ohci->frame_number & 0x1f;
1181 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
1182 }
1183
1184 /* Cancel all pending packets if either of the lists has been disabled. */
1185 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1186 ohci_stop_endpoints(ohci);
1187 }
1188 ohci->old_ctl = ohci->ctl;
1189 ohci_process_lists(ohci);
1190
1191 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1192 if (ohci->intr_status & OHCI_INTR_UE) {
1193 return;
1194 }
1195
1196 /* Frame boundary, so do EOF stuf here */
1197 ohci->frt = ohci->fit;
1198
1199 /* Increment frame number and take care of endianness. */
1200 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1201 hcca.frame = cpu_to_le16(ohci->frame_number);
1202
1203 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1204 if (!ohci->done)
1205 abort();
1206 if (ohci->intr & ohci->intr_status)
1207 ohci->done |= 1;
1208 hcca.done = cpu_to_le32(ohci->done);
1209 ohci->done = 0;
1210 ohci->done_count = 7;
1211 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1212 }
1213
1214 if (ohci->done_count != 7 && ohci->done_count != 0)
1215 ohci->done_count--;
1216
1217 /* Do SOF stuff here */
1218 ohci_sof(ohci);
1219
1220 /* Writeback HCCA */
1221 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) {
1222 ohci_die(ohci);
1223 }
1224 }
1225
1226 /* Start sending SOF tokens across the USB bus, lists are processed in
1227 * next frame
1228 */
1229 static int ohci_bus_start(OHCIState *ohci)
1230 {
1231 trace_usb_ohci_start(ohci->name);
1232
1233 /* Delay the first SOF event by one frame time as
1234 * linux driver is not ready to receive it and
1235 * can meet some race conditions
1236 */
1237
1238 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1239 ohci_eof_timer(ohci);
1240
1241 return 1;
1242 }
1243
1244 /* Stop sending SOF tokens on the bus */
1245 void ohci_bus_stop(OHCIState *ohci)
1246 {
1247 trace_usb_ohci_stop(ohci->name);
1248 timer_del(ohci->eof_timer);
1249 }
1250
1251 /* Sets a flag in a port status register but only set it if the port is
1252 * connected, if not set ConnectStatusChange flag. If flag is enabled
1253 * return 1.
1254 */
1255 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1256 {
1257 int ret = 1;
1258
1259 /* writing a 0 has no effect */
1260 if (val == 0)
1261 return 0;
1262
1263 /* If CurrentConnectStatus is cleared we set
1264 * ConnectStatusChange
1265 */
1266 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1267 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1268 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1269 /* TODO: CSC is a wakeup event */
1270 }
1271 return 0;
1272 }
1273
1274 if (ohci->rhport[i].ctrl & val)
1275 ret = 0;
1276
1277 /* set the bit */
1278 ohci->rhport[i].ctrl |= val;
1279
1280 return ret;
1281 }
1282
1283 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1284 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1285 {
1286 val &= OHCI_FMI_FI;
1287
1288 if (val != ohci->fi) {
1289 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi);
1290 }
1291
1292 ohci->fi = val;
1293 }
1294
1295 static void ohci_port_power(OHCIState *ohci, int i, int p)
1296 {
1297 if (p) {
1298 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1299 } else {
1300 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1301 OHCI_PORT_CCS|
1302 OHCI_PORT_PSS|
1303 OHCI_PORT_PRS);
1304 }
1305 }
1306
1307 /* Set HcControlRegister */
1308 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1309 {
1310 uint32_t old_state;
1311 uint32_t new_state;
1312
1313 old_state = ohci->ctl & OHCI_CTL_HCFS;
1314 ohci->ctl = val;
1315 new_state = ohci->ctl & OHCI_CTL_HCFS;
1316
1317 /* no state change */
1318 if (old_state == new_state)
1319 return;
1320
1321 trace_usb_ohci_set_ctl(ohci->name, new_state);
1322 switch (new_state) {
1323 case OHCI_USB_OPERATIONAL:
1324 ohci_bus_start(ohci);
1325 break;
1326 case OHCI_USB_SUSPEND:
1327 ohci_bus_stop(ohci);
1328 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1329 ohci->intr_status &= ~OHCI_INTR_SF;
1330 ohci_intr_update(ohci);
1331 break;
1332 case OHCI_USB_RESUME:
1333 trace_usb_ohci_resume(ohci->name);
1334 break;
1335 case OHCI_USB_RESET:
1336 ohci_roothub_reset(ohci);
1337 break;
1338 }
1339 }
1340
1341 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1342 {
1343 uint16_t fr;
1344 int64_t tks;
1345
1346 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1347 return (ohci->frt << 31);
1348
1349 /* Being in USB operational state guarnatees sof_time was
1350 * set already.
1351 */
1352 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time;
1353 if (tks < 0) {
1354 tks = 0;
1355 }
1356
1357 /* avoid muldiv if possible */
1358 if (tks >= usb_frame_time)
1359 return (ohci->frt << 31);
1360
1361 tks = tks / usb_bit_time;
1362 fr = (uint16_t)(ohci->fi - tks);
1363
1364 return (ohci->frt << 31) | fr;
1365 }
1366
1367
1368 /* Set root hub status */
1369 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1370 {
1371 uint32_t old_state;
1372
1373 old_state = ohci->rhstatus;
1374
1375 /* write 1 to clear OCIC */
1376 if (val & OHCI_RHS_OCIC)
1377 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1378
1379 if (val & OHCI_RHS_LPS) {
1380 int i;
1381
1382 for (i = 0; i < ohci->num_ports; i++)
1383 ohci_port_power(ohci, i, 0);
1384 trace_usb_ohci_hub_power_down();
1385 }
1386
1387 if (val & OHCI_RHS_LPSC) {
1388 int i;
1389
1390 for (i = 0; i < ohci->num_ports; i++)
1391 ohci_port_power(ohci, i, 1);
1392 trace_usb_ohci_hub_power_up();
1393 }
1394
1395 if (val & OHCI_RHS_DRWE)
1396 ohci->rhstatus |= OHCI_RHS_DRWE;
1397
1398 if (val & OHCI_RHS_CRWE)
1399 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1400
1401 if (old_state != ohci->rhstatus)
1402 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1403 }
1404
1405 /* Set root hub port status */
1406 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1407 {
1408 uint32_t old_state;
1409 OHCIPort *port;
1410
1411 port = &ohci->rhport[portnum];
1412 old_state = port->ctrl;
1413
1414 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1415 if (val & OHCI_PORT_WTC)
1416 port->ctrl &= ~(val & OHCI_PORT_WTC);
1417
1418 if (val & OHCI_PORT_CCS)
1419 port->ctrl &= ~OHCI_PORT_PES;
1420
1421 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1422
1423 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1424 trace_usb_ohci_port_suspend(portnum);
1425 }
1426
1427 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1428 trace_usb_ohci_port_reset(portnum);
1429 usb_device_reset(port->port.dev);
1430 port->ctrl &= ~OHCI_PORT_PRS;
1431 /* ??? Should this also set OHCI_PORT_PESC. */
1432 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1433 }
1434
1435 /* Invert order here to ensure in ambiguous case, device is
1436 * powered up...
1437 */
1438 if (val & OHCI_PORT_LSDA)
1439 ohci_port_power(ohci, portnum, 0);
1440 if (val & OHCI_PORT_PPS)
1441 ohci_port_power(ohci, portnum, 1);
1442
1443 if (old_state != port->ctrl)
1444 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1445 }
1446
1447 static uint64_t ohci_mem_read(void *opaque,
1448 hwaddr addr,
1449 unsigned size)
1450 {
1451 OHCIState *ohci = opaque;
1452 uint32_t retval;
1453
1454 /* Only aligned reads are allowed on OHCI */
1455 if (addr & 3) {
1456 trace_usb_ohci_mem_read_unaligned(addr);
1457 return 0xffffffff;
1458 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1459 /* HcRhPortStatus */
1460 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1461 } else {
1462 switch (addr >> 2) {
1463 case 0: /* HcRevision */
1464 retval = 0x10;
1465 break;
1466
1467 case 1: /* HcControl */
1468 retval = ohci->ctl;
1469 break;
1470
1471 case 2: /* HcCommandStatus */
1472 retval = ohci->status;
1473 break;
1474
1475 case 3: /* HcInterruptStatus */
1476 retval = ohci->intr_status;
1477 break;
1478
1479 case 4: /* HcInterruptEnable */
1480 case 5: /* HcInterruptDisable */
1481 retval = ohci->intr;
1482 break;
1483
1484 case 6: /* HcHCCA */
1485 retval = ohci->hcca;
1486 break;
1487
1488 case 7: /* HcPeriodCurrentED */
1489 retval = ohci->per_cur;
1490 break;
1491
1492 case 8: /* HcControlHeadED */
1493 retval = ohci->ctrl_head;
1494 break;
1495
1496 case 9: /* HcControlCurrentED */
1497 retval = ohci->ctrl_cur;
1498 break;
1499
1500 case 10: /* HcBulkHeadED */
1501 retval = ohci->bulk_head;
1502 break;
1503
1504 case 11: /* HcBulkCurrentED */
1505 retval = ohci->bulk_cur;
1506 break;
1507
1508 case 12: /* HcDoneHead */
1509 retval = ohci->done;
1510 break;
1511
1512 case 13: /* HcFmInterretval */
1513 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1514 break;
1515
1516 case 14: /* HcFmRemaining */
1517 retval = ohci_get_frame_remaining(ohci);
1518 break;
1519
1520 case 15: /* HcFmNumber */
1521 retval = ohci->frame_number;
1522 break;
1523
1524 case 16: /* HcPeriodicStart */
1525 retval = ohci->pstart;
1526 break;
1527
1528 case 17: /* HcLSThreshold */
1529 retval = ohci->lst;
1530 break;
1531
1532 case 18: /* HcRhDescriptorA */
1533 retval = ohci->rhdesc_a;
1534 break;
1535
1536 case 19: /* HcRhDescriptorB */
1537 retval = ohci->rhdesc_b;
1538 break;
1539
1540 case 20: /* HcRhStatus */
1541 retval = ohci->rhstatus;
1542 break;
1543
1544 /* PXA27x specific registers */
1545 case 24: /* HcStatus */
1546 retval = ohci->hstatus & ohci->hmask;
1547 break;
1548
1549 case 25: /* HcHReset */
1550 retval = ohci->hreset;
1551 break;
1552
1553 case 26: /* HcHInterruptEnable */
1554 retval = ohci->hmask;
1555 break;
1556
1557 case 27: /* HcHInterruptTest */
1558 retval = ohci->htest;
1559 break;
1560
1561 default:
1562 trace_usb_ohci_mem_read_bad_offset(addr);
1563 retval = 0xffffffff;
1564 }
1565 }
1566
1567 return retval;
1568 }
1569
1570 static void ohci_mem_write(void *opaque,
1571 hwaddr addr,
1572 uint64_t val,
1573 unsigned size)
1574 {
1575 OHCIState *ohci = opaque;
1576
1577 /* Only aligned reads are allowed on OHCI */
1578 if (addr & 3) {
1579 trace_usb_ohci_mem_write_unaligned(addr);
1580 return;
1581 }
1582
1583 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1584 /* HcRhPortStatus */
1585 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1586 return;
1587 }
1588
1589 switch (addr >> 2) {
1590 case 1: /* HcControl */
1591 ohci_set_ctl(ohci, val);
1592 break;
1593
1594 case 2: /* HcCommandStatus */
1595 /* SOC is read-only */
1596 val = (val & ~OHCI_STATUS_SOC);
1597
1598 /* Bits written as '0' remain unchanged in the register */
1599 ohci->status |= val;
1600
1601 if (ohci->status & OHCI_STATUS_HCR)
1602 ohci_soft_reset(ohci);
1603 break;
1604
1605 case 3: /* HcInterruptStatus */
1606 ohci->intr_status &= ~val;
1607 ohci_intr_update(ohci);
1608 break;
1609
1610 case 4: /* HcInterruptEnable */
1611 ohci->intr |= val;
1612 ohci_intr_update(ohci);
1613 break;
1614
1615 case 5: /* HcInterruptDisable */
1616 ohci->intr &= ~val;
1617 ohci_intr_update(ohci);
1618 break;
1619
1620 case 6: /* HcHCCA */
1621 ohci->hcca = val & OHCI_HCCA_MASK;
1622 break;
1623
1624 case 7: /* HcPeriodCurrentED */
1625 /* Ignore writes to this read-only register, Linux does them */
1626 break;
1627
1628 case 8: /* HcControlHeadED */
1629 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1630 break;
1631
1632 case 9: /* HcControlCurrentED */
1633 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1634 break;
1635
1636 case 10: /* HcBulkHeadED */
1637 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1638 break;
1639
1640 case 11: /* HcBulkCurrentED */
1641 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1642 break;
1643
1644 case 13: /* HcFmInterval */
1645 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1646 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1647 ohci_set_frame_interval(ohci, val);
1648 break;
1649
1650 case 15: /* HcFmNumber */
1651 break;
1652
1653 case 16: /* HcPeriodicStart */
1654 ohci->pstart = val & 0xffff;
1655 break;
1656
1657 case 17: /* HcLSThreshold */
1658 ohci->lst = val & 0xffff;
1659 break;
1660
1661 case 18: /* HcRhDescriptorA */
1662 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1663 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1664 break;
1665
1666 case 19: /* HcRhDescriptorB */
1667 break;
1668
1669 case 20: /* HcRhStatus */
1670 ohci_set_hub_status(ohci, val);
1671 break;
1672
1673 /* PXA27x specific registers */
1674 case 24: /* HcStatus */
1675 ohci->hstatus &= ~(val & ohci->hmask);
1676 break;
1677
1678 case 25: /* HcHReset */
1679 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1680 if (val & OHCI_HRESET_FSBIR)
1681 ohci_hard_reset(ohci);
1682 break;
1683
1684 case 26: /* HcHInterruptEnable */
1685 ohci->hmask = val;
1686 break;
1687
1688 case 27: /* HcHInterruptTest */
1689 ohci->htest = val;
1690 break;
1691
1692 default:
1693 trace_usb_ohci_mem_write_bad_offset(addr);
1694 break;
1695 }
1696 }
1697
1698 static const MemoryRegionOps ohci_mem_ops = {
1699 .read = ohci_mem_read,
1700 .write = ohci_mem_write,
1701 .endianness = DEVICE_LITTLE_ENDIAN,
1702 };
1703
1704 /* USBPortOps */
1705 static void ohci_attach(USBPort *port1)
1706 {
1707 OHCIState *s = port1->opaque;
1708 OHCIPort *port = &s->rhport[port1->index];
1709 uint32_t old_state = port->ctrl;
1710
1711 /* set connect status */
1712 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
1713
1714 /* update speed */
1715 if (port->port.dev->speed == USB_SPEED_LOW) {
1716 port->ctrl |= OHCI_PORT_LSDA;
1717 } else {
1718 port->ctrl &= ~OHCI_PORT_LSDA;
1719 }
1720
1721 /* notify of remote-wakeup */
1722 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
1723 ohci_set_interrupt(s, OHCI_INTR_RD);
1724 }
1725
1726 trace_usb_ohci_port_attach(port1->index);
1727
1728 if (old_state != port->ctrl) {
1729 ohci_set_interrupt(s, OHCI_INTR_RHSC);
1730 }
1731 }
1732
1733 static void ohci_child_detach(USBPort *port1, USBDevice *dev)
1734 {
1735 OHCIState *ohci = port1->opaque;
1736
1737 if (ohci->async_td &&
1738 usb_packet_is_inflight(&ohci->usb_packet) &&
1739 ohci->usb_packet.ep->dev == dev) {
1740 usb_cancel_packet(&ohci->usb_packet);
1741 ohci->async_td = 0;
1742 }
1743 }
1744
1745 static void ohci_detach(USBPort *port1)
1746 {
1747 OHCIState *s = port1->opaque;
1748 OHCIPort *port = &s->rhport[port1->index];
1749 uint32_t old_state = port->ctrl;
1750
1751 ohci_child_detach(port1, port1->dev);
1752
1753 /* set connect status */
1754 if (port->ctrl & OHCI_PORT_CCS) {
1755 port->ctrl &= ~OHCI_PORT_CCS;
1756 port->ctrl |= OHCI_PORT_CSC;
1757 }
1758 /* disable port */
1759 if (port->ctrl & OHCI_PORT_PES) {
1760 port->ctrl &= ~OHCI_PORT_PES;
1761 port->ctrl |= OHCI_PORT_PESC;
1762 }
1763 trace_usb_ohci_port_detach(port1->index);
1764
1765 if (old_state != port->ctrl) {
1766 ohci_set_interrupt(s, OHCI_INTR_RHSC);
1767 }
1768 }
1769
1770 static void ohci_wakeup(USBPort *port1)
1771 {
1772 OHCIState *s = port1->opaque;
1773 OHCIPort *port = &s->rhport[port1->index];
1774 uint32_t intr = 0;
1775 if (port->ctrl & OHCI_PORT_PSS) {
1776 trace_usb_ohci_port_wakeup(port1->index);
1777 port->ctrl |= OHCI_PORT_PSSC;
1778 port->ctrl &= ~OHCI_PORT_PSS;
1779 intr = OHCI_INTR_RHSC;
1780 }
1781 /* Note that the controller can be suspended even if this port is not */
1782 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
1783 trace_usb_ohci_remote_wakeup(s->name);
1784 /* This is the one state transition the controller can do by itself */
1785 s->ctl &= ~OHCI_CTL_HCFS;
1786 s->ctl |= OHCI_USB_RESUME;
1787 /*
1788 * In suspend mode only ResumeDetected is possible, not RHSC:
1789 * see the OHCI spec 5.1.2.3.
1790 */
1791 intr = OHCI_INTR_RD;
1792 }
1793 ohci_set_interrupt(s, intr);
1794 }
1795
1796 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
1797 {
1798 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
1799
1800 trace_usb_ohci_async_complete();
1801 ohci->async_complete = true;
1802 ohci_process_lists(ohci);
1803 }
1804
1805 static USBPortOps ohci_port_ops = {
1806 .attach = ohci_attach,
1807 .detach = ohci_detach,
1808 .child_detach = ohci_child_detach,
1809 .wakeup = ohci_wakeup,
1810 .complete = ohci_async_complete_packet,
1811 };
1812
1813 static USBBusOps ohci_bus_ops = {
1814 };
1815
1816 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
1817 dma_addr_t localmem_base, char *masterbus,
1818 uint32_t firstport, AddressSpace *as,
1819 void (*ohci_die_fn)(struct OHCIState *), Error **errp)
1820 {
1821 Error *err = NULL;
1822 int i;
1823
1824 ohci->as = as;
1825 ohci->ohci_die = ohci_die_fn;
1826
1827 if (num_ports > OHCI_MAX_PORTS) {
1828 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)",
1829 num_ports, OHCI_MAX_PORTS);
1830 return;
1831 }
1832
1833 if (usb_frame_time == 0) {
1834 #ifdef OHCI_TIME_WARP
1835 usb_frame_time = NANOSECONDS_PER_SECOND;
1836 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000);
1837 #else
1838 usb_frame_time = NANOSECONDS_PER_SECOND / 1000;
1839 if (NANOSECONDS_PER_SECOND >= USB_HZ) {
1840 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ;
1841 } else {
1842 usb_bit_time = 1;
1843 }
1844 #endif
1845 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time);
1846 }
1847
1848 ohci->num_ports = num_ports;
1849 if (masterbus) {
1850 USBPort *ports[OHCI_MAX_PORTS];
1851 for(i = 0; i < num_ports; i++) {
1852 ports[i] = &ohci->rhport[i].port;
1853 }
1854 usb_register_companion(masterbus, ports, num_ports,
1855 firstport, ohci, &ohci_port_ops,
1856 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1857 &err);
1858 if (err) {
1859 error_propagate(errp, err);
1860 return;
1861 }
1862 } else {
1863 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev);
1864 for (i = 0; i < num_ports; i++) {
1865 usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1866 ohci, i, &ohci_port_ops,
1867 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1868 }
1869 }
1870
1871 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops,
1872 ohci, "ohci", 256);
1873 ohci->localmem_base = localmem_base;
1874
1875 ohci->name = object_get_typename(OBJECT(dev));
1876 usb_packet_init(&ohci->usb_packet);
1877
1878 ohci->async_td = 0;
1879
1880 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1881 ohci_frame_boundary, ohci);
1882 }
1883
1884 /**
1885 * A typical OHCI will stop operating and set itself into error state
1886 * (which can be queried by MMIO) to signal that it got an error.
1887 */
1888 void ohci_sysbus_die(struct OHCIState *ohci)
1889 {
1890 trace_usb_ohci_die();
1891
1892 ohci_set_interrupt(ohci, OHCI_INTR_UE);
1893 ohci_bus_stop(ohci);
1894 }
1895
1896 static void ohci_realize_pxa(DeviceState *dev, Error **errp)
1897 {
1898 OHCISysBusState *s = SYSBUS_OHCI(dev);
1899 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1900 Error *err = NULL;
1901
1902 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
1903 s->masterbus, s->firstport,
1904 &address_space_memory, ohci_sysbus_die, &err);
1905 if (err) {
1906 error_propagate(errp, err);
1907 return;
1908 }
1909 sysbus_init_irq(sbd, &s->ohci.irq);
1910 sysbus_init_mmio(sbd, &s->ohci.mem);
1911 }
1912
1913 static void usb_ohci_reset_sysbus(DeviceState *dev)
1914 {
1915 OHCISysBusState *s = SYSBUS_OHCI(dev);
1916 OHCIState *ohci = &s->ohci;
1917
1918 ohci_hard_reset(ohci);
1919 }
1920
1921 static const VMStateDescription vmstate_ohci_state_port = {
1922 .name = "ohci-core/port",
1923 .version_id = 1,
1924 .minimum_version_id = 1,
1925 .fields = (VMStateField[]) {
1926 VMSTATE_UINT32(ctrl, OHCIPort),
1927 VMSTATE_END_OF_LIST()
1928 },
1929 };
1930
1931 static bool ohci_eof_timer_needed(void *opaque)
1932 {
1933 OHCIState *ohci = opaque;
1934
1935 return timer_pending(ohci->eof_timer);
1936 }
1937
1938 static const VMStateDescription vmstate_ohci_eof_timer = {
1939 .name = "ohci-core/eof-timer",
1940 .version_id = 1,
1941 .minimum_version_id = 1,
1942 .needed = ohci_eof_timer_needed,
1943 .fields = (VMStateField[]) {
1944 VMSTATE_TIMER_PTR(eof_timer, OHCIState),
1945 VMSTATE_END_OF_LIST()
1946 },
1947 };
1948
1949 const VMStateDescription vmstate_ohci_state = {
1950 .name = "ohci-core",
1951 .version_id = 1,
1952 .minimum_version_id = 1,
1953 .fields = (VMStateField[]) {
1954 VMSTATE_INT64(sof_time, OHCIState),
1955 VMSTATE_UINT32(ctl, OHCIState),
1956 VMSTATE_UINT32(status, OHCIState),
1957 VMSTATE_UINT32(intr_status, OHCIState),
1958 VMSTATE_UINT32(intr, OHCIState),
1959 VMSTATE_UINT32(hcca, OHCIState),
1960 VMSTATE_UINT32(ctrl_head, OHCIState),
1961 VMSTATE_UINT32(ctrl_cur, OHCIState),
1962 VMSTATE_UINT32(bulk_head, OHCIState),
1963 VMSTATE_UINT32(bulk_cur, OHCIState),
1964 VMSTATE_UINT32(per_cur, OHCIState),
1965 VMSTATE_UINT32(done, OHCIState),
1966 VMSTATE_INT32(done_count, OHCIState),
1967 VMSTATE_UINT16(fsmps, OHCIState),
1968 VMSTATE_UINT8(fit, OHCIState),
1969 VMSTATE_UINT16(fi, OHCIState),
1970 VMSTATE_UINT8(frt, OHCIState),
1971 VMSTATE_UINT16(frame_number, OHCIState),
1972 VMSTATE_UINT16(padding, OHCIState),
1973 VMSTATE_UINT32(pstart, OHCIState),
1974 VMSTATE_UINT32(lst, OHCIState),
1975 VMSTATE_UINT32(rhdesc_a, OHCIState),
1976 VMSTATE_UINT32(rhdesc_b, OHCIState),
1977 VMSTATE_UINT32(rhstatus, OHCIState),
1978 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0,
1979 vmstate_ohci_state_port, OHCIPort),
1980 VMSTATE_UINT32(hstatus, OHCIState),
1981 VMSTATE_UINT32(hmask, OHCIState),
1982 VMSTATE_UINT32(hreset, OHCIState),
1983 VMSTATE_UINT32(htest, OHCIState),
1984 VMSTATE_UINT32(old_ctl, OHCIState),
1985 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192),
1986 VMSTATE_UINT32(async_td, OHCIState),
1987 VMSTATE_BOOL(async_complete, OHCIState),
1988 VMSTATE_END_OF_LIST()
1989 },
1990 .subsections = (const VMStateDescription*[]) {
1991 &vmstate_ohci_eof_timer,
1992 NULL
1993 }
1994 };
1995
1996 static Property ohci_sysbus_properties[] = {
1997 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
1998 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1999 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
2000 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
2001 DEFINE_PROP_END_OF_LIST(),
2002 };
2003
2004 static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
2005 {
2006 DeviceClass *dc = DEVICE_CLASS(klass);
2007
2008 dc->realize = ohci_realize_pxa;
2009 set_bit(DEVICE_CATEGORY_USB, dc->categories);
2010 dc->desc = "OHCI USB Controller";
2011 device_class_set_props(dc, ohci_sysbus_properties);
2012 dc->reset = usb_ohci_reset_sysbus;
2013 }
2014
2015 static const TypeInfo ohci_sysbus_info = {
2016 .name = TYPE_SYSBUS_OHCI,
2017 .parent = TYPE_SYS_BUS_DEVICE,
2018 .instance_size = sizeof(OHCISysBusState),
2019 .class_init = ohci_sysbus_class_init,
2020 };
2021
2022 static void ohci_register_types(void)
2023 {
2024 type_register_static(&ohci_sysbus_info);
2025 }
2026
2027 type_init(ohci_register_types)
AR7 emulation for QEMU