2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
15 * This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU Lesser General Public
17 * License as published by the Free Software Foundation; either
18 * version 2.1 of the License, or (at your option) any later version.
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * Lesser General Public License for more details.
25 * You should have received a copy of the GNU Lesser General Public License
26 * along with this program; if not, see <http://www.gnu.org/licenses/>.
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
32 #include "hw/usb/ehci-regs.h"
33 #include "hw/usb/hcd-ehci.h"
34 #include "migration/vmstate.h"
36 #include "qemu/error-report.h"
37 #include "qemu/main-loop.h"
38 #include "sysemu/runstate.h"
40 #define FRAME_TIMER_FREQ 1000
41 #define FRAME_TIMER_NS (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ)
42 #define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8)
44 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
45 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
46 #define MAX_QH 100 // Max allowable queue heads in a chain
47 #define MIN_UFR_PER_TICK 24 /* Min frames to process when catching up */
48 #define PERIODIC_ACTIVE 512 /* Micro-frames */
50 /* Internal periodic / asynchronous schedule state machine states
57 /* The following states are internal to the state machine function
71 /* macros for accessing fields within next link pointer entry */
72 #define NLPTR_GET(x) ((x) & 0xffffffe0)
73 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
74 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
76 /* link pointer types */
77 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
78 #define NLPTR_TYPE_QH 1 // queue head
79 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
80 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
82 #define SET_LAST_RUN_CLOCK(s) \
83 (s)->last_run_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
85 /* nifty macros from Arnon's EHCI version */
86 #define get_field(data, field) \
87 (((data) & field##_MASK) >> field##_SH)
89 #define set_field(data, newval, field) do { \
90 uint32_t val = *data; \
91 val &= ~ field##_MASK; \
92 val |= ((newval) << field##_SH) & field##_MASK; \
96 static const char *ehci_state_names
[] = {
97 [EST_INACTIVE
] = "INACTIVE",
98 [EST_ACTIVE
] = "ACTIVE",
99 [EST_EXECUTING
] = "EXECUTING",
100 [EST_SLEEPING
] = "SLEEPING",
101 [EST_WAITLISTHEAD
] = "WAITLISTHEAD",
102 [EST_FETCHENTRY
] = "FETCH ENTRY",
103 [EST_FETCHQH
] = "FETCH QH",
104 [EST_FETCHITD
] = "FETCH ITD",
105 [EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
106 [EST_FETCHQTD
] = "FETCH QTD",
107 [EST_EXECUTE
] = "EXECUTE",
108 [EST_WRITEBACK
] = "WRITEBACK",
109 [EST_HORIZONTALQH
] = "HORIZONTALQH",
112 static const char *ehci_mmio_names
[] = {
115 [USBINTR
] = "USBINTR",
116 [FRINDEX
] = "FRINDEX",
117 [PERIODICLISTBASE
] = "P-LIST BASE",
118 [ASYNCLISTADDR
] = "A-LIST ADDR",
119 [CONFIGFLAG
] = "CONFIGFLAG",
122 static int ehci_state_executing(EHCIQueue
*q
);
123 static int ehci_state_writeback(EHCIQueue
*q
);
124 static int ehci_state_advqueue(EHCIQueue
*q
);
125 static int ehci_fill_queue(EHCIPacket
*p
);
126 static void ehci_free_packet(EHCIPacket
*p
);
128 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
130 if (nr
< len
&& n
[nr
] != NULL
) {
137 static const char *state2str(uint32_t state
)
139 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
142 static const char *addr2str(hwaddr addr
)
144 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
), addr
);
147 static void ehci_trace_usbsts(uint32_t mask
, int state
)
150 if (mask
& USBSTS_INT
) {
151 trace_usb_ehci_usbsts("INT", state
);
153 if (mask
& USBSTS_ERRINT
) {
154 trace_usb_ehci_usbsts("ERRINT", state
);
156 if (mask
& USBSTS_PCD
) {
157 trace_usb_ehci_usbsts("PCD", state
);
159 if (mask
& USBSTS_FLR
) {
160 trace_usb_ehci_usbsts("FLR", state
);
162 if (mask
& USBSTS_HSE
) {
163 trace_usb_ehci_usbsts("HSE", state
);
165 if (mask
& USBSTS_IAA
) {
166 trace_usb_ehci_usbsts("IAA", state
);
170 if (mask
& USBSTS_HALT
) {
171 trace_usb_ehci_usbsts("HALT", state
);
173 if (mask
& USBSTS_REC
) {
174 trace_usb_ehci_usbsts("REC", state
);
176 if (mask
& USBSTS_PSS
) {
177 trace_usb_ehci_usbsts("PSS", state
);
179 if (mask
& USBSTS_ASS
) {
180 trace_usb_ehci_usbsts("ASS", state
);
184 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
186 if ((s
->usbsts
& mask
) == mask
) {
189 ehci_trace_usbsts(mask
, 1);
193 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
195 if ((s
->usbsts
& mask
) == 0) {
198 ehci_trace_usbsts(mask
, 0);
202 /* update irq line */
203 static inline void ehci_update_irq(EHCIState
*s
)
207 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
211 trace_usb_ehci_irq(level
, s
->frindex
, s
->usbsts
, s
->usbintr
);
212 qemu_set_irq(s
->irq
, level
);
215 /* flag interrupt condition */
216 static inline void ehci_raise_irq(EHCIState
*s
, int intr
)
218 if (intr
& (USBSTS_PCD
| USBSTS_FLR
| USBSTS_HSE
)) {
222 s
->usbsts_pending
|= intr
;
227 * Commit pending interrupts (added via ehci_raise_irq),
228 * at the rate allowed by "Interrupt Threshold Control".
230 static inline void ehci_commit_irq(EHCIState
*s
)
234 if (!s
->usbsts_pending
) {
237 if (s
->usbsts_frindex
> s
->frindex
) {
241 itc
= (s
->usbcmd
>> 16) & 0xff;
242 s
->usbsts
|= s
->usbsts_pending
;
243 s
->usbsts_pending
= 0;
244 s
->usbsts_frindex
= s
->frindex
+ itc
;
248 static void ehci_update_halt(EHCIState
*s
)
250 if (s
->usbcmd
& USBCMD_RUNSTOP
) {
251 ehci_clear_usbsts(s
, USBSTS_HALT
);
253 if (s
->astate
== EST_INACTIVE
&& s
->pstate
== EST_INACTIVE
) {
254 ehci_set_usbsts(s
, USBSTS_HALT
);
259 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
262 trace_usb_ehci_state("async", state2str(state
));
264 if (s
->astate
== EST_INACTIVE
) {
265 ehci_clear_usbsts(s
, USBSTS_ASS
);
268 ehci_set_usbsts(s
, USBSTS_ASS
);
271 trace_usb_ehci_state("periodic", state2str(state
));
273 if (s
->pstate
== EST_INACTIVE
) {
274 ehci_clear_usbsts(s
, USBSTS_PSS
);
277 ehci_set_usbsts(s
, USBSTS_PSS
);
282 static int ehci_get_state(EHCIState
*s
, int async
)
284 return async
? s
->astate
: s
->pstate
;
287 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
290 s
->a_fetch_addr
= addr
;
292 s
->p_fetch_addr
= addr
;
296 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
298 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
301 static void ehci_trace_qh(EHCIQueue
*q
, hwaddr addr
, EHCIqh
*qh
)
303 /* need three here due to argument count limits */
304 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
305 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
306 trace_usb_ehci_qh_fields(addr
,
307 get_field(qh
->epchar
, QH_EPCHAR_RL
),
308 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
309 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
310 get_field(qh
->epchar
, QH_EPCHAR_EP
),
311 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
312 trace_usb_ehci_qh_bits(addr
,
313 (bool)(qh
->epchar
& QH_EPCHAR_C
),
314 (bool)(qh
->epchar
& QH_EPCHAR_H
),
315 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
316 (bool)(qh
->epchar
& QH_EPCHAR_I
));
319 static void ehci_trace_qtd(EHCIQueue
*q
, hwaddr addr
, EHCIqtd
*qtd
)
321 /* need three here due to argument count limits */
322 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
323 trace_usb_ehci_qtd_fields(addr
,
324 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
325 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
326 get_field(qtd
->token
, QTD_TOKEN_CERR
),
327 get_field(qtd
->token
, QTD_TOKEN_PID
));
328 trace_usb_ehci_qtd_bits(addr
,
329 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
330 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
331 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
332 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
333 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
336 static void ehci_trace_itd(EHCIState
*s
, hwaddr addr
, EHCIitd
*itd
)
338 trace_usb_ehci_itd(addr
, itd
->next
,
339 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
340 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
341 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
342 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
345 static void ehci_trace_sitd(EHCIState
*s
, hwaddr addr
,
348 trace_usb_ehci_sitd(addr
, sitd
->next
,
349 (bool)(sitd
->results
& SITD_RESULTS_ACTIVE
));
352 static void ehci_trace_guest_bug(EHCIState
*s
, const char *message
)
354 trace_usb_ehci_guest_bug(message
);
357 static inline bool ehci_enabled(EHCIState
*s
)
359 return s
->usbcmd
& USBCMD_RUNSTOP
;
362 static inline bool ehci_async_enabled(EHCIState
*s
)
364 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_ASE
);
367 static inline bool ehci_periodic_enabled(EHCIState
*s
)
369 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_PSE
);
372 /* Get an array of dwords from main memory */
373 static inline int get_dwords(EHCIState
*ehci
, uint32_t addr
,
374 uint32_t *buf
, int num
)
379 ehci_raise_irq(ehci
, USBSTS_HSE
);
380 ehci
->usbcmd
&= ~USBCMD_RUNSTOP
;
381 trace_usb_ehci_dma_error();
385 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
386 dma_memory_read(ehci
->as
, addr
, buf
, sizeof(*buf
),
387 MEMTXATTRS_UNSPECIFIED
);
388 *buf
= le32_to_cpu(*buf
);
394 /* Put an array of dwords in to main memory */
395 static inline int put_dwords(EHCIState
*ehci
, uint32_t addr
,
396 uint32_t *buf
, int num
)
401 ehci_raise_irq(ehci
, USBSTS_HSE
);
402 ehci
->usbcmd
&= ~USBCMD_RUNSTOP
;
403 trace_usb_ehci_dma_error();
407 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
408 uint32_t tmp
= cpu_to_le32(*buf
);
409 dma_memory_write(ehci
->as
, addr
, &tmp
, sizeof(tmp
),
410 MEMTXATTRS_UNSPECIFIED
);
416 static int ehci_get_pid(EHCIqtd
*qtd
)
418 switch (get_field(qtd
->token
, QTD_TOKEN_PID
)) {
420 return USB_TOKEN_OUT
;
424 return USB_TOKEN_SETUP
;
426 fprintf(stderr
, "bad token\n");
431 static bool ehci_verify_qh(EHCIQueue
*q
, EHCIqh
*qh
)
433 uint32_t devaddr
= get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
);
434 uint32_t endp
= get_field(qh
->epchar
, QH_EPCHAR_EP
);
435 if ((devaddr
!= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
)) ||
436 (endp
!= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
)) ||
437 (qh
->current_qtd
!= q
->qh
.current_qtd
) ||
438 (q
->async
&& qh
->next_qtd
!= q
->qh
.next_qtd
) ||
439 (memcmp(&qh
->altnext_qtd
, &q
->qh
.altnext_qtd
,
440 7 * sizeof(uint32_t)) != 0) ||
441 (q
->dev
!= NULL
&& q
->dev
->addr
!= devaddr
)) {
448 static bool ehci_verify_qtd(EHCIPacket
*p
, EHCIqtd
*qtd
)
450 if (p
->qtdaddr
!= p
->queue
->qtdaddr
||
451 (p
->queue
->async
&& !NLPTR_TBIT(p
->qtd
.next
) &&
452 (p
->qtd
.next
!= qtd
->next
)) ||
453 (!NLPTR_TBIT(p
->qtd
.altnext
) && (p
->qtd
.altnext
!= qtd
->altnext
)) ||
454 p
->qtd
.token
!= qtd
->token
||
455 p
->qtd
.bufptr
[0] != qtd
->bufptr
[0]) {
462 static bool ehci_verify_pid(EHCIQueue
*q
, EHCIqtd
*qtd
)
464 int ep
= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
);
465 int pid
= ehci_get_pid(qtd
);
467 /* Note the pid changing is normal for ep 0 (the control ep) */
468 if (q
->last_pid
&& ep
!= 0 && pid
!= q
->last_pid
) {
475 /* Finish executing and writeback a packet outside of the regular
476 fetchqh -> fetchqtd -> execute -> writeback cycle */
477 static void ehci_writeback_async_complete_packet(EHCIPacket
*p
)
479 EHCIQueue
*q
= p
->queue
;
484 /* Verify the qh + qtd, like we do when going through fetchqh & fetchqtd */
485 get_dwords(q
->ehci
, NLPTR_GET(q
->qhaddr
),
486 (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2);
487 get_dwords(q
->ehci
, NLPTR_GET(q
->qtdaddr
),
488 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2);
489 if (!ehci_verify_qh(q
, &qh
) || !ehci_verify_qtd(p
, &qtd
)) {
490 p
->async
= EHCI_ASYNC_INITIALIZED
;
495 state
= ehci_get_state(q
->ehci
, q
->async
);
496 ehci_state_executing(q
);
497 ehci_state_writeback(q
); /* Frees the packet! */
498 if (!(q
->qh
.token
& QTD_TOKEN_HALT
)) {
499 ehci_state_advqueue(q
);
501 ehci_set_state(q
->ehci
, q
->async
, state
);
504 /* packet management */
506 static EHCIPacket
*ehci_alloc_packet(EHCIQueue
*q
)
510 p
= g_new0(EHCIPacket
, 1);
512 usb_packet_init(&p
->packet
);
513 QTAILQ_INSERT_TAIL(&q
->packets
, p
, next
);
514 trace_usb_ehci_packet_action(p
->queue
, p
, "alloc");
518 static void ehci_free_packet(EHCIPacket
*p
)
520 if (p
->async
== EHCI_ASYNC_FINISHED
&&
521 !(p
->queue
->qh
.token
& QTD_TOKEN_HALT
)) {
522 ehci_writeback_async_complete_packet(p
);
525 trace_usb_ehci_packet_action(p
->queue
, p
, "free");
526 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
527 usb_cancel_packet(&p
->packet
);
529 if (p
->async
== EHCI_ASYNC_FINISHED
&&
530 p
->packet
.status
== USB_RET_SUCCESS
) {
532 "EHCI: Dropping completed packet from halted %s ep %02X\n",
533 (p
->pid
== USB_TOKEN_IN
) ? "in" : "out",
534 get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
));
536 if (p
->async
!= EHCI_ASYNC_NONE
) {
537 usb_packet_unmap(&p
->packet
, &p
->sgl
);
538 qemu_sglist_destroy(&p
->sgl
);
540 QTAILQ_REMOVE(&p
->queue
->packets
, p
, next
);
541 usb_packet_cleanup(&p
->packet
);
545 /* queue management */
547 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, uint32_t addr
, int async
)
549 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
552 q
= g_malloc0(sizeof(*q
));
556 QTAILQ_INIT(&q
->packets
);
557 QTAILQ_INSERT_HEAD(head
, q
, next
);
558 trace_usb_ehci_queue_action(q
, "alloc");
562 static void ehci_queue_stopped(EHCIQueue
*q
)
564 int endp
= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
);
566 if (!q
->last_pid
|| !q
->dev
) {
570 usb_device_ep_stopped(q
->dev
, usb_ep_get(q
->dev
, q
->last_pid
, endp
));
573 static int ehci_cancel_queue(EHCIQueue
*q
)
578 p
= QTAILQ_FIRST(&q
->packets
);
583 trace_usb_ehci_queue_action(q
, "cancel");
587 } while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
);
590 ehci_queue_stopped(q
);
594 static int ehci_reset_queue(EHCIQueue
*q
)
598 trace_usb_ehci_queue_action(q
, "reset");
599 packets
= ehci_cancel_queue(q
);
606 static void ehci_free_queue(EHCIQueue
*q
, const char *warn
)
608 EHCIQueueHead
*head
= q
->async
? &q
->ehci
->aqueues
: &q
->ehci
->pqueues
;
611 trace_usb_ehci_queue_action(q
, "free");
612 cancelled
= ehci_cancel_queue(q
);
613 if (warn
&& cancelled
> 0) {
614 ehci_trace_guest_bug(q
->ehci
, warn
);
616 QTAILQ_REMOVE(head
, q
, next
);
620 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
,
623 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
626 QTAILQ_FOREACH(q
, head
, next
) {
627 if (addr
== q
->qhaddr
) {
634 static void ehci_queues_rip_unused(EHCIState
*ehci
, int async
)
636 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
637 const char *warn
= async
? "guest unlinked busy QH" : NULL
;
638 uint64_t maxage
= FRAME_TIMER_NS
* ehci
->maxframes
* 4;
641 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
644 q
->ts
= ehci
->last_run_ns
;
647 if (ehci
->last_run_ns
< q
->ts
+ maxage
) {
650 ehci_free_queue(q
, warn
);
654 static void ehci_queues_rip_unseen(EHCIState
*ehci
, int async
)
656 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
659 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
661 ehci_free_queue(q
, NULL
);
666 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
, int async
)
668 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
671 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
675 ehci_free_queue(q
, NULL
);
679 static void ehci_queues_rip_all(EHCIState
*ehci
, int async
)
681 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
682 const char *warn
= async
? "guest stopped busy async schedule" : NULL
;
685 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
686 ehci_free_queue(q
, warn
);
690 /* Attach or detach a device on root hub */
692 static void ehci_attach(USBPort
*port
)
694 EHCIState
*s
= port
->opaque
;
695 uint32_t *portsc
= &s
->portsc
[port
->index
];
696 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
698 trace_usb_ehci_port_attach(port
->index
, owner
, port
->dev
->product_desc
);
700 if (*portsc
& PORTSC_POWNER
) {
701 USBPort
*companion
= s
->companion_ports
[port
->index
];
702 companion
->dev
= port
->dev
;
703 companion
->ops
->attach(companion
);
707 *portsc
|= PORTSC_CONNECT
;
708 *portsc
|= PORTSC_CSC
;
710 ehci_raise_irq(s
, USBSTS_PCD
);
713 static void ehci_detach(USBPort
*port
)
715 EHCIState
*s
= port
->opaque
;
716 uint32_t *portsc
= &s
->portsc
[port
->index
];
717 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
719 trace_usb_ehci_port_detach(port
->index
, owner
);
721 if (*portsc
& PORTSC_POWNER
) {
722 USBPort
*companion
= s
->companion_ports
[port
->index
];
723 companion
->ops
->detach(companion
);
724 companion
->dev
= NULL
;
726 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
727 * the port ownership is returned immediately to the EHCI controller."
729 *portsc
&= ~PORTSC_POWNER
;
733 ehci_queues_rip_device(s
, port
->dev
, 0);
734 ehci_queues_rip_device(s
, port
->dev
, 1);
736 *portsc
&= ~(PORTSC_CONNECT
|PORTSC_PED
|PORTSC_SUSPEND
);
737 *portsc
|= PORTSC_CSC
;
739 ehci_raise_irq(s
, USBSTS_PCD
);
742 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
744 EHCIState
*s
= port
->opaque
;
745 uint32_t portsc
= s
->portsc
[port
->index
];
747 if (portsc
& PORTSC_POWNER
) {
748 USBPort
*companion
= s
->companion_ports
[port
->index
];
749 companion
->ops
->child_detach(companion
, child
);
753 ehci_queues_rip_device(s
, child
, 0);
754 ehci_queues_rip_device(s
, child
, 1);
757 static void ehci_wakeup(USBPort
*port
)
759 EHCIState
*s
= port
->opaque
;
760 uint32_t *portsc
= &s
->portsc
[port
->index
];
762 if (*portsc
& PORTSC_POWNER
) {
763 USBPort
*companion
= s
->companion_ports
[port
->index
];
764 if (companion
->ops
->wakeup
) {
765 companion
->ops
->wakeup(companion
);
770 if (*portsc
& PORTSC_SUSPEND
) {
771 trace_usb_ehci_port_wakeup(port
->index
);
772 *portsc
|= PORTSC_FPRES
;
773 ehci_raise_irq(s
, USBSTS_PCD
);
776 qemu_bh_schedule(s
->async_bh
);
779 static void ehci_register_companion(USBBus
*bus
, USBPort
*ports
[],
780 uint32_t portcount
, uint32_t firstport
,
783 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
786 if (firstport
+ portcount
> NB_PORTS
) {
787 error_setg(errp
, "firstport must be between 0 and %u",
788 NB_PORTS
- portcount
);
792 for (i
= 0; i
< portcount
; i
++) {
793 if (s
->companion_ports
[firstport
+ i
]) {
794 error_setg(errp
, "firstport %u asks for ports %u-%u,"
795 " but port %u has a companion assigned already",
796 firstport
, firstport
, firstport
+ portcount
- 1,
802 for (i
= 0; i
< portcount
; i
++) {
803 s
->companion_ports
[firstport
+ i
] = ports
[i
];
804 s
->ports
[firstport
+ i
].speedmask
|=
805 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
;
806 /* Ensure devs attached before the initial reset go to the companion */
807 s
->portsc
[firstport
+ i
] = PORTSC_POWNER
;
810 s
->companion_count
++;
811 s
->caps
[0x05] = (s
->companion_count
<< 4) | portcount
;
814 static void ehci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
817 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
818 uint32_t portsc
= s
->portsc
[ep
->dev
->port
->index
];
820 if (portsc
& PORTSC_POWNER
) {
824 s
->periodic_sched_active
= PERIODIC_ACTIVE
;
825 qemu_bh_schedule(s
->async_bh
);
828 static USBDevice
*ehci_find_device(EHCIState
*ehci
, uint8_t addr
)
834 for (i
= 0; i
< NB_PORTS
; i
++) {
835 port
= &ehci
->ports
[i
];
836 if (!(ehci
->portsc
[i
] & PORTSC_PED
)) {
837 DPRINTF("Port %d not enabled\n", i
);
840 dev
= usb_find_device(port
, addr
);
848 /* 4.1 host controller initialization */
849 void ehci_reset(void *opaque
)
851 EHCIState
*s
= opaque
;
853 USBDevice
*devs
[NB_PORTS
];
855 trace_usb_ehci_reset();
858 * Do the detach before touching portsc, so that it correctly gets send to
859 * us or to our companion based on PORTSC_POWNER before the reset.
861 for(i
= 0; i
< NB_PORTS
; i
++) {
862 devs
[i
] = s
->ports
[i
].dev
;
863 if (devs
[i
] && devs
[i
]->attached
) {
864 usb_detach(&s
->ports
[i
]);
868 memset(&s
->opreg
, 0x00, sizeof(s
->opreg
));
869 memset(&s
->portsc
, 0x00, sizeof(s
->portsc
));
871 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
872 s
->usbsts
= USBSTS_HALT
;
873 s
->usbsts_pending
= 0;
874 s
->usbsts_frindex
= 0;
877 s
->astate
= EST_INACTIVE
;
878 s
->pstate
= EST_INACTIVE
;
880 for(i
= 0; i
< NB_PORTS
; i
++) {
881 if (s
->companion_ports
[i
]) {
882 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
884 s
->portsc
[i
] = PORTSC_PPOWER
;
886 if (devs
[i
] && devs
[i
]->attached
) {
887 usb_attach(&s
->ports
[i
]);
888 usb_device_reset(devs
[i
]);
891 ehci_queues_rip_all(s
, 0);
892 ehci_queues_rip_all(s
, 1);
893 timer_del(s
->frame_timer
);
894 qemu_bh_cancel(s
->async_bh
);
897 static uint64_t ehci_caps_read(void *ptr
, hwaddr addr
,
901 return s
->caps
[addr
];
904 static void ehci_caps_write(void *ptr
, hwaddr addr
,
905 uint64_t val
, unsigned size
)
909 static uint64_t ehci_opreg_read(void *ptr
, hwaddr addr
,
917 /* Round down to mult of 8, else it can go backwards on migration */
918 val
= s
->frindex
& ~7;
921 val
= s
->opreg
[addr
>> 2];
924 trace_usb_ehci_opreg_read(addr
+ s
->opregbase
, addr2str(addr
), val
);
928 static uint64_t ehci_port_read(void *ptr
, hwaddr addr
,
934 val
= s
->portsc
[addr
>> 2];
935 trace_usb_ehci_portsc_read(addr
+ s
->portscbase
, addr
>> 2, val
);
939 static void handle_port_owner_write(EHCIState
*s
, int port
, uint32_t owner
)
941 USBDevice
*dev
= s
->ports
[port
].dev
;
942 uint32_t *portsc
= &s
->portsc
[port
];
945 if (s
->companion_ports
[port
] == NULL
)
948 owner
= owner
& PORTSC_POWNER
;
949 orig
= *portsc
& PORTSC_POWNER
;
951 if (!(owner
^ orig
)) {
955 if (dev
&& dev
->attached
) {
956 usb_detach(&s
->ports
[port
]);
959 *portsc
&= ~PORTSC_POWNER
;
962 if (dev
&& dev
->attached
) {
963 usb_attach(&s
->ports
[port
]);
967 static void ehci_port_write(void *ptr
, hwaddr addr
,
968 uint64_t val
, unsigned size
)
971 int port
= addr
>> 2;
972 uint32_t *portsc
= &s
->portsc
[port
];
973 uint32_t old
= *portsc
;
974 USBDevice
*dev
= s
->ports
[port
].dev
;
976 trace_usb_ehci_portsc_write(addr
+ s
->portscbase
, addr
>> 2, val
);
979 *portsc
&= ~(val
& PORTSC_RWC_MASK
);
980 /* The guest may clear, but not set the PED bit */
981 *portsc
&= val
| ~PORTSC_PED
;
982 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
983 handle_port_owner_write(s
, port
, val
);
984 /* And finally apply RO_MASK */
985 val
&= PORTSC_RO_MASK
;
987 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
988 trace_usb_ehci_port_reset(port
, 1);
991 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
992 trace_usb_ehci_port_reset(port
, 0);
993 if (dev
&& dev
->attached
) {
994 usb_port_reset(&s
->ports
[port
]);
995 *portsc
&= ~PORTSC_CSC
;
999 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1000 * to SW that this port has a high speed device attached
1002 if (dev
&& dev
->attached
&& (dev
->speedmask
& USB_SPEED_MASK_HIGH
)) {
1007 if ((val
& PORTSC_SUSPEND
) && !(*portsc
& PORTSC_SUSPEND
)) {
1008 trace_usb_ehci_port_suspend(port
);
1010 if (!(val
& PORTSC_FPRES
) && (*portsc
& PORTSC_FPRES
)) {
1011 trace_usb_ehci_port_resume(port
);
1012 val
&= ~PORTSC_SUSPEND
;
1015 *portsc
&= ~PORTSC_RO_MASK
;
1017 trace_usb_ehci_portsc_change(addr
+ s
->portscbase
, addr
>> 2, *portsc
, old
);
1020 static void ehci_opreg_write(void *ptr
, hwaddr addr
,
1021 uint64_t val
, unsigned size
)
1024 uint32_t *mmio
= s
->opreg
+ (addr
>> 2);
1025 uint32_t old
= *mmio
;
1028 trace_usb_ehci_opreg_write(addr
+ s
->opregbase
, addr2str(addr
), val
);
1032 if (val
& USBCMD_HCRESET
) {
1038 /* not supporting dynamic frame list size at the moment */
1039 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
1040 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
1041 (int)val
& USBCMD_FLS
);
1045 if (val
& USBCMD_IAAD
) {
1047 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1048 * trigger and re-use a qh without us seeing the unlink.
1050 s
->async_stepdown
= 0;
1051 qemu_bh_schedule(s
->async_bh
);
1052 trace_usb_ehci_doorbell_ring();
1055 if (((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & val
) !=
1056 ((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & s
->usbcmd
)) {
1057 if (s
->pstate
== EST_INACTIVE
) {
1058 SET_LAST_RUN_CLOCK(s
);
1060 s
->usbcmd
= val
; /* Set usbcmd for ehci_update_halt() */
1061 ehci_update_halt(s
);
1062 s
->async_stepdown
= 0;
1063 qemu_bh_schedule(s
->async_bh
);
1068 val
&= USBSTS_RO_MASK
; // bits 6 through 31 are RO
1069 ehci_clear_usbsts(s
, val
); // bits 0 through 5 are R/WC
1075 val
&= USBINTR_MASK
;
1076 if (ehci_enabled(s
) && (USBSTS_FLR
& val
)) {
1077 qemu_bh_schedule(s
->async_bh
);
1082 val
&= 0x00003fff; /* frindex is 14bits */
1083 s
->usbsts_frindex
= val
;
1089 for(i
= 0; i
< NB_PORTS
; i
++)
1090 handle_port_owner_write(s
, i
, 0);
1094 case PERIODICLISTBASE
:
1095 if (ehci_periodic_enabled(s
)) {
1097 "ehci: PERIODIC list base register set while periodic schedule\n"
1098 " is enabled and HC is enabled\n");
1103 if (ehci_async_enabled(s
)) {
1105 "ehci: ASYNC list address register set while async schedule\n"
1106 " is enabled and HC is enabled\n");
1112 trace_usb_ehci_opreg_change(addr
+ s
->opregbase
, addr2str(addr
),
1117 * Write the qh back to guest physical memory. This step isn't
1118 * in the EHCI spec but we need to do it since we don't share
1119 * physical memory with our guest VM.
1121 * The first three dwords are read-only for the EHCI, so skip them
1122 * when writing back the qh.
1124 static void ehci_flush_qh(EHCIQueue
*q
)
1126 uint32_t *qh
= (uint32_t *) &q
->qh
;
1127 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1128 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1130 put_dwords(q
->ehci
, addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1135 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1137 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1145 assert(p
->qtdaddr
== q
->qtdaddr
);
1147 // remember values in fields to preserve in qh after overlay
1149 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1150 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1152 q
->qh
.current_qtd
= p
->qtdaddr
;
1153 q
->qh
.next_qtd
= p
->qtd
.next
;
1154 q
->qh
.altnext_qtd
= p
->qtd
.altnext
;
1155 q
->qh
.token
= p
->qtd
.token
;
1158 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1159 if (eps
== EHCI_QH_EPS_HIGH
) {
1160 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1161 q
->qh
.token
|= ping
;
1164 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1165 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1167 for (i
= 0; i
< 5; i
++) {
1168 q
->qh
.bufptr
[i
] = p
->qtd
.bufptr
[i
];
1171 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1172 // preserve QH DT bit
1173 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1174 q
->qh
.token
|= dtoggle
;
1177 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1178 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1185 static int ehci_init_transfer(EHCIPacket
*p
)
1187 uint32_t cpage
, offset
, bytes
, plen
;
1190 cpage
= get_field(p
->qtd
.token
, QTD_TOKEN_CPAGE
);
1191 bytes
= get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
);
1192 offset
= p
->qtd
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1193 qemu_sglist_init(&p
->sgl
, p
->queue
->ehci
->device
, 5, p
->queue
->ehci
->as
);
1197 fprintf(stderr
, "cpage out of range (%u)\n", cpage
);
1198 qemu_sglist_destroy(&p
->sgl
);
1202 page
= p
->qtd
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1205 if (plen
> 4096 - offset
) {
1206 plen
= 4096 - offset
;
1211 qemu_sglist_add(&p
->sgl
, page
, plen
);
1217 static void ehci_finish_transfer(EHCIQueue
*q
, int len
)
1219 uint32_t cpage
, offset
;
1222 /* update cpage & offset */
1223 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1224 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1227 cpage
+= offset
>> QTD_BUFPTR_SH
;
1228 offset
&= ~QTD_BUFPTR_MASK
;
1230 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1231 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1232 q
->qh
.bufptr
[0] |= offset
;
1236 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1239 EHCIState
*s
= port
->opaque
;
1240 uint32_t portsc
= s
->portsc
[port
->index
];
1242 if (portsc
& PORTSC_POWNER
) {
1243 USBPort
*companion
= s
->companion_ports
[port
->index
];
1244 companion
->ops
->complete(companion
, packet
);
1248 p
= container_of(packet
, EHCIPacket
, packet
);
1249 assert(p
->async
== EHCI_ASYNC_INFLIGHT
);
1251 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
1252 trace_usb_ehci_packet_action(p
->queue
, p
, "remove");
1253 ehci_free_packet(p
);
1257 trace_usb_ehci_packet_action(p
->queue
, p
, "wakeup");
1258 p
->async
= EHCI_ASYNC_FINISHED
;
1260 if (!p
->queue
->async
) {
1261 s
->periodic_sched_active
= PERIODIC_ACTIVE
;
1263 qemu_bh_schedule(s
->async_bh
);
1266 static void ehci_execute_complete(EHCIQueue
*q
)
1268 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1272 assert(p
->qtdaddr
== q
->qtdaddr
);
1273 assert(p
->async
== EHCI_ASYNC_INITIALIZED
||
1274 p
->async
== EHCI_ASYNC_FINISHED
);
1276 DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, "
1277 "status %d, actual_length %d\n",
1278 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
,
1279 p
->packet
.status
, p
->packet
.actual_length
);
1281 switch (p
->packet
.status
) {
1282 case USB_RET_SUCCESS
:
1284 case USB_RET_IOERROR
:
1286 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1287 set_field(&q
->qh
.token
, 0, QTD_TOKEN_CERR
);
1288 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1291 q
->qh
.token
|= QTD_TOKEN_HALT
;
1292 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1295 set_field(&q
->qh
.altnext_qtd
, 0, QH_ALTNEXT_NAKCNT
);
1296 return; /* We're not done yet with this transaction */
1297 case USB_RET_BABBLE
:
1298 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1299 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1302 /* should not be triggerable */
1303 fprintf(stderr
, "USB invalid response %d\n", p
->packet
.status
);
1304 g_assert_not_reached();
1307 /* TODO check 4.12 for splits */
1308 tbytes
= get_field(q
->qh
.token
, QTD_TOKEN_TBYTES
);
1309 if (tbytes
&& p
->pid
== USB_TOKEN_IN
) {
1310 tbytes
-= p
->packet
.actual_length
;
1312 /* 4.15.1.2 must raise int on a short input packet */
1313 ehci_raise_irq(q
->ehci
, USBSTS_INT
);
1315 q
->ehci
->int_req_by_async
= true;
1321 DPRINTF("updating tbytes to %d\n", tbytes
);
1322 set_field(&q
->qh
.token
, tbytes
, QTD_TOKEN_TBYTES
);
1324 ehci_finish_transfer(q
, p
->packet
.actual_length
);
1325 usb_packet_unmap(&p
->packet
, &p
->sgl
);
1326 qemu_sglist_destroy(&p
->sgl
);
1327 p
->async
= EHCI_ASYNC_NONE
;
1329 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1330 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1332 if (q
->qh
.token
& QTD_TOKEN_IOC
) {
1333 ehci_raise_irq(q
->ehci
, USBSTS_INT
);
1335 q
->ehci
->int_req_by_async
= true;
1340 /* 4.10.3 returns "again" */
1341 static int ehci_execute(EHCIPacket
*p
, const char *action
)
1347 assert(p
->async
== EHCI_ASYNC_NONE
||
1348 p
->async
== EHCI_ASYNC_INITIALIZED
);
1350 if (!(p
->qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1351 fprintf(stderr
, "Attempting to execute inactive qtd\n");
1355 if (get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
) > BUFF_SIZE
) {
1356 ehci_trace_guest_bug(p
->queue
->ehci
,
1357 "guest requested more bytes than allowed");
1361 if (!ehci_verify_pid(p
->queue
, &p
->qtd
)) {
1362 ehci_queue_stopped(p
->queue
); /* Mark the ep in the prev dir stopped */
1364 p
->pid
= ehci_get_pid(&p
->qtd
);
1365 p
->queue
->last_pid
= p
->pid
;
1366 endp
= get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
);
1367 ep
= usb_ep_get(p
->queue
->dev
, p
->pid
, endp
);
1369 if (p
->async
== EHCI_ASYNC_NONE
) {
1370 if (ehci_init_transfer(p
) != 0) {
1374 spd
= (p
->pid
== USB_TOKEN_IN
&& NLPTR_TBIT(p
->qtd
.altnext
) == 0);
1375 usb_packet_setup(&p
->packet
, p
->pid
, ep
, 0, p
->qtdaddr
, spd
,
1376 (p
->qtd
.token
& QTD_TOKEN_IOC
) != 0);
1377 if (usb_packet_map(&p
->packet
, &p
->sgl
)) {
1378 qemu_sglist_destroy(&p
->sgl
);
1381 p
->async
= EHCI_ASYNC_INITIALIZED
;
1384 trace_usb_ehci_packet_action(p
->queue
, p
, action
);
1385 usb_handle_packet(p
->queue
->dev
, &p
->packet
);
1386 DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
1387 "status %d actual_length %d\n", p
->queue
->qhaddr
, p
->qtd
.next
,
1388 p
->qtdaddr
, p
->pid
, p
->packet
.iov
.size
, endp
, p
->packet
.status
,
1389 p
->packet
.actual_length
);
1391 if (p
->packet
.actual_length
> BUFF_SIZE
) {
1392 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1402 static int ehci_process_itd(EHCIState
*ehci
,
1408 uint32_t i
, len
, pid
, dir
, devaddr
, endp
;
1409 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1411 ehci
->periodic_sched_active
= PERIODIC_ACTIVE
;
1413 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1414 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1415 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1416 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1417 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1419 for(i
= 0; i
< 8; i
++) {
1420 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1421 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1422 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1423 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1425 if (len
> max
* mult
) {
1428 if (len
> BUFF_SIZE
|| pg
> 6) {
1432 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1433 qemu_sglist_init(&ehci
->isgl
, ehci
->device
, 2, ehci
->as
);
1434 if (off
+ len
> 4096) {
1435 /* transfer crosses page border */
1437 qemu_sglist_destroy(&ehci
->isgl
);
1438 return -1; /* avoid page pg + 1 */
1440 ptr2
= (itd
->bufptr
[pg
+ 1] & ITD_BUFPTR_MASK
);
1441 uint32_t len2
= off
+ len
- 4096;
1442 uint32_t len1
= len
- len2
;
1443 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len1
);
1444 qemu_sglist_add(&ehci
->isgl
, ptr2
, len2
);
1446 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len
);
1449 dev
= ehci_find_device(ehci
, devaddr
);
1451 ehci_trace_guest_bug(ehci
, "no device found");
1452 ehci
->ipacket
.status
= USB_RET_NODEV
;
1453 ehci
->ipacket
.actual_length
= 0;
1455 pid
= dir
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1456 ep
= usb_ep_get(dev
, pid
, endp
);
1457 if (ep
&& ep
->type
== USB_ENDPOINT_XFER_ISOC
) {
1458 usb_packet_setup(&ehci
->ipacket
, pid
, ep
, 0, addr
, false,
1459 (itd
->transact
[i
] & ITD_XACT_IOC
) != 0);
1460 if (usb_packet_map(&ehci
->ipacket
, &ehci
->isgl
)) {
1461 qemu_sglist_destroy(&ehci
->isgl
);
1464 usb_handle_packet(dev
, &ehci
->ipacket
);
1465 usb_packet_unmap(&ehci
->ipacket
, &ehci
->isgl
);
1467 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1468 ehci
->ipacket
.status
= USB_RET_NAK
;
1469 ehci
->ipacket
.actual_length
= 0;
1472 qemu_sglist_destroy(&ehci
->isgl
);
1474 switch (ehci
->ipacket
.status
) {
1475 case USB_RET_SUCCESS
:
1478 fprintf(stderr
, "Unexpected iso usb result: %d\n",
1479 ehci
->ipacket
.status
);
1481 case USB_RET_IOERROR
:
1483 /* 3.3.2: XACTERR is only allowed on IN transactions */
1485 itd
->transact
[i
] |= ITD_XACT_XACTERR
;
1486 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1489 case USB_RET_BABBLE
:
1490 itd
->transact
[i
] |= ITD_XACT_BABBLE
;
1491 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1494 /* no data for us, so do a zero-length transfer */
1495 ehci
->ipacket
.actual_length
= 0;
1499 set_field(&itd
->transact
[i
], len
- ehci
->ipacket
.actual_length
,
1500 ITD_XACT_LENGTH
); /* OUT */
1502 set_field(&itd
->transact
[i
], ehci
->ipacket
.actual_length
,
1503 ITD_XACT_LENGTH
); /* IN */
1505 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1506 ehci_raise_irq(ehci
, USBSTS_INT
);
1508 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1515 /* This state is the entry point for asynchronous schedule
1516 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1518 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1523 uint32_t entry
= ehci
->asynclistaddr
;
1525 /* set reclamation flag at start event (4.8.6) */
1527 ehci_set_usbsts(ehci
, USBSTS_REC
);
1530 ehci_queues_rip_unused(ehci
, async
);
1532 /* Find the head of the list (4.9.1.1) */
1533 for(i
= 0; i
< MAX_QH
; i
++) {
1534 if (get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &qh
,
1535 sizeof(EHCIqh
) >> 2) < 0) {
1538 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1540 if (qh
.epchar
& QH_EPCHAR_H
) {
1542 entry
|= (NLPTR_TYPE_QH
<< 1);
1545 ehci_set_fetch_addr(ehci
, async
, entry
);
1546 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1552 if (entry
== ehci
->asynclistaddr
) {
1557 /* no head found for list. */
1559 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1566 /* This state is the entry point for periodic schedule processing as
1567 * well as being a continuation state for async processing.
1569 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1572 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1574 if (NLPTR_TBIT(entry
)) {
1575 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1579 /* section 4.8, only QH in async schedule */
1580 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1581 fprintf(stderr
, "non queue head request in async schedule\n");
1585 switch (NLPTR_TYPE_GET(entry
)) {
1587 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1591 case NLPTR_TYPE_ITD
:
1592 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1596 case NLPTR_TYPE_STITD
:
1597 ehci_set_state(ehci
, async
, EST_FETCHSITD
);
1602 /* TODO: handle FSTN type */
1603 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %u "
1604 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1612 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1618 entry
= ehci_get_fetch_addr(ehci
, async
);
1619 q
= ehci_find_queue_by_qh(ehci
, entry
, async
);
1621 q
= ehci_alloc_queue(ehci
, entry
, async
);
1626 /* we are going in circles -- stop processing */
1627 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1632 if (get_dwords(ehci
, NLPTR_GET(q
->qhaddr
),
1633 (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2) < 0) {
1637 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &qh
);
1640 * The overlay area of the qh should never be changed by the guest,
1641 * except when idle, in which case the reset is a nop.
1643 if (!ehci_verify_qh(q
, &qh
)) {
1644 if (ehci_reset_queue(q
) > 0) {
1645 ehci_trace_guest_bug(ehci
, "guest updated active QH");
1650 q
->transact_ctr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
1651 if (q
->transact_ctr
== 0) { /* Guest bug in some versions of windows */
1652 q
->transact_ctr
= 4;
1655 if (q
->dev
== NULL
) {
1656 q
->dev
= ehci_find_device(q
->ehci
,
1657 get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
));
1660 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1662 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1663 if (ehci
->usbsts
& USBSTS_REC
) {
1664 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1666 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1667 " - done processing\n", q
->qhaddr
);
1668 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1675 if (q
->qhaddr
!= q
->qh
.next
) {
1676 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1678 q
->qh
.epchar
& QH_EPCHAR_H
,
1679 q
->qh
.token
& QTD_TOKEN_HALT
,
1680 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1685 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1686 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1688 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) &&
1689 (NLPTR_TBIT(q
->qh
.current_qtd
) == 0) &&
1690 (q
->qh
.current_qtd
!= 0)) {
1691 q
->qtdaddr
= q
->qh
.current_qtd
;
1692 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1695 /* EHCI spec version 1.0 Section 4.10.2 */
1696 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1703 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1709 entry
= ehci_get_fetch_addr(ehci
, async
);
1711 if (get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1712 sizeof(EHCIitd
) >> 2) < 0) {
1715 ehci_trace_itd(ehci
, entry
, &itd
);
1717 if (ehci_process_itd(ehci
, &itd
, entry
) != 0) {
1721 put_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1722 sizeof(EHCIitd
) >> 2);
1723 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1724 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1729 static int ehci_state_fetchsitd(EHCIState
*ehci
, int async
)
1735 entry
= ehci_get_fetch_addr(ehci
, async
);
1737 if (get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *)&sitd
,
1738 sizeof(EHCIsitd
) >> 2) < 0) {
1741 ehci_trace_sitd(ehci
, entry
, &sitd
);
1743 if (!(sitd
.results
& SITD_RESULTS_ACTIVE
)) {
1744 /* siTD is not active, nothing to do */;
1746 /* TODO: split transfers are not implemented */
1747 warn_report("Skipping active siTD");
1750 ehci_set_fetch_addr(ehci
, async
, sitd
.next
);
1751 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1755 /* Section 4.10.2 - paragraph 3 */
1756 static int ehci_state_advqueue(EHCIQueue
*q
)
1759 /* TO-DO: 4.10.2 - paragraph 2
1760 * if I-bit is set to 1 and QH is not active
1761 * go to horizontal QH
1764 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1770 * want data and alt-next qTD is valid
1772 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1773 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1774 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1775 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1780 } else if (NLPTR_TBIT(q
->qh
.next_qtd
) == 0) {
1781 q
->qtdaddr
= q
->qh
.next_qtd
;
1782 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1785 * no valid qTD, try next QH
1788 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1794 /* Section 4.10.2 - paragraph 4 */
1795 static int ehci_state_fetchqtd(EHCIQueue
*q
)
1802 addr
= NLPTR_GET(q
->qtdaddr
);
1803 if (get_dwords(q
->ehci
, addr
+ 8, &qtd
.token
, 1) < 0) {
1807 if (get_dwords(q
->ehci
, addr
+ 0, &qtd
.next
, 1) < 0 ||
1808 get_dwords(q
->ehci
, addr
+ 4, &qtd
.altnext
, 1) < 0 ||
1809 get_dwords(q
->ehci
, addr
+ 12, qtd
.bufptr
,
1810 ARRAY_SIZE(qtd
.bufptr
)) < 0) {
1813 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &qtd
);
1815 p
= QTAILQ_FIRST(&q
->packets
);
1817 if (!ehci_verify_qtd(p
, &qtd
)) {
1818 ehci_cancel_queue(q
);
1819 if (qtd
.token
& QTD_TOKEN_ACTIVE
) {
1820 ehci_trace_guest_bug(q
->ehci
, "guest updated active qTD");
1825 ehci_qh_do_overlay(q
);
1829 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1830 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1831 } else if (p
!= NULL
) {
1833 case EHCI_ASYNC_NONE
:
1834 case EHCI_ASYNC_INITIALIZED
:
1835 /* Not yet executed (MULT), or previously nacked (int) packet */
1836 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
1838 case EHCI_ASYNC_INFLIGHT
:
1839 /* Check if the guest has added new tds to the queue */
1840 again
= ehci_fill_queue(QTAILQ_LAST(&q
->packets
));
1841 /* Unfinished async handled packet, go horizontal */
1842 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1844 case EHCI_ASYNC_FINISHED
:
1845 /* Complete executing of the packet */
1846 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
1849 } else if (q
->dev
== NULL
) {
1850 ehci_trace_guest_bug(q
->ehci
, "no device attached to queue");
1851 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1853 p
= ehci_alloc_packet(q
);
1854 p
->qtdaddr
= q
->qtdaddr
;
1856 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
1862 static int ehci_state_horizqh(EHCIQueue
*q
)
1866 if (ehci_get_fetch_addr(q
->ehci
, q
->async
) != q
->qh
.next
) {
1867 ehci_set_fetch_addr(q
->ehci
, q
->async
, q
->qh
.next
);
1868 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHENTRY
);
1871 ehci_set_state(q
->ehci
, q
->async
, EST_ACTIVE
);
1877 /* Returns "again" */
1878 static int ehci_fill_queue(EHCIPacket
*p
)
1880 USBEndpoint
*ep
= p
->packet
.ep
;
1881 EHCIQueue
*q
= p
->queue
;
1882 EHCIqtd qtd
= p
->qtd
;
1886 if (NLPTR_TBIT(qtd
.next
) != 0) {
1891 * Detect circular td lists, Windows creates these, counting on the
1892 * active bit going low after execution to make the queue stop.
1894 QTAILQ_FOREACH(p
, &q
->packets
, next
) {
1895 if (p
->qtdaddr
== qtdaddr
) {
1899 if (get_dwords(q
->ehci
, NLPTR_GET(qtdaddr
),
1900 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2) < 0) {
1903 ehci_trace_qtd(q
, NLPTR_GET(qtdaddr
), &qtd
);
1904 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1907 if (!ehci_verify_pid(q
, &qtd
)) {
1908 ehci_trace_guest_bug(q
->ehci
, "guest queued token with wrong pid");
1911 p
= ehci_alloc_packet(q
);
1912 p
->qtdaddr
= qtdaddr
;
1914 if (ehci_execute(p
, "queue") == -1) {
1917 assert(p
->packet
.status
== USB_RET_ASYNC
);
1918 p
->async
= EHCI_ASYNC_INFLIGHT
;
1921 usb_device_flush_ep_queue(ep
->dev
, ep
);
1925 static int ehci_state_execute(EHCIQueue
*q
)
1927 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1931 assert(p
->qtdaddr
== q
->qtdaddr
);
1933 if (ehci_qh_do_overlay(q
) != 0) {
1937 // TODO verify enough time remains in the uframe as in 4.4.1.1
1938 // TODO write back ptr to async list when done or out of time
1940 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
1941 if (!q
->async
&& q
->transact_ctr
== 0) {
1942 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1948 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
1951 again
= ehci_execute(p
, "process");
1955 if (p
->packet
.status
== USB_RET_ASYNC
) {
1957 trace_usb_ehci_packet_action(p
->queue
, p
, "async");
1958 p
->async
= EHCI_ASYNC_INFLIGHT
;
1959 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1961 again
= ehci_fill_queue(p
);
1968 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
1975 static int ehci_state_executing(EHCIQueue
*q
)
1977 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1980 assert(p
->qtdaddr
== q
->qtdaddr
);
1982 ehci_execute_complete(q
);
1985 if (!q
->async
&& q
->transact_ctr
> 0) {
1990 if (p
->packet
.status
== USB_RET_NAK
) {
1991 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1993 ehci_set_state(q
->ehci
, q
->async
, EST_WRITEBACK
);
2001 static int ehci_state_writeback(EHCIQueue
*q
)
2003 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2004 uint32_t *qtd
, addr
;
2007 /* Write back the QTD from the QH area */
2009 assert(p
->qtdaddr
== q
->qtdaddr
);
2011 ehci_trace_qtd(q
, NLPTR_GET(p
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
2012 qtd
= (uint32_t *) &q
->qh
.next_qtd
;
2013 addr
= NLPTR_GET(p
->qtdaddr
);
2014 put_dwords(q
->ehci
, addr
+ 2 * sizeof(uint32_t), qtd
+ 2, 2);
2015 ehci_free_packet(p
);
2018 * EHCI specs say go horizontal here.
2020 * We can also advance the queue here for performance reasons. We
2021 * need to take care to only take that shortcut in case we've
2022 * processed the qtd just written back without errors, i.e. halt
2025 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
2026 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2029 ehci_set_state(q
->ehci
, q
->async
, EST_ADVANCEQUEUE
);
2036 * This is the state machine that is common to both async and periodic
2039 static void ehci_advance_state(EHCIState
*ehci
, int async
)
2041 EHCIQueue
*q
= NULL
;
2046 switch(ehci_get_state(ehci
, async
)) {
2047 case EST_WAITLISTHEAD
:
2048 again
= ehci_state_waitlisthead(ehci
, async
);
2051 case EST_FETCHENTRY
:
2052 again
= ehci_state_fetchentry(ehci
, async
);
2056 q
= ehci_state_fetchqh(ehci
, async
);
2058 assert(q
->async
== async
);
2066 again
= ehci_state_fetchitd(ehci
, async
);
2071 again
= ehci_state_fetchsitd(ehci
, async
);
2075 case EST_ADVANCEQUEUE
:
2077 again
= ehci_state_advqueue(q
);
2082 again
= ehci_state_fetchqtd(q
);
2085 case EST_HORIZONTALQH
:
2087 again
= ehci_state_horizqh(q
);
2092 again
= ehci_state_execute(q
);
2094 ehci
->async_stepdown
= 0;
2101 ehci
->async_stepdown
= 0;
2103 again
= ehci_state_executing(q
);
2108 again
= ehci_state_writeback(q
);
2110 ehci
->periodic_sched_active
= PERIODIC_ACTIVE
;
2115 fprintf(stderr
, "Bad state!\n");
2116 g_assert_not_reached();
2119 if (again
< 0 || itd_count
> 16) {
2120 /* TODO: notify guest (raise HSE irq?) */
2121 fprintf(stderr
, "processing error - resetting ehci HC\n");
2129 static void ehci_advance_async_state(EHCIState
*ehci
)
2131 const int async
= 1;
2133 switch(ehci_get_state(ehci
, async
)) {
2135 if (!ehci_async_enabled(ehci
)) {
2138 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2139 // No break, fall through to ACTIVE
2142 if (!ehci_async_enabled(ehci
)) {
2143 ehci_queues_rip_all(ehci
, async
);
2144 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2148 /* make sure guest has acknowledged the doorbell interrupt */
2149 /* TO-DO: is this really needed? */
2150 if (ehci
->usbsts
& USBSTS_IAA
) {
2151 DPRINTF("IAA status bit still set.\n");
2155 /* check that address register has been set */
2156 if (ehci
->asynclistaddr
== 0) {
2160 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
2161 ehci_advance_state(ehci
, async
);
2163 /* If the doorbell is set, the guest wants to make a change to the
2164 * schedule. The host controller needs to release cached data.
2167 if (ehci
->usbcmd
& USBCMD_IAAD
) {
2168 /* Remove all unseen qhs from the async qhs queue */
2169 ehci_queues_rip_unseen(ehci
, async
);
2170 trace_usb_ehci_doorbell_ack();
2171 ehci
->usbcmd
&= ~USBCMD_IAAD
;
2172 ehci_raise_irq(ehci
, USBSTS_IAA
);
2177 /* this should only be due to a developer mistake */
2178 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
2179 "Resetting to active\n", ehci
->astate
);
2180 g_assert_not_reached();
2184 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2188 const int async
= 0;
2192 switch(ehci_get_state(ehci
, async
)) {
2194 if (!(ehci
->frindex
& 7) && ehci_periodic_enabled(ehci
)) {
2195 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2196 // No break, fall through to ACTIVE
2201 if (!(ehci
->frindex
& 7) && !ehci_periodic_enabled(ehci
)) {
2202 ehci_queues_rip_all(ehci
, async
);
2203 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2207 list
= ehci
->periodiclistbase
& 0xfffff000;
2208 /* check that register has been set */
2212 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2214 if (get_dwords(ehci
, list
, &entry
, 1) < 0) {
2218 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2219 ehci
->frindex
/ 8, list
, entry
);
2220 ehci_set_fetch_addr(ehci
, async
,entry
);
2221 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2222 ehci_advance_state(ehci
, async
);
2223 ehci_queues_rip_unused(ehci
, async
);
2227 /* this should only be due to a developer mistake */
2228 fprintf(stderr
, "ehci: Bad periodic state %d. "
2229 "Resetting to active\n", ehci
->pstate
);
2230 g_assert_not_reached();
2234 static void ehci_update_frindex(EHCIState
*ehci
, int uframes
)
2236 if (!ehci_enabled(ehci
) && ehci
->pstate
== EST_INACTIVE
) {
2240 /* Generate FLR interrupt if frame index rolls over 0x2000 */
2241 if ((ehci
->frindex
% 0x2000) + uframes
>= 0x2000) {
2242 ehci_raise_irq(ehci
, USBSTS_FLR
);
2245 /* How many times will frindex roll over 0x4000 with this frame count?
2246 * usbsts_frindex is decremented by 0x4000 on rollover until it reaches 0
2248 int rollovers
= (ehci
->frindex
+ uframes
) / 0x4000;
2249 if (rollovers
> 0) {
2250 if (ehci
->usbsts_frindex
>= (rollovers
* 0x4000)) {
2251 ehci
->usbsts_frindex
-= 0x4000 * rollovers
;
2253 ehci
->usbsts_frindex
= 0;
2257 ehci
->frindex
= (ehci
->frindex
+ uframes
) % 0x4000;
2260 static void ehci_work_bh(void *opaque
)
2262 EHCIState
*ehci
= opaque
;
2264 int64_t expire_time
, t_now
;
2265 uint64_t ns_elapsed
;
2266 uint64_t uframes
, skipped_uframes
;
2269 if (ehci
->working
) {
2272 ehci
->working
= true;
2274 t_now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2275 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2276 uframes
= ns_elapsed
/ UFRAME_TIMER_NS
;
2278 if (ehci_periodic_enabled(ehci
) || ehci
->pstate
!= EST_INACTIVE
) {
2281 if (uframes
> (ehci
->maxframes
* 8)) {
2282 skipped_uframes
= uframes
- (ehci
->maxframes
* 8);
2283 ehci_update_frindex(ehci
, skipped_uframes
);
2284 ehci
->last_run_ns
+= UFRAME_TIMER_NS
* skipped_uframes
;
2285 uframes
-= skipped_uframes
;
2286 DPRINTF("WARNING - EHCI skipped %d uframes\n", skipped_uframes
);
2289 for (i
= 0; i
< uframes
; i
++) {
2291 * If we're running behind schedule, we should not catch up
2292 * too fast, as that will make some guests unhappy:
2293 * 1) We must process a minimum of MIN_UFR_PER_TICK frames,
2294 * otherwise we will never catch up
2295 * 2) Process frames until the guest has requested an irq (IOC)
2297 if (i
>= MIN_UFR_PER_TICK
) {
2298 ehci_commit_irq(ehci
);
2299 if ((ehci
->usbsts
& USBINTR_MASK
) & ehci
->usbintr
) {
2303 if (ehci
->periodic_sched_active
) {
2304 ehci
->periodic_sched_active
--;
2306 ehci_update_frindex(ehci
, 1);
2307 if ((ehci
->frindex
& 7) == 0) {
2308 ehci_advance_periodic_state(ehci
);
2310 ehci
->last_run_ns
+= UFRAME_TIMER_NS
;
2313 ehci
->periodic_sched_active
= 0;
2314 ehci_update_frindex(ehci
, uframes
);
2315 ehci
->last_run_ns
+= UFRAME_TIMER_NS
* uframes
;
2318 if (ehci
->periodic_sched_active
) {
2319 ehci
->async_stepdown
= 0;
2320 } else if (ehci
->async_stepdown
< ehci
->maxframes
/ 2) {
2321 ehci
->async_stepdown
++;
2324 /* Async is not inside loop since it executes everything it can once
2327 if (ehci_async_enabled(ehci
) || ehci
->astate
!= EST_INACTIVE
) {
2329 ehci_advance_async_state(ehci
);
2332 ehci_commit_irq(ehci
);
2333 if (ehci
->usbsts_pending
) {
2335 ehci
->async_stepdown
= 0;
2338 if (ehci_enabled(ehci
) && (ehci
->usbintr
& USBSTS_FLR
)) {
2343 /* If we've raised int, we speed up the timer, so that we quickly
2344 * notice any new packets queued up in response */
2345 if (ehci
->int_req_by_async
&& (ehci
->usbsts
& USBSTS_INT
)) {
2346 expire_time
= t_now
+
2347 NANOSECONDS_PER_SECOND
/ (FRAME_TIMER_FREQ
* 4);
2348 ehci
->int_req_by_async
= false;
2350 expire_time
= t_now
+ (NANOSECONDS_PER_SECOND
2351 * (ehci
->async_stepdown
+1) / FRAME_TIMER_FREQ
);
2353 timer_mod(ehci
->frame_timer
, expire_time
);
2356 ehci
->working
= false;
2359 static void ehci_work_timer(void *opaque
)
2361 EHCIState
*ehci
= opaque
;
2363 qemu_bh_schedule(ehci
->async_bh
);
2366 static const MemoryRegionOps ehci_mmio_caps_ops
= {
2367 .read
= ehci_caps_read
,
2368 .write
= ehci_caps_write
,
2369 .valid
.min_access_size
= 1,
2370 .valid
.max_access_size
= 4,
2371 .impl
.min_access_size
= 1,
2372 .impl
.max_access_size
= 1,
2373 .endianness
= DEVICE_LITTLE_ENDIAN
,
2376 static const MemoryRegionOps ehci_mmio_opreg_ops
= {
2377 .read
= ehci_opreg_read
,
2378 .write
= ehci_opreg_write
,
2379 .valid
.min_access_size
= 4,
2380 .valid
.max_access_size
= 4,
2381 .endianness
= DEVICE_LITTLE_ENDIAN
,
2384 static const MemoryRegionOps ehci_mmio_port_ops
= {
2385 .read
= ehci_port_read
,
2386 .write
= ehci_port_write
,
2387 .valid
.min_access_size
= 4,
2388 .valid
.max_access_size
= 4,
2389 .endianness
= DEVICE_LITTLE_ENDIAN
,
2392 static USBPortOps ehci_port_ops
= {
2393 .attach
= ehci_attach
,
2394 .detach
= ehci_detach
,
2395 .child_detach
= ehci_child_detach
,
2396 .wakeup
= ehci_wakeup
,
2397 .complete
= ehci_async_complete_packet
,
2400 static USBBusOps ehci_bus_ops_companion
= {
2401 .register_companion
= ehci_register_companion
,
2402 .wakeup_endpoint
= ehci_wakeup_endpoint
,
2404 static USBBusOps ehci_bus_ops_standalone
= {
2405 .wakeup_endpoint
= ehci_wakeup_endpoint
,
2408 static int usb_ehci_pre_save(void *opaque
)
2410 EHCIState
*ehci
= opaque
;
2411 uint32_t new_frindex
;
2413 /* Round down frindex to a multiple of 8 for migration compatibility */
2414 new_frindex
= ehci
->frindex
& ~7;
2415 ehci
->last_run_ns
-= (ehci
->frindex
- new_frindex
) * UFRAME_TIMER_NS
;
2416 ehci
->frindex
= new_frindex
;
2421 static int usb_ehci_post_load(void *opaque
, int version_id
)
2423 EHCIState
*s
= opaque
;
2426 for (i
= 0; i
< NB_PORTS
; i
++) {
2427 USBPort
*companion
= s
->companion_ports
[i
];
2428 if (companion
== NULL
) {
2431 if (s
->portsc
[i
] & PORTSC_POWNER
) {
2432 companion
->dev
= s
->ports
[i
].dev
;
2434 companion
->dev
= NULL
;
2441 static void usb_ehci_vm_state_change(void *opaque
, bool running
, RunState state
)
2443 EHCIState
*ehci
= opaque
;
2446 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2447 * schedule in guest memory. We must do the rebuilt ASAP, so that
2448 * USB-devices which have async handled packages have a packet in the
2449 * ep queue to match the completion with.
2451 if (state
== RUN_STATE_RUNNING
) {
2452 ehci_advance_async_state(ehci
);
2456 * The schedule rebuilt from guest memory could cause the migration dest
2457 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2458 * will never have existed on the destination. Therefor we must flush the
2459 * async schedule on savevm to catch any not yet noticed unlinks.
2461 if (state
== RUN_STATE_SAVE_VM
) {
2462 ehci_advance_async_state(ehci
);
2463 ehci_queues_rip_unseen(ehci
, 1);
2467 const VMStateDescription vmstate_ehci
= {
2468 .name
= "ehci-core",
2470 .minimum_version_id
= 1,
2471 .pre_save
= usb_ehci_pre_save
,
2472 .post_load
= usb_ehci_post_load
,
2473 .fields
= (VMStateField
[]) {
2474 /* mmio registers */
2475 VMSTATE_UINT32(usbcmd
, EHCIState
),
2476 VMSTATE_UINT32(usbsts
, EHCIState
),
2477 VMSTATE_UINT32_V(usbsts_pending
, EHCIState
, 2),
2478 VMSTATE_UINT32_V(usbsts_frindex
, EHCIState
, 2),
2479 VMSTATE_UINT32(usbintr
, EHCIState
),
2480 VMSTATE_UINT32(frindex
, EHCIState
),
2481 VMSTATE_UINT32(ctrldssegment
, EHCIState
),
2482 VMSTATE_UINT32(periodiclistbase
, EHCIState
),
2483 VMSTATE_UINT32(asynclistaddr
, EHCIState
),
2484 VMSTATE_UINT32(configflag
, EHCIState
),
2485 VMSTATE_UINT32(portsc
[0], EHCIState
),
2486 VMSTATE_UINT32(portsc
[1], EHCIState
),
2487 VMSTATE_UINT32(portsc
[2], EHCIState
),
2488 VMSTATE_UINT32(portsc
[3], EHCIState
),
2489 VMSTATE_UINT32(portsc
[4], EHCIState
),
2490 VMSTATE_UINT32(portsc
[5], EHCIState
),
2492 VMSTATE_TIMER_PTR(frame_timer
, EHCIState
),
2493 VMSTATE_UINT64(last_run_ns
, EHCIState
),
2494 VMSTATE_UINT32(async_stepdown
, EHCIState
),
2495 /* schedule state */
2496 VMSTATE_UINT32(astate
, EHCIState
),
2497 VMSTATE_UINT32(pstate
, EHCIState
),
2498 VMSTATE_UINT32(a_fetch_addr
, EHCIState
),
2499 VMSTATE_UINT32(p_fetch_addr
, EHCIState
),
2500 VMSTATE_END_OF_LIST()
2504 void usb_ehci_realize(EHCIState
*s
, DeviceState
*dev
, Error
**errp
)
2508 if (s
->portnr
> NB_PORTS
) {
2509 error_setg(errp
, "Too many ports! Max. port number is %d.",
2513 if (s
->maxframes
< 8 || s
->maxframes
> 512) {
2514 error_setg(errp
, "maxframes %d out if range (8 .. 512)",
2519 memory_region_add_subregion(&s
->mem
, s
->capsbase
, &s
->mem_caps
);
2520 memory_region_add_subregion(&s
->mem
, s
->opregbase
, &s
->mem_opreg
);
2521 memory_region_add_subregion(&s
->mem
, s
->opregbase
+ s
->portscbase
,
2524 usb_bus_new(&s
->bus
, sizeof(s
->bus
), s
->companion_enable
?
2525 &ehci_bus_ops_companion
: &ehci_bus_ops_standalone
, dev
);
2526 for (i
= 0; i
< s
->portnr
; i
++) {
2527 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2528 USB_SPEED_MASK_HIGH
);
2529 s
->ports
[i
].dev
= 0;
2532 s
->frame_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, ehci_work_timer
, s
);
2533 s
->async_bh
= qemu_bh_new(ehci_work_bh
, s
);
2536 s
->vmstate
= qemu_add_vm_change_state_handler(usb_ehci_vm_state_change
, s
);
2539 void usb_ehci_unrealize(EHCIState
*s
, DeviceState
*dev
)
2541 trace_usb_ehci_unrealize();
2543 if (s
->frame_timer
) {
2544 timer_free(s
->frame_timer
);
2545 s
->frame_timer
= NULL
;
2548 qemu_bh_delete(s
->async_bh
);
2551 ehci_queues_rip_all(s
, 0);
2552 ehci_queues_rip_all(s
, 1);
2554 memory_region_del_subregion(&s
->mem
, &s
->mem_caps
);
2555 memory_region_del_subregion(&s
->mem
, &s
->mem_opreg
);
2556 memory_region_del_subregion(&s
->mem
, &s
->mem_ports
);
2558 usb_bus_release(&s
->bus
);
2561 qemu_del_vm_change_state_handler(s
->vmstate
);
2565 void usb_ehci_init(EHCIState
*s
, DeviceState
*dev
)
2567 /* 2.2 host controller interface version */
2568 s
->caps
[0x00] = (uint8_t)(s
->opregbase
- s
->capsbase
);
2569 s
->caps
[0x01] = 0x00;
2570 s
->caps
[0x02] = 0x00;
2571 s
->caps
[0x03] = 0x01; /* HC version */
2572 s
->caps
[0x04] = s
->portnr
; /* Number of downstream ports */
2573 s
->caps
[0x05] = 0x00; /* No companion ports at present */
2574 s
->caps
[0x06] = 0x00;
2575 s
->caps
[0x07] = 0x00;
2576 s
->caps
[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2577 s
->caps
[0x0a] = 0x00;
2578 s
->caps
[0x0b] = 0x00;
2580 QTAILQ_INIT(&s
->aqueues
);
2581 QTAILQ_INIT(&s
->pqueues
);
2582 usb_packet_init(&s
->ipacket
);
2584 memory_region_init(&s
->mem
, OBJECT(dev
), "ehci", MMIO_SIZE
);
2585 memory_region_init_io(&s
->mem_caps
, OBJECT(dev
), &ehci_mmio_caps_ops
, s
,
2586 "capabilities", CAPA_SIZE
);
2587 memory_region_init_io(&s
->mem_opreg
, OBJECT(dev
), &ehci_mmio_opreg_ops
, s
,
2588 "operational", s
->portscbase
);
2589 memory_region_init_io(&s
->mem_ports
, OBJECT(dev
), &ehci_mmio_port_ops
, s
,
2590 "ports", 4 * s
->portnr
);
2593 void usb_ehci_finalize(EHCIState
*s
)
2595 usb_packet_cleanup(&s
->ipacket
);
2599 * vim: expandtab ts=4