2 * ASPEED System Control Unit
4 * Andrew Jeffery <andrew@aj.id.au>
6 * Copyright 2016 IBM Corp.
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include "hw/misc/aspeed_scu.h"
14 #include "hw/qdev-properties.h"
15 #include "migration/vmstate.h"
16 #include "qapi/error.h"
17 #include "qapi/visitor.h"
18 #include "qemu/bitops.h"
20 #include "qemu/guest-random.h"
21 #include "qemu/module.h"
24 #define TO_REG(offset) ((offset) >> 2)
26 #define PROT_KEY TO_REG(0x00)
27 #define SYS_RST_CTRL TO_REG(0x04)
28 #define CLK_SEL TO_REG(0x08)
29 #define CLK_STOP_CTRL TO_REG(0x0C)
30 #define FREQ_CNTR_CTRL TO_REG(0x10)
31 #define FREQ_CNTR_EVAL TO_REG(0x14)
32 #define IRQ_CTRL TO_REG(0x18)
33 #define D2PLL_PARAM TO_REG(0x1C)
34 #define MPLL_PARAM TO_REG(0x20)
35 #define HPLL_PARAM TO_REG(0x24)
36 #define FREQ_CNTR_RANGE TO_REG(0x28)
37 #define MISC_CTRL1 TO_REG(0x2C)
38 #define PCI_CTRL1 TO_REG(0x30)
39 #define PCI_CTRL2 TO_REG(0x34)
40 #define PCI_CTRL3 TO_REG(0x38)
41 #define SYS_RST_STATUS TO_REG(0x3C)
42 #define SOC_SCRATCH1 TO_REG(0x40)
43 #define SOC_SCRATCH2 TO_REG(0x44)
44 #define MAC_CLK_DELAY TO_REG(0x48)
45 #define MISC_CTRL2 TO_REG(0x4C)
46 #define VGA_SCRATCH1 TO_REG(0x50)
47 #define VGA_SCRATCH2 TO_REG(0x54)
48 #define VGA_SCRATCH3 TO_REG(0x58)
49 #define VGA_SCRATCH4 TO_REG(0x5C)
50 #define VGA_SCRATCH5 TO_REG(0x60)
51 #define VGA_SCRATCH6 TO_REG(0x64)
52 #define VGA_SCRATCH7 TO_REG(0x68)
53 #define VGA_SCRATCH8 TO_REG(0x6C)
54 #define HW_STRAP1 TO_REG(0x70)
55 #define RNG_CTRL TO_REG(0x74)
56 #define RNG_DATA TO_REG(0x78)
57 #define SILICON_REV TO_REG(0x7C)
58 #define PINMUX_CTRL1 TO_REG(0x80)
59 #define PINMUX_CTRL2 TO_REG(0x84)
60 #define PINMUX_CTRL3 TO_REG(0x88)
61 #define PINMUX_CTRL4 TO_REG(0x8C)
62 #define PINMUX_CTRL5 TO_REG(0x90)
63 #define PINMUX_CTRL6 TO_REG(0x94)
64 #define WDT_RST_CTRL TO_REG(0x9C)
65 #define PINMUX_CTRL7 TO_REG(0xA0)
66 #define PINMUX_CTRL8 TO_REG(0xA4)
67 #define PINMUX_CTRL9 TO_REG(0xA8)
68 #define WAKEUP_EN TO_REG(0xC0)
69 #define WAKEUP_CTRL TO_REG(0xC4)
70 #define HW_STRAP2 TO_REG(0xD0)
71 #define FREE_CNTR4 TO_REG(0xE0)
72 #define FREE_CNTR4_EXT TO_REG(0xE4)
73 #define CPU2_CTRL TO_REG(0x100)
74 #define CPU2_BASE_SEG1 TO_REG(0x104)
75 #define CPU2_BASE_SEG2 TO_REG(0x108)
76 #define CPU2_BASE_SEG3 TO_REG(0x10C)
77 #define CPU2_BASE_SEG4 TO_REG(0x110)
78 #define CPU2_BASE_SEG5 TO_REG(0x114)
79 #define CPU2_CACHE_CTRL TO_REG(0x118)
80 #define CHIP_ID0 TO_REG(0x150)
81 #define CHIP_ID1 TO_REG(0x154)
82 #define UART_HPLL_CLK TO_REG(0x160)
83 #define PCIE_CTRL TO_REG(0x180)
84 #define BMC_MMIO_CTRL TO_REG(0x184)
85 #define RELOC_DECODE_BASE1 TO_REG(0x188)
86 #define RELOC_DECODE_BASE2 TO_REG(0x18C)
87 #define MAILBOX_DECODE_BASE TO_REG(0x190)
88 #define SRAM_DECODE_BASE1 TO_REG(0x194)
89 #define SRAM_DECODE_BASE2 TO_REG(0x198)
90 #define BMC_REV TO_REG(0x19C)
91 #define BMC_DEV_ID TO_REG(0x1A4)
93 #define AST2600_PROT_KEY TO_REG(0x00)
94 #define AST2600_SILICON_REV TO_REG(0x04)
95 #define AST2600_SILICON_REV2 TO_REG(0x14)
96 #define AST2600_SYS_RST_CTRL TO_REG(0x40)
97 #define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44)
98 #define AST2600_SYS_RST_CTRL2 TO_REG(0x50)
99 #define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54)
100 #define AST2600_CLK_STOP_CTRL TO_REG(0x80)
101 #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
102 #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
103 #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
104 #define AST2600_DEBUG_CTRL TO_REG(0xC8)
105 #define AST2600_DEBUG_CTRL2 TO_REG(0xD8)
106 #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
107 #define AST2600_HPLL_PARAM TO_REG(0x200)
108 #define AST2600_HPLL_EXT TO_REG(0x204)
109 #define AST2600_APLL_PARAM TO_REG(0x210)
110 #define AST2600_APLL_EXT TO_REG(0x214)
111 #define AST2600_MPLL_PARAM TO_REG(0x220)
112 #define AST2600_MPLL_EXT TO_REG(0x224)
113 #define AST2600_EPLL_PARAM TO_REG(0x240)
114 #define AST2600_EPLL_EXT TO_REG(0x244)
115 #define AST2600_DPLL_PARAM TO_REG(0x260)
116 #define AST2600_DPLL_EXT TO_REG(0x264)
117 #define AST2600_CLK_SEL TO_REG(0x300)
118 #define AST2600_CLK_SEL2 TO_REG(0x304)
119 #define AST2600_CLK_SEL3 TO_REG(0x308)
120 #define AST2600_CLK_SEL4 TO_REG(0x310)
121 #define AST2600_CLK_SEL5 TO_REG(0x314)
122 #define AST2600_UARTCLK TO_REG(0x338)
123 #define AST2600_HUARTCLK TO_REG(0x33C)
124 #define AST2600_HW_STRAP1 TO_REG(0x500)
125 #define AST2600_HW_STRAP1_CLR TO_REG(0x504)
126 #define AST2600_HW_STRAP1_PROT TO_REG(0x508)
127 #define AST2600_HW_STRAP2 TO_REG(0x510)
128 #define AST2600_HW_STRAP2_CLR TO_REG(0x514)
129 #define AST2600_HW_STRAP2_PROT TO_REG(0x518)
130 #define AST2600_RNG_CTRL TO_REG(0x524)
131 #define AST2600_RNG_DATA TO_REG(0x540)
132 #define AST2600_CHIP_ID0 TO_REG(0x5B0)
133 #define AST2600_CHIP_ID1 TO_REG(0x5B4)
135 #define AST2600_CLK TO_REG(0x40)
137 #define SCU_IO_REGION_SIZE 0x1000
139 static const uint32_t ast2400_a0_resets
[ASPEED_SCU_NR_REGS
] = {
140 [SYS_RST_CTRL
] = 0xFFCFFEDCU
,
141 [CLK_SEL
] = 0xF3F40000U
,
142 [CLK_STOP_CTRL
] = 0x19FC3E8BU
,
143 [D2PLL_PARAM
] = 0x00026108U
,
144 [MPLL_PARAM
] = 0x00030291U
,
145 [HPLL_PARAM
] = 0x00000291U
,
146 [MISC_CTRL1
] = 0x00000010U
,
147 [PCI_CTRL1
] = 0x20001A03U
,
148 [PCI_CTRL2
] = 0x20001A03U
,
149 [PCI_CTRL3
] = 0x04000030U
,
150 [SYS_RST_STATUS
] = 0x00000001U
,
151 [SOC_SCRATCH1
] = 0x000000C0U
, /* SoC completed DRAM init */
152 [MISC_CTRL2
] = 0x00000023U
,
153 [RNG_CTRL
] = 0x0000000EU
,
154 [PINMUX_CTRL2
] = 0x0000F000U
,
155 [PINMUX_CTRL3
] = 0x01000000U
,
156 [PINMUX_CTRL4
] = 0x000000FFU
,
157 [PINMUX_CTRL5
] = 0x0000A000U
,
158 [WDT_RST_CTRL
] = 0x003FFFF3U
,
159 [PINMUX_CTRL8
] = 0xFFFF0000U
,
160 [PINMUX_CTRL9
] = 0x000FFFFFU
,
161 [FREE_CNTR4
] = 0x000000FFU
,
162 [FREE_CNTR4_EXT
] = 0x000000FFU
,
163 [CPU2_BASE_SEG1
] = 0x80000000U
,
164 [CPU2_BASE_SEG4
] = 0x1E600000U
,
165 [CPU2_BASE_SEG5
] = 0xC0000000U
,
166 [UART_HPLL_CLK
] = 0x00001903U
,
167 [PCIE_CTRL
] = 0x0000007BU
,
168 [BMC_DEV_ID
] = 0x00002402U
171 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
172 /* AST2500 revision A1 */
174 static const uint32_t ast2500_a1_resets
[ASPEED_SCU_NR_REGS
] = {
175 [SYS_RST_CTRL
] = 0xFFCFFEDCU
,
176 [CLK_SEL
] = 0xF3F40000U
,
177 [CLK_STOP_CTRL
] = 0x19FC3E8BU
,
178 [D2PLL_PARAM
] = 0x00026108U
,
179 [MPLL_PARAM
] = 0x00030291U
,
180 [HPLL_PARAM
] = 0x93000400U
,
181 [MISC_CTRL1
] = 0x00000010U
,
182 [PCI_CTRL1
] = 0x20001A03U
,
183 [PCI_CTRL2
] = 0x20001A03U
,
184 [PCI_CTRL3
] = 0x04000030U
,
185 [SYS_RST_STATUS
] = 0x00000001U
,
186 [SOC_SCRATCH1
] = 0x000000C0U
, /* SoC completed DRAM init */
187 [MISC_CTRL2
] = 0x00000023U
,
188 [RNG_CTRL
] = 0x0000000EU
,
189 [PINMUX_CTRL2
] = 0x0000F000U
,
190 [PINMUX_CTRL3
] = 0x03000000U
,
191 [PINMUX_CTRL4
] = 0x00000000U
,
192 [PINMUX_CTRL5
] = 0x0000A000U
,
193 [WDT_RST_CTRL
] = 0x023FFFF3U
,
194 [PINMUX_CTRL8
] = 0xFFFF0000U
,
195 [PINMUX_CTRL9
] = 0x000FFFFFU
,
196 [FREE_CNTR4
] = 0x000000FFU
,
197 [FREE_CNTR4_EXT
] = 0x000000FFU
,
198 [CPU2_BASE_SEG1
] = 0x80000000U
,
199 [CPU2_BASE_SEG4
] = 0x1E600000U
,
200 [CPU2_BASE_SEG5
] = 0xC0000000U
,
201 [CHIP_ID0
] = 0x1234ABCDU
,
202 [CHIP_ID1
] = 0x88884444U
,
203 [UART_HPLL_CLK
] = 0x00001903U
,
204 [PCIE_CTRL
] = 0x0000007BU
,
205 [BMC_DEV_ID
] = 0x00002402U
208 static uint32_t aspeed_scu_get_random(void)
211 qemu_guest_getrandom_nofail(&num
, sizeof(num
));
215 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState
*s
)
217 return ASPEED_SCU_GET_CLASS(s
)->get_apb(s
);
220 static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState
*s
)
222 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(s
);
223 uint32_t hpll
= asc
->calc_hpll(s
, s
->regs
[HPLL_PARAM
]);
225 return hpll
/ (SCU_CLK_GET_PCLK_DIV(s
->regs
[CLK_SEL
]) + 1)
229 static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState
*s
)
231 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(s
);
232 uint32_t hpll
= asc
->calc_hpll(s
, s
->regs
[AST2600_HPLL_PARAM
]);
234 return hpll
/ (SCU_CLK_GET_PCLK_DIV(s
->regs
[AST2600_CLK_SEL
]) + 1)
238 static uint32_t aspeed_1030_scu_get_apb_freq(AspeedSCUState
*s
)
240 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(s
);
241 uint32_t hpll
= asc
->calc_hpll(s
, s
->regs
[AST2600_HPLL_PARAM
]);
243 return hpll
/ (SCU_AST1030_CLK_GET_PCLK_DIV(s
->regs
[AST2600_CLK_SEL4
]) + 1)
247 static uint64_t aspeed_scu_read(void *opaque
, hwaddr offset
, unsigned size
)
249 AspeedSCUState
*s
= ASPEED_SCU(opaque
);
250 int reg
= TO_REG(offset
);
252 if (reg
>= ASPEED_SCU_NR_REGS
) {
253 qemu_log_mask(LOG_GUEST_ERROR
,
254 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx
"\n",
261 /* On hardware, RNG_DATA works regardless of
262 * the state of the enable bit in RNG_CTRL
264 s
->regs
[RNG_DATA
] = aspeed_scu_get_random();
267 qemu_log_mask(LOG_GUEST_ERROR
,
268 "%s: Read of write-only offset 0x%" HWADDR_PRIx
"\n",
276 static void aspeed_ast2400_scu_write(void *opaque
, hwaddr offset
,
277 uint64_t data
, unsigned size
)
279 AspeedSCUState
*s
= ASPEED_SCU(opaque
);
280 int reg
= TO_REG(offset
);
282 if (reg
>= ASPEED_SCU_NR_REGS
) {
283 qemu_log_mask(LOG_GUEST_ERROR
,
284 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx
"\n",
289 if (reg
> PROT_KEY
&& reg
< CPU2_BASE_SEG1
&&
290 !s
->regs
[PROT_KEY
]) {
291 qemu_log_mask(LOG_GUEST_ERROR
, "%s: SCU is locked!\n", __func__
);
294 trace_aspeed_scu_write(offset
, size
, data
);
298 s
->regs
[reg
] = (data
== ASPEED_SCU_PROT_KEY
) ? 1 : 0;
302 case VGA_SCRATCH1
... VGA_SCRATCH8
:
306 qemu_log_mask(LOG_GUEST_ERROR
,
307 "%s: Write to read-only offset 0x%" HWADDR_PRIx
"\n",
315 static void aspeed_ast2500_scu_write(void *opaque
, hwaddr offset
,
316 uint64_t data
, unsigned size
)
318 AspeedSCUState
*s
= ASPEED_SCU(opaque
);
319 int reg
= TO_REG(offset
);
321 if (reg
>= ASPEED_SCU_NR_REGS
) {
322 qemu_log_mask(LOG_GUEST_ERROR
,
323 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx
"\n",
328 if (reg
> PROT_KEY
&& reg
< CPU2_BASE_SEG1
&&
329 !s
->regs
[PROT_KEY
]) {
330 qemu_log_mask(LOG_GUEST_ERROR
, "%s: SCU is locked!\n", __func__
);
334 trace_aspeed_scu_write(offset
, size
, data
);
338 s
->regs
[reg
] = (data
== ASPEED_SCU_PROT_KEY
) ? 1 : 0;
341 s
->regs
[HW_STRAP1
] |= data
;
344 s
->regs
[HW_STRAP1
] &= ~data
;
347 case VGA_SCRATCH1
... VGA_SCRATCH8
:
353 qemu_log_mask(LOG_GUEST_ERROR
,
354 "%s: Write to read-only offset 0x%" HWADDR_PRIx
"\n",
362 static const MemoryRegionOps aspeed_ast2400_scu_ops
= {
363 .read
= aspeed_scu_read
,
364 .write
= aspeed_ast2400_scu_write
,
365 .endianness
= DEVICE_LITTLE_ENDIAN
,
367 .min_access_size
= 1,
368 .max_access_size
= 4,
372 static const MemoryRegionOps aspeed_ast2500_scu_ops
= {
373 .read
= aspeed_scu_read
,
374 .write
= aspeed_ast2500_scu_write
,
375 .endianness
= DEVICE_LITTLE_ENDIAN
,
376 .valid
.min_access_size
= 4,
377 .valid
.max_access_size
= 4,
378 .valid
.unaligned
= false,
381 static uint32_t aspeed_scu_get_clkin(AspeedSCUState
*s
)
383 if (s
->hw_strap1
& SCU_HW_STRAP_CLK_25M_IN
||
384 ASPEED_SCU_GET_CLASS(s
)->clkin_25Mhz
) {
386 } else if (s
->hw_strap1
& SCU_HW_STRAP_CLK_48M_IN
) {
394 * Strapped frequencies for the AST2400 in MHz. They depend on the
397 static const uint32_t hpll_ast2400_freqs
[][4] = {
398 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
399 { 400, 375, 350, 425 }, /* 25MHz */
402 static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState
*s
, uint32_t hpll_reg
)
406 uint32_t clkin
= aspeed_scu_get_clkin(s
);
408 if (hpll_reg
& SCU_AST2400_H_PLL_OFF
) {
412 if (hpll_reg
& SCU_AST2400_H_PLL_PROGRAMMED
) {
413 uint32_t multiplier
= 1;
415 if (!(hpll_reg
& SCU_AST2400_H_PLL_BYPASS_EN
)) {
416 uint32_t n
= (hpll_reg
>> 5) & 0x3f;
417 uint32_t od
= (hpll_reg
>> 4) & 0x1;
418 uint32_t d
= hpll_reg
& 0xf;
420 multiplier
= (2 - od
) * ((n
+ 2) / (d
+ 1));
423 return clkin
* multiplier
;
427 clk_25m_in
= !!(s
->hw_strap1
& SCU_HW_STRAP_CLK_25M_IN
);
428 freq_select
= SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s
->hw_strap1
);
430 return hpll_ast2400_freqs
[clk_25m_in
][freq_select
] * 1000000;
433 static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState
*s
, uint32_t hpll_reg
)
435 uint32_t multiplier
= 1;
436 uint32_t clkin
= aspeed_scu_get_clkin(s
);
438 if (hpll_reg
& SCU_H_PLL_OFF
) {
442 if (!(hpll_reg
& SCU_H_PLL_BYPASS_EN
)) {
443 uint32_t p
= (hpll_reg
>> 13) & 0x3f;
444 uint32_t m
= (hpll_reg
>> 5) & 0xff;
445 uint32_t n
= hpll_reg
& 0x1f;
447 multiplier
= ((m
+ 1) / (n
+ 1)) / (p
+ 1);
450 return clkin
* multiplier
;
453 static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState
*s
, uint32_t hpll_reg
)
455 uint32_t multiplier
= 1;
456 uint32_t clkin
= aspeed_scu_get_clkin(s
);
458 if (hpll_reg
& SCU_AST2600_H_PLL_OFF
) {
462 if (!(hpll_reg
& SCU_AST2600_H_PLL_BYPASS_EN
)) {
463 uint32_t p
= (hpll_reg
>> 19) & 0xf;
464 uint32_t n
= (hpll_reg
>> 13) & 0x3f;
465 uint32_t m
= hpll_reg
& 0x1fff;
467 multiplier
= ((m
+ 1) / (n
+ 1)) / (p
+ 1);
470 return clkin
* multiplier
;
473 static void aspeed_scu_reset(DeviceState
*dev
)
475 AspeedSCUState
*s
= ASPEED_SCU(dev
);
476 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(dev
);
478 memcpy(s
->regs
, asc
->resets
, asc
->nr_regs
* 4);
479 s
->regs
[SILICON_REV
] = s
->silicon_rev
;
480 s
->regs
[HW_STRAP1
] = s
->hw_strap1
;
481 s
->regs
[HW_STRAP2
] = s
->hw_strap2
;
482 s
->regs
[PROT_KEY
] = s
->hw_prot_key
;
485 static uint32_t aspeed_silicon_revs
[] = {
486 AST2400_A0_SILICON_REV
,
487 AST2400_A1_SILICON_REV
,
488 AST2500_A0_SILICON_REV
,
489 AST2500_A1_SILICON_REV
,
490 AST2600_A0_SILICON_REV
,
491 AST2600_A1_SILICON_REV
,
492 AST2600_A2_SILICON_REV
,
493 AST2600_A3_SILICON_REV
,
494 AST1030_A0_SILICON_REV
,
495 AST1030_A1_SILICON_REV
,
498 bool is_supported_silicon_rev(uint32_t silicon_rev
)
502 for (i
= 0; i
< ARRAY_SIZE(aspeed_silicon_revs
); i
++) {
503 if (silicon_rev
== aspeed_silicon_revs
[i
]) {
511 static void aspeed_scu_realize(DeviceState
*dev
, Error
**errp
)
513 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
514 AspeedSCUState
*s
= ASPEED_SCU(dev
);
515 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(dev
);
517 if (!is_supported_silicon_rev(s
->silicon_rev
)) {
518 error_setg(errp
, "Unknown silicon revision: 0x%" PRIx32
,
523 memory_region_init_io(&s
->iomem
, OBJECT(s
), asc
->ops
, s
,
524 TYPE_ASPEED_SCU
, SCU_IO_REGION_SIZE
);
526 sysbus_init_mmio(sbd
, &s
->iomem
);
529 static const VMStateDescription vmstate_aspeed_scu
= {
530 .name
= "aspeed.scu",
532 .minimum_version_id
= 2,
533 .fields
= (VMStateField
[]) {
534 VMSTATE_UINT32_ARRAY(regs
, AspeedSCUState
, ASPEED_AST2600_SCU_NR_REGS
),
535 VMSTATE_END_OF_LIST()
539 static Property aspeed_scu_properties
[] = {
540 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState
, silicon_rev
, 0),
541 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState
, hw_strap1
, 0),
542 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState
, hw_strap2
, 0),
543 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState
, hw_prot_key
, 0),
544 DEFINE_PROP_END_OF_LIST(),
547 static void aspeed_scu_class_init(ObjectClass
*klass
, void *data
)
549 DeviceClass
*dc
= DEVICE_CLASS(klass
);
550 dc
->realize
= aspeed_scu_realize
;
551 dc
->reset
= aspeed_scu_reset
;
552 dc
->desc
= "ASPEED System Control Unit";
553 dc
->vmsd
= &vmstate_aspeed_scu
;
554 device_class_set_props(dc
, aspeed_scu_properties
);
557 static const TypeInfo aspeed_scu_info
= {
558 .name
= TYPE_ASPEED_SCU
,
559 .parent
= TYPE_SYS_BUS_DEVICE
,
560 .instance_size
= sizeof(AspeedSCUState
),
561 .class_init
= aspeed_scu_class_init
,
562 .class_size
= sizeof(AspeedSCUClass
),
566 static void aspeed_2400_scu_class_init(ObjectClass
*klass
, void *data
)
568 DeviceClass
*dc
= DEVICE_CLASS(klass
);
569 AspeedSCUClass
*asc
= ASPEED_SCU_CLASS(klass
);
571 dc
->desc
= "ASPEED 2400 System Control Unit";
572 asc
->resets
= ast2400_a0_resets
;
573 asc
->calc_hpll
= aspeed_2400_scu_calc_hpll
;
574 asc
->get_apb
= aspeed_2400_scu_get_apb_freq
;
575 asc
->apb_divider
= 2;
576 asc
->nr_regs
= ASPEED_SCU_NR_REGS
;
577 asc
->clkin_25Mhz
= false;
578 asc
->ops
= &aspeed_ast2400_scu_ops
;
581 static const TypeInfo aspeed_2400_scu_info
= {
582 .name
= TYPE_ASPEED_2400_SCU
,
583 .parent
= TYPE_ASPEED_SCU
,
584 .instance_size
= sizeof(AspeedSCUState
),
585 .class_init
= aspeed_2400_scu_class_init
,
588 static void aspeed_2500_scu_class_init(ObjectClass
*klass
, void *data
)
590 DeviceClass
*dc
= DEVICE_CLASS(klass
);
591 AspeedSCUClass
*asc
= ASPEED_SCU_CLASS(klass
);
593 dc
->desc
= "ASPEED 2500 System Control Unit";
594 asc
->resets
= ast2500_a1_resets
;
595 asc
->calc_hpll
= aspeed_2500_scu_calc_hpll
;
596 asc
->get_apb
= aspeed_2400_scu_get_apb_freq
;
597 asc
->apb_divider
= 4;
598 asc
->nr_regs
= ASPEED_SCU_NR_REGS
;
599 asc
->clkin_25Mhz
= false;
600 asc
->ops
= &aspeed_ast2500_scu_ops
;
603 static const TypeInfo aspeed_2500_scu_info
= {
604 .name
= TYPE_ASPEED_2500_SCU
,
605 .parent
= TYPE_ASPEED_SCU
,
606 .instance_size
= sizeof(AspeedSCUState
),
607 .class_init
= aspeed_2500_scu_class_init
,
610 static uint64_t aspeed_ast2600_scu_read(void *opaque
, hwaddr offset
,
613 AspeedSCUState
*s
= ASPEED_SCU(opaque
);
614 int reg
= TO_REG(offset
);
616 if (reg
>= ASPEED_AST2600_SCU_NR_REGS
) {
617 qemu_log_mask(LOG_GUEST_ERROR
,
618 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx
"\n",
624 case AST2600_HPLL_EXT
:
625 case AST2600_EPLL_EXT
:
626 case AST2600_MPLL_EXT
:
627 /* PLLs are always "locked" */
628 return s
->regs
[reg
] | BIT(31);
629 case AST2600_RNG_DATA
:
631 * On hardware, RNG_DATA works regardless of the state of the
632 * enable bit in RNG_CTRL
634 * TODO: Check this is true for ast2600
636 s
->regs
[AST2600_RNG_DATA
] = aspeed_scu_get_random();
643 static void aspeed_ast2600_scu_write(void *opaque
, hwaddr offset
,
644 uint64_t data64
, unsigned size
)
646 AspeedSCUState
*s
= ASPEED_SCU(opaque
);
647 int reg
= TO_REG(offset
);
648 /* Truncate here so bitwise operations below behave as expected */
649 uint32_t data
= data64
;
651 if (reg
>= ASPEED_AST2600_SCU_NR_REGS
) {
652 qemu_log_mask(LOG_GUEST_ERROR
,
653 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx
"\n",
658 if (reg
> PROT_KEY
&& !s
->regs
[PROT_KEY
]) {
659 qemu_log_mask(LOG_GUEST_ERROR
, "%s: SCU is locked!\n", __func__
);
662 trace_aspeed_scu_write(offset
, size
, data
);
665 case AST2600_PROT_KEY
:
666 s
->regs
[reg
] = (data
== ASPEED_SCU_PROT_KEY
) ? 1 : 0;
668 case AST2600_HW_STRAP1
:
669 case AST2600_HW_STRAP2
:
670 if (s
->regs
[reg
+ 2]) {
674 case AST2600_SYS_RST_CTRL
:
675 case AST2600_SYS_RST_CTRL2
:
676 case AST2600_CLK_STOP_CTRL
:
677 case AST2600_CLK_STOP_CTRL2
:
678 /* W1S (Write 1 to set) registers */
679 s
->regs
[reg
] |= data
;
681 case AST2600_SYS_RST_CTRL_CLR
:
682 case AST2600_SYS_RST_CTRL2_CLR
:
683 case AST2600_CLK_STOP_CTRL_CLR
:
684 case AST2600_CLK_STOP_CTRL2_CLR
:
685 case AST2600_HW_STRAP1_CLR
:
686 case AST2600_HW_STRAP2_CLR
:
688 * W1C (Write 1 to clear) registers are offset by one address from
691 s
->regs
[reg
- 1] &= ~data
;
694 case AST2600_RNG_DATA
:
695 case AST2600_SILICON_REV
:
696 case AST2600_SILICON_REV2
:
697 case AST2600_CHIP_ID0
:
698 case AST2600_CHIP_ID1
:
699 /* Add read only registers here */
700 qemu_log_mask(LOG_GUEST_ERROR
,
701 "%s: Write to read-only offset 0x%" HWADDR_PRIx
"\n",
709 static const MemoryRegionOps aspeed_ast2600_scu_ops
= {
710 .read
= aspeed_ast2600_scu_read
,
711 .write
= aspeed_ast2600_scu_write
,
712 .endianness
= DEVICE_LITTLE_ENDIAN
,
713 .valid
.min_access_size
= 4,
714 .valid
.max_access_size
= 4,
715 .valid
.unaligned
= false,
718 static const uint32_t ast2600_a3_resets
[ASPEED_AST2600_SCU_NR_REGS
] = {
719 [AST2600_SYS_RST_CTRL
] = 0xF7C3FED8,
720 [AST2600_SYS_RST_CTRL2
] = 0x0DFFFFFC,
721 [AST2600_CLK_STOP_CTRL
] = 0xFFFF7F8A,
722 [AST2600_CLK_STOP_CTRL2
] = 0xFFF0FFF0,
723 [AST2600_DEBUG_CTRL
] = 0x00000FFF,
724 [AST2600_DEBUG_CTRL2
] = 0x000000FF,
725 [AST2600_SDRAM_HANDSHAKE
] = 0x00000000,
726 [AST2600_HPLL_PARAM
] = 0x1000408F,
727 [AST2600_APLL_PARAM
] = 0x1000405F,
728 [AST2600_MPLL_PARAM
] = 0x1008405F,
729 [AST2600_EPLL_PARAM
] = 0x1004077F,
730 [AST2600_DPLL_PARAM
] = 0x1078405F,
731 [AST2600_CLK_SEL
] = 0xF3940000,
732 [AST2600_CLK_SEL2
] = 0x00700000,
733 [AST2600_CLK_SEL3
] = 0x00000000,
734 [AST2600_CLK_SEL4
] = 0xF3F40000,
735 [AST2600_CLK_SEL5
] = 0x30000000,
736 [AST2600_UARTCLK
] = 0x00014506,
737 [AST2600_HUARTCLK
] = 0x000145C0,
738 [AST2600_CHIP_ID0
] = 0x1234ABCD,
739 [AST2600_CHIP_ID1
] = 0x88884444,
742 static void aspeed_ast2600_scu_reset(DeviceState
*dev
)
744 AspeedSCUState
*s
= ASPEED_SCU(dev
);
745 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(dev
);
747 memcpy(s
->regs
, asc
->resets
, asc
->nr_regs
* 4);
750 * A0 reports A0 in _REV, but subsequent revisions report A1 regardless
751 * of actual revision. QEMU and Linux only support A1 onwards so this is
754 s
->regs
[AST2600_SILICON_REV
] = AST2600_A3_SILICON_REV
;
755 s
->regs
[AST2600_SILICON_REV2
] = s
->silicon_rev
;
756 s
->regs
[AST2600_HW_STRAP1
] = s
->hw_strap1
;
757 s
->regs
[AST2600_HW_STRAP2
] = s
->hw_strap2
;
758 s
->regs
[PROT_KEY
] = s
->hw_prot_key
;
761 static void aspeed_2600_scu_class_init(ObjectClass
*klass
, void *data
)
763 DeviceClass
*dc
= DEVICE_CLASS(klass
);
764 AspeedSCUClass
*asc
= ASPEED_SCU_CLASS(klass
);
766 dc
->desc
= "ASPEED 2600 System Control Unit";
767 dc
->reset
= aspeed_ast2600_scu_reset
;
768 asc
->resets
= ast2600_a3_resets
;
769 asc
->calc_hpll
= aspeed_2600_scu_calc_hpll
;
770 asc
->get_apb
= aspeed_2600_scu_get_apb_freq
;
771 asc
->apb_divider
= 4;
772 asc
->nr_regs
= ASPEED_AST2600_SCU_NR_REGS
;
773 asc
->clkin_25Mhz
= true;
774 asc
->ops
= &aspeed_ast2600_scu_ops
;
777 static const TypeInfo aspeed_2600_scu_info
= {
778 .name
= TYPE_ASPEED_2600_SCU
,
779 .parent
= TYPE_ASPEED_SCU
,
780 .instance_size
= sizeof(AspeedSCUState
),
781 .class_init
= aspeed_2600_scu_class_init
,
784 static const uint32_t ast1030_a1_resets
[ASPEED_AST2600_SCU_NR_REGS
] = {
785 [AST2600_SYS_RST_CTRL
] = 0xFFC3FED8,
786 [AST2600_SYS_RST_CTRL2
] = 0x09FFFFFC,
787 [AST2600_CLK_STOP_CTRL
] = 0xFFFF7F8A,
788 [AST2600_CLK_STOP_CTRL2
] = 0xFFF0FFF0,
789 [AST2600_DEBUG_CTRL2
] = 0x00000000,
790 [AST2600_HPLL_PARAM
] = 0x10004077,
791 [AST2600_HPLL_EXT
] = 0x00000031,
792 [AST2600_CLK_SEL4
] = 0x43F90900,
793 [AST2600_CLK_SEL5
] = 0x40000000,
794 [AST2600_CHIP_ID0
] = 0xDEADBEEF,
795 [AST2600_CHIP_ID1
] = 0x0BADCAFE,
798 static void aspeed_ast1030_scu_reset(DeviceState
*dev
)
800 AspeedSCUState
*s
= ASPEED_SCU(dev
);
801 AspeedSCUClass
*asc
= ASPEED_SCU_GET_CLASS(dev
);
803 memcpy(s
->regs
, asc
->resets
, asc
->nr_regs
* 4);
805 s
->regs
[AST2600_SILICON_REV
] = AST1030_A1_SILICON_REV
;
806 s
->regs
[AST2600_SILICON_REV2
] = s
->silicon_rev
;
807 s
->regs
[AST2600_HW_STRAP1
] = s
->hw_strap1
;
808 s
->regs
[AST2600_HW_STRAP2
] = s
->hw_strap2
;
809 s
->regs
[PROT_KEY
] = s
->hw_prot_key
;
812 static void aspeed_1030_scu_class_init(ObjectClass
*klass
, void *data
)
814 DeviceClass
*dc
= DEVICE_CLASS(klass
);
815 AspeedSCUClass
*asc
= ASPEED_SCU_CLASS(klass
);
817 dc
->desc
= "ASPEED 1030 System Control Unit";
818 dc
->reset
= aspeed_ast1030_scu_reset
;
819 asc
->resets
= ast1030_a1_resets
;
820 asc
->calc_hpll
= aspeed_2600_scu_calc_hpll
;
821 asc
->get_apb
= aspeed_1030_scu_get_apb_freq
;
822 asc
->apb_divider
= 2;
823 asc
->nr_regs
= ASPEED_AST2600_SCU_NR_REGS
;
824 asc
->clkin_25Mhz
= true;
825 asc
->ops
= &aspeed_ast2600_scu_ops
;
828 static const TypeInfo aspeed_1030_scu_info
= {
829 .name
= TYPE_ASPEED_1030_SCU
,
830 .parent
= TYPE_ASPEED_SCU
,
831 .instance_size
= sizeof(AspeedSCUState
),
832 .class_init
= aspeed_1030_scu_class_init
,
835 static void aspeed_scu_register_types(void)
837 type_register_static(&aspeed_scu_info
);
838 type_register_static(&aspeed_2400_scu_info
);
839 type_register_static(&aspeed_2500_scu_info
);
840 type_register_static(&aspeed_2600_scu_info
);
841 type_register_static(&aspeed_1030_scu_info
);
844 type_init(aspeed_scu_register_types
);