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target/arm: Use isar_feature_aa32_simd_r32 more places
[qemu/ar7.git] / target / arm / helper.c
blob79db169e0469e25a296f635cfd1132ca445f5f4c
1 /*
2 * ARM generic helpers.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
12 #include "trace.h"
13 #include "cpu.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
24 #include "hw/irq.h"
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/tcg.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
33 #ifdef CONFIG_TCG
34 #include "arm_ldst.h"
35 #include "exec/cpu_ldst.h"
36 #endif
37
38 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
39
40 #ifndef CONFIG_USER_ONLY
41
42 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
43 MMUAccessType access_type, ARMMMUIdx mmu_idx,
44 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
45 target_ulong *page_size_ptr,
46 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
47 #endif
48
49 static void switch_mode(CPUARMState *env, int mode);
50
51 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
52 {
53 ARMCPU *cpu = env_archcpu(env);
54 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
55
56 /* VFP data registers are always little-endian. */
57 if (reg < nregs) {
58 stq_le_p(buf, *aa32_vfp_dreg(env, reg));
59 return 8;
60 }
61 if (arm_feature(env, ARM_FEATURE_NEON)) {
62 /* Aliases for Q regs. */
63 nregs += 16;
64 if (reg < nregs) {
65 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
66 stq_le_p(buf, q[0]);
67 stq_le_p(buf + 8, q[1]);
68 return 16;
69 }
70 }
71 switch (reg - nregs) {
72 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
73 case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
74 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
75 }
76 return 0;
77 }
78
79 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
80 {
81 ARMCPU *cpu = env_archcpu(env);
82 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
83
84 if (reg < nregs) {
85 *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
86 return 8;
87 }
88 if (arm_feature(env, ARM_FEATURE_NEON)) {
89 nregs += 16;
90 if (reg < nregs) {
91 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
92 q[0] = ldq_le_p(buf);
93 q[1] = ldq_le_p(buf + 8);
94 return 16;
95 }
96 }
97 switch (reg - nregs) {
98 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
99 case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
100 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
101 }
102 return 0;
103 }
104
105 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
106 {
107 switch (reg) {
108 case 0 ... 31:
109 /* 128 bit FP register */
110 {
111 uint64_t *q = aa64_vfp_qreg(env, reg);
112 stq_le_p(buf, q[0]);
113 stq_le_p(buf + 8, q[1]);
114 return 16;
115 }
116 case 32:
117 /* FPSR */
118 stl_p(buf, vfp_get_fpsr(env));
119 return 4;
120 case 33:
121 /* FPCR */
122 stl_p(buf, vfp_get_fpcr(env));
123 return 4;
124 default:
125 return 0;
126 }
127 }
128
129 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
130 {
131 switch (reg) {
132 case 0 ... 31:
133 /* 128 bit FP register */
134 {
135 uint64_t *q = aa64_vfp_qreg(env, reg);
136 q[0] = ldq_le_p(buf);
137 q[1] = ldq_le_p(buf + 8);
138 return 16;
139 }
140 case 32:
141 /* FPSR */
142 vfp_set_fpsr(env, ldl_p(buf));
143 return 4;
144 case 33:
145 /* FPCR */
146 vfp_set_fpcr(env, ldl_p(buf));
147 return 4;
148 default:
149 return 0;
150 }
151 }
152
153 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
154 {
155 assert(ri->fieldoffset);
156 if (cpreg_field_is_64bit(ri)) {
157 return CPREG_FIELD64(env, ri);
158 } else {
159 return CPREG_FIELD32(env, ri);
160 }
161 }
162
163 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
164 uint64_t value)
165 {
166 assert(ri->fieldoffset);
167 if (cpreg_field_is_64bit(ri)) {
168 CPREG_FIELD64(env, ri) = value;
169 } else {
170 CPREG_FIELD32(env, ri) = value;
171 }
172 }
173
174 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
175 {
176 return (char *)env + ri->fieldoffset;
177 }
178
179 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
180 {
181 /* Raw read of a coprocessor register (as needed for migration, etc). */
182 if (ri->type & ARM_CP_CONST) {
183 return ri->resetvalue;
184 } else if (ri->raw_readfn) {
185 return ri->raw_readfn(env, ri);
186 } else if (ri->readfn) {
187 return ri->readfn(env, ri);
188 } else {
189 return raw_read(env, ri);
190 }
191 }
192
193 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
194 uint64_t v)
195 {
196 /* Raw write of a coprocessor register (as needed for migration, etc).
197 * Note that constant registers are treated as write-ignored; the
198 * caller should check for success by whether a readback gives the
199 * value written.
200 */
201 if (ri->type & ARM_CP_CONST) {
202 return;
203 } else if (ri->raw_writefn) {
204 ri->raw_writefn(env, ri, v);
205 } else if (ri->writefn) {
206 ri->writefn(env, ri, v);
207 } else {
208 raw_write(env, ri, v);
209 }
210 }
211
212 static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg)
213 {
214 ARMCPU *cpu = env_archcpu(env);
215 const ARMCPRegInfo *ri;
216 uint32_t key;
217
218 key = cpu->dyn_xml.cpregs_keys[reg];
219 ri = get_arm_cp_reginfo(cpu->cp_regs, key);
220 if (ri) {
221 if (cpreg_field_is_64bit(ri)) {
222 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
223 } else {
224 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
225 }
226 }
227 return 0;
228 }
229
230 static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
231 {
232 return 0;
233 }
234
235 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
236 {
237 /* Return true if the regdef would cause an assertion if you called
238 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
239 * program bug for it not to have the NO_RAW flag).
240 * NB that returning false here doesn't necessarily mean that calling
241 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
242 * read/write access functions which are safe for raw use" from "has
243 * read/write access functions which have side effects but has forgotten
244 * to provide raw access functions".
245 * The tests here line up with the conditions in read/write_raw_cp_reg()
246 * and assertions in raw_read()/raw_write().
247 */
248 if ((ri->type & ARM_CP_CONST) ||
249 ri->fieldoffset ||
250 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
251 return false;
252 }
253 return true;
254 }
255
256 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
257 {
258 /* Write the coprocessor state from cpu->env to the (index,value) list. */
259 int i;
260 bool ok = true;
261
262 for (i = 0; i < cpu->cpreg_array_len; i++) {
263 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
264 const ARMCPRegInfo *ri;
265 uint64_t newval;
266
267 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
268 if (!ri) {
269 ok = false;
270 continue;
271 }
272 if (ri->type & ARM_CP_NO_RAW) {
273 continue;
274 }
275
276 newval = read_raw_cp_reg(&cpu->env, ri);
277 if (kvm_sync) {
278 /*
279 * Only sync if the previous list->cpustate sync succeeded.
280 * Rather than tracking the success/failure state for every
281 * item in the list, we just recheck "does the raw write we must
282 * have made in write_list_to_cpustate() read back OK" here.
283 */
284 uint64_t oldval = cpu->cpreg_values[i];
285
286 if (oldval == newval) {
287 continue;
288 }
289
290 write_raw_cp_reg(&cpu->env, ri, oldval);
291 if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
292 continue;
293 }
294
295 write_raw_cp_reg(&cpu->env, ri, newval);
296 }
297 cpu->cpreg_values[i] = newval;
298 }
299 return ok;
300 }
301
302 bool write_list_to_cpustate(ARMCPU *cpu)
303 {
304 int i;
305 bool ok = true;
306
307 for (i = 0; i < cpu->cpreg_array_len; i++) {
308 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
309 uint64_t v = cpu->cpreg_values[i];
310 const ARMCPRegInfo *ri;
311
312 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
313 if (!ri) {
314 ok = false;
315 continue;
316 }
317 if (ri->type & ARM_CP_NO_RAW) {
318 continue;
319 }
320 /* Write value and confirm it reads back as written
321 * (to catch read-only registers and partially read-only
322 * registers where the incoming migration value doesn't match)
323 */
324 write_raw_cp_reg(&cpu->env, ri, v);
325 if (read_raw_cp_reg(&cpu->env, ri) != v) {
326 ok = false;
327 }
328 }
329 return ok;
330 }
331
332 static void add_cpreg_to_list(gpointer key, gpointer opaque)
333 {
334 ARMCPU *cpu = opaque;
335 uint64_t regidx;
336 const ARMCPRegInfo *ri;
337
338 regidx = *(uint32_t *)key;
339 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
340
341 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
342 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
343 /* The value array need not be initialized at this point */
344 cpu->cpreg_array_len++;
345 }
346 }
347
348 static void count_cpreg(gpointer key, gpointer opaque)
349 {
350 ARMCPU *cpu = opaque;
351 uint64_t regidx;
352 const ARMCPRegInfo *ri;
353
354 regidx = *(uint32_t *)key;
355 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
356
357 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
358 cpu->cpreg_array_len++;
359 }
360 }
361
362 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
363 {
364 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
365 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
366
367 if (aidx > bidx) {
368 return 1;
369 }
370 if (aidx < bidx) {
371 return -1;
372 }
373 return 0;
374 }
375
376 void init_cpreg_list(ARMCPU *cpu)
377 {
378 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
379 * Note that we require cpreg_tuples[] to be sorted by key ID.
380 */
381 GList *keys;
382 int arraylen;
383
384 keys = g_hash_table_get_keys(cpu->cp_regs);
385 keys = g_list_sort(keys, cpreg_key_compare);
386
387 cpu->cpreg_array_len = 0;
388
389 g_list_foreach(keys, count_cpreg, cpu);
390
391 arraylen = cpu->cpreg_array_len;
392 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
393 cpu->cpreg_values = g_new(uint64_t, arraylen);
394 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
395 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
396 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
397 cpu->cpreg_array_len = 0;
398
399 g_list_foreach(keys, add_cpreg_to_list, cpu);
400
401 assert(cpu->cpreg_array_len == arraylen);
402
403 g_list_free(keys);
404 }
405
406 /*
407 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
408 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
409 *
410 * access_el3_aa32ns: Used to check AArch32 register views.
411 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
412 */
413 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
414 const ARMCPRegInfo *ri,
415 bool isread)
416 {
417 bool secure = arm_is_secure_below_el3(env);
418
419 assert(!arm_el_is_aa64(env, 3));
420 if (secure) {
421 return CP_ACCESS_TRAP_UNCATEGORIZED;
422 }
423 return CP_ACCESS_OK;
424 }
425
426 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
427 const ARMCPRegInfo *ri,
428 bool isread)
429 {
430 if (!arm_el_is_aa64(env, 3)) {
431 return access_el3_aa32ns(env, ri, isread);
432 }
433 return CP_ACCESS_OK;
434 }
435
436 /* Some secure-only AArch32 registers trap to EL3 if used from
437 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
438 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
439 * We assume that the .access field is set to PL1_RW.
440 */
441 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
442 const ARMCPRegInfo *ri,
443 bool isread)
444 {
445 if (arm_current_el(env) == 3) {
446 return CP_ACCESS_OK;
447 }
448 if (arm_is_secure_below_el3(env)) {
449 return CP_ACCESS_TRAP_EL3;
450 }
451 /* This will be EL1 NS and EL2 NS, which just UNDEF */
452 return CP_ACCESS_TRAP_UNCATEGORIZED;
453 }
454
455 /* Check for traps to "powerdown debug" registers, which are controlled
456 * by MDCR.TDOSA
457 */
458 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
459 bool isread)
460 {
461 int el = arm_current_el(env);
462 bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
463 (env->cp15.mdcr_el2 & MDCR_TDE) ||
464 (arm_hcr_el2_eff(env) & HCR_TGE);
465
466 if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
467 return CP_ACCESS_TRAP_EL2;
468 }
469 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
470 return CP_ACCESS_TRAP_EL3;
471 }
472 return CP_ACCESS_OK;
473 }
474
475 /* Check for traps to "debug ROM" registers, which are controlled
476 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
477 */
478 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
479 bool isread)
480 {
481 int el = arm_current_el(env);
482 bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
483 (env->cp15.mdcr_el2 & MDCR_TDE) ||
484 (arm_hcr_el2_eff(env) & HCR_TGE);
485
486 if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
487 return CP_ACCESS_TRAP_EL2;
488 }
489 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
490 return CP_ACCESS_TRAP_EL3;
491 }
492 return CP_ACCESS_OK;
493 }
494
495 /* Check for traps to general debug registers, which are controlled
496 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
497 */
498 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
499 bool isread)
500 {
501 int el = arm_current_el(env);
502 bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
503 (env->cp15.mdcr_el2 & MDCR_TDE) ||
504 (arm_hcr_el2_eff(env) & HCR_TGE);
505
506 if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
507 return CP_ACCESS_TRAP_EL2;
508 }
509 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
510 return CP_ACCESS_TRAP_EL3;
511 }
512 return CP_ACCESS_OK;
513 }
514
515 /* Check for traps to performance monitor registers, which are controlled
516 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
517 */
518 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
519 bool isread)
520 {
521 int el = arm_current_el(env);
522
523 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
524 && !arm_is_secure_below_el3(env)) {
525 return CP_ACCESS_TRAP_EL2;
526 }
527 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
528 return CP_ACCESS_TRAP_EL3;
529 }
530 return CP_ACCESS_OK;
531 }
532
533 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
534 {
535 ARMCPU *cpu = env_archcpu(env);
536
537 raw_write(env, ri, value);
538 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
539 }
540
541 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
542 {
543 ARMCPU *cpu = env_archcpu(env);
544
545 if (raw_read(env, ri) != value) {
546 /* Unlike real hardware the qemu TLB uses virtual addresses,
547 * not modified virtual addresses, so this causes a TLB flush.
548 */
549 tlb_flush(CPU(cpu));
550 raw_write(env, ri, value);
551 }
552 }
553
554 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
555 uint64_t value)
556 {
557 ARMCPU *cpu = env_archcpu(env);
558
559 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
560 && !extended_addresses_enabled(env)) {
561 /* For VMSA (when not using the LPAE long descriptor page table
562 * format) this register includes the ASID, so do a TLB flush.
563 * For PMSA it is purely a process ID and no action is needed.
564 */
565 tlb_flush(CPU(cpu));
566 }
567 raw_write(env, ri, value);
568 }
569
570 /* IS variants of TLB operations must affect all cores */
571 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
572 uint64_t value)
573 {
574 CPUState *cs = env_cpu(env);
575
576 tlb_flush_all_cpus_synced(cs);
577 }
578
579 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
580 uint64_t value)
581 {
582 CPUState *cs = env_cpu(env);
583
584 tlb_flush_all_cpus_synced(cs);
585 }
586
587 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
588 uint64_t value)
589 {
590 CPUState *cs = env_cpu(env);
591
592 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
593 }
594
595 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
596 uint64_t value)
597 {
598 CPUState *cs = env_cpu(env);
599
600 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
601 }
602
603 /*
604 * Non-IS variants of TLB operations are upgraded to
605 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
606 * force broadcast of these operations.
607 */
608 static bool tlb_force_broadcast(CPUARMState *env)
609 {
610 return (env->cp15.hcr_el2 & HCR_FB) &&
611 arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
612 }
613
614 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
615 uint64_t value)
616 {
617 /* Invalidate all (TLBIALL) */
618 CPUState *cs = env_cpu(env);
619
620 if (tlb_force_broadcast(env)) {
621 tlb_flush_all_cpus_synced(cs);
622 } else {
623 tlb_flush(cs);
624 }
625 }
626
627 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
628 uint64_t value)
629 {
630 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
631 CPUState *cs = env_cpu(env);
632
633 value &= TARGET_PAGE_MASK;
634 if (tlb_force_broadcast(env)) {
635 tlb_flush_page_all_cpus_synced(cs, value);
636 } else {
637 tlb_flush_page(cs, value);
638 }
639 }
640
641 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
642 uint64_t value)
643 {
644 /* Invalidate by ASID (TLBIASID) */
645 CPUState *cs = env_cpu(env);
646
647 if (tlb_force_broadcast(env)) {
648 tlb_flush_all_cpus_synced(cs);
649 } else {
650 tlb_flush(cs);
651 }
652 }
653
654 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
655 uint64_t value)
656 {
657 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
658 CPUState *cs = env_cpu(env);
659
660 value &= TARGET_PAGE_MASK;
661 if (tlb_force_broadcast(env)) {
662 tlb_flush_page_all_cpus_synced(cs, value);
663 } else {
664 tlb_flush_page(cs, value);
665 }
666 }
667
668 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
669 uint64_t value)
670 {
671 CPUState *cs = env_cpu(env);
672
673 tlb_flush_by_mmuidx(cs,
674 ARMMMUIdxBit_E10_1 |
675 ARMMMUIdxBit_E10_1_PAN |
676 ARMMMUIdxBit_E10_0 |
677 ARMMMUIdxBit_Stage2);
678 }
679
680 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
681 uint64_t value)
682 {
683 CPUState *cs = env_cpu(env);
684
685 tlb_flush_by_mmuidx_all_cpus_synced(cs,
686 ARMMMUIdxBit_E10_1 |
687 ARMMMUIdxBit_E10_1_PAN |
688 ARMMMUIdxBit_E10_0 |
689 ARMMMUIdxBit_Stage2);
690 }
691
692 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
693 uint64_t value)
694 {
695 /* Invalidate by IPA. This has to invalidate any structures that
696 * contain only stage 2 translation information, but does not need
697 * to apply to structures that contain combined stage 1 and stage 2
698 * translation information.
699 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
700 */
701 CPUState *cs = env_cpu(env);
702 uint64_t pageaddr;
703
704 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
705 return;
706 }
707
708 pageaddr = sextract64(value << 12, 0, 40);
709
710 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
711 }
712
713 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
714 uint64_t value)
715 {
716 CPUState *cs = env_cpu(env);
717 uint64_t pageaddr;
718
719 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
720 return;
721 }
722
723 pageaddr = sextract64(value << 12, 0, 40);
724
725 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
726 ARMMMUIdxBit_Stage2);
727 }
728
729 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
730 uint64_t value)
731 {
732 CPUState *cs = env_cpu(env);
733
734 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
735 }
736
737 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
738 uint64_t value)
739 {
740 CPUState *cs = env_cpu(env);
741
742 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
743 }
744
745 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
746 uint64_t value)
747 {
748 CPUState *cs = env_cpu(env);
749 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
750
751 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
752 }
753
754 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
755 uint64_t value)
756 {
757 CPUState *cs = env_cpu(env);
758 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
759
760 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
761 ARMMMUIdxBit_E2);
762 }
763
764 static const ARMCPRegInfo cp_reginfo[] = {
765 /* Define the secure and non-secure FCSE identifier CP registers
766 * separately because there is no secure bank in V8 (no _EL3). This allows
767 * the secure register to be properly reset and migrated. There is also no
768 * v8 EL1 version of the register so the non-secure instance stands alone.
769 */
770 { .name = "FCSEIDR",
771 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
772 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
773 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
774 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
775 { .name = "FCSEIDR_S",
776 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
777 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
778 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
779 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
780 /* Define the secure and non-secure context identifier CP registers
781 * separately because there is no secure bank in V8 (no _EL3). This allows
782 * the secure register to be properly reset and migrated. In the
783 * non-secure case, the 32-bit register will have reset and migration
784 * disabled during registration as it is handled by the 64-bit instance.
785 */
786 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
787 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
788 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
789 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
790 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
791 { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
792 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
793 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
794 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
795 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
796 REGINFO_SENTINEL
797 };
798
799 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
800 /* NB: Some of these registers exist in v8 but with more precise
801 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
802 */
803 /* MMU Domain access control / MPU write buffer control */
804 { .name = "DACR",
805 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
806 .access = PL1_RW, .resetvalue = 0,
807 .writefn = dacr_write, .raw_writefn = raw_write,
808 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
809 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
810 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
811 * For v6 and v5, these mappings are overly broad.
812 */
813 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
814 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
815 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
816 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
817 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
818 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
819 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
820 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
821 /* Cache maintenance ops; some of this space may be overridden later. */
822 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
823 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
824 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
825 REGINFO_SENTINEL
826 };
827
828 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
829 /* Not all pre-v6 cores implemented this WFI, so this is slightly
830 * over-broad.
831 */
832 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
833 .access = PL1_W, .type = ARM_CP_WFI },
834 REGINFO_SENTINEL
835 };
836
837 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
838 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
839 * is UNPREDICTABLE; we choose to NOP as most implementations do).
840 */
841 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
842 .access = PL1_W, .type = ARM_CP_WFI },
843 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
844 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
845 * OMAPCP will override this space.
846 */
847 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
848 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
849 .resetvalue = 0 },
850 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
851 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
852 .resetvalue = 0 },
853 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
854 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
855 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
856 .resetvalue = 0 },
857 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
858 * implementing it as RAZ means the "debug architecture version" bits
859 * will read as a reserved value, which should cause Linux to not try
860 * to use the debug hardware.
861 */
862 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
863 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
864 /* MMU TLB control. Note that the wildcarding means we cover not just
865 * the unified TLB ops but also the dside/iside/inner-shareable variants.
866 */
867 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
868 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
869 .type = ARM_CP_NO_RAW },
870 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
871 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
872 .type = ARM_CP_NO_RAW },
873 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
874 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
875 .type = ARM_CP_NO_RAW },
876 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
877 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
878 .type = ARM_CP_NO_RAW },
879 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
880 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
881 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
882 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
883 REGINFO_SENTINEL
884 };
885
886 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
887 uint64_t value)
888 {
889 uint32_t mask = 0;
890
891 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
892 if (!arm_feature(env, ARM_FEATURE_V8)) {
893 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
894 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
895 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
896 */
897 if (arm_feature(env, ARM_FEATURE_VFP)) {
898 /* VFP coprocessor: cp10 & cp11 [23:20] */
899 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
900
901 if (!arm_feature(env, ARM_FEATURE_NEON)) {
902 /* ASEDIS [31] bit is RAO/WI */
903 value |= (1 << 31);
904 }
905
906 /* VFPv3 and upwards with NEON implement 32 double precision
907 * registers (D0-D31).
908 */
909 if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
910 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
911 value |= (1 << 30);
912 }
913 }
914 value &= mask;
915 }
916
917 /*
918 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
919 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
920 */
921 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
922 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
923 value &= ~(0xf << 20);
924 value |= env->cp15.cpacr_el1 & (0xf << 20);
925 }
926
927 env->cp15.cpacr_el1 = value;
928 }
929
930 static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
931 {
932 /*
933 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
934 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
935 */
936 uint64_t value = env->cp15.cpacr_el1;
937
938 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
939 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
940 value &= ~(0xf << 20);
941 }
942 return value;
943 }
944
945
946 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
947 {
948 /* Call cpacr_write() so that we reset with the correct RAO bits set
949 * for our CPU features.
950 */
951 cpacr_write(env, ri, 0);
952 }
953
954 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
955 bool isread)
956 {
957 if (arm_feature(env, ARM_FEATURE_V8)) {
958 /* Check if CPACR accesses are to be trapped to EL2 */
959 if (arm_current_el(env) == 1 &&
960 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
961 return CP_ACCESS_TRAP_EL2;
962 /* Check if CPACR accesses are to be trapped to EL3 */
963 } else if (arm_current_el(env) < 3 &&
964 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
965 return CP_ACCESS_TRAP_EL3;
966 }
967 }
968
969 return CP_ACCESS_OK;
970 }
971
972 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
973 bool isread)
974 {
975 /* Check if CPTR accesses are set to trap to EL3 */
976 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
977 return CP_ACCESS_TRAP_EL3;
978 }
979
980 return CP_ACCESS_OK;
981 }
982
983 static const ARMCPRegInfo v6_cp_reginfo[] = {
984 /* prefetch by MVA in v6, NOP in v7 */
985 { .name = "MVA_prefetch",
986 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
987 .access = PL1_W, .type = ARM_CP_NOP },
988 /* We need to break the TB after ISB to execute self-modifying code
989 * correctly and also to take any pending interrupts immediately.
990 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
991 */
992 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
993 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
994 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
995 .access = PL0_W, .type = ARM_CP_NOP },
996 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
997 .access = PL0_W, .type = ARM_CP_NOP },
998 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
999 .access = PL1_RW,
1000 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
1001 offsetof(CPUARMState, cp15.ifar_ns) },
1002 .resetvalue = 0, },
1003 /* Watchpoint Fault Address Register : should actually only be present
1004 * for 1136, 1176, 11MPCore.
1005 */
1006 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1007 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
1008 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
1009 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
1010 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
1011 .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
1012 REGINFO_SENTINEL
1013 };
1014
1015 /* Definitions for the PMU registers */
1016 #define PMCRN_MASK 0xf800
1017 #define PMCRN_SHIFT 11
1018 #define PMCRLC 0x40
1019 #define PMCRDP 0x20
1020 #define PMCRX 0x10
1021 #define PMCRD 0x8
1022 #define PMCRC 0x4
1023 #define PMCRP 0x2
1024 #define PMCRE 0x1
1025 /*
1026 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1027 * which can be written as 1 to trigger behaviour but which stay RAZ).
1028 */
1029 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1030
1031 #define PMXEVTYPER_P 0x80000000
1032 #define PMXEVTYPER_U 0x40000000
1033 #define PMXEVTYPER_NSK 0x20000000
1034 #define PMXEVTYPER_NSU 0x10000000
1035 #define PMXEVTYPER_NSH 0x08000000
1036 #define PMXEVTYPER_M 0x04000000
1037 #define PMXEVTYPER_MT 0x02000000
1038 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1039 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1040 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1041 PMXEVTYPER_M | PMXEVTYPER_MT | \
1042 PMXEVTYPER_EVTCOUNT)
1043
1044 #define PMCCFILTR 0xf8000000
1045 #define PMCCFILTR_M PMXEVTYPER_M
1046 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1047
1048 static inline uint32_t pmu_num_counters(CPUARMState *env)
1049 {
1050 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
1051 }
1052
1053 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1054 static inline uint64_t pmu_counter_mask(CPUARMState *env)
1055 {
1056 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
1057 }
1058
1059 typedef struct pm_event {
1060 uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
1061 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1062 bool (*supported)(CPUARMState *);
1063 /*
1064 * Retrieve the current count of the underlying event. The programmed
1065 * counters hold a difference from the return value from this function
1066 */
1067 uint64_t (*get_count)(CPUARMState *);
1068 /*
1069 * Return how many nanoseconds it will take (at a minimum) for count events
1070 * to occur. A negative value indicates the counter will never overflow, or
1071 * that the counter has otherwise arranged for the overflow bit to be set
1072 * and the PMU interrupt to be raised on overflow.
1073 */
1074 int64_t (*ns_per_count)(uint64_t);
1075 } pm_event;
1076
1077 static bool event_always_supported(CPUARMState *env)
1078 {
1079 return true;
1080 }
1081
1082 static uint64_t swinc_get_count(CPUARMState *env)
1083 {
1084 /*
1085 * SW_INCR events are written directly to the pmevcntr's by writes to
1086 * PMSWINC, so there is no underlying count maintained by the PMU itself
1087 */
1088 return 0;
1089 }
1090
1091 static int64_t swinc_ns_per(uint64_t ignored)
1092 {
1093 return -1;
1094 }
1095
1096 /*
1097 * Return the underlying cycle count for the PMU cycle counters. If we're in
1098 * usermode, simply return 0.
1099 */
1100 static uint64_t cycles_get_count(CPUARMState *env)
1101 {
1102 #ifndef CONFIG_USER_ONLY
1103 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1104 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1105 #else
1106 return cpu_get_host_ticks();
1107 #endif
1108 }
1109
1110 #ifndef CONFIG_USER_ONLY
1111 static int64_t cycles_ns_per(uint64_t cycles)
1112 {
1113 return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles;
1114 }
1115
1116 static bool instructions_supported(CPUARMState *env)
1117 {
1118 return use_icount == 1 /* Precise instruction counting */;
1119 }
1120
1121 static uint64_t instructions_get_count(CPUARMState *env)
1122 {
1123 return (uint64_t)cpu_get_icount_raw();
1124 }
1125
1126 static int64_t instructions_ns_per(uint64_t icount)
1127 {
1128 return cpu_icount_to_ns((int64_t)icount);
1129 }
1130 #endif
1131
1132 static bool pmu_8_1_events_supported(CPUARMState *env)
1133 {
1134 /* For events which are supported in any v8.1 PMU */
1135 return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
1136 }
1137
1138 static bool pmu_8_4_events_supported(CPUARMState *env)
1139 {
1140 /* For events which are supported in any v8.1 PMU */
1141 return cpu_isar_feature(any_pmu_8_4, env_archcpu(env));
1142 }
1143
1144 static uint64_t zero_event_get_count(CPUARMState *env)
1145 {
1146 /* For events which on QEMU never fire, so their count is always zero */
1147 return 0;
1148 }
1149
1150 static int64_t zero_event_ns_per(uint64_t cycles)
1151 {
1152 /* An event which never fires can never overflow */
1153 return -1;
1154 }
1155
1156 static const pm_event pm_events[] = {
1157 { .number = 0x000, /* SW_INCR */
1158 .supported = event_always_supported,
1159 .get_count = swinc_get_count,
1160 .ns_per_count = swinc_ns_per,
1161 },
1162 #ifndef CONFIG_USER_ONLY
1163 { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
1164 .supported = instructions_supported,
1165 .get_count = instructions_get_count,
1166 .ns_per_count = instructions_ns_per,
1167 },
1168 { .number = 0x011, /* CPU_CYCLES, Cycle */
1169 .supported = event_always_supported,
1170 .get_count = cycles_get_count,
1171 .ns_per_count = cycles_ns_per,
1172 },
1173 #endif
1174 { .number = 0x023, /* STALL_FRONTEND */
1175 .supported = pmu_8_1_events_supported,
1176 .get_count = zero_event_get_count,
1177 .ns_per_count = zero_event_ns_per,
1178 },
1179 { .number = 0x024, /* STALL_BACKEND */
1180 .supported = pmu_8_1_events_supported,
1181 .get_count = zero_event_get_count,
1182 .ns_per_count = zero_event_ns_per,
1183 },
1184 { .number = 0x03c, /* STALL */
1185 .supported = pmu_8_4_events_supported,
1186 .get_count = zero_event_get_count,
1187 .ns_per_count = zero_event_ns_per,
1188 },
1189 };
1190
1191 /*
1192 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1193 * events (i.e. the statistical profiling extension), this implementation
1194 * should first be updated to something sparse instead of the current
1195 * supported_event_map[] array.
1196 */
1197 #define MAX_EVENT_ID 0x3c
1198 #define UNSUPPORTED_EVENT UINT16_MAX
1199 static uint16_t supported_event_map[MAX_EVENT_ID + 1];
1200
1201 /*
1202 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1203 * of ARM event numbers to indices in our pm_events array.
1204 *
1205 * Note: Events in the 0x40XX range are not currently supported.
1206 */
1207 void pmu_init(ARMCPU *cpu)
1208 {
1209 unsigned int i;
1210
1211 /*
1212 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1213 * events to them
1214 */
1215 for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) {
1216 supported_event_map[i] = UNSUPPORTED_EVENT;
1217 }
1218 cpu->pmceid0 = 0;
1219 cpu->pmceid1 = 0;
1220
1221 for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
1222 const pm_event *cnt = &pm_events[i];
1223 assert(cnt->number <= MAX_EVENT_ID);
1224 /* We do not currently support events in the 0x40xx range */
1225 assert(cnt->number <= 0x3f);
1226
1227 if (cnt->supported(&cpu->env)) {
1228 supported_event_map[cnt->number] = i;
1229 uint64_t event_mask = 1ULL << (cnt->number & 0x1f);
1230 if (cnt->number & 0x20) {
1231 cpu->pmceid1 |= event_mask;
1232 } else {
1233 cpu->pmceid0 |= event_mask;
1234 }
1235 }
1236 }
1237 }
1238
1239 /*
1240 * Check at runtime whether a PMU event is supported for the current machine
1241 */
1242 static bool event_supported(uint16_t number)
1243 {
1244 if (number > MAX_EVENT_ID) {
1245 return false;
1246 }
1247 return supported_event_map[number] != UNSUPPORTED_EVENT;
1248 }
1249
1250 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
1251 bool isread)
1252 {
1253 /* Performance monitor registers user accessibility is controlled
1254 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1255 * trapping to EL2 or EL3 for other accesses.
1256 */
1257 int el = arm_current_el(env);
1258
1259 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
1260 return CP_ACCESS_TRAP;
1261 }
1262 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
1263 && !arm_is_secure_below_el3(env)) {
1264 return CP_ACCESS_TRAP_EL2;
1265 }
1266 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
1267 return CP_ACCESS_TRAP_EL3;
1268 }
1269
1270 return CP_ACCESS_OK;
1271 }
1272
1273 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
1274 const ARMCPRegInfo *ri,
1275 bool isread)
1276 {
1277 /* ER: event counter read trap control */
1278 if (arm_feature(env, ARM_FEATURE_V8)
1279 && arm_current_el(env) == 0
1280 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
1281 && isread) {
1282 return CP_ACCESS_OK;
1283 }
1284
1285 return pmreg_access(env, ri, isread);
1286 }
1287
1288 static CPAccessResult pmreg_access_swinc(CPUARMState *env,
1289 const ARMCPRegInfo *ri,
1290 bool isread)
1291 {
1292 /* SW: software increment write trap control */
1293 if (arm_feature(env, ARM_FEATURE_V8)
1294 && arm_current_el(env) == 0
1295 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
1296 && !isread) {
1297 return CP_ACCESS_OK;
1298 }
1299
1300 return pmreg_access(env, ri, isread);
1301 }
1302
1303 static CPAccessResult pmreg_access_selr(CPUARMState *env,
1304 const ARMCPRegInfo *ri,
1305 bool isread)
1306 {
1307 /* ER: event counter read trap control */
1308 if (arm_feature(env, ARM_FEATURE_V8)
1309 && arm_current_el(env) == 0
1310 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
1311 return CP_ACCESS_OK;
1312 }
1313
1314 return pmreg_access(env, ri, isread);
1315 }
1316
1317 static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
1318 const ARMCPRegInfo *ri,
1319 bool isread)
1320 {
1321 /* CR: cycle counter read trap control */
1322 if (arm_feature(env, ARM_FEATURE_V8)
1323 && arm_current_el(env) == 0
1324 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
1325 && isread) {
1326 return CP_ACCESS_OK;
1327 }
1328
1329 return pmreg_access(env, ri, isread);
1330 }
1331
1332 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1333 * the current EL, security state, and register configuration.
1334 */
1335 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
1336 {
1337 uint64_t filter;
1338 bool e, p, u, nsk, nsu, nsh, m;
1339 bool enabled, prohibited, filtered;
1340 bool secure = arm_is_secure(env);
1341 int el = arm_current_el(env);
1342 uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
1343
1344 if (!arm_feature(env, ARM_FEATURE_PMU)) {
1345 return false;
1346 }
1347
1348 if (!arm_feature(env, ARM_FEATURE_EL2) ||
1349 (counter < hpmn || counter == 31)) {
1350 e = env->cp15.c9_pmcr & PMCRE;
1351 } else {
1352 e = env->cp15.mdcr_el2 & MDCR_HPME;
1353 }
1354 enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
1355
1356 if (!secure) {
1357 if (el == 2 && (counter < hpmn || counter == 31)) {
1358 prohibited = env->cp15.mdcr_el2 & MDCR_HPMD;
1359 } else {
1360 prohibited = false;
1361 }
1362 } else {
1363 prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
1364 (env->cp15.mdcr_el3 & MDCR_SPME);
1365 }
1366
1367 if (prohibited && counter == 31) {
1368 prohibited = env->cp15.c9_pmcr & PMCRDP;
1369 }
1370
1371 if (counter == 31) {
1372 filter = env->cp15.pmccfiltr_el0;
1373 } else {
1374 filter = env->cp15.c14_pmevtyper[counter];
1375 }
1376
1377 p = filter & PMXEVTYPER_P;
1378 u = filter & PMXEVTYPER_U;
1379 nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK);
1380 nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU);
1381 nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH);
1382 m = arm_el_is_aa64(env, 1) &&
1383 arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M);
1384
1385 if (el == 0) {
1386 filtered = secure ? u : u != nsu;
1387 } else if (el == 1) {
1388 filtered = secure ? p : p != nsk;
1389 } else if (el == 2) {
1390 filtered = !nsh;
1391 } else { /* EL3 */
1392 filtered = m != p;
1393 }
1394
1395 if (counter != 31) {
1396 /*
1397 * If not checking PMCCNTR, ensure the counter is setup to an event we
1398 * support
1399 */
1400 uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
1401 if (!event_supported(event)) {
1402 return false;
1403 }
1404 }
1405
1406 return enabled && !prohibited && !filtered;
1407 }
1408
1409 static void pmu_update_irq(CPUARMState *env)
1410 {
1411 ARMCPU *cpu = env_archcpu(env);
1412 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
1413 (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
1414 }
1415
1416 /*
1417 * Ensure c15_ccnt is the guest-visible count so that operations such as
1418 * enabling/disabling the counter or filtering, modifying the count itself,
1419 * etc. can be done logically. This is essentially a no-op if the counter is
1420 * not enabled at the time of the call.
1421 */
1422 static void pmccntr_op_start(CPUARMState *env)
1423 {
1424 uint64_t cycles = cycles_get_count(env);
1425
1426 if (pmu_counter_enabled(env, 31)) {
1427 uint64_t eff_cycles = cycles;
1428 if (env->cp15.c9_pmcr & PMCRD) {
1429 /* Increment once every 64 processor clock cycles */
1430 eff_cycles /= 64;
1431 }
1432
1433 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta;
1434
1435 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
1436 1ull << 63 : 1ull << 31;
1437 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
1438 env->cp15.c9_pmovsr |= (1 << 31);
1439 pmu_update_irq(env);
1440 }
1441
1442 env->cp15.c15_ccnt = new_pmccntr;
1443 }
1444 env->cp15.c15_ccnt_delta = cycles;
1445 }
1446
1447 /*
1448 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1449 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1450 * pmccntr_op_start.
1451 */
1452 static void pmccntr_op_finish(CPUARMState *env)
1453 {
1454 if (pmu_counter_enabled(env, 31)) {
1455 #ifndef CONFIG_USER_ONLY
1456 /* Calculate when the counter will next overflow */
1457 uint64_t remaining_cycles = -env->cp15.c15_ccnt;
1458 if (!(env->cp15.c9_pmcr & PMCRLC)) {
1459 remaining_cycles = (uint32_t)remaining_cycles;
1460 }
1461 int64_t overflow_in = cycles_ns_per(remaining_cycles);
1462
1463 if (overflow_in > 0) {
1464 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1465 overflow_in;
1466 ARMCPU *cpu = env_archcpu(env);
1467 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1468 }
1469 #endif
1470
1471 uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
1472 if (env->cp15.c9_pmcr & PMCRD) {
1473 /* Increment once every 64 processor clock cycles */
1474 prev_cycles /= 64;
1475 }
1476 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;
1477 }
1478 }
1479
1480 static void pmevcntr_op_start(CPUARMState *env, uint8_t counter)
1481 {
1482
1483 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1484 uint64_t count = 0;
1485 if (event_supported(event)) {
1486 uint16_t event_idx = supported_event_map[event];
1487 count = pm_events[event_idx].get_count(env);
1488 }
1489
1490 if (pmu_counter_enabled(env, counter)) {
1491 uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter];
1492
1493 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) {
1494 env->cp15.c9_pmovsr |= (1 << counter);
1495 pmu_update_irq(env);
1496 }
1497 env->cp15.c14_pmevcntr[counter] = new_pmevcntr;
1498 }
1499 env->cp15.c14_pmevcntr_delta[counter] = count;
1500 }
1501
1502 static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
1503 {
1504 if (pmu_counter_enabled(env, counter)) {
1505 #ifndef CONFIG_USER_ONLY
1506 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1507 uint16_t event_idx = supported_event_map[event];
1508 uint64_t delta = UINT32_MAX -
1509 (uint32_t)env->cp15.c14_pmevcntr[counter] + 1;
1510 int64_t overflow_in = pm_events[event_idx].ns_per_count(delta);
1511
1512 if (overflow_in > 0) {
1513 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1514 overflow_in;
1515 ARMCPU *cpu = env_archcpu(env);
1516 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1517 }
1518 #endif
1519
1520 env->cp15.c14_pmevcntr_delta[counter] -=
1521 env->cp15.c14_pmevcntr[counter];
1522 }
1523 }
1524
1525 void pmu_op_start(CPUARMState *env)
1526 {
1527 unsigned int i;
1528 pmccntr_op_start(env);
1529 for (i = 0; i < pmu_num_counters(env); i++) {
1530 pmevcntr_op_start(env, i);
1531 }
1532 }
1533
1534 void pmu_op_finish(CPUARMState *env)
1535 {
1536 unsigned int i;
1537 pmccntr_op_finish(env);
1538 for (i = 0; i < pmu_num_counters(env); i++) {
1539 pmevcntr_op_finish(env, i);
1540 }
1541 }
1542
1543 void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
1544 {
1545 pmu_op_start(&cpu->env);
1546 }
1547
1548 void pmu_post_el_change(ARMCPU *cpu, void *ignored)
1549 {
1550 pmu_op_finish(&cpu->env);
1551 }
1552
1553 void arm_pmu_timer_cb(void *opaque)
1554 {
1555 ARMCPU *cpu = opaque;
1556
1557 /*
1558 * Update all the counter values based on the current underlying counts,
1559 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1560 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1561 * counter may expire.
1562 */
1563 pmu_op_start(&cpu->env);
1564 pmu_op_finish(&cpu->env);
1565 }
1566
1567 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1568 uint64_t value)
1569 {
1570 pmu_op_start(env);
1571
1572 if (value & PMCRC) {
1573 /* The counter has been reset */
1574 env->cp15.c15_ccnt = 0;
1575 }
1576
1577 if (value & PMCRP) {
1578 unsigned int i;
1579 for (i = 0; i < pmu_num_counters(env); i++) {
1580 env->cp15.c14_pmevcntr[i] = 0;
1581 }
1582 }
1583
1584 env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
1585 env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
1586
1587 pmu_op_finish(env);
1588 }
1589
1590 static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri,
1591 uint64_t value)
1592 {
1593 unsigned int i;
1594 for (i = 0; i < pmu_num_counters(env); i++) {
1595 /* Increment a counter's count iff: */
1596 if ((value & (1 << i)) && /* counter's bit is set */
1597 /* counter is enabled and not filtered */
1598 pmu_counter_enabled(env, i) &&
1599 /* counter is SW_INCR */
1600 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
1601 pmevcntr_op_start(env, i);
1602
1603 /*
1604 * Detect if this write causes an overflow since we can't predict
1605 * PMSWINC overflows like we can for other events
1606 */
1607 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
1608
1609 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
1610 env->cp15.c9_pmovsr |= (1 << i);
1611 pmu_update_irq(env);
1612 }
1613
1614 env->cp15.c14_pmevcntr[i] = new_pmswinc;
1615
1616 pmevcntr_op_finish(env, i);
1617 }
1618 }
1619 }
1620
1621 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1622 {
1623 uint64_t ret;
1624 pmccntr_op_start(env);
1625 ret = env->cp15.c15_ccnt;
1626 pmccntr_op_finish(env);
1627 return ret;
1628 }
1629
1630 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1631 uint64_t value)
1632 {
1633 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1634 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1635 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1636 * accessed.
1637 */
1638 env->cp15.c9_pmselr = value & 0x1f;
1639 }
1640
1641 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1642 uint64_t value)
1643 {
1644 pmccntr_op_start(env);
1645 env->cp15.c15_ccnt = value;
1646 pmccntr_op_finish(env);
1647 }
1648
1649 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
1650 uint64_t value)
1651 {
1652 uint64_t cur_val = pmccntr_read(env, NULL);
1653
1654 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
1655 }
1656
1657 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1658 uint64_t value)
1659 {
1660 pmccntr_op_start(env);
1661 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0;
1662 pmccntr_op_finish(env);
1663 }
1664
1665 static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
1666 uint64_t value)
1667 {
1668 pmccntr_op_start(env);
1669 /* M is not accessible from AArch32 */
1670 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) |
1671 (value & PMCCFILTR);
1672 pmccntr_op_finish(env);
1673 }
1674
1675 static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
1676 {
1677 /* M is not visible in AArch32 */
1678 return env->cp15.pmccfiltr_el0 & PMCCFILTR;
1679 }
1680
1681 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1682 uint64_t value)
1683 {
1684 value &= pmu_counter_mask(env);
1685 env->cp15.c9_pmcnten |= value;
1686 }
1687
1688 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1689 uint64_t value)
1690 {
1691 value &= pmu_counter_mask(env);
1692 env->cp15.c9_pmcnten &= ~value;
1693 }
1694
1695 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1696 uint64_t value)
1697 {
1698 value &= pmu_counter_mask(env);
1699 env->cp15.c9_pmovsr &= ~value;
1700 pmu_update_irq(env);
1701 }
1702
1703 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1704 uint64_t value)
1705 {
1706 value &= pmu_counter_mask(env);
1707 env->cp15.c9_pmovsr |= value;
1708 pmu_update_irq(env);
1709 }
1710
1711 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1712 uint64_t value, const uint8_t counter)
1713 {
1714 if (counter == 31) {
1715 pmccfiltr_write(env, ri, value);
1716 } else if (counter < pmu_num_counters(env)) {
1717 pmevcntr_op_start(env, counter);
1718
1719 /*
1720 * If this counter's event type is changing, store the current
1721 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1722 * pmevcntr_op_finish has the correct baseline when it converts back to
1723 * a delta.
1724 */
1725 uint16_t old_event = env->cp15.c14_pmevtyper[counter] &
1726 PMXEVTYPER_EVTCOUNT;
1727 uint16_t new_event = value & PMXEVTYPER_EVTCOUNT;
1728 if (old_event != new_event) {
1729 uint64_t count = 0;
1730 if (event_supported(new_event)) {
1731 uint16_t event_idx = supported_event_map[new_event];
1732 count = pm_events[event_idx].get_count(env);
1733 }
1734 env->cp15.c14_pmevcntr_delta[counter] = count;
1735 }
1736
1737 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
1738 pmevcntr_op_finish(env, counter);
1739 }
1740 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1741 * PMSELR value is equal to or greater than the number of implemented
1742 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1743 */
1744 }
1745
1746 static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri,
1747 const uint8_t counter)
1748 {
1749 if (counter == 31) {
1750 return env->cp15.pmccfiltr_el0;
1751 } else if (counter < pmu_num_counters(env)) {
1752 return env->cp15.c14_pmevtyper[counter];
1753 } else {
1754 /*
1755 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1756 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1757 */
1758 return 0;
1759 }
1760 }
1761
1762 static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1763 uint64_t value)
1764 {
1765 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1766 pmevtyper_write(env, ri, value, counter);
1767 }
1768
1769 static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1770 uint64_t value)
1771 {
1772 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1773 env->cp15.c14_pmevtyper[counter] = value;
1774
1775 /*
1776 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1777 * pmu_op_finish calls when loading saved state for a migration. Because
1778 * we're potentially updating the type of event here, the value written to
1779 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1780 * different counter type. Therefore, we need to set this value to the
1781 * current count for the counter type we're writing so that pmu_op_finish
1782 * has the correct count for its calculation.
1783 */
1784 uint16_t event = value & PMXEVTYPER_EVTCOUNT;
1785 if (event_supported(event)) {
1786 uint16_t event_idx = supported_event_map[event];
1787 env->cp15.c14_pmevcntr_delta[counter] =
1788 pm_events[event_idx].get_count(env);
1789 }
1790 }
1791
1792 static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1793 {
1794 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1795 return pmevtyper_read(env, ri, counter);
1796 }
1797
1798 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1799 uint64_t value)
1800 {
1801 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31);
1802 }
1803
1804 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
1805 {
1806 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31);
1807 }
1808
1809 static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1810 uint64_t value, uint8_t counter)
1811 {
1812 if (counter < pmu_num_counters(env)) {
1813 pmevcntr_op_start(env, counter);
1814 env->cp15.c14_pmevcntr[counter] = value;
1815 pmevcntr_op_finish(env, counter);
1816 }
1817 /*
1818 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1819 * are CONSTRAINED UNPREDICTABLE.
1820 */
1821 }
1822
1823 static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1824 uint8_t counter)
1825 {
1826 if (counter < pmu_num_counters(env)) {
1827 uint64_t ret;
1828 pmevcntr_op_start(env, counter);
1829 ret = env->cp15.c14_pmevcntr[counter];
1830 pmevcntr_op_finish(env, counter);
1831 return ret;
1832 } else {
1833 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1834 * are CONSTRAINED UNPREDICTABLE. */
1835 return 0;
1836 }
1837 }
1838
1839 static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1840 uint64_t value)
1841 {
1842 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1843 pmevcntr_write(env, ri, value, counter);
1844 }
1845
1846 static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1847 {
1848 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1849 return pmevcntr_read(env, ri, counter);
1850 }
1851
1852 static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1853 uint64_t value)
1854 {
1855 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1856 assert(counter < pmu_num_counters(env));
1857 env->cp15.c14_pmevcntr[counter] = value;
1858 pmevcntr_write(env, ri, value, counter);
1859 }
1860
1861 static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri)
1862 {
1863 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1864 assert(counter < pmu_num_counters(env));
1865 return env->cp15.c14_pmevcntr[counter];
1866 }
1867
1868 static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1869 uint64_t value)
1870 {
1871 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31);
1872 }
1873
1874 static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1875 {
1876 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31);
1877 }
1878
1879 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1880 uint64_t value)
1881 {
1882 if (arm_feature(env, ARM_FEATURE_V8)) {
1883 env->cp15.c9_pmuserenr = value & 0xf;
1884 } else {
1885 env->cp15.c9_pmuserenr = value & 1;
1886 }
1887 }
1888
1889 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1890 uint64_t value)
1891 {
1892 /* We have no event counters so only the C bit can be changed */
1893 value &= pmu_counter_mask(env);
1894 env->cp15.c9_pminten |= value;
1895 pmu_update_irq(env);
1896 }
1897
1898 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1899 uint64_t value)
1900 {
1901 value &= pmu_counter_mask(env);
1902 env->cp15.c9_pminten &= ~value;
1903 pmu_update_irq(env);
1904 }
1905
1906 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1907 uint64_t value)
1908 {
1909 /* Note that even though the AArch64 view of this register has bits
1910 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1911 * architectural requirements for bits which are RES0 only in some
1912 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1913 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1914 */
1915 raw_write(env, ri, value & ~0x1FULL);
1916 }
1917
1918 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1919 {
1920 /* Begin with base v8.0 state. */
1921 uint32_t valid_mask = 0x3fff;
1922 ARMCPU *cpu = env_archcpu(env);
1923
1924 if (arm_el_is_aa64(env, 3)) {
1925 value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
1926 valid_mask &= ~SCR_NET;
1927 } else {
1928 valid_mask &= ~(SCR_RW | SCR_ST);
1929 }
1930
1931 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1932 valid_mask &= ~SCR_HCE;
1933
1934 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1935 * supported if EL2 exists. The bit is UNK/SBZP when
1936 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1937 * when EL2 is unavailable.
1938 * On ARMv8, this bit is always available.
1939 */
1940 if (arm_feature(env, ARM_FEATURE_V7) &&
1941 !arm_feature(env, ARM_FEATURE_V8)) {
1942 valid_mask &= ~SCR_SMD;
1943 }
1944 }
1945 if (cpu_isar_feature(aa64_lor, cpu)) {
1946 valid_mask |= SCR_TLOR;
1947 }
1948 if (cpu_isar_feature(aa64_pauth, cpu)) {
1949 valid_mask |= SCR_API | SCR_APK;
1950 }
1951
1952 /* Clear all-context RES0 bits. */
1953 value &= valid_mask;
1954 raw_write(env, ri, value);
1955 }
1956
1957 static CPAccessResult access_aa64_tid2(CPUARMState *env,
1958 const ARMCPRegInfo *ri,
1959 bool isread)
1960 {
1961 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
1962 return CP_ACCESS_TRAP_EL2;
1963 }
1964
1965 return CP_ACCESS_OK;
1966 }
1967
1968 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1969 {
1970 ARMCPU *cpu = env_archcpu(env);
1971
1972 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1973 * bank
1974 */
1975 uint32_t index = A32_BANKED_REG_GET(env, csselr,
1976 ri->secure & ARM_CP_SECSTATE_S);
1977
1978 return cpu->ccsidr[index];
1979 }
1980
1981 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1982 uint64_t value)
1983 {
1984 raw_write(env, ri, value & 0xf);
1985 }
1986
1987 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1988 {
1989 CPUState *cs = env_cpu(env);
1990 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
1991 uint64_t ret = 0;
1992 bool allow_virt = (arm_current_el(env) == 1 &&
1993 (!arm_is_secure_below_el3(env) ||
1994 (env->cp15.scr_el3 & SCR_EEL2)));
1995
1996 if (allow_virt && (hcr_el2 & HCR_IMO)) {
1997 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
1998 ret |= CPSR_I;
1999 }
2000 } else {
2001 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
2002 ret |= CPSR_I;
2003 }
2004 }
2005
2006 if (allow_virt && (hcr_el2 & HCR_FMO)) {
2007 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
2008 ret |= CPSR_F;
2009 }
2010 } else {
2011 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
2012 ret |= CPSR_F;
2013 }
2014 }
2015
2016 /* External aborts are not possible in QEMU so A bit is always clear */
2017 return ret;
2018 }
2019
2020 static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2021 bool isread)
2022 {
2023 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) {
2024 return CP_ACCESS_TRAP_EL2;
2025 }
2026
2027 return CP_ACCESS_OK;
2028 }
2029
2030 static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2031 bool isread)
2032 {
2033 if (arm_feature(env, ARM_FEATURE_V8)) {
2034 return access_aa64_tid1(env, ri, isread);
2035 }
2036
2037 return CP_ACCESS_OK;
2038 }
2039
2040 static const ARMCPRegInfo v7_cp_reginfo[] = {
2041 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2042 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
2043 .access = PL1_W, .type = ARM_CP_NOP },
2044 /* Performance monitors are implementation defined in v7,
2045 * but with an ARM recommended set of registers, which we
2046 * follow.
2047 *
2048 * Performance registers fall into three categories:
2049 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2050 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2051 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2052 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2053 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2054 */
2055 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
2056 .access = PL0_RW, .type = ARM_CP_ALIAS,
2057 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
2058 .writefn = pmcntenset_write,
2059 .accessfn = pmreg_access,
2060 .raw_writefn = raw_write },
2061 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
2062 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
2063 .access = PL0_RW, .accessfn = pmreg_access,
2064 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
2065 .writefn = pmcntenset_write, .raw_writefn = raw_write },
2066 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
2067 .access = PL0_RW,
2068 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
2069 .accessfn = pmreg_access,
2070 .writefn = pmcntenclr_write,
2071 .type = ARM_CP_ALIAS },
2072 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
2073 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
2074 .access = PL0_RW, .accessfn = pmreg_access,
2075 .type = ARM_CP_ALIAS,
2076 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
2077 .writefn = pmcntenclr_write },
2078 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
2079 .access = PL0_RW, .type = ARM_CP_IO,
2080 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2081 .accessfn = pmreg_access,
2082 .writefn = pmovsr_write,
2083 .raw_writefn = raw_write },
2084 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
2085 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
2086 .access = PL0_RW, .accessfn = pmreg_access,
2087 .type = ARM_CP_ALIAS | ARM_CP_IO,
2088 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2089 .writefn = pmovsr_write,
2090 .raw_writefn = raw_write },
2091 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
2092 .access = PL0_W, .accessfn = pmreg_access_swinc,
2093 .type = ARM_CP_NO_RAW | ARM_CP_IO,
2094 .writefn = pmswinc_write },
2095 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
2096 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
2097 .access = PL0_W, .accessfn = pmreg_access_swinc,
2098 .type = ARM_CP_NO_RAW | ARM_CP_IO,
2099 .writefn = pmswinc_write },
2100 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
2101 .access = PL0_RW, .type = ARM_CP_ALIAS,
2102 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
2103 .accessfn = pmreg_access_selr, .writefn = pmselr_write,
2104 .raw_writefn = raw_write},
2105 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
2106 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
2107 .access = PL0_RW, .accessfn = pmreg_access_selr,
2108 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
2109 .writefn = pmselr_write, .raw_writefn = raw_write, },
2110 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
2111 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
2112 .readfn = pmccntr_read, .writefn = pmccntr_write32,
2113 .accessfn = pmreg_access_ccntr },
2114 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
2115 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
2116 .access = PL0_RW, .accessfn = pmreg_access_ccntr,
2117 .type = ARM_CP_IO,
2118 .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
2119 .readfn = pmccntr_read, .writefn = pmccntr_write,
2120 .raw_readfn = raw_read, .raw_writefn = raw_write, },
2121 { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
2122 .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
2123 .access = PL0_RW, .accessfn = pmreg_access,
2124 .type = ARM_CP_ALIAS | ARM_CP_IO,
2125 .resetvalue = 0, },
2126 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
2127 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
2128 .writefn = pmccfiltr_write, .raw_writefn = raw_write,
2129 .access = PL0_RW, .accessfn = pmreg_access,
2130 .type = ARM_CP_IO,
2131 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
2132 .resetvalue = 0, },
2133 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
2134 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2135 .accessfn = pmreg_access,
2136 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2137 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
2138 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
2139 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2140 .accessfn = pmreg_access,
2141 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2142 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
2143 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2144 .accessfn = pmreg_access_xevcntr,
2145 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2146 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
2147 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
2148 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2149 .accessfn = pmreg_access_xevcntr,
2150 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2151 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
2152 .access = PL0_R | PL1_RW, .accessfn = access_tpm,
2153 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
2154 .resetvalue = 0,
2155 .writefn = pmuserenr_write, .raw_writefn = raw_write },
2156 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
2157 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
2158 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
2159 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
2160 .resetvalue = 0,
2161 .writefn = pmuserenr_write, .raw_writefn = raw_write },
2162 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
2163 .access = PL1_RW, .accessfn = access_tpm,
2164 .type = ARM_CP_ALIAS | ARM_CP_IO,
2165 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
2166 .resetvalue = 0,
2167 .writefn = pmintenset_write, .raw_writefn = raw_write },
2168 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
2169 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
2170 .access = PL1_RW, .accessfn = access_tpm,
2171 .type = ARM_CP_IO,
2172 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2173 .writefn = pmintenset_write, .raw_writefn = raw_write,
2174 .resetvalue = 0x0 },
2175 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
2176 .access = PL1_RW, .accessfn = access_tpm,
2177 .type = ARM_CP_ALIAS | ARM_CP_IO,
2178 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2179 .writefn = pmintenclr_write, },
2180 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
2181 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
2182 .access = PL1_RW, .accessfn = access_tpm,
2183 .type = ARM_CP_ALIAS | ARM_CP_IO,
2184 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2185 .writefn = pmintenclr_write },
2186 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2187 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
2188 .access = PL1_R,
2189 .accessfn = access_aa64_tid2,
2190 .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
2191 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2192 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
2193 .access = PL1_RW,
2194 .accessfn = access_aa64_tid2,
2195 .writefn = csselr_write, .resetvalue = 0,
2196 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
2197 offsetof(CPUARMState, cp15.csselr_ns) } },
2198 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2199 * just RAZ for all cores:
2200 */
2201 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2202 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
2203 .access = PL1_R, .type = ARM_CP_CONST,
2204 .accessfn = access_aa64_tid1,
2205 .resetvalue = 0 },
2206 /* Auxiliary fault status registers: these also are IMPDEF, and we
2207 * choose to RAZ/WI for all cores.
2208 */
2209 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
2210 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
2211 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2212 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
2213 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
2214 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2215 /* MAIR can just read-as-written because we don't implement caches
2216 * and so don't need to care about memory attributes.
2217 */
2218 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
2219 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2220 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
2221 .resetvalue = 0 },
2222 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
2223 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
2224 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
2225 .resetvalue = 0 },
2226 /* For non-long-descriptor page tables these are PRRR and NMRR;
2227 * regardless they still act as reads-as-written for QEMU.
2228 */
2229 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2230 * allows them to assign the correct fieldoffset based on the endianness
2231 * handled in the field definitions.
2232 */
2233 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2234 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
2235 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
2236 offsetof(CPUARMState, cp15.mair0_ns) },
2237 .resetfn = arm_cp_reset_ignore },
2238 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
2239 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
2240 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
2241 offsetof(CPUARMState, cp15.mair1_ns) },
2242 .resetfn = arm_cp_reset_ignore },
2243 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2244 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
2245 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
2246 /* 32 bit ITLB invalidates */
2247 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2248 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
2249 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2250 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
2251 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2252 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
2253 /* 32 bit DTLB invalidates */
2254 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2255 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
2256 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2257 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
2258 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2259 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
2260 /* 32 bit TLB invalidates */
2261 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2262 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
2263 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2264 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
2265 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2266 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
2267 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2268 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
2269 REGINFO_SENTINEL
2270 };
2271
2272 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
2273 /* 32 bit TLB invalidates, Inner Shareable */
2274 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2275 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
2276 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2277 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
2278 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2279 .type = ARM_CP_NO_RAW, .access = PL1_W,
2280 .writefn = tlbiasid_is_write },
2281 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2282 .type = ARM_CP_NO_RAW, .access = PL1_W,
2283 .writefn = tlbimvaa_is_write },
2284 REGINFO_SENTINEL
2285 };
2286
2287 static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
2288 /* PMOVSSET is not implemented in v7 before v7ve */
2289 { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
2290 .access = PL0_RW, .accessfn = pmreg_access,
2291 .type = ARM_CP_ALIAS | ARM_CP_IO,
2292 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2293 .writefn = pmovsset_write,
2294 .raw_writefn = raw_write },
2295 { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
2296 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
2297 .access = PL0_RW, .accessfn = pmreg_access,
2298 .type = ARM_CP_ALIAS | ARM_CP_IO,
2299 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2300 .writefn = pmovsset_write,
2301 .raw_writefn = raw_write },
2302 REGINFO_SENTINEL
2303 };
2304
2305 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2306 uint64_t value)
2307 {
2308 value &= 1;
2309 env->teecr = value;
2310 }
2311
2312 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
2313 bool isread)
2314 {
2315 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
2316 return CP_ACCESS_TRAP;
2317 }
2318 return CP_ACCESS_OK;
2319 }
2320
2321 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
2322 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
2323 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
2324 .resetvalue = 0,
2325 .writefn = teecr_write },
2326 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
2327 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
2328 .accessfn = teehbr_access, .resetvalue = 0 },
2329 REGINFO_SENTINEL
2330 };
2331
2332 static const ARMCPRegInfo v6k_cp_reginfo[] = {
2333 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
2334 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
2335 .access = PL0_RW,
2336 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
2337 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
2338 .access = PL0_RW,
2339 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
2340 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
2341 .resetfn = arm_cp_reset_ignore },
2342 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
2343 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
2344 .access = PL0_R|PL1_W,
2345 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
2346 .resetvalue = 0},
2347 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
2348 .access = PL0_R|PL1_W,
2349 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
2350 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
2351 .resetfn = arm_cp_reset_ignore },
2352 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
2353 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
2354 .access = PL1_RW,
2355 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
2356 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
2357 .access = PL1_RW,
2358 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
2359 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
2360 .resetvalue = 0 },
2361 REGINFO_SENTINEL
2362 };
2363
2364 #ifndef CONFIG_USER_ONLY
2365
2366 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
2367 bool isread)
2368 {
2369 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2370 * Writable only at the highest implemented exception level.
2371 */
2372 int el = arm_current_el(env);
2373 uint64_t hcr;
2374 uint32_t cntkctl;
2375
2376 switch (el) {
2377 case 0:
2378 hcr = arm_hcr_el2_eff(env);
2379 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2380 cntkctl = env->cp15.cnthctl_el2;
2381 } else {
2382 cntkctl = env->cp15.c14_cntkctl;
2383 }
2384 if (!extract32(cntkctl, 0, 2)) {
2385 return CP_ACCESS_TRAP;
2386 }
2387 break;
2388 case 1:
2389 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
2390 arm_is_secure_below_el3(env)) {
2391 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2392 return CP_ACCESS_TRAP_UNCATEGORIZED;
2393 }
2394 break;
2395 case 2:
2396 case 3:
2397 break;
2398 }
2399
2400 if (!isread && el < arm_highest_el(env)) {
2401 return CP_ACCESS_TRAP_UNCATEGORIZED;
2402 }
2403
2404 return CP_ACCESS_OK;
2405 }
2406
2407 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
2408 bool isread)
2409 {
2410 unsigned int cur_el = arm_current_el(env);
2411 bool secure = arm_is_secure(env);
2412 uint64_t hcr = arm_hcr_el2_eff(env);
2413
2414 switch (cur_el) {
2415 case 0:
2416 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2417 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2418 return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
2419 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2420 }
2421
2422 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2423 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
2424 return CP_ACCESS_TRAP;
2425 }
2426
2427 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2428 if (hcr & HCR_E2H) {
2429 if (timeridx == GTIMER_PHYS &&
2430 !extract32(env->cp15.cnthctl_el2, 10, 1)) {
2431 return CP_ACCESS_TRAP_EL2;
2432 }
2433 } else {
2434 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2435 if (arm_feature(env, ARM_FEATURE_EL2) &&
2436 timeridx == GTIMER_PHYS && !secure &&
2437 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
2438 return CP_ACCESS_TRAP_EL2;
2439 }
2440 }
2441 break;
2442
2443 case 1:
2444 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2445 if (arm_feature(env, ARM_FEATURE_EL2) &&
2446 timeridx == GTIMER_PHYS && !secure &&
2447 (hcr & HCR_E2H
2448 ? !extract32(env->cp15.cnthctl_el2, 10, 1)
2449 : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
2450 return CP_ACCESS_TRAP_EL2;
2451 }
2452 break;
2453 }
2454 return CP_ACCESS_OK;
2455 }
2456
2457 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
2458 bool isread)
2459 {
2460 unsigned int cur_el = arm_current_el(env);
2461 bool secure = arm_is_secure(env);
2462 uint64_t hcr = arm_hcr_el2_eff(env);
2463
2464 switch (cur_el) {
2465 case 0:
2466 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2467 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2468 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
2469 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2470 }
2471
2472 /*
2473 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2474 * EL0 if EL0[PV]TEN is zero.
2475 */
2476 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
2477 return CP_ACCESS_TRAP;
2478 }
2479 /* fall through */
2480
2481 case 1:
2482 if (arm_feature(env, ARM_FEATURE_EL2) &&
2483 timeridx == GTIMER_PHYS && !secure) {
2484 if (hcr & HCR_E2H) {
2485 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2486 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
2487 return CP_ACCESS_TRAP_EL2;
2488 }
2489 } else {
2490 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2491 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
2492 return CP_ACCESS_TRAP_EL2;
2493 }
2494 }
2495 }
2496 break;
2497 }
2498 return CP_ACCESS_OK;
2499 }
2500
2501 static CPAccessResult gt_pct_access(CPUARMState *env,
2502 const ARMCPRegInfo *ri,
2503 bool isread)
2504 {
2505 return gt_counter_access(env, GTIMER_PHYS, isread);
2506 }
2507
2508 static CPAccessResult gt_vct_access(CPUARMState *env,
2509 const ARMCPRegInfo *ri,
2510 bool isread)
2511 {
2512 return gt_counter_access(env, GTIMER_VIRT, isread);
2513 }
2514
2515 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2516 bool isread)
2517 {
2518 return gt_timer_access(env, GTIMER_PHYS, isread);
2519 }
2520
2521 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2522 bool isread)
2523 {
2524 return gt_timer_access(env, GTIMER_VIRT, isread);
2525 }
2526
2527 static CPAccessResult gt_stimer_access(CPUARMState *env,
2528 const ARMCPRegInfo *ri,
2529 bool isread)
2530 {
2531 /* The AArch64 register view of the secure physical timer is
2532 * always accessible from EL3, and configurably accessible from
2533 * Secure EL1.
2534 */
2535 switch (arm_current_el(env)) {
2536 case 1:
2537 if (!arm_is_secure(env)) {
2538 return CP_ACCESS_TRAP;
2539 }
2540 if (!(env->cp15.scr_el3 & SCR_ST)) {
2541 return CP_ACCESS_TRAP_EL3;
2542 }
2543 return CP_ACCESS_OK;
2544 case 0:
2545 case 2:
2546 return CP_ACCESS_TRAP;
2547 case 3:
2548 return CP_ACCESS_OK;
2549 default:
2550 g_assert_not_reached();
2551 }
2552 }
2553
2554 static uint64_t gt_get_countervalue(CPUARMState *env)
2555 {
2556 ARMCPU *cpu = env_archcpu(env);
2557
2558 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu);
2559 }
2560
2561 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
2562 {
2563 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
2564
2565 if (gt->ctl & 1) {
2566 /* Timer enabled: calculate and set current ISTATUS, irq, and
2567 * reset timer to when ISTATUS next has to change
2568 */
2569 uint64_t offset = timeridx == GTIMER_VIRT ?
2570 cpu->env.cp15.cntvoff_el2 : 0;
2571 uint64_t count = gt_get_countervalue(&cpu->env);
2572 /* Note that this must be unsigned 64 bit arithmetic: */
2573 int istatus = count - offset >= gt->cval;
2574 uint64_t nexttick;
2575 int irqstate;
2576
2577 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
2578
2579 irqstate = (istatus && !(gt->ctl & 2));
2580 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2581
2582 if (istatus) {
2583 /* Next transition is when count rolls back over to zero */
2584 nexttick = UINT64_MAX;
2585 } else {
2586 /* Next transition is when we hit cval */
2587 nexttick = gt->cval + offset;
2588 }
2589 /* Note that the desired next expiry time might be beyond the
2590 * signed-64-bit range of a QEMUTimer -- in this case we just
2591 * set the timer for as far in the future as possible. When the
2592 * timer expires we will reset the timer for any remaining period.
2593 */
2594 if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {
2595 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX);
2596 } else {
2597 timer_mod(cpu->gt_timer[timeridx], nexttick);
2598 }
2599 trace_arm_gt_recalc(timeridx, irqstate, nexttick);
2600 } else {
2601 /* Timer disabled: ISTATUS and timer output always clear */
2602 gt->ctl &= ~4;
2603 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
2604 timer_del(cpu->gt_timer[timeridx]);
2605 trace_arm_gt_recalc_disabled(timeridx);
2606 }
2607 }
2608
2609 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
2610 int timeridx)
2611 {
2612 ARMCPU *cpu = env_archcpu(env);
2613
2614 timer_del(cpu->gt_timer[timeridx]);
2615 }
2616
2617 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2618 {
2619 return gt_get_countervalue(env);
2620 }
2621
2622 static uint64_t gt_virt_cnt_offset(CPUARMState *env)
2623 {
2624 uint64_t hcr;
2625
2626 switch (arm_current_el(env)) {
2627 case 2:
2628 hcr = arm_hcr_el2_eff(env);
2629 if (hcr & HCR_E2H) {
2630 return 0;
2631 }
2632 break;
2633 case 0:
2634 hcr = arm_hcr_el2_eff(env);
2635 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2636 return 0;
2637 }
2638 break;
2639 }
2640
2641 return env->cp15.cntvoff_el2;
2642 }
2643
2644 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2645 {
2646 return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
2647 }
2648
2649 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2650 int timeridx,
2651 uint64_t value)
2652 {
2653 trace_arm_gt_cval_write(timeridx, value);
2654 env->cp15.c14_timer[timeridx].cval = value;
2655 gt_recalc_timer(env_archcpu(env), timeridx);
2656 }
2657
2658 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
2659 int timeridx)
2660 {
2661 uint64_t offset = 0;
2662
2663 switch (timeridx) {
2664 case GTIMER_VIRT:
2665 case GTIMER_HYPVIRT:
2666 offset = gt_virt_cnt_offset(env);
2667 break;
2668 }
2669
2670 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
2671 (gt_get_countervalue(env) - offset));
2672 }
2673
2674 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2675 int timeridx,
2676 uint64_t value)
2677 {
2678 uint64_t offset = 0;
2679
2680 switch (timeridx) {
2681 case GTIMER_VIRT:
2682 case GTIMER_HYPVIRT:
2683 offset = gt_virt_cnt_offset(env);
2684 break;
2685 }
2686
2687 trace_arm_gt_tval_write(timeridx, value);
2688 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
2689 sextract64(value, 0, 32);
2690 gt_recalc_timer(env_archcpu(env), timeridx);
2691 }
2692
2693 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2694 int timeridx,
2695 uint64_t value)
2696 {
2697 ARMCPU *cpu = env_archcpu(env);
2698 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
2699
2700 trace_arm_gt_ctl_write(timeridx, value);
2701 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
2702 if ((oldval ^ value) & 1) {
2703 /* Enable toggled */
2704 gt_recalc_timer(cpu, timeridx);
2705 } else if ((oldval ^ value) & 2) {
2706 /* IMASK toggled: don't need to recalculate,
2707 * just set the interrupt line based on ISTATUS
2708 */
2709 int irqstate = (oldval & 4) && !(value & 2);
2710
2711 trace_arm_gt_imask_toggle(timeridx, irqstate);
2712 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2713 }
2714 }
2715
2716 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2717 {
2718 gt_timer_reset(env, ri, GTIMER_PHYS);
2719 }
2720
2721 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2722 uint64_t value)
2723 {
2724 gt_cval_write(env, ri, GTIMER_PHYS, value);
2725 }
2726
2727 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2728 {
2729 return gt_tval_read(env, ri, GTIMER_PHYS);
2730 }
2731
2732 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2733 uint64_t value)
2734 {
2735 gt_tval_write(env, ri, GTIMER_PHYS, value);
2736 }
2737
2738 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2739 uint64_t value)
2740 {
2741 gt_ctl_write(env, ri, GTIMER_PHYS, value);
2742 }
2743
2744 static int gt_phys_redir_timeridx(CPUARMState *env)
2745 {
2746 switch (arm_mmu_idx(env)) {
2747 case ARMMMUIdx_E20_0:
2748 case ARMMMUIdx_E20_2:
2749 case ARMMMUIdx_E20_2_PAN:
2750 return GTIMER_HYP;
2751 default:
2752 return GTIMER_PHYS;
2753 }
2754 }
2755
2756 static int gt_virt_redir_timeridx(CPUARMState *env)
2757 {
2758 switch (arm_mmu_idx(env)) {
2759 case ARMMMUIdx_E20_0:
2760 case ARMMMUIdx_E20_2:
2761 case ARMMMUIdx_E20_2_PAN:
2762 return GTIMER_HYPVIRT;
2763 default:
2764 return GTIMER_VIRT;
2765 }
2766 }
2767
2768 static uint64_t gt_phys_redir_cval_read(CPUARMState *env,
2769 const ARMCPRegInfo *ri)
2770 {
2771 int timeridx = gt_phys_redir_timeridx(env);
2772 return env->cp15.c14_timer[timeridx].cval;
2773 }
2774
2775 static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2776 uint64_t value)
2777 {
2778 int timeridx = gt_phys_redir_timeridx(env);
2779 gt_cval_write(env, ri, timeridx, value);
2780 }
2781
2782 static uint64_t gt_phys_redir_tval_read(CPUARMState *env,
2783 const ARMCPRegInfo *ri)
2784 {
2785 int timeridx = gt_phys_redir_timeridx(env);
2786 return gt_tval_read(env, ri, timeridx);
2787 }
2788
2789 static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2790 uint64_t value)
2791 {
2792 int timeridx = gt_phys_redir_timeridx(env);
2793 gt_tval_write(env, ri, timeridx, value);
2794 }
2795
2796 static uint64_t gt_phys_redir_ctl_read(CPUARMState *env,
2797 const ARMCPRegInfo *ri)
2798 {
2799 int timeridx = gt_phys_redir_timeridx(env);
2800 return env->cp15.c14_timer[timeridx].ctl;
2801 }
2802
2803 static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2804 uint64_t value)
2805 {
2806 int timeridx = gt_phys_redir_timeridx(env);
2807 gt_ctl_write(env, ri, timeridx, value);
2808 }
2809
2810 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2811 {
2812 gt_timer_reset(env, ri, GTIMER_VIRT);
2813 }
2814
2815 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2816 uint64_t value)
2817 {
2818 gt_cval_write(env, ri, GTIMER_VIRT, value);
2819 }
2820
2821 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2822 {
2823 return gt_tval_read(env, ri, GTIMER_VIRT);
2824 }
2825
2826 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2827 uint64_t value)
2828 {
2829 gt_tval_write(env, ri, GTIMER_VIRT, value);
2830 }
2831
2832 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2833 uint64_t value)
2834 {
2835 gt_ctl_write(env, ri, GTIMER_VIRT, value);
2836 }
2837
2838 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
2839 uint64_t value)
2840 {
2841 ARMCPU *cpu = env_archcpu(env);
2842
2843 trace_arm_gt_cntvoff_write(value);
2844 raw_write(env, ri, value);
2845 gt_recalc_timer(cpu, GTIMER_VIRT);
2846 }
2847
2848 static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
2849 const ARMCPRegInfo *ri)
2850 {
2851 int timeridx = gt_virt_redir_timeridx(env);
2852 return env->cp15.c14_timer[timeridx].cval;
2853 }
2854
2855 static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856 uint64_t value)
2857 {
2858 int timeridx = gt_virt_redir_timeridx(env);
2859 gt_cval_write(env, ri, timeridx, value);
2860 }
2861
2862 static uint64_t gt_virt_redir_tval_read(CPUARMState *env,
2863 const ARMCPRegInfo *ri)
2864 {
2865 int timeridx = gt_virt_redir_timeridx(env);
2866 return gt_tval_read(env, ri, timeridx);
2867 }
2868
2869 static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2870 uint64_t value)
2871 {
2872 int timeridx = gt_virt_redir_timeridx(env);
2873 gt_tval_write(env, ri, timeridx, value);
2874 }
2875
2876 static uint64_t gt_virt_redir_ctl_read(CPUARMState *env,
2877 const ARMCPRegInfo *ri)
2878 {
2879 int timeridx = gt_virt_redir_timeridx(env);
2880 return env->cp15.c14_timer[timeridx].ctl;
2881 }
2882
2883 static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2884 uint64_t value)
2885 {
2886 int timeridx = gt_virt_redir_timeridx(env);
2887 gt_ctl_write(env, ri, timeridx, value);
2888 }
2889
2890 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2891 {
2892 gt_timer_reset(env, ri, GTIMER_HYP);
2893 }
2894
2895 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2896 uint64_t value)
2897 {
2898 gt_cval_write(env, ri, GTIMER_HYP, value);
2899 }
2900
2901 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2902 {
2903 return gt_tval_read(env, ri, GTIMER_HYP);
2904 }
2905
2906 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2907 uint64_t value)
2908 {
2909 gt_tval_write(env, ri, GTIMER_HYP, value);
2910 }
2911
2912 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2913 uint64_t value)
2914 {
2915 gt_ctl_write(env, ri, GTIMER_HYP, value);
2916 }
2917
2918 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2919 {
2920 gt_timer_reset(env, ri, GTIMER_SEC);
2921 }
2922
2923 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2924 uint64_t value)
2925 {
2926 gt_cval_write(env, ri, GTIMER_SEC, value);
2927 }
2928
2929 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2930 {
2931 return gt_tval_read(env, ri, GTIMER_SEC);
2932 }
2933
2934 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2935 uint64_t value)
2936 {
2937 gt_tval_write(env, ri, GTIMER_SEC, value);
2938 }
2939
2940 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2941 uint64_t value)
2942 {
2943 gt_ctl_write(env, ri, GTIMER_SEC, value);
2944 }
2945
2946 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2947 {
2948 gt_timer_reset(env, ri, GTIMER_HYPVIRT);
2949 }
2950
2951 static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2952 uint64_t value)
2953 {
2954 gt_cval_write(env, ri, GTIMER_HYPVIRT, value);
2955 }
2956
2957 static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2958 {
2959 return gt_tval_read(env, ri, GTIMER_HYPVIRT);
2960 }
2961
2962 static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2963 uint64_t value)
2964 {
2965 gt_tval_write(env, ri, GTIMER_HYPVIRT, value);
2966 }
2967
2968 static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2969 uint64_t value)
2970 {
2971 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value);
2972 }
2973
2974 void arm_gt_ptimer_cb(void *opaque)
2975 {
2976 ARMCPU *cpu = opaque;
2977
2978 gt_recalc_timer(cpu, GTIMER_PHYS);
2979 }
2980
2981 void arm_gt_vtimer_cb(void *opaque)
2982 {
2983 ARMCPU *cpu = opaque;
2984
2985 gt_recalc_timer(cpu, GTIMER_VIRT);
2986 }
2987
2988 void arm_gt_htimer_cb(void *opaque)
2989 {
2990 ARMCPU *cpu = opaque;
2991
2992 gt_recalc_timer(cpu, GTIMER_HYP);
2993 }
2994
2995 void arm_gt_stimer_cb(void *opaque)
2996 {
2997 ARMCPU *cpu = opaque;
2998
2999 gt_recalc_timer(cpu, GTIMER_SEC);
3000 }
3001
3002 void arm_gt_hvtimer_cb(void *opaque)
3003 {
3004 ARMCPU *cpu = opaque;
3005
3006 gt_recalc_timer(cpu, GTIMER_HYPVIRT);
3007 }
3008
3009 static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
3010 {
3011 ARMCPU *cpu = env_archcpu(env);
3012
3013 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
3014 }
3015
3016 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3017 /* Note that CNTFRQ is purely reads-as-written for the benefit
3018 * of software; writing it doesn't actually change the timer frequency.
3019 * Our reset value matches the fixed frequency we implement the timer at.
3020 */
3021 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
3022 .type = ARM_CP_ALIAS,
3023 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3024 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
3025 },
3026 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3027 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3028 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3029 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3030 .resetfn = arm_gt_cntfrq_reset,
3031 },
3032 /* overall control: mostly access permissions */
3033 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
3034 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
3035 .access = PL1_RW,
3036 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
3037 .resetvalue = 0,
3038 },
3039 /* per-timer control */
3040 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3041 .secure = ARM_CP_SECSTATE_NS,
3042 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3043 .accessfn = gt_ptimer_access,
3044 .fieldoffset = offsetoflow32(CPUARMState,
3045 cp15.c14_timer[GTIMER_PHYS].ctl),
3046 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3047 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
3048 },
3049 { .name = "CNTP_CTL_S",
3050 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3051 .secure = ARM_CP_SECSTATE_S,
3052 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3053 .accessfn = gt_ptimer_access,
3054 .fieldoffset = offsetoflow32(CPUARMState,
3055 cp15.c14_timer[GTIMER_SEC].ctl),
3056 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3057 },
3058 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
3059 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
3060 .type = ARM_CP_IO, .access = PL0_RW,
3061 .accessfn = gt_ptimer_access,
3062 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
3063 .resetvalue = 0,
3064 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3065 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
3066 },
3067 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
3068 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3069 .accessfn = gt_vtimer_access,
3070 .fieldoffset = offsetoflow32(CPUARMState,
3071 cp15.c14_timer[GTIMER_VIRT].ctl),
3072 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3073 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
3074 },
3075 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
3076 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
3077 .type = ARM_CP_IO, .access = PL0_RW,
3078 .accessfn = gt_vtimer_access,
3079 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
3080 .resetvalue = 0,
3081 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3082 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
3083 },
3084 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3085 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3086 .secure = ARM_CP_SECSTATE_NS,
3087 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3088 .accessfn = gt_ptimer_access,
3089 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
3090 },
3091 { .name = "CNTP_TVAL_S",
3092 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3093 .secure = ARM_CP_SECSTATE_S,
3094 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3095 .accessfn = gt_ptimer_access,
3096 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
3097 },
3098 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3099 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
3100 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3101 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
3102 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
3103 },
3104 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
3105 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3106 .accessfn = gt_vtimer_access,
3107 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
3108 },
3109 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3110 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
3111 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3112 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
3113 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
3114 },
3115 /* The counter itself */
3116 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
3117 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3118 .accessfn = gt_pct_access,
3119 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
3120 },
3121 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
3122 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
3123 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3124 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
3125 },
3126 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
3127 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3128 .accessfn = gt_vct_access,
3129 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
3130 },
3131 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3132 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3133 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3134 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
3135 },
3136 /* Comparison value, indicating when the timer goes off */
3137 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
3138 .secure = ARM_CP_SECSTATE_NS,
3139 .access = PL0_RW,
3140 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3141 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
3142 .accessfn = gt_ptimer_access,
3143 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3144 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
3145 },
3146 { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
3147 .secure = ARM_CP_SECSTATE_S,
3148 .access = PL0_RW,
3149 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3150 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3151 .accessfn = gt_ptimer_access,
3152 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3153 },
3154 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3155 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
3156 .access = PL0_RW,
3157 .type = ARM_CP_IO,
3158 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
3159 .resetvalue = 0, .accessfn = gt_ptimer_access,
3160 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3161 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
3162 },
3163 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
3164 .access = PL0_RW,
3165 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3166 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3167 .accessfn = gt_vtimer_access,
3168 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3169 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
3170 },
3171 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3172 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
3173 .access = PL0_RW,
3174 .type = ARM_CP_IO,
3175 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3176 .resetvalue = 0, .accessfn = gt_vtimer_access,
3177 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3178 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
3179 },
3180 /* Secure timer -- this is actually restricted to only EL3
3181 * and configurably Secure-EL1 via the accessfn.
3182 */
3183 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
3184 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
3185 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
3186 .accessfn = gt_stimer_access,
3187 .readfn = gt_sec_tval_read,
3188 .writefn = gt_sec_tval_write,
3189 .resetfn = gt_sec_timer_reset,
3190 },
3191 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
3192 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
3193 .type = ARM_CP_IO, .access = PL1_RW,
3194 .accessfn = gt_stimer_access,
3195 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
3196 .resetvalue = 0,
3197 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3198 },
3199 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
3200 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
3201 .type = ARM_CP_IO, .access = PL1_RW,
3202 .accessfn = gt_stimer_access,
3203 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3204 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3205 },
3206 REGINFO_SENTINEL
3207 };
3208
3209 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
3210 bool isread)
3211 {
3212 if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
3213 return CP_ACCESS_TRAP;
3214 }
3215 return CP_ACCESS_OK;
3216 }
3217
3218 #else
3219
3220 /* In user-mode most of the generic timer registers are inaccessible
3221 * however modern kernels (4.12+) allow access to cntvct_el0
3222 */
3223
3224 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
3225 {
3226 ARMCPU *cpu = env_archcpu(env);
3227
3228 /* Currently we have no support for QEMUTimer in linux-user so we
3229 * can't call gt_get_countervalue(env), instead we directly
3230 * call the lower level functions.
3231 */
3232 return cpu_get_clock() / gt_cntfrq_period_ns(cpu);
3233 }
3234
3235 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3236 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3237 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3238 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
3239 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3240 .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
3241 },
3242 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3243 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3244 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3245 .readfn = gt_virt_cnt_read,
3246 },
3247 REGINFO_SENTINEL
3248 };
3249
3250 #endif
3251
3252 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3253 {
3254 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3255 raw_write(env, ri, value);
3256 } else if (arm_feature(env, ARM_FEATURE_V7)) {
3257 raw_write(env, ri, value & 0xfffff6ff);
3258 } else {
3259 raw_write(env, ri, value & 0xfffff1ff);
3260 }
3261 }
3262
3263 #ifndef CONFIG_USER_ONLY
3264 /* get_phys_addr() isn't present for user-mode-only targets */
3265
3266 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
3267 bool isread)
3268 {
3269 if (ri->opc2 & 4) {
3270 /* The ATS12NSO* operations must trap to EL3 if executed in
3271 * Secure EL1 (which can only happen if EL3 is AArch64).
3272 * They are simply UNDEF if executed from NS EL1.
3273 * They function normally from EL2 or EL3.
3274 */
3275 if (arm_current_el(env) == 1) {
3276 if (arm_is_secure_below_el3(env)) {
3277 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
3278 }
3279 return CP_ACCESS_TRAP_UNCATEGORIZED;
3280 }
3281 }
3282 return CP_ACCESS_OK;
3283 }
3284
3285 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
3286 MMUAccessType access_type, ARMMMUIdx mmu_idx)
3287 {
3288 hwaddr phys_addr;
3289 target_ulong page_size;
3290 int prot;
3291 bool ret;
3292 uint64_t par64;
3293 bool format64 = false;
3294 MemTxAttrs attrs = {};
3295 ARMMMUFaultInfo fi = {};
3296 ARMCacheAttrs cacheattrs = {};
3297
3298 ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
3299 &prot, &page_size, &fi, &cacheattrs);
3300
3301 if (ret) {
3302 /*
3303 * Some kinds of translation fault must cause exceptions rather
3304 * than being reported in the PAR.
3305 */
3306 int current_el = arm_current_el(env);
3307 int target_el;
3308 uint32_t syn, fsr, fsc;
3309 bool take_exc = false;
3310
3311 if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
3312 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
3313 /*
3314 * Synchronous stage 2 fault on an access made as part of the
3315 * translation table walk for AT S1E0* or AT S1E1* insn
3316 * executed from NS EL1. If this is a synchronous external abort
3317 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3318 * to EL3. Otherwise the fault is taken as an exception to EL2,
3319 * and HPFAR_EL2 holds the faulting IPA.
3320 */
3321 if (fi.type == ARMFault_SyncExternalOnWalk &&
3322 (env->cp15.scr_el3 & SCR_EA)) {
3323 target_el = 3;
3324 } else {
3325 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
3326 target_el = 2;
3327 }
3328 take_exc = true;
3329 } else if (fi.type == ARMFault_SyncExternalOnWalk) {
3330 /*
3331 * Synchronous external aborts during a translation table walk
3332 * are taken as Data Abort exceptions.
3333 */
3334 if (fi.stage2) {
3335 if (current_el == 3) {
3336 target_el = 3;
3337 } else {
3338 target_el = 2;
3339 }
3340 } else {
3341 target_el = exception_target_el(env);
3342 }
3343 take_exc = true;
3344 }
3345
3346 if (take_exc) {
3347 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3348 if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
3349 arm_s1_regime_using_lpae_format(env, mmu_idx)) {
3350 fsr = arm_fi_to_lfsc(&fi);
3351 fsc = extract32(fsr, 0, 6);
3352 } else {
3353 fsr = arm_fi_to_sfsc(&fi);
3354 fsc = 0x3f;
3355 }
3356 /*
3357 * Report exception with ESR indicating a fault due to a
3358 * translation table walk for a cache maintenance instruction.
3359 */
3360 syn = syn_data_abort_no_iss(current_el == target_el,
3361 fi.ea, 1, fi.s1ptw, 1, fsc);
3362 env->exception.vaddress = value;
3363 env->exception.fsr = fsr;
3364 raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
3365 }
3366 }
3367
3368 if (is_a64(env)) {
3369 format64 = true;
3370 } else if (arm_feature(env, ARM_FEATURE_LPAE)) {
3371 /*
3372 * ATS1Cxx:
3373 * * TTBCR.EAE determines whether the result is returned using the
3374 * 32-bit or the 64-bit PAR format
3375 * * Instructions executed in Hyp mode always use the 64bit format
3376 *
3377 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3378 * * The Non-secure TTBCR.EAE bit is set to 1
3379 * * The implementation includes EL2, and the value of HCR.VM is 1
3380 *
3381 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3382 *
3383 * ATS1Hx always uses the 64bit format.
3384 */
3385 format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
3386
3387 if (arm_feature(env, ARM_FEATURE_EL2)) {
3388 if (mmu_idx == ARMMMUIdx_E10_0 ||
3389 mmu_idx == ARMMMUIdx_E10_1 ||
3390 mmu_idx == ARMMMUIdx_E10_1_PAN) {
3391 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
3392 } else {
3393 format64 |= arm_current_el(env) == 2;
3394 }
3395 }
3396 }
3397
3398 if (format64) {
3399 /* Create a 64-bit PAR */
3400 par64 = (1 << 11); /* LPAE bit always set */
3401 if (!ret) {
3402 par64 |= phys_addr & ~0xfffULL;
3403 if (!attrs.secure) {
3404 par64 |= (1 << 9); /* NS */
3405 }
3406 par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
3407 par64 |= cacheattrs.shareability << 7; /* SH */
3408 } else {
3409 uint32_t fsr = arm_fi_to_lfsc(&fi);
3410
3411 par64 |= 1; /* F */
3412 par64 |= (fsr & 0x3f) << 1; /* FS */
3413 if (fi.stage2) {
3414 par64 |= (1 << 9); /* S */
3415 }
3416 if (fi.s1ptw) {
3417 par64 |= (1 << 8); /* PTW */
3418 }
3419 }
3420 } else {
3421 /* fsr is a DFSR/IFSR value for the short descriptor
3422 * translation table format (with WnR always clear).
3423 * Convert it to a 32-bit PAR.
3424 */
3425 if (!ret) {
3426 /* We do not set any attribute bits in the PAR */
3427 if (page_size == (1 << 24)
3428 && arm_feature(env, ARM_FEATURE_V7)) {
3429 par64 = (phys_addr & 0xff000000) | (1 << 1);
3430 } else {
3431 par64 = phys_addr & 0xfffff000;
3432 }
3433 if (!attrs.secure) {
3434 par64 |= (1 << 9); /* NS */
3435 }
3436 } else {
3437 uint32_t fsr = arm_fi_to_sfsc(&fi);
3438
3439 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
3440 ((fsr & 0xf) << 1) | 1;
3441 }
3442 }
3443 return par64;
3444 }
3445
3446 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3447 {
3448 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3449 uint64_t par64;
3450 ARMMMUIdx mmu_idx;
3451 int el = arm_current_el(env);
3452 bool secure = arm_is_secure_below_el3(env);
3453
3454 switch (ri->opc2 & 6) {
3455 case 0:
3456 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3457 switch (el) {
3458 case 3:
3459 mmu_idx = ARMMMUIdx_SE3;
3460 break;
3461 case 2:
3462 g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */
3463 /* fall through */
3464 case 1:
3465 if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
3466 mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN
3467 : ARMMMUIdx_Stage1_E1_PAN);
3468 } else {
3469 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
3470 }
3471 break;
3472 default:
3473 g_assert_not_reached();
3474 }
3475 break;
3476 case 2:
3477 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3478 switch (el) {
3479 case 3:
3480 mmu_idx = ARMMMUIdx_SE10_0;
3481 break;
3482 case 2:
3483 mmu_idx = ARMMMUIdx_Stage1_E0;
3484 break;
3485 case 1:
3486 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
3487 break;
3488 default:
3489 g_assert_not_reached();
3490 }
3491 break;
3492 case 4:
3493 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3494 mmu_idx = ARMMMUIdx_E10_1;
3495 break;
3496 case 6:
3497 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3498 mmu_idx = ARMMMUIdx_E10_0;
3499 break;
3500 default:
3501 g_assert_not_reached();
3502 }
3503
3504 par64 = do_ats_write(env, value, access_type, mmu_idx);
3505
3506 A32_BANKED_CURRENT_REG_SET(env, par, par64);
3507 }
3508
3509 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
3510 uint64_t value)
3511 {
3512 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3513 uint64_t par64;
3514
3515 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
3516
3517 A32_BANKED_CURRENT_REG_SET(env, par, par64);
3518 }
3519
3520 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
3521 bool isread)
3522 {
3523 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
3524 return CP_ACCESS_TRAP;
3525 }
3526 return CP_ACCESS_OK;
3527 }
3528
3529 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
3530 uint64_t value)
3531 {
3532 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3533 ARMMMUIdx mmu_idx;
3534 int secure = arm_is_secure_below_el3(env);
3535
3536 switch (ri->opc2 & 6) {
3537 case 0:
3538 switch (ri->opc1) {
3539 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3540 if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
3541 mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN
3542 : ARMMMUIdx_Stage1_E1_PAN);
3543 } else {
3544 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
3545 }
3546 break;
3547 case 4: /* AT S1E2R, AT S1E2W */
3548 mmu_idx = ARMMMUIdx_E2;
3549 break;
3550 case 6: /* AT S1E3R, AT S1E3W */
3551 mmu_idx = ARMMMUIdx_SE3;
3552 break;
3553 default:
3554 g_assert_not_reached();
3555 }
3556 break;
3557 case 2: /* AT S1E0R, AT S1E0W */
3558 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
3559 break;
3560 case 4: /* AT S12E1R, AT S12E1W */
3561 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
3562 break;
3563 case 6: /* AT S12E0R, AT S12E0W */
3564 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
3565 break;
3566 default:
3567 g_assert_not_reached();
3568 }
3569
3570 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
3571 }
3572 #endif
3573
3574 static const ARMCPRegInfo vapa_cp_reginfo[] = {
3575 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
3576 .access = PL1_RW, .resetvalue = 0,
3577 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
3578 offsetoflow32(CPUARMState, cp15.par_ns) },
3579 .writefn = par_write },
3580 #ifndef CONFIG_USER_ONLY
3581 /* This underdecoding is safe because the reginfo is NO_RAW. */
3582 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
3583 .access = PL1_W, .accessfn = ats_access,
3584 .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
3585 #endif
3586 REGINFO_SENTINEL
3587 };
3588
3589 /* Return basic MPU access permission bits. */
3590 static uint32_t simple_mpu_ap_bits(uint32_t val)
3591 {
3592 uint32_t ret;
3593 uint32_t mask;
3594 int i;
3595 ret = 0;
3596 mask = 3;
3597 for (i = 0; i < 16; i += 2) {
3598 ret |= (val >> i) & mask;
3599 mask <<= 2;
3600 }
3601 return ret;
3602 }
3603
3604 /* Pad basic MPU access permission bits to extended format. */
3605 static uint32_t extended_mpu_ap_bits(uint32_t val)
3606 {
3607 uint32_t ret;
3608 uint32_t mask;
3609 int i;
3610 ret = 0;
3611 mask = 3;
3612 for (i = 0; i < 16; i += 2) {
3613 ret |= (val & mask) << i;
3614 mask <<= 2;
3615 }
3616 return ret;
3617 }
3618
3619 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3620 uint64_t value)
3621 {
3622 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
3623 }
3624
3625 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
3626 {
3627 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
3628 }
3629
3630 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3631 uint64_t value)
3632 {
3633 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
3634 }
3635
3636 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
3637 {
3638 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
3639 }
3640
3641 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
3642 {
3643 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3644
3645 if (!u32p) {
3646 return 0;
3647 }
3648
3649 u32p += env->pmsav7.rnr[M_REG_NS];
3650 return *u32p;
3651 }
3652
3653 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
3654 uint64_t value)
3655 {
3656 ARMCPU *cpu = env_archcpu(env);
3657 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3658
3659 if (!u32p) {
3660 return;
3661 }
3662
3663 u32p += env->pmsav7.rnr[M_REG_NS];
3664 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
3665 *u32p = value;
3666 }
3667
3668 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3669 uint64_t value)
3670 {
3671 ARMCPU *cpu = env_archcpu(env);
3672 uint32_t nrgs = cpu->pmsav7_dregion;
3673
3674 if (value >= nrgs) {
3675 qemu_log_mask(LOG_GUEST_ERROR,
3676 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3677 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
3678 return;
3679 }
3680
3681 raw_write(env, ri, value);
3682 }
3683
3684 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
3685 /* Reset for all these registers is handled in arm_cpu_reset(),
3686 * because the PMSAv7 is also used by M-profile CPUs, which do
3687 * not register cpregs but still need the state to be reset.
3688 */
3689 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
3690 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3691 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
3692 .readfn = pmsav7_read, .writefn = pmsav7_write,
3693 .resetfn = arm_cp_reset_ignore },
3694 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
3695 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3696 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
3697 .readfn = pmsav7_read, .writefn = pmsav7_write,
3698 .resetfn = arm_cp_reset_ignore },
3699 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
3700 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3701 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
3702 .readfn = pmsav7_read, .writefn = pmsav7_write,
3703 .resetfn = arm_cp_reset_ignore },
3704 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
3705 .access = PL1_RW,
3706 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
3707 .writefn = pmsav7_rgnr_write,
3708 .resetfn = arm_cp_reset_ignore },
3709 REGINFO_SENTINEL
3710 };
3711
3712 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
3713 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
3714 .access = PL1_RW, .type = ARM_CP_ALIAS,
3715 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3716 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
3717 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
3718 .access = PL1_RW, .type = ARM_CP_ALIAS,
3719 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3720 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
3721 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
3722 .access = PL1_RW,
3723 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3724 .resetvalue = 0, },
3725 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
3726 .access = PL1_RW,
3727 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3728 .resetvalue = 0, },
3729 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3730 .access = PL1_RW,
3731 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
3732 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
3733 .access = PL1_RW,
3734 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
3735 /* Protection region base and size registers */
3736 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
3737 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3738 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
3739 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
3740 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3741 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
3742 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
3743 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3744 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
3745 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
3746 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3747 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
3748 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
3749 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3750 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
3751 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
3752 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3753 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
3754 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
3755 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3756 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
3757 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
3758 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3759 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
3760 REGINFO_SENTINEL
3761 };
3762
3763 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
3764 uint64_t value)
3765 {
3766 TCR *tcr = raw_ptr(env, ri);
3767 int maskshift = extract32(value, 0, 3);
3768
3769 if (!arm_feature(env, ARM_FEATURE_V8)) {
3770 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
3771 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3772 * using Long-desciptor translation table format */
3773 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
3774 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
3775 /* In an implementation that includes the Security Extensions
3776 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3777 * Short-descriptor translation table format.
3778 */
3779 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
3780 } else {
3781 value &= TTBCR_N;
3782 }
3783 }
3784
3785 /* Update the masks corresponding to the TCR bank being written
3786 * Note that we always calculate mask and base_mask, but
3787 * they are only used for short-descriptor tables (ie if EAE is 0);
3788 * for long-descriptor tables the TCR fields are used differently
3789 * and the mask and base_mask values are meaningless.
3790 */
3791 tcr->raw_tcr = value;
3792 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
3793 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
3794 }
3795
3796 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3797 uint64_t value)
3798 {
3799 ARMCPU *cpu = env_archcpu(env);
3800 TCR *tcr = raw_ptr(env, ri);
3801
3802 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3803 /* With LPAE the TTBCR could result in a change of ASID
3804 * via the TTBCR.A1 bit, so do a TLB flush.
3805 */
3806 tlb_flush(CPU(cpu));
3807 }
3808 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3809 value = deposit64(tcr->raw_tcr, 0, 32, value);
3810 vmsa_ttbcr_raw_write(env, ri, value);
3811 }
3812
3813 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3814 {
3815 TCR *tcr = raw_ptr(env, ri);
3816
3817 /* Reset both the TCR as well as the masks corresponding to the bank of
3818 * the TCR being reset.
3819 */
3820 tcr->raw_tcr = 0;
3821 tcr->mask = 0;
3822 tcr->base_mask = 0xffffc000u;
3823 }
3824
3825 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
3826 uint64_t value)
3827 {
3828 ARMCPU *cpu = env_archcpu(env);
3829 TCR *tcr = raw_ptr(env, ri);
3830
3831 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3832 tlb_flush(CPU(cpu));
3833 tcr->raw_tcr = value;
3834 }
3835
3836 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3837 uint64_t value)
3838 {
3839 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3840 if (cpreg_field_is_64bit(ri) &&
3841 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
3842 ARMCPU *cpu = env_archcpu(env);
3843 tlb_flush(CPU(cpu));
3844 }
3845 raw_write(env, ri, value);
3846 }
3847
3848 static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3849 uint64_t value)
3850 {
3851 /*
3852 * If we are running with E2&0 regime, then an ASID is active.
3853 * Flush if that might be changing. Note we're not checking
3854 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3855 * holds the active ASID, only checking the field that might.
3856 */
3857 if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
3858 (arm_hcr_el2_eff(env) & HCR_E2H)) {
3859 tlb_flush_by_mmuidx(env_cpu(env),
3860 ARMMMUIdxBit_E20_2 |
3861 ARMMMUIdxBit_E20_2_PAN |
3862 ARMMMUIdxBit_E20_0);
3863 }
3864 raw_write(env, ri, value);
3865 }
3866
3867 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3868 uint64_t value)
3869 {
3870 ARMCPU *cpu = env_archcpu(env);
3871 CPUState *cs = CPU(cpu);
3872
3873 /*
3874 * A change in VMID to the stage2 page table (Stage2) invalidates
3875 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3876 */
3877 if (raw_read(env, ri) != value) {
3878 tlb_flush_by_mmuidx(cs,
3879 ARMMMUIdxBit_E10_1 |
3880 ARMMMUIdxBit_E10_1_PAN |
3881 ARMMMUIdxBit_E10_0 |
3882 ARMMMUIdxBit_Stage2);
3883 raw_write(env, ri, value);
3884 }
3885 }
3886
3887 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
3888 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
3889 .access = PL1_RW, .type = ARM_CP_ALIAS,
3890 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
3891 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
3892 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
3893 .access = PL1_RW, .resetvalue = 0,
3894 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
3895 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
3896 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
3897 .access = PL1_RW, .resetvalue = 0,
3898 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
3899 offsetof(CPUARMState, cp15.dfar_ns) } },
3900 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
3901 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
3902 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
3903 .resetvalue = 0, },
3904 REGINFO_SENTINEL
3905 };
3906
3907 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
3908 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
3909 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
3910 .access = PL1_RW,
3911 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
3912 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
3913 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
3914 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3915 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
3916 offsetof(CPUARMState, cp15.ttbr0_ns) } },
3917 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
3918 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
3919 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3920 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
3921 offsetof(CPUARMState, cp15.ttbr1_ns) } },
3922 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
3923 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
3924 .access = PL1_RW, .writefn = vmsa_tcr_el12_write,
3925 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3926 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
3927 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
3928 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
3929 .raw_writefn = vmsa_ttbcr_raw_write,
3930 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
3931 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
3932 REGINFO_SENTINEL
3933 };
3934
3935 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3936 * qemu tlbs nor adjusting cached masks.
3937 */
3938 static const ARMCPRegInfo ttbcr2_reginfo = {
3939 .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
3940 .access = PL1_RW, .type = ARM_CP_ALIAS,
3941 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
3942 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
3943 };
3944
3945 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
3946 uint64_t value)
3947 {
3948 env->cp15.c15_ticonfig = value & 0xe7;
3949 /* The OS_TYPE bit in this register changes the reported CPUID! */
3950 env->cp15.c0_cpuid = (value & (1 << 5)) ?
3951 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
3952 }
3953
3954 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
3955 uint64_t value)
3956 {
3957 env->cp15.c15_threadid = value & 0xffff;
3958 }
3959
3960 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
3961 uint64_t value)
3962 {
3963 /* Wait-for-interrupt (deprecated) */
3964 cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
3965 }
3966
3967 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
3968 uint64_t value)
3969 {
3970 /* On OMAP there are registers indicating the max/min index of dcache lines
3971 * containing a dirty line; cache flush operations have to reset these.
3972 */
3973 env->cp15.c15_i_max = 0x000;
3974 env->cp15.c15_i_min = 0xff0;
3975 }
3976
3977 static const ARMCPRegInfo omap_cp_reginfo[] = {
3978 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
3979 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
3980 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
3981 .resetvalue = 0, },
3982 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
3983 .access = PL1_RW, .type = ARM_CP_NOP },
3984 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
3985 .access = PL1_RW,
3986 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
3987 .writefn = omap_ticonfig_write },
3988 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
3989 .access = PL1_RW,
3990 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
3991 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
3992 .access = PL1_RW, .resetvalue = 0xff0,
3993 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
3994 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
3995 .access = PL1_RW,
3996 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
3997 .writefn = omap_threadid_write },
3998 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
3999 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4000 .type = ARM_CP_NO_RAW,
4001 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
4002 /* TODO: Peripheral port remap register:
4003 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4004 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4005 * when MMU is off.
4006 */
4007 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
4008 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
4009 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
4010 .writefn = omap_cachemaint_write },
4011 { .name = "C9", .cp = 15, .crn = 9,
4012 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
4013 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
4014 REGINFO_SENTINEL
4015 };
4016
4017 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
4018 uint64_t value)
4019 {
4020 env->cp15.c15_cpar = value & 0x3fff;
4021 }
4022
4023 static const ARMCPRegInfo xscale_cp_reginfo[] = {
4024 { .name = "XSCALE_CPAR",
4025 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4026 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
4027 .writefn = xscale_cpar_write, },
4028 { .name = "XSCALE_AUXCR",
4029 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
4030 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
4031 .resetvalue = 0, },
4032 /* XScale specific cache-lockdown: since we have no cache we NOP these
4033 * and hope the guest does not really rely on cache behaviour.
4034 */
4035 { .name = "XSCALE_LOCK_ICACHE_LINE",
4036 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
4037 .access = PL1_W, .type = ARM_CP_NOP },
4038 { .name = "XSCALE_UNLOCK_ICACHE",
4039 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
4040 .access = PL1_W, .type = ARM_CP_NOP },
4041 { .name = "XSCALE_DCACHE_LOCK",
4042 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
4043 .access = PL1_RW, .type = ARM_CP_NOP },
4044 { .name = "XSCALE_UNLOCK_DCACHE",
4045 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
4046 .access = PL1_W, .type = ARM_CP_NOP },
4047 REGINFO_SENTINEL
4048 };
4049
4050 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
4051 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4052 * implementation of this implementation-defined space.
4053 * Ideally this should eventually disappear in favour of actually
4054 * implementing the correct behaviour for all cores.
4055 */
4056 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
4057 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
4058 .access = PL1_RW,
4059 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
4060 .resetvalue = 0 },
4061 REGINFO_SENTINEL
4062 };
4063
4064 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
4065 /* Cache status: RAZ because we have no cache so it's always clean */
4066 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
4067 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4068 .resetvalue = 0 },
4069 REGINFO_SENTINEL
4070 };
4071
4072 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
4073 /* We never have a a block transfer operation in progress */
4074 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
4075 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4076 .resetvalue = 0 },
4077 /* The cache ops themselves: these all NOP for QEMU */
4078 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
4079 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4080 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
4081 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4082 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
4083 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4084 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
4085 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4086 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
4087 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4088 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
4089 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4090 REGINFO_SENTINEL
4091 };
4092
4093 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
4094 /* The cache test-and-clean instructions always return (1 << 30)
4095 * to indicate that there are no dirty cache lines.
4096 */
4097 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
4098 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4099 .resetvalue = (1 << 30) },
4100 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
4101 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4102 .resetvalue = (1 << 30) },
4103 REGINFO_SENTINEL
4104 };
4105
4106 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
4107 /* Ignore ReadBuffer accesses */
4108 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
4109 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
4110 .access = PL1_RW, .resetvalue = 0,
4111 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
4112 REGINFO_SENTINEL
4113 };
4114
4115 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4116 {
4117 ARMCPU *cpu = env_archcpu(env);
4118 unsigned int cur_el = arm_current_el(env);
4119 bool secure = arm_is_secure(env);
4120
4121 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
4122 return env->cp15.vpidr_el2;
4123 }
4124 return raw_read(env, ri);
4125 }
4126
4127 static uint64_t mpidr_read_val(CPUARMState *env)
4128 {
4129 ARMCPU *cpu = env_archcpu(env);
4130 uint64_t mpidr = cpu->mp_affinity;
4131
4132 if (arm_feature(env, ARM_FEATURE_V7MP)) {
4133 mpidr |= (1U << 31);
4134 /* Cores which are uniprocessor (non-coherent)
4135 * but still implement the MP extensions set
4136 * bit 30. (For instance, Cortex-R5).
4137 */
4138 if (cpu->mp_is_up) {
4139 mpidr |= (1u << 30);
4140 }
4141 }
4142 return mpidr;
4143 }
4144
4145 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4146 {
4147 unsigned int cur_el = arm_current_el(env);
4148 bool secure = arm_is_secure(env);
4149
4150 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
4151 return env->cp15.vmpidr_el2;
4152 }
4153 return mpidr_read_val(env);
4154 }
4155
4156 static const ARMCPRegInfo lpae_cp_reginfo[] = {
4157 /* NOP AMAIR0/1 */
4158 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
4159 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
4160 .access = PL1_RW, .type = ARM_CP_CONST,
4161 .resetvalue = 0 },
4162 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4163 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
4164 .access = PL1_RW, .type = ARM_CP_CONST,
4165 .resetvalue = 0 },
4166 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
4167 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
4168 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
4169 offsetof(CPUARMState, cp15.par_ns)} },
4170 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
4171 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4172 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4173 offsetof(CPUARMState, cp15.ttbr0_ns) },
4174 .writefn = vmsa_ttbr_write, },
4175 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
4176 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4177 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4178 offsetof(CPUARMState, cp15.ttbr1_ns) },
4179 .writefn = vmsa_ttbr_write, },
4180 REGINFO_SENTINEL
4181 };
4182
4183 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4184 {
4185 return vfp_get_fpcr(env);
4186 }
4187
4188 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4189 uint64_t value)
4190 {
4191 vfp_set_fpcr(env, value);
4192 }
4193
4194 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4195 {
4196 return vfp_get_fpsr(env);
4197 }
4198
4199 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4200 uint64_t value)
4201 {
4202 vfp_set_fpsr(env, value);
4203 }
4204
4205 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
4206 bool isread)
4207 {
4208 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
4209 return CP_ACCESS_TRAP;
4210 }
4211 return CP_ACCESS_OK;
4212 }
4213
4214 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
4215 uint64_t value)
4216 {
4217 env->daif = value & PSTATE_DAIF;
4218 }
4219
4220 static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri)
4221 {
4222 return env->pstate & PSTATE_PAN;
4223 }
4224
4225 static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri,
4226 uint64_t value)
4227 {
4228 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN);
4229 }
4230
4231 static const ARMCPRegInfo pan_reginfo = {
4232 .name = "PAN", .state = ARM_CP_STATE_AA64,
4233 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3,
4234 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4235 .readfn = aa64_pan_read, .writefn = aa64_pan_write
4236 };
4237
4238 static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri)
4239 {
4240 return env->pstate & PSTATE_UAO;
4241 }
4242
4243 static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri,
4244 uint64_t value)
4245 {
4246 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO);
4247 }
4248
4249 static const ARMCPRegInfo uao_reginfo = {
4250 .name = "UAO", .state = ARM_CP_STATE_AA64,
4251 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
4252 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4253 .readfn = aa64_uao_read, .writefn = aa64_uao_write
4254 };
4255
4256 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
4257 const ARMCPRegInfo *ri,
4258 bool isread)
4259 {
4260 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
4261 * SCTLR_EL1.UCI is set.
4262 */
4263 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) {
4264 return CP_ACCESS_TRAP;
4265 }
4266 return CP_ACCESS_OK;
4267 }
4268
4269 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4270 * Page D4-1736 (DDI0487A.b)
4271 */
4272
4273 static int vae1_tlbmask(CPUARMState *env)
4274 {
4275 /* Since we exclude secure first, we may read HCR_EL2 directly. */
4276 if (arm_is_secure_below_el3(env)) {
4277 return ARMMMUIdxBit_SE10_1 |
4278 ARMMMUIdxBit_SE10_1_PAN |
4279 ARMMMUIdxBit_SE10_0;
4280 } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
4281 == (HCR_E2H | HCR_TGE)) {
4282 return ARMMMUIdxBit_E20_2 |
4283 ARMMMUIdxBit_E20_2_PAN |
4284 ARMMMUIdxBit_E20_0;
4285 } else {
4286 return ARMMMUIdxBit_E10_1 |
4287 ARMMMUIdxBit_E10_1_PAN |
4288 ARMMMUIdxBit_E10_0;
4289 }
4290 }
4291
4292 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4293 uint64_t value)
4294 {
4295 CPUState *cs = env_cpu(env);
4296 int mask = vae1_tlbmask(env);
4297
4298 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4299 }
4300
4301 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4302 uint64_t value)
4303 {
4304 CPUState *cs = env_cpu(env);
4305 int mask = vae1_tlbmask(env);
4306
4307 if (tlb_force_broadcast(env)) {
4308 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4309 } else {
4310 tlb_flush_by_mmuidx(cs, mask);
4311 }
4312 }
4313
4314 static int alle1_tlbmask(CPUARMState *env)
4315 {
4316 /*
4317 * Note that the 'ALL' scope must invalidate both stage 1 and
4318 * stage 2 translations, whereas most other scopes only invalidate
4319 * stage 1 translations.
4320 */
4321 if (arm_is_secure_below_el3(env)) {
4322 return ARMMMUIdxBit_SE10_1 |
4323 ARMMMUIdxBit_SE10_1_PAN |
4324 ARMMMUIdxBit_SE10_0;
4325 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
4326 return ARMMMUIdxBit_E10_1 |
4327 ARMMMUIdxBit_E10_1_PAN |
4328 ARMMMUIdxBit_E10_0 |
4329 ARMMMUIdxBit_Stage2;
4330 } else {
4331 return ARMMMUIdxBit_E10_1 |
4332 ARMMMUIdxBit_E10_1_PAN |
4333 ARMMMUIdxBit_E10_0;
4334 }
4335 }
4336
4337 static int e2_tlbmask(CPUARMState *env)
4338 {
4339 /* TODO: ARMv8.4-SecEL2 */
4340 return ARMMMUIdxBit_E20_0 |
4341 ARMMMUIdxBit_E20_2 |
4342 ARMMMUIdxBit_E20_2_PAN |
4343 ARMMMUIdxBit_E2;
4344 }
4345
4346 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4347 uint64_t value)
4348 {
4349 CPUState *cs = env_cpu(env);
4350 int mask = alle1_tlbmask(env);
4351
4352 tlb_flush_by_mmuidx(cs, mask);
4353 }
4354
4355 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4356 uint64_t value)
4357 {
4358 CPUState *cs = env_cpu(env);
4359 int mask = e2_tlbmask(env);
4360
4361 tlb_flush_by_mmuidx(cs, mask);
4362 }
4363
4364 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4365 uint64_t value)
4366 {
4367 ARMCPU *cpu = env_archcpu(env);
4368 CPUState *cs = CPU(cpu);
4369
4370 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
4371 }
4372
4373 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4374 uint64_t value)
4375 {
4376 CPUState *cs = env_cpu(env);
4377 int mask = alle1_tlbmask(env);
4378
4379 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4380 }
4381
4382 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4383 uint64_t value)
4384 {
4385 CPUState *cs = env_cpu(env);
4386 int mask = e2_tlbmask(env);
4387
4388 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4389 }
4390
4391 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4392 uint64_t value)
4393 {
4394 CPUState *cs = env_cpu(env);
4395
4396 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
4397 }
4398
4399 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4400 uint64_t value)
4401 {
4402 /* Invalidate by VA, EL2
4403 * Currently handles both VAE2 and VALE2, since we don't support
4404 * flush-last-level-only.
4405 */
4406 CPUState *cs = env_cpu(env);
4407 int mask = e2_tlbmask(env);
4408 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4409
4410 tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
4411 }
4412
4413 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4414 uint64_t value)
4415 {
4416 /* Invalidate by VA, EL3
4417 * Currently handles both VAE3 and VALE3, since we don't support
4418 * flush-last-level-only.
4419 */
4420 ARMCPU *cpu = env_archcpu(env);
4421 CPUState *cs = CPU(cpu);
4422 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4423
4424 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
4425 }
4426
4427 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4428 uint64_t value)
4429 {
4430 CPUState *cs = env_cpu(env);
4431 int mask = vae1_tlbmask(env);
4432 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4433
4434 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
4435 }
4436
4437 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4438 uint64_t value)
4439 {
4440 /* Invalidate by VA, EL1&0 (AArch64 version).
4441 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4442 * since we don't support flush-for-specific-ASID-only or
4443 * flush-last-level-only.
4444 */
4445 CPUState *cs = env_cpu(env);
4446 int mask = vae1_tlbmask(env);
4447 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4448
4449 if (tlb_force_broadcast(env)) {
4450 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
4451 } else {
4452 tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
4453 }
4454 }
4455
4456 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4457 uint64_t value)
4458 {
4459 CPUState *cs = env_cpu(env);
4460 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4461
4462 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
4463 ARMMMUIdxBit_E2);
4464 }
4465
4466 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4467 uint64_t value)
4468 {
4469 CPUState *cs = env_cpu(env);
4470 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4471
4472 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
4473 ARMMMUIdxBit_SE3);
4474 }
4475
4476 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4477 uint64_t value)
4478 {
4479 /* Invalidate by IPA. This has to invalidate any structures that
4480 * contain only stage 2 translation information, but does not need
4481 * to apply to structures that contain combined stage 1 and stage 2
4482 * translation information.
4483 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
4484 */
4485 ARMCPU *cpu = env_archcpu(env);
4486 CPUState *cs = CPU(cpu);
4487 uint64_t pageaddr;
4488
4489 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
4490 return;
4491 }
4492
4493 pageaddr = sextract64(value << 12, 0, 48);
4494
4495 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
4496 }
4497
4498 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4499 uint64_t value)
4500 {
4501 CPUState *cs = env_cpu(env);
4502 uint64_t pageaddr;
4503
4504 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
4505 return;
4506 }
4507
4508 pageaddr = sextract64(value << 12, 0, 48);
4509
4510 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
4511 ARMMMUIdxBit_Stage2);
4512 }
4513
4514 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
4515 bool isread)
4516 {
4517 int cur_el = arm_current_el(env);
4518
4519 if (cur_el < 2) {
4520 uint64_t hcr = arm_hcr_el2_eff(env);
4521
4522 if (cur_el == 0) {
4523 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
4524 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
4525 return CP_ACCESS_TRAP_EL2;
4526 }
4527 } else {
4528 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
4529 return CP_ACCESS_TRAP;
4530 }
4531 if (hcr & HCR_TDZ) {
4532 return CP_ACCESS_TRAP_EL2;
4533 }
4534 }
4535 } else if (hcr & HCR_TDZ) {
4536 return CP_ACCESS_TRAP_EL2;
4537 }
4538 }
4539 return CP_ACCESS_OK;
4540 }
4541
4542 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
4543 {
4544 ARMCPU *cpu = env_archcpu(env);
4545 int dzp_bit = 1 << 4;
4546
4547 /* DZP indicates whether DC ZVA access is allowed */
4548 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
4549 dzp_bit = 0;
4550 }
4551 return cpu->dcz_blocksize | dzp_bit;
4552 }
4553
4554 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4555 bool isread)
4556 {
4557 if (!(env->pstate & PSTATE_SP)) {
4558 /* Access to SP_EL0 is undefined if it's being used as
4559 * the stack pointer.
4560 */
4561 return CP_ACCESS_TRAP_UNCATEGORIZED;
4562 }
4563 return CP_ACCESS_OK;
4564 }
4565
4566 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
4567 {
4568 return env->pstate & PSTATE_SP;
4569 }
4570
4571 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
4572 {
4573 update_spsel(env, val);
4574 }
4575
4576 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4577 uint64_t value)
4578 {
4579 ARMCPU *cpu = env_archcpu(env);
4580
4581 if (raw_read(env, ri) == value) {
4582 /* Skip the TLB flush if nothing actually changed; Linux likes
4583 * to do a lot of pointless SCTLR writes.
4584 */
4585 return;
4586 }
4587
4588 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
4589 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4590 value &= ~SCTLR_M;
4591 }
4592
4593 raw_write(env, ri, value);
4594 /* ??? Lots of these bits are not implemented. */
4595 /* This may enable/disable the MMU, so do a TLB flush. */
4596 tlb_flush(CPU(cpu));
4597
4598 if (ri->type & ARM_CP_SUPPRESS_TB_END) {
4599 /*
4600 * Normally we would always end the TB on an SCTLR write; see the
4601 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4602 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4603 * of hflags from the translator, so do it here.
4604 */
4605 arm_rebuild_hflags(env);
4606 }
4607 }
4608
4609 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
4610 bool isread)
4611 {
4612 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
4613 return CP_ACCESS_TRAP_FP_EL2;
4614 }
4615 if (env->cp15.cptr_el[3] & CPTR_TFP) {
4616 return CP_ACCESS_TRAP_FP_EL3;
4617 }
4618 return CP_ACCESS_OK;
4619 }
4620
4621 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4622 uint64_t value)
4623 {
4624 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
4625 }
4626
4627 static const ARMCPRegInfo v8_cp_reginfo[] = {
4628 /* Minimal set of EL0-visible registers. This will need to be expanded
4629 * significantly for system emulation of AArch64 CPUs.
4630 */
4631 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
4632 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
4633 .access = PL0_RW, .type = ARM_CP_NZCV },
4634 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
4635 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
4636 .type = ARM_CP_NO_RAW,
4637 .access = PL0_RW, .accessfn = aa64_daif_access,
4638 .fieldoffset = offsetof(CPUARMState, daif),
4639 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
4640 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
4641 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
4642 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
4643 .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
4644 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
4645 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
4646 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
4647 .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
4648 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
4649 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
4650 .access = PL0_R, .type = ARM_CP_NO_RAW,
4651 .readfn = aa64_dczid_read },
4652 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
4653 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
4654 .access = PL0_W, .type = ARM_CP_DC_ZVA,
4655 #ifndef CONFIG_USER_ONLY
4656 /* Avoid overhead of an access check that always passes in user-mode */
4657 .accessfn = aa64_zva_access,
4658 #endif
4659 },
4660 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
4661 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
4662 .access = PL1_R, .type = ARM_CP_CURRENTEL },
4663 /* Cache ops: all NOPs since we don't emulate caches */
4664 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
4665 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
4666 .access = PL1_W, .type = ARM_CP_NOP },
4667 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
4668 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
4669 .access = PL1_W, .type = ARM_CP_NOP },
4670 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
4671 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
4672 .access = PL0_W, .type = ARM_CP_NOP,
4673 .accessfn = aa64_cacheop_access },
4674 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
4675 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
4676 .access = PL1_W, .type = ARM_CP_NOP },
4677 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
4678 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
4679 .access = PL1_W, .type = ARM_CP_NOP },
4680 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
4681 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
4682 .access = PL0_W, .type = ARM_CP_NOP,
4683 .accessfn = aa64_cacheop_access },
4684 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
4685 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
4686 .access = PL1_W, .type = ARM_CP_NOP },
4687 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
4688 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
4689 .access = PL0_W, .type = ARM_CP_NOP,
4690 .accessfn = aa64_cacheop_access },
4691 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
4692 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
4693 .access = PL0_W, .type = ARM_CP_NOP,
4694 .accessfn = aa64_cacheop_access },
4695 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
4696 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
4697 .access = PL1_W, .type = ARM_CP_NOP },
4698 /* TLBI operations */
4699 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
4700 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
4701 .access = PL1_W, .type = ARM_CP_NO_RAW,
4702 .writefn = tlbi_aa64_vmalle1is_write },
4703 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
4704 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
4705 .access = PL1_W, .type = ARM_CP_NO_RAW,
4706 .writefn = tlbi_aa64_vae1is_write },
4707 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
4708 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
4709 .access = PL1_W, .type = ARM_CP_NO_RAW,
4710 .writefn = tlbi_aa64_vmalle1is_write },
4711 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
4712 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
4713 .access = PL1_W, .type = ARM_CP_NO_RAW,
4714 .writefn = tlbi_aa64_vae1is_write },
4715 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
4716 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
4717 .access = PL1_W, .type = ARM_CP_NO_RAW,
4718 .writefn = tlbi_aa64_vae1is_write },
4719 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
4720 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
4721 .access = PL1_W, .type = ARM_CP_NO_RAW,
4722 .writefn = tlbi_aa64_vae1is_write },
4723 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
4724 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
4725 .access = PL1_W, .type = ARM_CP_NO_RAW,
4726 .writefn = tlbi_aa64_vmalle1_write },
4727 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
4728 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
4729 .access = PL1_W, .type = ARM_CP_NO_RAW,
4730 .writefn = tlbi_aa64_vae1_write },
4731 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
4732 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
4733 .access = PL1_W, .type = ARM_CP_NO_RAW,
4734 .writefn = tlbi_aa64_vmalle1_write },
4735 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
4736 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
4737 .access = PL1_W, .type = ARM_CP_NO_RAW,
4738 .writefn = tlbi_aa64_vae1_write },
4739 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
4740 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
4741 .access = PL1_W, .type = ARM_CP_NO_RAW,
4742 .writefn = tlbi_aa64_vae1_write },
4743 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
4744 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
4745 .access = PL1_W, .type = ARM_CP_NO_RAW,
4746 .writefn = tlbi_aa64_vae1_write },
4747 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
4748 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
4749 .access = PL2_W, .type = ARM_CP_NO_RAW,
4750 .writefn = tlbi_aa64_ipas2e1is_write },
4751 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
4752 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
4753 .access = PL2_W, .type = ARM_CP_NO_RAW,
4754 .writefn = tlbi_aa64_ipas2e1is_write },
4755 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
4756 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
4757 .access = PL2_W, .type = ARM_CP_NO_RAW,
4758 .writefn = tlbi_aa64_alle1is_write },
4759 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
4760 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
4761 .access = PL2_W, .type = ARM_CP_NO_RAW,
4762 .writefn = tlbi_aa64_alle1is_write },
4763 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
4764 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
4765 .access = PL2_W, .type = ARM_CP_NO_RAW,
4766 .writefn = tlbi_aa64_ipas2e1_write },
4767 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
4768 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
4769 .access = PL2_W, .type = ARM_CP_NO_RAW,
4770 .writefn = tlbi_aa64_ipas2e1_write },
4771 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
4772 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
4773 .access = PL2_W, .type = ARM_CP_NO_RAW,
4774 .writefn = tlbi_aa64_alle1_write },
4775 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
4776 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
4777 .access = PL2_W, .type = ARM_CP_NO_RAW,
4778 .writefn = tlbi_aa64_alle1is_write },
4779 #ifndef CONFIG_USER_ONLY
4780 /* 64 bit address translation operations */
4781 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
4782 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
4783 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4784 .writefn = ats_write64 },
4785 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
4786 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
4787 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4788 .writefn = ats_write64 },
4789 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
4790 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
4791 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4792 .writefn = ats_write64 },
4793 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
4794 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
4795 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4796 .writefn = ats_write64 },
4797 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
4798 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
4799 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4800 .writefn = ats_write64 },
4801 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
4802 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
4803 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4804 .writefn = ats_write64 },
4805 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
4806 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
4807 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4808 .writefn = ats_write64 },
4809 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
4810 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
4811 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4812 .writefn = ats_write64 },
4813 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4814 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
4815 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
4816 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4817 .writefn = ats_write64 },
4818 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
4819 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
4820 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4821 .writefn = ats_write64 },
4822 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
4823 .type = ARM_CP_ALIAS,
4824 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
4825 .access = PL1_RW, .resetvalue = 0,
4826 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
4827 .writefn = par_write },
4828 #endif
4829 /* TLB invalidate last level of translation table walk */
4830 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
4831 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
4832 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
4833 .type = ARM_CP_NO_RAW, .access = PL1_W,
4834 .writefn = tlbimvaa_is_write },
4835 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
4836 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
4837 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
4838 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
4839 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
4840 .type = ARM_CP_NO_RAW, .access = PL2_W,
4841 .writefn = tlbimva_hyp_write },
4842 { .name = "TLBIMVALHIS",
4843 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
4844 .type = ARM_CP_NO_RAW, .access = PL2_W,
4845 .writefn = tlbimva_hyp_is_write },
4846 { .name = "TLBIIPAS2",
4847 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
4848 .type = ARM_CP_NO_RAW, .access = PL2_W,
4849 .writefn = tlbiipas2_write },
4850 { .name = "TLBIIPAS2IS",
4851 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
4852 .type = ARM_CP_NO_RAW, .access = PL2_W,
4853 .writefn = tlbiipas2_is_write },
4854 { .name = "TLBIIPAS2L",
4855 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
4856 .type = ARM_CP_NO_RAW, .access = PL2_W,
4857 .writefn = tlbiipas2_write },
4858 { .name = "TLBIIPAS2LIS",
4859 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
4860 .type = ARM_CP_NO_RAW, .access = PL2_W,
4861 .writefn = tlbiipas2_is_write },
4862 /* 32 bit cache operations */
4863 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
4864 .type = ARM_CP_NOP, .access = PL1_W },
4865 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
4866 .type = ARM_CP_NOP, .access = PL1_W },
4867 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
4868 .type = ARM_CP_NOP, .access = PL1_W },
4869 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
4870 .type = ARM_CP_NOP, .access = PL1_W },
4871 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
4872 .type = ARM_CP_NOP, .access = PL1_W },
4873 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
4874 .type = ARM_CP_NOP, .access = PL1_W },
4875 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
4876 .type = ARM_CP_NOP, .access = PL1_W },
4877 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
4878 .type = ARM_CP_NOP, .access = PL1_W },
4879 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
4880 .type = ARM_CP_NOP, .access = PL1_W },
4881 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
4882 .type = ARM_CP_NOP, .access = PL1_W },
4883 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
4884 .type = ARM_CP_NOP, .access = PL1_W },
4885 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
4886 .type = ARM_CP_NOP, .access = PL1_W },
4887 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
4888 .type = ARM_CP_NOP, .access = PL1_W },
4889 /* MMU Domain access control / MPU write buffer control */
4890 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
4891 .access = PL1_RW, .resetvalue = 0,
4892 .writefn = dacr_write, .raw_writefn = raw_write,
4893 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
4894 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
4895 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
4896 .type = ARM_CP_ALIAS,
4897 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
4898 .access = PL1_RW,
4899 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
4900 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
4901 .type = ARM_CP_ALIAS,
4902 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
4903 .access = PL1_RW,
4904 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
4905 /* We rely on the access checks not allowing the guest to write to the
4906 * state field when SPSel indicates that it's being used as the stack
4907 * pointer.
4908 */
4909 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
4910 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
4911 .access = PL1_RW, .accessfn = sp_el0_access,
4912 .type = ARM_CP_ALIAS,
4913 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
4914 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
4915 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
4916 .access = PL2_RW, .type = ARM_CP_ALIAS,
4917 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
4918 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
4919 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
4920 .type = ARM_CP_NO_RAW,
4921 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
4922 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
4923 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
4924 .type = ARM_CP_ALIAS,
4925 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
4926 .access = PL2_RW, .accessfn = fpexc32_access },
4927 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
4928 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
4929 .access = PL2_RW, .resetvalue = 0,
4930 .writefn = dacr_write, .raw_writefn = raw_write,
4931 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
4932 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
4933 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
4934 .access = PL2_RW, .resetvalue = 0,
4935 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
4936 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
4937 .type = ARM_CP_ALIAS,
4938 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
4939 .access = PL2_RW,
4940 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
4941 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
4942 .type = ARM_CP_ALIAS,
4943 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
4944 .access = PL2_RW,
4945 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
4946 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
4947 .type = ARM_CP_ALIAS,
4948 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
4949 .access = PL2_RW,
4950 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
4951 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
4952 .type = ARM_CP_ALIAS,
4953 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
4954 .access = PL2_RW,
4955 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
4956 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
4957 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
4958 .resetvalue = 0,
4959 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
4960 { .name = "SDCR", .type = ARM_CP_ALIAS,
4961 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
4962 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
4963 .writefn = sdcr_write,
4964 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
4965 REGINFO_SENTINEL
4966 };
4967
4968 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4969 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
4970 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
4971 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
4972 .access = PL2_RW,
4973 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
4974 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
4975 .type = ARM_CP_NO_RAW,
4976 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
4977 .access = PL2_RW,
4978 .type = ARM_CP_CONST, .resetvalue = 0 },
4979 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
4980 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
4981 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
4982 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
4983 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
4984 .access = PL2_RW,
4985 .type = ARM_CP_CONST, .resetvalue = 0 },
4986 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
4987 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
4988 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
4989 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
4990 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
4991 .access = PL2_RW, .type = ARM_CP_CONST,
4992 .resetvalue = 0 },
4993 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
4994 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
4995 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
4996 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
4997 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
4998 .access = PL2_RW, .type = ARM_CP_CONST,
4999 .resetvalue = 0 },
5000 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
5001 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5002 .access = PL2_RW, .type = ARM_CP_CONST,
5003 .resetvalue = 0 },
5004 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5005 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5006 .access = PL2_RW, .type = ARM_CP_CONST,
5007 .resetvalue = 0 },
5008 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5009 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5010 .access = PL2_RW, .type = ARM_CP_CONST,
5011 .resetvalue = 0 },
5012 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5013 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5014 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5015 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
5016 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5017 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
5018 .type = ARM_CP_CONST, .resetvalue = 0 },
5019 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5020 .cp = 15, .opc1 = 6, .crm = 2,
5021 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5022 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
5023 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5024 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5025 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5026 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5027 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5028 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5029 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5030 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5031 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5032 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5033 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5034 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5035 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5036 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5037 .resetvalue = 0 },
5038 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5039 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5040 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5041 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5042 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5043 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5044 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5045 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5046 .resetvalue = 0 },
5047 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5048 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5049 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5050 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5051 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5052 .resetvalue = 0 },
5053 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5054 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5055 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5056 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5057 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5058 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5059 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5060 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5061 .access = PL2_RW, .accessfn = access_tda,
5062 .type = ARM_CP_CONST, .resetvalue = 0 },
5063 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
5064 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5065 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
5066 .type = ARM_CP_CONST, .resetvalue = 0 },
5067 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5068 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5069 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5070 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5071 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5072 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5073 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5074 .type = ARM_CP_CONST,
5075 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5076 .access = PL2_RW, .resetvalue = 0 },
5077 REGINFO_SENTINEL
5078 };
5079
5080 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5081 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
5082 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5083 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5084 .access = PL2_RW,
5085 .type = ARM_CP_CONST, .resetvalue = 0 },
5086 REGINFO_SENTINEL
5087 };
5088
5089 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
5090 {
5091 ARMCPU *cpu = env_archcpu(env);
5092 /* Begin with bits defined in base ARMv8.0. */
5093 uint64_t valid_mask = MAKE_64BIT_MASK(0, 34);
5094
5095 if (arm_feature(env, ARM_FEATURE_EL3)) {
5096 valid_mask &= ~HCR_HCD;
5097 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
5098 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5099 * However, if we're using the SMC PSCI conduit then QEMU is
5100 * effectively acting like EL3 firmware and so the guest at
5101 * EL2 should retain the ability to prevent EL1 from being
5102 * able to make SMC calls into the ersatz firmware, so in
5103 * that case HCR.TSC should be read/write.
5104 */
5105 valid_mask &= ~HCR_TSC;
5106 }
5107 if (cpu_isar_feature(aa64_vh, cpu)) {
5108 valid_mask |= HCR_E2H;
5109 }
5110 if (cpu_isar_feature(aa64_lor, cpu)) {
5111 valid_mask |= HCR_TLOR;
5112 }
5113 if (cpu_isar_feature(aa64_pauth, cpu)) {
5114 valid_mask |= HCR_API | HCR_APK;
5115 }
5116
5117 /* Clear RES0 bits. */
5118 value &= valid_mask;
5119
5120 /* These bits change the MMU setup:
5121 * HCR_VM enables stage 2 translation
5122 * HCR_PTW forbids certain page-table setups
5123 * HCR_DC Disables stage1 and enables stage2 translation
5124 */
5125 if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
5126 tlb_flush(CPU(cpu));
5127 }
5128 env->cp15.hcr_el2 = value;
5129
5130 /*
5131 * Updates to VI and VF require us to update the status of
5132 * virtual interrupts, which are the logical OR of these bits
5133 * and the state of the input lines from the GIC. (This requires
5134 * that we have the iothread lock, which is done by marking the
5135 * reginfo structs as ARM_CP_IO.)
5136 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5137 * possible for it to be taken immediately, because VIRQ and
5138 * VFIQ are masked unless running at EL0 or EL1, and HCR
5139 * can only be written at EL2.
5140 */
5141 g_assert(qemu_mutex_iothread_locked());
5142 arm_cpu_update_virq(cpu);
5143 arm_cpu_update_vfiq(cpu);
5144 }
5145
5146 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
5147 uint64_t value)
5148 {
5149 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5150 value = deposit64(env->cp15.hcr_el2, 32, 32, value);
5151 hcr_write(env, NULL, value);
5152 }
5153
5154 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
5155 uint64_t value)
5156 {
5157 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5158 value = deposit64(env->cp15.hcr_el2, 0, 32, value);
5159 hcr_write(env, NULL, value);
5160 }
5161
5162 /*
5163 * Return the effective value of HCR_EL2.
5164 * Bits that are not included here:
5165 * RW (read from SCR_EL3.RW as needed)
5166 */
5167 uint64_t arm_hcr_el2_eff(CPUARMState *env)
5168 {
5169 uint64_t ret = env->cp15.hcr_el2;
5170
5171 if (arm_is_secure_below_el3(env)) {
5172 /*
5173 * "This register has no effect if EL2 is not enabled in the
5174 * current Security state". This is ARMv8.4-SecEL2 speak for
5175 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5176 *
5177 * Prior to that, the language was "In an implementation that
5178 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5179 * as if this field is 0 for all purposes other than a direct
5180 * read or write access of HCR_EL2". With lots of enumeration
5181 * on a per-field basis. In current QEMU, this is condition
5182 * is arm_is_secure_below_el3.
5183 *
5184 * Since the v8.4 language applies to the entire register, and
5185 * appears to be backward compatible, use that.
5186 */
5187 ret = 0;
5188 } else if (ret & HCR_TGE) {
5189 /* These bits are up-to-date as of ARMv8.4. */
5190 if (ret & HCR_E2H) {
5191 ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
5192 HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
5193 HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
5194 HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE);
5195 } else {
5196 ret |= HCR_FMO | HCR_IMO | HCR_AMO;
5197 }
5198 ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
5199 HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
5200 HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
5201 HCR_TLOR);
5202 }
5203
5204 return ret;
5205 }
5206
5207 static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
5208 uint64_t value)
5209 {
5210 /*
5211 * For A-profile AArch32 EL3, if NSACR.CP10
5212 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5213 */
5214 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5215 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5216 value &= ~(0x3 << 10);
5217 value |= env->cp15.cptr_el[2] & (0x3 << 10);
5218 }
5219 env->cp15.cptr_el[2] = value;
5220 }
5221
5222 static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
5223 {
5224 /*
5225 * For A-profile AArch32 EL3, if NSACR.CP10
5226 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5227 */
5228 uint64_t value = env->cp15.cptr_el[2];
5229
5230 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5231 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5232 value |= 0x3 << 10;
5233 }
5234 return value;
5235 }
5236
5237 static const ARMCPRegInfo el2_cp_reginfo[] = {
5238 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
5239 .type = ARM_CP_IO,
5240 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5241 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
5242 .writefn = hcr_write },
5243 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5244 .type = ARM_CP_ALIAS | ARM_CP_IO,
5245 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5246 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
5247 .writefn = hcr_writelow },
5248 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5249 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5250 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5251 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
5252 .type = ARM_CP_ALIAS,
5253 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
5254 .access = PL2_RW,
5255 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
5256 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5257 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5258 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
5259 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5260 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5261 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
5262 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5263 .type = ARM_CP_ALIAS,
5264 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5265 .access = PL2_RW,
5266 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) },
5267 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
5268 .type = ARM_CP_ALIAS,
5269 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
5270 .access = PL2_RW,
5271 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
5272 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
5273 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5274 .access = PL2_RW, .writefn = vbar_write,
5275 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
5276 .resetvalue = 0 },
5277 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
5278 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
5279 .access = PL3_RW, .type = ARM_CP_ALIAS,
5280 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
5281 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5282 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5283 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
5284 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]),
5285 .readfn = cptr_el2_read, .writefn = cptr_el2_write },
5286 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5287 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5288 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
5289 .resetvalue = 0 },
5290 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
5291 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
5292 .access = PL2_RW, .type = ARM_CP_ALIAS,
5293 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
5294 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5295 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5296 .access = PL2_RW, .type = ARM_CP_CONST,
5297 .resetvalue = 0 },
5298 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5299 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
5300 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5301 .access = PL2_RW, .type = ARM_CP_CONST,
5302 .resetvalue = 0 },
5303 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5304 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5305 .access = PL2_RW, .type = ARM_CP_CONST,
5306 .resetvalue = 0 },
5307 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5308 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5309 .access = PL2_RW, .type = ARM_CP_CONST,
5310 .resetvalue = 0 },
5311 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5312 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5313 .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
5314 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5315 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
5316 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5317 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5318 .type = ARM_CP_ALIAS,
5319 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5320 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5321 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
5322 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5323 .access = PL2_RW,
5324 /* no .writefn needed as this can't cause an ASID change;
5325 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5326 */
5327 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5328 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5329 .cp = 15, .opc1 = 6, .crm = 2,
5330 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5331 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5332 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
5333 .writefn = vttbr_write },
5334 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5335 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5336 .access = PL2_RW, .writefn = vttbr_write,
5337 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
5338 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5339 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5340 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
5341 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
5342 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5343 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5344 .access = PL2_RW, .resetvalue = 0,
5345 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
5346 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5347 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5348 .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
5349 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5350 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5351 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5352 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5353 { .name = "TLBIALLNSNH",
5354 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
5355 .type = ARM_CP_NO_RAW, .access = PL2_W,
5356 .writefn = tlbiall_nsnh_write },
5357 { .name = "TLBIALLNSNHIS",
5358 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
5359 .type = ARM_CP_NO_RAW, .access = PL2_W,
5360 .writefn = tlbiall_nsnh_is_write },
5361 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5362 .type = ARM_CP_NO_RAW, .access = PL2_W,
5363 .writefn = tlbiall_hyp_write },
5364 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5365 .type = ARM_CP_NO_RAW, .access = PL2_W,
5366 .writefn = tlbiall_hyp_is_write },
5367 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5368 .type = ARM_CP_NO_RAW, .access = PL2_W,
5369 .writefn = tlbimva_hyp_write },
5370 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5371 .type = ARM_CP_NO_RAW, .access = PL2_W,
5372 .writefn = tlbimva_hyp_is_write },
5373 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
5374 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5375 .type = ARM_CP_NO_RAW, .access = PL2_W,
5376 .writefn = tlbi_aa64_alle2_write },
5377 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
5378 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5379 .type = ARM_CP_NO_RAW, .access = PL2_W,
5380 .writefn = tlbi_aa64_vae2_write },
5381 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
5382 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5383 .access = PL2_W, .type = ARM_CP_NO_RAW,
5384 .writefn = tlbi_aa64_vae2_write },
5385 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
5386 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5387 .access = PL2_W, .type = ARM_CP_NO_RAW,
5388 .writefn = tlbi_aa64_alle2is_write },
5389 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
5390 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5391 .type = ARM_CP_NO_RAW, .access = PL2_W,
5392 .writefn = tlbi_aa64_vae2is_write },
5393 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
5394 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5395 .access = PL2_W, .type = ARM_CP_NO_RAW,
5396 .writefn = tlbi_aa64_vae2is_write },
5397 #ifndef CONFIG_USER_ONLY
5398 /* Unlike the other EL2-related AT operations, these must
5399 * UNDEF from EL3 if EL2 is not implemented, which is why we
5400 * define them here rather than with the rest of the AT ops.
5401 */
5402 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
5403 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5404 .access = PL2_W, .accessfn = at_s1e2_access,
5405 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
5406 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
5407 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5408 .access = PL2_W, .accessfn = at_s1e2_access,
5409 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
5410 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5411 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5412 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5413 * to behave as if SCR.NS was 1.
5414 */
5415 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5416 .access = PL2_W,
5417 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
5418 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5419 .access = PL2_W,
5420 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
5421 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5422 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5423 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5424 * reset values as IMPDEF. We choose to reset to 3 to comply with
5425 * both ARMv7 and ARMv8.
5426 */
5427 .access = PL2_RW, .resetvalue = 3,
5428 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
5429 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5430 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5431 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
5432 .writefn = gt_cntvoff_write,
5433 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5434 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5435 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
5436 .writefn = gt_cntvoff_write,
5437 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5438 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5439 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5440 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5441 .type = ARM_CP_IO, .access = PL2_RW,
5442 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5443 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5444 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5445 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
5446 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5447 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5448 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5449 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
5450 .resetfn = gt_hyp_timer_reset,
5451 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
5452 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5453 .type = ARM_CP_IO,
5454 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5455 .access = PL2_RW,
5456 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
5457 .resetvalue = 0,
5458 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
5459 #endif
5460 /* The only field of MDCR_EL2 that has a defined architectural reset value
5461 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5462 * don't implement any PMU event counters, so using zero as a reset
5463 * value for MDCR_EL2 is okay
5464 */
5465 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5466 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5467 .access = PL2_RW, .resetvalue = 0,
5468 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
5469 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
5470 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5471 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5472 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5473 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
5474 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5475 .access = PL2_RW,
5476 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5477 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5478 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5479 .access = PL2_RW,
5480 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
5481 REGINFO_SENTINEL
5482 };
5483
5484 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
5485 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5486 .type = ARM_CP_ALIAS | ARM_CP_IO,
5487 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5488 .access = PL2_RW,
5489 .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
5490 .writefn = hcr_writehigh },
5491 REGINFO_SENTINEL
5492 };
5493
5494 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
5495 bool isread)
5496 {
5497 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5498 * At Secure EL1 it traps to EL3.
5499 */
5500 if (arm_current_el(env) == 3) {
5501 return CP_ACCESS_OK;
5502 }
5503 if (arm_is_secure_below_el3(env)) {
5504 return CP_ACCESS_TRAP_EL3;
5505 }
5506 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5507 if (isread) {
5508 return CP_ACCESS_OK;
5509 }
5510 return CP_ACCESS_TRAP_UNCATEGORIZED;
5511 }
5512
5513 static const ARMCPRegInfo el3_cp_reginfo[] = {
5514 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
5515 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
5516 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
5517 .resetvalue = 0, .writefn = scr_write },
5518 { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
5519 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
5520 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5521 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
5522 .writefn = scr_write },
5523 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
5524 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
5525 .access = PL3_RW, .resetvalue = 0,
5526 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
5527 { .name = "SDER",
5528 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
5529 .access = PL3_RW, .resetvalue = 0,
5530 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
5531 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
5532 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5533 .writefn = vbar_write, .resetvalue = 0,
5534 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
5535 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
5536 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
5537 .access = PL3_RW, .resetvalue = 0,
5538 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
5539 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
5540 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
5541 .access = PL3_RW,
5542 /* no .writefn needed as this can't cause an ASID change;
5543 * we must provide a .raw_writefn and .resetfn because we handle
5544 * reset and migration for the AArch32 TTBCR(S), which might be
5545 * using mask and base_mask.
5546 */
5547 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
5548 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
5549 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
5550 .type = ARM_CP_ALIAS,
5551 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
5552 .access = PL3_RW,
5553 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
5554 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
5555 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
5556 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
5557 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
5558 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
5559 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
5560 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
5561 .type = ARM_CP_ALIAS,
5562 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
5563 .access = PL3_RW,
5564 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
5565 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
5566 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
5567 .access = PL3_RW, .writefn = vbar_write,
5568 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
5569 .resetvalue = 0 },
5570 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
5571 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
5572 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
5573 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
5574 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
5575 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
5576 .access = PL3_RW, .resetvalue = 0,
5577 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
5578 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
5579 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
5580 .access = PL3_RW, .type = ARM_CP_CONST,
5581 .resetvalue = 0 },
5582 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
5583 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
5584 .access = PL3_RW, .type = ARM_CP_CONST,
5585 .resetvalue = 0 },
5586 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
5587 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
5588 .access = PL3_RW, .type = ARM_CP_CONST,
5589 .resetvalue = 0 },
5590 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
5591 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
5592 .access = PL3_W, .type = ARM_CP_NO_RAW,
5593 .writefn = tlbi_aa64_alle3is_write },
5594 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
5595 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
5596 .access = PL3_W, .type = ARM_CP_NO_RAW,
5597 .writefn = tlbi_aa64_vae3is_write },
5598 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
5599 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
5600 .access = PL3_W, .type = ARM_CP_NO_RAW,
5601 .writefn = tlbi_aa64_vae3is_write },
5602 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
5603 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
5604 .access = PL3_W, .type = ARM_CP_NO_RAW,
5605 .writefn = tlbi_aa64_alle3_write },
5606 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
5607 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
5608 .access = PL3_W, .type = ARM_CP_NO_RAW,
5609 .writefn = tlbi_aa64_vae3_write },
5610 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
5611 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
5612 .access = PL3_W, .type = ARM_CP_NO_RAW,
5613 .writefn = tlbi_aa64_vae3_write },
5614 REGINFO_SENTINEL
5615 };
5616
5617 #ifndef CONFIG_USER_ONLY
5618 /* Test if system register redirection is to occur in the current state. */
5619 static bool redirect_for_e2h(CPUARMState *env)
5620 {
5621 return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H);
5622 }
5623
5624 static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
5625 {
5626 CPReadFn *readfn;
5627
5628 if (redirect_for_e2h(env)) {
5629 /* Switch to the saved EL2 version of the register. */
5630 ri = ri->opaque;
5631 readfn = ri->readfn;
5632 } else {
5633 readfn = ri->orig_readfn;
5634 }
5635 if (readfn == NULL) {
5636 readfn = raw_read;
5637 }
5638 return readfn(env, ri);
5639 }
5640
5641 static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
5642 uint64_t value)
5643 {
5644 CPWriteFn *writefn;
5645
5646 if (redirect_for_e2h(env)) {
5647 /* Switch to the saved EL2 version of the register. */
5648 ri = ri->opaque;
5649 writefn = ri->writefn;
5650 } else {
5651 writefn = ri->orig_writefn;
5652 }
5653 if (writefn == NULL) {
5654 writefn = raw_write;
5655 }
5656 writefn(env, ri, value);
5657 }
5658
5659 static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
5660 {
5661 struct E2HAlias {
5662 uint32_t src_key, dst_key, new_key;
5663 const char *src_name, *dst_name, *new_name;
5664 bool (*feature)(const ARMISARegisters *id);
5665 };
5666
5667 #define K(op0, op1, crn, crm, op2) \
5668 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5669
5670 static const struct E2HAlias aliases[] = {
5671 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5672 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5673 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5674 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5675 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5676 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5677 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5678 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5679 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5680 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5681 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5682 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5683 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5684 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5685 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5686 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5687 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5688 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5689 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5690 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5691 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5692 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5693 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5694 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5695 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5696 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5697 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5698 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5699 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5700 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5701 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5702 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5703
5704 /*
5705 * Note that redirection of ZCR is mentioned in the description
5706 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5707 * not in the summary table.
5708 */
5709 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5710 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
5711
5712 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5713 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5714 };
5715 #undef K
5716
5717 size_t i;
5718
5719 for (i = 0; i < ARRAY_SIZE(aliases); i++) {
5720 const struct E2HAlias *a = &aliases[i];
5721 ARMCPRegInfo *src_reg, *dst_reg;
5722
5723 if (a->feature && !a->feature(&cpu->isar)) {
5724 continue;
5725 }
5726
5727 src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
5728 dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
5729 g_assert(src_reg != NULL);
5730 g_assert(dst_reg != NULL);
5731
5732 /* Cross-compare names to detect typos in the keys. */
5733 g_assert(strcmp(src_reg->name, a->src_name) == 0);
5734 g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
5735
5736 /* None of the core system registers use opaque; we will. */
5737 g_assert(src_reg->opaque == NULL);
5738
5739 /* Create alias before redirection so we dup the right data. */
5740 if (a->new_key) {
5741 ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
5742 uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
5743 bool ok;
5744
5745 new_reg->name = a->new_name;
5746 new_reg->type |= ARM_CP_ALIAS;
5747 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5748 new_reg->access &= PL2_RW | PL3_RW;
5749
5750 ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
5751 g_assert(ok);
5752 }
5753
5754 src_reg->opaque = dst_reg;
5755 src_reg->orig_readfn = src_reg->readfn ?: raw_read;
5756 src_reg->orig_writefn = src_reg->writefn ?: raw_write;
5757 if (!src_reg->raw_readfn) {
5758 src_reg->raw_readfn = raw_read;
5759 }
5760 if (!src_reg->raw_writefn) {
5761 src_reg->raw_writefn = raw_write;
5762 }
5763 src_reg->readfn = el2_e2h_read;
5764 src_reg->writefn = el2_e2h_write;
5765 }
5766 }
5767 #endif
5768
5769 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
5770 bool isread)
5771 {
5772 int cur_el = arm_current_el(env);
5773
5774 if (cur_el < 2) {
5775 uint64_t hcr = arm_hcr_el2_eff(env);
5776
5777 if (cur_el == 0) {
5778 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
5779 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
5780 return CP_ACCESS_TRAP_EL2;
5781 }
5782 } else {
5783 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
5784 return CP_ACCESS_TRAP;
5785 }
5786 if (hcr & HCR_TID2) {
5787 return CP_ACCESS_TRAP_EL2;
5788 }
5789 }
5790 } else if (hcr & HCR_TID2) {
5791 return CP_ACCESS_TRAP_EL2;
5792 }
5793 }
5794
5795 if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
5796 return CP_ACCESS_TRAP_EL2;
5797 }
5798
5799 return CP_ACCESS_OK;
5800 }
5801
5802 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
5803 uint64_t value)
5804 {
5805 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5806 * read via a bit in OSLSR_EL1.
5807 */
5808 int oslock;
5809
5810 if (ri->state == ARM_CP_STATE_AA32) {
5811 oslock = (value == 0xC5ACCE55);
5812 } else {
5813 oslock = value & 1;
5814 }
5815
5816 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
5817 }
5818
5819 static const ARMCPRegInfo debug_cp_reginfo[] = {
5820 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5821 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5822 * unlike DBGDRAR it is never accessible from EL0.
5823 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5824 * accessor.
5825 */
5826 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
5827 .access = PL0_R, .accessfn = access_tdra,
5828 .type = ARM_CP_CONST, .resetvalue = 0 },
5829 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
5830 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
5831 .access = PL1_R, .accessfn = access_tdra,
5832 .type = ARM_CP_CONST, .resetvalue = 0 },
5833 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
5834 .access = PL0_R, .accessfn = access_tdra,
5835 .type = ARM_CP_CONST, .resetvalue = 0 },
5836 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5837 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
5838 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
5839 .access = PL1_RW, .accessfn = access_tda,
5840 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
5841 .resetvalue = 0 },
5842 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5843 * We don't implement the configurable EL0 access.
5844 */
5845 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
5846 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
5847 .type = ARM_CP_ALIAS,
5848 .access = PL1_R, .accessfn = access_tda,
5849 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
5850 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
5851 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
5852 .access = PL1_W, .type = ARM_CP_NO_RAW,
5853 .accessfn = access_tdosa,
5854 .writefn = oslar_write },
5855 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
5856 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
5857 .access = PL1_R, .resetvalue = 10,
5858 .accessfn = access_tdosa,
5859 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
5860 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5861 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
5862 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
5863 .access = PL1_RW, .accessfn = access_tdosa,
5864 .type = ARM_CP_NOP },
5865 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5866 * implement vector catch debug events yet.
5867 */
5868 { .name = "DBGVCR",
5869 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
5870 .access = PL1_RW, .accessfn = access_tda,
5871 .type = ARM_CP_NOP },
5872 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5873 * to save and restore a 32-bit guest's DBGVCR)
5874 */
5875 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
5876 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
5877 .access = PL2_RW, .accessfn = access_tda,
5878 .type = ARM_CP_NOP },
5879 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5880 * Channel but Linux may try to access this register. The 32-bit
5881 * alias is DBGDCCINT.
5882 */
5883 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
5884 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
5885 .access = PL1_RW, .accessfn = access_tda,
5886 .type = ARM_CP_NOP },
5887 REGINFO_SENTINEL
5888 };
5889
5890 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
5891 /* 64 bit access versions of the (dummy) debug registers */
5892 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
5893 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
5894 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
5895 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
5896 REGINFO_SENTINEL
5897 };
5898
5899 /* Return the exception level to which exceptions should be taken
5900 * via SVEAccessTrap. If an exception should be routed through
5901 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5902 * take care of raising that exception.
5903 * C.f. the ARM pseudocode function CheckSVEEnabled.
5904 */
5905 int sve_exception_el(CPUARMState *env, int el)
5906 {
5907 #ifndef CONFIG_USER_ONLY
5908 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
5909
5910 if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
5911 bool disabled = false;
5912
5913 /* The CPACR.ZEN controls traps to EL1:
5914 * 0, 2 : trap EL0 and EL1 accesses
5915 * 1 : trap only EL0 accesses
5916 * 3 : trap no accesses
5917 */
5918 if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
5919 disabled = true;
5920 } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
5921 disabled = el == 0;
5922 }
5923 if (disabled) {
5924 /* route_to_el2 */
5925 return hcr_el2 & HCR_TGE ? 2 : 1;
5926 }
5927
5928 /* Check CPACR.FPEN. */
5929 if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
5930 disabled = true;
5931 } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
5932 disabled = el == 0;
5933 }
5934 if (disabled) {
5935 return 0;
5936 }
5937 }
5938
5939 /* CPTR_EL2. Since TZ and TFP are positive,
5940 * they will be zero when EL2 is not present.
5941 */
5942 if (el <= 2 && !arm_is_secure_below_el3(env)) {
5943 if (env->cp15.cptr_el[2] & CPTR_TZ) {
5944 return 2;
5945 }
5946 if (env->cp15.cptr_el[2] & CPTR_TFP) {
5947 return 0;
5948 }
5949 }
5950
5951 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5952 if (arm_feature(env, ARM_FEATURE_EL3)
5953 && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
5954 return 3;
5955 }
5956 #endif
5957 return 0;
5958 }
5959
5960 static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
5961 {
5962 uint32_t end_len;
5963
5964 end_len = start_len &= 0xf;
5965 if (!test_bit(start_len, cpu->sve_vq_map)) {
5966 end_len = find_last_bit(cpu->sve_vq_map, start_len);
5967 assert(end_len < start_len);
5968 }
5969 return end_len;
5970 }
5971
5972 /*
5973 * Given that SVE is enabled, return the vector length for EL.
5974 */
5975 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
5976 {
5977 ARMCPU *cpu = env_archcpu(env);
5978 uint32_t zcr_len = cpu->sve_max_vq - 1;
5979
5980 if (el <= 1) {
5981 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
5982 }
5983 if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
5984 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
5985 }
5986 if (arm_feature(env, ARM_FEATURE_EL3)) {
5987 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
5988 }
5989
5990 return sve_zcr_get_valid_len(cpu, zcr_len);
5991 }
5992
5993 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
5994 uint64_t value)
5995 {
5996 int cur_el = arm_current_el(env);
5997 int old_len = sve_zcr_len_for_el(env, cur_el);
5998 int new_len;
5999
6000 /* Bits other than [3:0] are RAZ/WI. */
6001 QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
6002 raw_write(env, ri, value & 0xf);
6003
6004 /*
6005 * Because we arrived here, we know both FP and SVE are enabled;
6006 * otherwise we would have trapped access to the ZCR_ELn register.
6007 */
6008 new_len = sve_zcr_len_for_el(env, cur_el);
6009 if (new_len < old_len) {
6010 aarch64_sve_narrow_vq(env, new_len + 1);
6011 }
6012 }
6013
6014 static const ARMCPRegInfo zcr_el1_reginfo = {
6015 .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
6016 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
6017 .access = PL1_RW, .type = ARM_CP_SVE,
6018 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
6019 .writefn = zcr_write, .raw_writefn = raw_write
6020 };
6021
6022 static const ARMCPRegInfo zcr_el2_reginfo = {
6023 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6024 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6025 .access = PL2_RW, .type = ARM_CP_SVE,
6026 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
6027 .writefn = zcr_write, .raw_writefn = raw_write
6028 };
6029
6030 static const ARMCPRegInfo zcr_no_el2_reginfo = {
6031 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6032 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6033 .access = PL2_RW, .type = ARM_CP_SVE,
6034 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
6035 };
6036
6037 static const ARMCPRegInfo zcr_el3_reginfo = {
6038 .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
6039 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
6040 .access = PL3_RW, .type = ARM_CP_SVE,
6041 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
6042 .writefn = zcr_write, .raw_writefn = raw_write
6043 };
6044
6045 void hw_watchpoint_update(ARMCPU *cpu, int n)
6046 {
6047 CPUARMState *env = &cpu->env;
6048 vaddr len = 0;
6049 vaddr wvr = env->cp15.dbgwvr[n];
6050 uint64_t wcr = env->cp15.dbgwcr[n];
6051 int mask;
6052 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
6053
6054 if (env->cpu_watchpoint[n]) {
6055 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
6056 env->cpu_watchpoint[n] = NULL;
6057 }
6058
6059 if (!extract64(wcr, 0, 1)) {
6060 /* E bit clear : watchpoint disabled */
6061 return;
6062 }
6063
6064 switch (extract64(wcr, 3, 2)) {
6065 case 0:
6066 /* LSC 00 is reserved and must behave as if the wp is disabled */
6067 return;
6068 case 1:
6069 flags |= BP_MEM_READ;
6070 break;
6071 case 2:
6072 flags |= BP_MEM_WRITE;
6073 break;
6074 case 3:
6075 flags |= BP_MEM_ACCESS;
6076 break;
6077 }
6078
6079 /* Attempts to use both MASK and BAS fields simultaneously are
6080 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6081 * thus generating a watchpoint for every byte in the masked region.
6082 */
6083 mask = extract64(wcr, 24, 4);
6084 if (mask == 1 || mask == 2) {
6085 /* Reserved values of MASK; we must act as if the mask value was
6086 * some non-reserved value, or as if the watchpoint were disabled.
6087 * We choose the latter.
6088 */
6089 return;
6090 } else if (mask) {
6091 /* Watchpoint covers an aligned area up to 2GB in size */
6092 len = 1ULL << mask;
6093 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6094 * whether the watchpoint fires when the unmasked bits match; we opt
6095 * to generate the exceptions.
6096 */
6097 wvr &= ~(len - 1);
6098 } else {
6099 /* Watchpoint covers bytes defined by the byte address select bits */
6100 int bas = extract64(wcr, 5, 8);
6101 int basstart;
6102
6103 if (bas == 0) {
6104 /* This must act as if the watchpoint is disabled */
6105 return;
6106 }
6107
6108 if (extract64(wvr, 2, 1)) {
6109 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6110 * ignored, and BAS[3:0] define which bytes to watch.
6111 */
6112 bas &= 0xf;
6113 }
6114 /* The BAS bits are supposed to be programmed to indicate a contiguous
6115 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6116 * we fire for each byte in the word/doubleword addressed by the WVR.
6117 * We choose to ignore any non-zero bits after the first range of 1s.
6118 */
6119 basstart = ctz32(bas);
6120 len = cto32(bas >> basstart);
6121 wvr += basstart;
6122 }
6123
6124 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
6125 &env->cpu_watchpoint[n]);
6126 }
6127
6128 void hw_watchpoint_update_all(ARMCPU *cpu)
6129 {
6130 int i;
6131 CPUARMState *env = &cpu->env;
6132
6133 /* Completely clear out existing QEMU watchpoints and our array, to
6134 * avoid possible stale entries following migration load.
6135 */
6136 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
6137 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
6138
6139 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
6140 hw_watchpoint_update(cpu, i);
6141 }
6142 }
6143
6144 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6145 uint64_t value)
6146 {
6147 ARMCPU *cpu = env_archcpu(env);
6148 int i = ri->crm;
6149
6150 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6151 * register reads and behaves as if values written are sign extended.
6152 * Bits [1:0] are RES0.
6153 */
6154 value = sextract64(value, 0, 49) & ~3ULL;
6155
6156 raw_write(env, ri, value);
6157 hw_watchpoint_update(cpu, i);
6158 }
6159
6160 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6161 uint64_t value)
6162 {
6163 ARMCPU *cpu = env_archcpu(env);
6164 int i = ri->crm;
6165
6166 raw_write(env, ri, value);
6167 hw_watchpoint_update(cpu, i);
6168 }
6169
6170 void hw_breakpoint_update(ARMCPU *cpu, int n)
6171 {
6172 CPUARMState *env = &cpu->env;
6173 uint64_t bvr = env->cp15.dbgbvr[n];
6174 uint64_t bcr = env->cp15.dbgbcr[n];
6175 vaddr addr;
6176 int bt;
6177 int flags = BP_CPU;
6178
6179 if (env->cpu_breakpoint[n]) {
6180 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
6181 env->cpu_breakpoint[n] = NULL;
6182 }
6183
6184 if (!extract64(bcr, 0, 1)) {
6185 /* E bit clear : watchpoint disabled */
6186 return;
6187 }
6188
6189 bt = extract64(bcr, 20, 4);
6190
6191 switch (bt) {
6192 case 4: /* unlinked address mismatch (reserved if AArch64) */
6193 case 5: /* linked address mismatch (reserved if AArch64) */
6194 qemu_log_mask(LOG_UNIMP,
6195 "arm: address mismatch breakpoint types not implemented\n");
6196 return;
6197 case 0: /* unlinked address match */
6198 case 1: /* linked address match */
6199 {
6200 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6201 * we behave as if the register was sign extended. Bits [1:0] are
6202 * RES0. The BAS field is used to allow setting breakpoints on 16
6203 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6204 * a bp will fire if the addresses covered by the bp and the addresses
6205 * covered by the insn overlap but the insn doesn't start at the
6206 * start of the bp address range. We choose to require the insn and
6207 * the bp to have the same address. The constraints on writing to
6208 * BAS enforced in dbgbcr_write mean we have only four cases:
6209 * 0b0000 => no breakpoint
6210 * 0b0011 => breakpoint on addr
6211 * 0b1100 => breakpoint on addr + 2
6212 * 0b1111 => breakpoint on addr
6213 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6214 */
6215 int bas = extract64(bcr, 5, 4);
6216 addr = sextract64(bvr, 0, 49) & ~3ULL;
6217 if (bas == 0) {
6218 return;
6219 }
6220 if (bas == 0xc) {
6221 addr += 2;
6222 }
6223 break;
6224 }
6225 case 2: /* unlinked context ID match */
6226 case 8: /* unlinked VMID match (reserved if no EL2) */
6227 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6228 qemu_log_mask(LOG_UNIMP,
6229 "arm: unlinked context breakpoint types not implemented\n");
6230 return;
6231 case 9: /* linked VMID match (reserved if no EL2) */
6232 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6233 case 3: /* linked context ID match */
6234 default:
6235 /* We must generate no events for Linked context matches (unless
6236 * they are linked to by some other bp/wp, which is handled in
6237 * updates for the linking bp/wp). We choose to also generate no events
6238 * for reserved values.
6239 */
6240 return;
6241 }
6242
6243 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
6244 }
6245
6246 void hw_breakpoint_update_all(ARMCPU *cpu)
6247 {
6248 int i;
6249 CPUARMState *env = &cpu->env;
6250
6251 /* Completely clear out existing QEMU breakpoints and our array, to
6252 * avoid possible stale entries following migration load.
6253 */
6254 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
6255 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
6256
6257 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
6258 hw_breakpoint_update(cpu, i);
6259 }
6260 }
6261
6262 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6263 uint64_t value)
6264 {
6265 ARMCPU *cpu = env_archcpu(env);
6266 int i = ri->crm;
6267
6268 raw_write(env, ri, value);
6269 hw_breakpoint_update(cpu, i);
6270 }
6271
6272 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6273 uint64_t value)
6274 {
6275 ARMCPU *cpu = env_archcpu(env);
6276 int i = ri->crm;
6277
6278 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6279 * copy of BAS[0].
6280 */
6281 value = deposit64(value, 6, 1, extract64(value, 5, 1));
6282 value = deposit64(value, 8, 1, extract64(value, 7, 1));
6283
6284 raw_write(env, ri, value);
6285 hw_breakpoint_update(cpu, i);
6286 }
6287
6288 static void define_debug_regs(ARMCPU *cpu)
6289 {
6290 /* Define v7 and v8 architectural debug registers.
6291 * These are just dummy implementations for now.
6292 */
6293 int i;
6294 int wrps, brps, ctx_cmps;
6295 ARMCPRegInfo dbgdidr = {
6296 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
6297 .access = PL0_R, .accessfn = access_tda,
6298 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
6299 };
6300
6301 /* Note that all these register fields hold "number of Xs minus 1". */
6302 brps = arm_num_brps(cpu);
6303 wrps = arm_num_wrps(cpu);
6304 ctx_cmps = arm_num_ctx_cmps(cpu);
6305
6306 assert(ctx_cmps <= brps);
6307
6308 define_one_arm_cp_reg(cpu, &dbgdidr);
6309 define_arm_cp_regs(cpu, debug_cp_reginfo);
6310
6311 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
6312 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
6313 }
6314
6315 for (i = 0; i < brps; i++) {
6316 ARMCPRegInfo dbgregs[] = {
6317 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
6318 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
6319 .access = PL1_RW, .accessfn = access_tda,
6320 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
6321 .writefn = dbgbvr_write, .raw_writefn = raw_write
6322 },
6323 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
6324 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
6325 .access = PL1_RW, .accessfn = access_tda,
6326 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
6327 .writefn = dbgbcr_write, .raw_writefn = raw_write
6328 },
6329 REGINFO_SENTINEL
6330 };
6331 define_arm_cp_regs(cpu, dbgregs);
6332 }
6333
6334 for (i = 0; i < wrps; i++) {
6335 ARMCPRegInfo dbgregs[] = {
6336 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
6337 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
6338 .access = PL1_RW, .accessfn = access_tda,
6339 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
6340 .writefn = dbgwvr_write, .raw_writefn = raw_write
6341 },
6342 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
6343 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
6344 .access = PL1_RW, .accessfn = access_tda,
6345 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
6346 .writefn = dbgwcr_write, .raw_writefn = raw_write
6347 },
6348 REGINFO_SENTINEL
6349 };
6350 define_arm_cp_regs(cpu, dbgregs);
6351 }
6352 }
6353
6354 static void define_pmu_regs(ARMCPU *cpu)
6355 {
6356 /*
6357 * v7 performance monitor control register: same implementor
6358 * field as main ID register, and we implement four counters in
6359 * addition to the cycle count register.
6360 */
6361 unsigned int i, pmcrn = 4;
6362 ARMCPRegInfo pmcr = {
6363 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
6364 .access = PL0_RW,
6365 .type = ARM_CP_IO | ARM_CP_ALIAS,
6366 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
6367 .accessfn = pmreg_access, .writefn = pmcr_write,
6368 .raw_writefn = raw_write,
6369 };
6370 ARMCPRegInfo pmcr64 = {
6371 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
6372 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
6373 .access = PL0_RW, .accessfn = pmreg_access,
6374 .type = ARM_CP_IO,
6375 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
6376 .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
6377 PMCRLC,
6378 .writefn = pmcr_write, .raw_writefn = raw_write,
6379 };
6380 define_one_arm_cp_reg(cpu, &pmcr);
6381 define_one_arm_cp_reg(cpu, &pmcr64);
6382 for (i = 0; i < pmcrn; i++) {
6383 char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
6384 char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
6385 char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
6386 char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
6387 ARMCPRegInfo pmev_regs[] = {
6388 { .name = pmevcntr_name, .cp = 15, .crn = 14,
6389 .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6390 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6391 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6392 .accessfn = pmreg_access },
6393 { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
6394 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
6395 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6396 .type = ARM_CP_IO,
6397 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6398 .raw_readfn = pmevcntr_rawread,
6399 .raw_writefn = pmevcntr_rawwrite },
6400 { .name = pmevtyper_name, .cp = 15, .crn = 14,
6401 .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6402 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6403 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6404 .accessfn = pmreg_access },
6405 { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
6406 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
6407 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6408 .type = ARM_CP_IO,
6409 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6410 .raw_writefn = pmevtyper_rawwrite },
6411 REGINFO_SENTINEL
6412 };
6413 define_arm_cp_regs(cpu, pmev_regs);
6414 g_free(pmevcntr_name);
6415 g_free(pmevcntr_el0_name);
6416 g_free(pmevtyper_name);
6417 g_free(pmevtyper_el0_name);
6418 }
6419 if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
6420 ARMCPRegInfo v81_pmu_regs[] = {
6421 { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
6422 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
6423 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6424 .resetvalue = extract64(cpu->pmceid0, 32, 32) },
6425 { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
6426 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
6427 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6428 .resetvalue = extract64(cpu->pmceid1, 32, 32) },
6429 REGINFO_SENTINEL
6430 };
6431 define_arm_cp_regs(cpu, v81_pmu_regs);
6432 }
6433 if (cpu_isar_feature(any_pmu_8_4, cpu)) {
6434 static const ARMCPRegInfo v84_pmmir = {
6435 .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
6436 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
6437 .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6438 .resetvalue = 0
6439 };
6440 define_one_arm_cp_reg(cpu, &v84_pmmir);
6441 }
6442 }
6443
6444 /* We don't know until after realize whether there's a GICv3
6445 * attached, and that is what registers the gicv3 sysregs.
6446 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6447 * at runtime.
6448 */
6449 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
6450 {
6451 ARMCPU *cpu = env_archcpu(env);
6452 uint64_t pfr1 = cpu->id_pfr1;
6453
6454 if (env->gicv3state) {
6455 pfr1 |= 1 << 28;
6456 }
6457 return pfr1;
6458 }
6459
6460 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
6461 {
6462 ARMCPU *cpu = env_archcpu(env);
6463 uint64_t pfr0 = cpu->isar.id_aa64pfr0;
6464
6465 if (env->gicv3state) {
6466 pfr0 |= 1 << 24;
6467 }
6468 return pfr0;
6469 }
6470
6471 /* Shared logic between LORID and the rest of the LOR* registers.
6472 * Secure state has already been delt with.
6473 */
6474 static CPAccessResult access_lor_ns(CPUARMState *env)
6475 {
6476 int el = arm_current_el(env);
6477
6478 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) {
6479 return CP_ACCESS_TRAP_EL2;
6480 }
6481 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) {
6482 return CP_ACCESS_TRAP_EL3;
6483 }
6484 return CP_ACCESS_OK;
6485 }
6486
6487 static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
6488 bool isread)
6489 {
6490 if (arm_is_secure_below_el3(env)) {
6491 /* Access ok in secure mode. */
6492 return CP_ACCESS_OK;
6493 }
6494 return access_lor_ns(env);
6495 }
6496
6497 static CPAccessResult access_lor_other(CPUARMState *env,
6498 const ARMCPRegInfo *ri, bool isread)
6499 {
6500 if (arm_is_secure_below_el3(env)) {
6501 /* Access denied in secure mode. */
6502 return CP_ACCESS_TRAP;
6503 }
6504 return access_lor_ns(env);
6505 }
6506
6507 /*
6508 * A trivial implementation of ARMv8.1-LOR leaves all of these
6509 * registers fixed at 0, which indicates that there are zero
6510 * supported Limited Ordering regions.
6511 */
6512 static const ARMCPRegInfo lor_reginfo[] = {
6513 { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
6514 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
6515 .access = PL1_RW, .accessfn = access_lor_other,
6516 .type = ARM_CP_CONST, .resetvalue = 0 },
6517 { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
6518 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
6519 .access = PL1_RW, .accessfn = access_lor_other,
6520 .type = ARM_CP_CONST, .resetvalue = 0 },
6521 { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
6522 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
6523 .access = PL1_RW, .accessfn = access_lor_other,
6524 .type = ARM_CP_CONST, .resetvalue = 0 },
6525 { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
6526 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
6527 .access = PL1_RW, .accessfn = access_lor_other,
6528 .type = ARM_CP_CONST, .resetvalue = 0 },
6529 { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
6530 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
6531 .access = PL1_R, .accessfn = access_lorid,
6532 .type = ARM_CP_CONST, .resetvalue = 0 },
6533 REGINFO_SENTINEL
6534 };
6535
6536 #ifdef TARGET_AARCH64
6537 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
6538 bool isread)
6539 {
6540 int el = arm_current_el(env);
6541
6542 if (el < 2 &&
6543 arm_feature(env, ARM_FEATURE_EL2) &&
6544 !(arm_hcr_el2_eff(env) & HCR_APK)) {
6545 return CP_ACCESS_TRAP_EL2;
6546 }
6547 if (el < 3 &&
6548 arm_feature(env, ARM_FEATURE_EL3) &&
6549 !(env->cp15.scr_el3 & SCR_APK)) {
6550 return CP_ACCESS_TRAP_EL3;
6551 }
6552 return CP_ACCESS_OK;
6553 }
6554
6555 static const ARMCPRegInfo pauth_reginfo[] = {
6556 { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6557 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
6558 .access = PL1_RW, .accessfn = access_pauth,
6559 .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
6560 { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6561 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
6562 .access = PL1_RW, .accessfn = access_pauth,
6563 .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
6564 { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6565 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
6566 .access = PL1_RW, .accessfn = access_pauth,
6567 .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
6568 { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6569 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
6570 .access = PL1_RW, .accessfn = access_pauth,
6571 .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
6572 { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6573 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
6574 .access = PL1_RW, .accessfn = access_pauth,
6575 .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
6576 { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6577 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
6578 .access = PL1_RW, .accessfn = access_pauth,
6579 .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
6580 { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6581 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
6582 .access = PL1_RW, .accessfn = access_pauth,
6583 .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
6584 { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6585 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
6586 .access = PL1_RW, .accessfn = access_pauth,
6587 .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
6588 { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6589 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
6590 .access = PL1_RW, .accessfn = access_pauth,
6591 .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
6592 { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6593 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
6594 .access = PL1_RW, .accessfn = access_pauth,
6595 .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
6596 REGINFO_SENTINEL
6597 };
6598
6599 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
6600 {
6601 Error *err = NULL;
6602 uint64_t ret;
6603
6604 /* Success sets NZCV = 0000. */
6605 env->NF = env->CF = env->VF = 0, env->ZF = 1;
6606
6607 if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) {
6608 /*
6609 * ??? Failed, for unknown reasons in the crypto subsystem.
6610 * The best we can do is log the reason and return the
6611 * timed-out indication to the guest. There is no reason
6612 * we know to expect this failure to be transitory, so the
6613 * guest may well hang retrying the operation.
6614 */
6615 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
6616 ri->name, error_get_pretty(err));
6617 error_free(err);
6618
6619 env->ZF = 0; /* NZCF = 0100 */
6620 return 0;
6621 }
6622 return ret;
6623 }
6624
6625 /* We do not support re-seeding, so the two registers operate the same. */
6626 static const ARMCPRegInfo rndr_reginfo[] = {
6627 { .name = "RNDR", .state = ARM_CP_STATE_AA64,
6628 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6629 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0,
6630 .access = PL0_R, .readfn = rndr_readfn },
6631 { .name = "RNDRRS", .state = ARM_CP_STATE_AA64,
6632 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6633 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
6634 .access = PL0_R, .readfn = rndr_readfn },
6635 REGINFO_SENTINEL
6636 };
6637
6638 #ifndef CONFIG_USER_ONLY
6639 static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
6640 uint64_t value)
6641 {
6642 ARMCPU *cpu = env_archcpu(env);
6643 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6644 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF);
6645 uint64_t vaddr_in = (uint64_t) value;
6646 uint64_t vaddr = vaddr_in & ~(dline_size - 1);
6647 void *haddr;
6648 int mem_idx = cpu_mmu_index(env, false);
6649
6650 /* This won't be crossing page boundaries */
6651 haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
6652 if (haddr) {
6653
6654 ram_addr_t offset;
6655 MemoryRegion *mr;
6656
6657 /* RCU lock is already being held */
6658 mr = memory_region_from_host(haddr, &offset);
6659
6660 if (mr) {
6661 memory_region_do_writeback(mr, offset, dline_size);
6662 }
6663 }
6664 }
6665
6666 static const ARMCPRegInfo dcpop_reg[] = {
6667 { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
6668 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
6669 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
6670 .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn },
6671 REGINFO_SENTINEL
6672 };
6673
6674 static const ARMCPRegInfo dcpodp_reg[] = {
6675 { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
6676 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
6677 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
6678 .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn },
6679 REGINFO_SENTINEL
6680 };
6681 #endif /*CONFIG_USER_ONLY*/
6682
6683 #endif
6684
6685 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
6686 bool isread)
6687 {
6688 int el = arm_current_el(env);
6689
6690 if (el == 0) {
6691 uint64_t sctlr = arm_sctlr(env, el);
6692 if (!(sctlr & SCTLR_EnRCTX)) {
6693 return CP_ACCESS_TRAP;
6694 }
6695 } else if (el == 1) {
6696 uint64_t hcr = arm_hcr_el2_eff(env);
6697 if (hcr & HCR_NV) {
6698 return CP_ACCESS_TRAP_EL2;
6699 }
6700 }
6701 return CP_ACCESS_OK;
6702 }
6703
6704 static const ARMCPRegInfo predinv_reginfo[] = {
6705 { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
6706 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
6707 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
6708 { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
6709 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
6710 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
6711 { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
6712 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
6713 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
6714 /*
6715 * Note the AArch32 opcodes have a different OPC1.
6716 */
6717 { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
6718 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
6719 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
6720 { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
6721 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
6722 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
6723 { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
6724 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
6725 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
6726 REGINFO_SENTINEL
6727 };
6728
6729 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
6730 bool isread)
6731 {
6732 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
6733 return CP_ACCESS_TRAP_EL2;
6734 }
6735
6736 return CP_ACCESS_OK;
6737 }
6738
6739 static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
6740 bool isread)
6741 {
6742 if (arm_feature(env, ARM_FEATURE_V8)) {
6743 return access_aa64_tid3(env, ri, isread);
6744 }
6745
6746 return CP_ACCESS_OK;
6747 }
6748
6749 static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
6750 bool isread)
6751 {
6752 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) {
6753 return CP_ACCESS_TRAP_EL2;
6754 }
6755
6756 return CP_ACCESS_OK;
6757 }
6758
6759 static const ARMCPRegInfo jazelle_regs[] = {
6760 { .name = "JIDR",
6761 .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
6762 .access = PL1_R, .accessfn = access_jazelle,
6763 .type = ARM_CP_CONST, .resetvalue = 0 },
6764 { .name = "JOSCR",
6765 .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
6766 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
6767 { .name = "JMCR",
6768 .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
6769 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
6770 REGINFO_SENTINEL
6771 };
6772
6773 static const ARMCPRegInfo vhe_reginfo[] = {
6774 { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
6775 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
6776 .access = PL2_RW,
6777 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
6778 { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
6779 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
6780 .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
6781 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
6782 #ifndef CONFIG_USER_ONLY
6783 { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
6784 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2,
6785 .fieldoffset =
6786 offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval),
6787 .type = ARM_CP_IO, .access = PL2_RW,
6788 .writefn = gt_hv_cval_write, .raw_writefn = raw_write },
6789 { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
6790 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0,
6791 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
6792 .resetfn = gt_hv_timer_reset,
6793 .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write },
6794 { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH,
6795 .type = ARM_CP_IO,
6796 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1,
6797 .access = PL2_RW,
6798 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl),
6799 .writefn = gt_hv_ctl_write, .raw_writefn = raw_write },
6800 { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
6801 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
6802 .type = ARM_CP_IO | ARM_CP_ALIAS,
6803 .access = PL2_RW, .accessfn = e2h_access,
6804 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
6805 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
6806 { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
6807 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
6808 .type = ARM_CP_IO | ARM_CP_ALIAS,
6809 .access = PL2_RW, .accessfn = e2h_access,
6810 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
6811 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
6812 { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64,
6813 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0,
6814 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
6815 .access = PL2_RW, .accessfn = e2h_access,
6816 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write },
6817 { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64,
6818 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0,
6819 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
6820 .access = PL2_RW, .accessfn = e2h_access,
6821 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write },
6822 { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64,
6823 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2,
6824 .type = ARM_CP_IO | ARM_CP_ALIAS,
6825 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
6826 .access = PL2_RW, .accessfn = e2h_access,
6827 .writefn = gt_phys_cval_write, .raw_writefn = raw_write },
6828 { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
6829 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
6830 .type = ARM_CP_IO | ARM_CP_ALIAS,
6831 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
6832 .access = PL2_RW, .accessfn = e2h_access,
6833 .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
6834 #endif
6835 REGINFO_SENTINEL
6836 };
6837
6838 #ifndef CONFIG_USER_ONLY
6839 static const ARMCPRegInfo ats1e1_reginfo[] = {
6840 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
6841 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
6842 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
6843 .writefn = ats_write64 },
6844 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
6845 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
6846 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
6847 .writefn = ats_write64 },
6848 REGINFO_SENTINEL
6849 };
6850
6851 static const ARMCPRegInfo ats1cp_reginfo[] = {
6852 { .name = "ATS1CPRP",
6853 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
6854 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
6855 .writefn = ats_write },
6856 { .name = "ATS1CPWP",
6857 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
6858 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
6859 .writefn = ats_write },
6860 REGINFO_SENTINEL
6861 };
6862 #endif
6863
6864 /*
6865 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
6866 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
6867 * is non-zero, which is never for ARMv7, optionally in ARMv8
6868 * and mandatorily for ARMv8.2 and up.
6869 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
6870 * implementation is RAZ/WI we can ignore this detail, as we
6871 * do for ACTLR.
6872 */
6873 static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
6874 { .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
6875 .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
6876 .access = PL1_RW, .type = ARM_CP_CONST,
6877 .resetvalue = 0 },
6878 { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
6879 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
6880 .access = PL2_RW, .type = ARM_CP_CONST,
6881 .resetvalue = 0 },
6882 REGINFO_SENTINEL
6883 };
6884
6885 void register_cp_regs_for_features(ARMCPU *cpu)
6886 {
6887 /* Register all the coprocessor registers based on feature bits */
6888 CPUARMState *env = &cpu->env;
6889 if (arm_feature(env, ARM_FEATURE_M)) {
6890 /* M profile has no coprocessor registers */
6891 return;
6892 }
6893
6894 define_arm_cp_regs(cpu, cp_reginfo);
6895 if (!arm_feature(env, ARM_FEATURE_V8)) {
6896 /* Must go early as it is full of wildcards that may be
6897 * overridden by later definitions.
6898 */
6899 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
6900 }
6901
6902 if (arm_feature(env, ARM_FEATURE_V6)) {
6903 /* The ID registers all have impdef reset values */
6904 ARMCPRegInfo v6_idregs[] = {
6905 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
6906 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
6907 .access = PL1_R, .type = ARM_CP_CONST,
6908 .accessfn = access_aa32_tid3,
6909 .resetvalue = cpu->id_pfr0 },
6910 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
6911 * the value of the GIC field until after we define these regs.
6912 */
6913 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
6914 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
6915 .access = PL1_R, .type = ARM_CP_NO_RAW,
6916 .accessfn = access_aa32_tid3,
6917 .readfn = id_pfr1_read,
6918 .writefn = arm_cp_write_ignore },
6919 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
6920 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
6921 .access = PL1_R, .type = ARM_CP_CONST,
6922 .accessfn = access_aa32_tid3,
6923 .resetvalue = cpu->isar.id_dfr0 },
6924 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
6925 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
6926 .access = PL1_R, .type = ARM_CP_CONST,
6927 .accessfn = access_aa32_tid3,
6928 .resetvalue = cpu->id_afr0 },
6929 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
6930 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
6931 .access = PL1_R, .type = ARM_CP_CONST,
6932 .accessfn = access_aa32_tid3,
6933 .resetvalue = cpu->isar.id_mmfr0 },
6934 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
6935 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
6936 .access = PL1_R, .type = ARM_CP_CONST,
6937 .accessfn = access_aa32_tid3,
6938 .resetvalue = cpu->isar.id_mmfr1 },
6939 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
6940 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
6941 .access = PL1_R, .type = ARM_CP_CONST,
6942 .accessfn = access_aa32_tid3,
6943 .resetvalue = cpu->isar.id_mmfr2 },
6944 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
6945 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
6946 .access = PL1_R, .type = ARM_CP_CONST,
6947 .accessfn = access_aa32_tid3,
6948 .resetvalue = cpu->isar.id_mmfr3 },
6949 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
6950 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
6951 .access = PL1_R, .type = ARM_CP_CONST,
6952 .accessfn = access_aa32_tid3,
6953 .resetvalue = cpu->isar.id_isar0 },
6954 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
6955 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
6956 .access = PL1_R, .type = ARM_CP_CONST,
6957 .accessfn = access_aa32_tid3,
6958 .resetvalue = cpu->isar.id_isar1 },
6959 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
6960 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
6961 .access = PL1_R, .type = ARM_CP_CONST,
6962 .accessfn = access_aa32_tid3,
6963 .resetvalue = cpu->isar.id_isar2 },
6964 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
6965 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
6966 .access = PL1_R, .type = ARM_CP_CONST,
6967 .accessfn = access_aa32_tid3,
6968 .resetvalue = cpu->isar.id_isar3 },
6969 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
6970 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
6971 .access = PL1_R, .type = ARM_CP_CONST,
6972 .accessfn = access_aa32_tid3,
6973 .resetvalue = cpu->isar.id_isar4 },
6974 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
6975 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
6976 .access = PL1_R, .type = ARM_CP_CONST,
6977 .accessfn = access_aa32_tid3,
6978 .resetvalue = cpu->isar.id_isar5 },
6979 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
6980 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
6981 .access = PL1_R, .type = ARM_CP_CONST,
6982 .accessfn = access_aa32_tid3,
6983 .resetvalue = cpu->isar.id_mmfr4 },
6984 { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
6985 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
6986 .access = PL1_R, .type = ARM_CP_CONST,
6987 .accessfn = access_aa32_tid3,
6988 .resetvalue = cpu->isar.id_isar6 },
6989 REGINFO_SENTINEL
6990 };
6991 define_arm_cp_regs(cpu, v6_idregs);
6992 define_arm_cp_regs(cpu, v6_cp_reginfo);
6993 } else {
6994 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
6995 }
6996 if (arm_feature(env, ARM_FEATURE_V6K)) {
6997 define_arm_cp_regs(cpu, v6k_cp_reginfo);
6998 }
6999 if (arm_feature(env, ARM_FEATURE_V7MP) &&
7000 !arm_feature(env, ARM_FEATURE_PMSA)) {
7001 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
7002 }
7003 if (arm_feature(env, ARM_FEATURE_V7VE)) {
7004 define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
7005 }
7006 if (arm_feature(env, ARM_FEATURE_V7)) {
7007 ARMCPRegInfo clidr = {
7008 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
7009 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
7010 .access = PL1_R, .type = ARM_CP_CONST,
7011 .accessfn = access_aa64_tid2,
7012 .resetvalue = cpu->clidr
7013 };
7014 define_one_arm_cp_reg(cpu, &clidr);
7015 define_arm_cp_regs(cpu, v7_cp_reginfo);
7016 define_debug_regs(cpu);
7017 define_pmu_regs(cpu);
7018 } else {
7019 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
7020 }
7021 if (arm_feature(env, ARM_FEATURE_V8)) {
7022 /* AArch64 ID registers, which all have impdef reset values.
7023 * Note that within the ID register ranges the unused slots
7024 * must all RAZ, not UNDEF; future architecture versions may
7025 * define new registers here.
7026 */
7027 ARMCPRegInfo v8_idregs[] = {
7028 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
7029 * know the right value for the GIC field until after we
7030 * define these regs.
7031 */
7032 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
7033 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
7034 .access = PL1_R, .type = ARM_CP_NO_RAW,
7035 .accessfn = access_aa64_tid3,
7036 .readfn = id_aa64pfr0_read,
7037 .writefn = arm_cp_write_ignore },
7038 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
7039 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
7040 .access = PL1_R, .type = ARM_CP_CONST,
7041 .accessfn = access_aa64_tid3,
7042 .resetvalue = cpu->isar.id_aa64pfr1},
7043 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7044 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
7045 .access = PL1_R, .type = ARM_CP_CONST,
7046 .accessfn = access_aa64_tid3,
7047 .resetvalue = 0 },
7048 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7049 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
7050 .access = PL1_R, .type = ARM_CP_CONST,
7051 .accessfn = access_aa64_tid3,
7052 .resetvalue = 0 },
7053 { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
7054 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
7055 .access = PL1_R, .type = ARM_CP_CONST,
7056 .accessfn = access_aa64_tid3,
7057 /* At present, only SVEver == 0 is defined anyway. */
7058 .resetvalue = 0 },
7059 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7060 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
7061 .access = PL1_R, .type = ARM_CP_CONST,
7062 .accessfn = access_aa64_tid3,
7063 .resetvalue = 0 },
7064 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7065 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
7066 .access = PL1_R, .type = ARM_CP_CONST,
7067 .accessfn = access_aa64_tid3,
7068 .resetvalue = 0 },
7069 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7070 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
7071 .access = PL1_R, .type = ARM_CP_CONST,
7072 .accessfn = access_aa64_tid3,
7073 .resetvalue = 0 },
7074 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
7075 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
7076 .access = PL1_R, .type = ARM_CP_CONST,
7077 .accessfn = access_aa64_tid3,
7078 .resetvalue = cpu->isar.id_aa64dfr0 },
7079 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
7080 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
7081 .access = PL1_R, .type = ARM_CP_CONST,
7082 .accessfn = access_aa64_tid3,
7083 .resetvalue = cpu->isar.id_aa64dfr1 },
7084 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7085 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
7086 .access = PL1_R, .type = ARM_CP_CONST,
7087 .accessfn = access_aa64_tid3,
7088 .resetvalue = 0 },
7089 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7090 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
7091 .access = PL1_R, .type = ARM_CP_CONST,
7092 .accessfn = access_aa64_tid3,
7093 .resetvalue = 0 },
7094 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
7095 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
7096 .access = PL1_R, .type = ARM_CP_CONST,
7097 .accessfn = access_aa64_tid3,
7098 .resetvalue = cpu->id_aa64afr0 },
7099 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
7100 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
7101 .access = PL1_R, .type = ARM_CP_CONST,
7102 .accessfn = access_aa64_tid3,
7103 .resetvalue = cpu->id_aa64afr1 },
7104 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7105 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
7106 .access = PL1_R, .type = ARM_CP_CONST,
7107 .accessfn = access_aa64_tid3,
7108 .resetvalue = 0 },
7109 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7110 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
7111 .access = PL1_R, .type = ARM_CP_CONST,
7112 .accessfn = access_aa64_tid3,
7113 .resetvalue = 0 },
7114 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
7115 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
7116 .access = PL1_R, .type = ARM_CP_CONST,
7117 .accessfn = access_aa64_tid3,
7118 .resetvalue = cpu->isar.id_aa64isar0 },
7119 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
7120 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
7121 .access = PL1_R, .type = ARM_CP_CONST,
7122 .accessfn = access_aa64_tid3,
7123 .resetvalue = cpu->isar.id_aa64isar1 },
7124 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7125 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
7126 .access = PL1_R, .type = ARM_CP_CONST,
7127 .accessfn = access_aa64_tid3,
7128 .resetvalue = 0 },
7129 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7130 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
7131 .access = PL1_R, .type = ARM_CP_CONST,
7132 .accessfn = access_aa64_tid3,
7133 .resetvalue = 0 },
7134 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7135 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
7136 .access = PL1_R, .type = ARM_CP_CONST,
7137 .accessfn = access_aa64_tid3,
7138 .resetvalue = 0 },
7139 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7140 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
7141 .access = PL1_R, .type = ARM_CP_CONST,
7142 .accessfn = access_aa64_tid3,
7143 .resetvalue = 0 },
7144 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7145 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
7146 .access = PL1_R, .type = ARM_CP_CONST,
7147 .accessfn = access_aa64_tid3,
7148 .resetvalue = 0 },
7149 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7150 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
7151 .access = PL1_R, .type = ARM_CP_CONST,
7152 .accessfn = access_aa64_tid3,
7153 .resetvalue = 0 },
7154 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
7155 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
7156 .access = PL1_R, .type = ARM_CP_CONST,
7157 .accessfn = access_aa64_tid3,
7158 .resetvalue = cpu->isar.id_aa64mmfr0 },
7159 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
7160 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
7161 .access = PL1_R, .type = ARM_CP_CONST,
7162 .accessfn = access_aa64_tid3,
7163 .resetvalue = cpu->isar.id_aa64mmfr1 },
7164 { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
7165 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
7166 .access = PL1_R, .type = ARM_CP_CONST,
7167 .accessfn = access_aa64_tid3,
7168 .resetvalue = cpu->isar.id_aa64mmfr2 },
7169 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7170 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
7171 .access = PL1_R, .type = ARM_CP_CONST,
7172 .accessfn = access_aa64_tid3,
7173 .resetvalue = 0 },
7174 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7175 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
7176 .access = PL1_R, .type = ARM_CP_CONST,
7177 .accessfn = access_aa64_tid3,
7178 .resetvalue = 0 },
7179 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7180 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
7181 .access = PL1_R, .type = ARM_CP_CONST,
7182 .accessfn = access_aa64_tid3,
7183 .resetvalue = 0 },
7184 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7185 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
7186 .access = PL1_R, .type = ARM_CP_CONST,
7187 .accessfn = access_aa64_tid3,
7188 .resetvalue = 0 },
7189 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7190 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
7191 .access = PL1_R, .type = ARM_CP_CONST,
7192 .accessfn = access_aa64_tid3,
7193 .resetvalue = 0 },
7194 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
7195 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
7196 .access = PL1_R, .type = ARM_CP_CONST,
7197 .accessfn = access_aa64_tid3,
7198 .resetvalue = cpu->isar.mvfr0 },
7199 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
7200 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
7201 .access = PL1_R, .type = ARM_CP_CONST,
7202 .accessfn = access_aa64_tid3,
7203 .resetvalue = cpu->isar.mvfr1 },
7204 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
7205 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
7206 .access = PL1_R, .type = ARM_CP_CONST,
7207 .accessfn = access_aa64_tid3,
7208 .resetvalue = cpu->isar.mvfr2 },
7209 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7210 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
7211 .access = PL1_R, .type = ARM_CP_CONST,
7212 .accessfn = access_aa64_tid3,
7213 .resetvalue = 0 },
7214 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7215 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
7216 .access = PL1_R, .type = ARM_CP_CONST,
7217 .accessfn = access_aa64_tid3,
7218 .resetvalue = 0 },
7219 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7220 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
7221 .access = PL1_R, .type = ARM_CP_CONST,
7222 .accessfn = access_aa64_tid3,
7223 .resetvalue = 0 },
7224 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7225 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
7226 .access = PL1_R, .type = ARM_CP_CONST,
7227 .accessfn = access_aa64_tid3,
7228 .resetvalue = 0 },
7229 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7230 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
7231 .access = PL1_R, .type = ARM_CP_CONST,
7232 .accessfn = access_aa64_tid3,
7233 .resetvalue = 0 },
7234 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
7235 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
7236 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7237 .resetvalue = extract64(cpu->pmceid0, 0, 32) },
7238 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
7239 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
7240 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7241 .resetvalue = cpu->pmceid0 },
7242 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
7243 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
7244 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7245 .resetvalue = extract64(cpu->pmceid1, 0, 32) },
7246 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
7247 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
7248 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7249 .resetvalue = cpu->pmceid1 },
7250 REGINFO_SENTINEL
7251 };
7252 #ifdef CONFIG_USER_ONLY
7253 ARMCPRegUserSpaceInfo v8_user_idregs[] = {
7254 { .name = "ID_AA64PFR0_EL1",
7255 .exported_bits = 0x000f000f00ff0000,
7256 .fixed_bits = 0x0000000000000011 },
7257 { .name = "ID_AA64PFR1_EL1",
7258 .exported_bits = 0x00000000000000f0 },
7259 { .name = "ID_AA64PFR*_EL1_RESERVED",
7260 .is_glob = true },
7261 { .name = "ID_AA64ZFR0_EL1" },
7262 { .name = "ID_AA64MMFR0_EL1",
7263 .fixed_bits = 0x00000000ff000000 },
7264 { .name = "ID_AA64MMFR1_EL1" },
7265 { .name = "ID_AA64MMFR*_EL1_RESERVED",
7266 .is_glob = true },
7267 { .name = "ID_AA64DFR0_EL1",
7268 .fixed_bits = 0x0000000000000006 },
7269 { .name = "ID_AA64DFR1_EL1" },
7270 { .name = "ID_AA64DFR*_EL1_RESERVED",
7271 .is_glob = true },
7272 { .name = "ID_AA64AFR*",
7273 .is_glob = true },
7274 { .name = "ID_AA64ISAR0_EL1",
7275 .exported_bits = 0x00fffffff0fffff0 },
7276 { .name = "ID_AA64ISAR1_EL1",
7277 .exported_bits = 0x000000f0ffffffff },
7278 { .name = "ID_AA64ISAR*_EL1_RESERVED",
7279 .is_glob = true },
7280 REGUSERINFO_SENTINEL
7281 };
7282 modify_arm_cp_regs(v8_idregs, v8_user_idregs);
7283 #endif
7284 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7285 if (!arm_feature(env, ARM_FEATURE_EL3) &&
7286 !arm_feature(env, ARM_FEATURE_EL2)) {
7287 ARMCPRegInfo rvbar = {
7288 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
7289 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
7290 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
7291 };
7292 define_one_arm_cp_reg(cpu, &rvbar);
7293 }
7294 define_arm_cp_regs(cpu, v8_idregs);
7295 define_arm_cp_regs(cpu, v8_cp_reginfo);
7296 }
7297 if (arm_feature(env, ARM_FEATURE_EL2)) {
7298 uint64_t vmpidr_def = mpidr_read_val(env);
7299 ARMCPRegInfo vpidr_regs[] = {
7300 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
7301 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7302 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7303 .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
7304 .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
7305 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
7306 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7307 .access = PL2_RW, .resetvalue = cpu->midr,
7308 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
7309 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
7310 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7311 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7312 .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
7313 .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
7314 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
7315 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7316 .access = PL2_RW,
7317 .resetvalue = vmpidr_def,
7318 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
7319 REGINFO_SENTINEL
7320 };
7321 define_arm_cp_regs(cpu, vpidr_regs);
7322 define_arm_cp_regs(cpu, el2_cp_reginfo);
7323 if (arm_feature(env, ARM_FEATURE_V8)) {
7324 define_arm_cp_regs(cpu, el2_v8_cp_reginfo);
7325 }
7326 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7327 if (!arm_feature(env, ARM_FEATURE_EL3)) {
7328 ARMCPRegInfo rvbar = {
7329 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
7330 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
7331 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
7332 };
7333 define_one_arm_cp_reg(cpu, &rvbar);
7334 }
7335 } else {
7336 /* If EL2 is missing but higher ELs are enabled, we need to
7337 * register the no_el2 reginfos.
7338 */
7339 if (arm_feature(env, ARM_FEATURE_EL3)) {
7340 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7341 * of MIDR_EL1 and MPIDR_EL1.
7342 */
7343 ARMCPRegInfo vpidr_regs[] = {
7344 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7345 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7346 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
7347 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
7348 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
7349 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7350 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7351 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
7352 .type = ARM_CP_NO_RAW,
7353 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
7354 REGINFO_SENTINEL
7355 };
7356 define_arm_cp_regs(cpu, vpidr_regs);
7357 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
7358 if (arm_feature(env, ARM_FEATURE_V8)) {
7359 define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
7360 }
7361 }
7362 }
7363 if (arm_feature(env, ARM_FEATURE_EL3)) {
7364 define_arm_cp_regs(cpu, el3_cp_reginfo);
7365 ARMCPRegInfo el3_regs[] = {
7366 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
7367 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
7368 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
7369 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
7370 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
7371 .access = PL3_RW,
7372 .raw_writefn = raw_write, .writefn = sctlr_write,
7373 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
7374 .resetvalue = cpu->reset_sctlr },
7375 REGINFO_SENTINEL
7376 };
7377
7378 define_arm_cp_regs(cpu, el3_regs);
7379 }
7380 /* The behaviour of NSACR is sufficiently various that we don't
7381 * try to describe it in a single reginfo:
7382 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7383 * reads as constant 0xc00 from NS EL1 and NS EL2
7384 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7385 * if v7 without EL3, register doesn't exist
7386 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7387 */
7388 if (arm_feature(env, ARM_FEATURE_EL3)) {
7389 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
7390 ARMCPRegInfo nsacr = {
7391 .name = "NSACR", .type = ARM_CP_CONST,
7392 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7393 .access = PL1_RW, .accessfn = nsacr_access,
7394 .resetvalue = 0xc00
7395 };
7396 define_one_arm_cp_reg(cpu, &nsacr);
7397 } else {
7398 ARMCPRegInfo nsacr = {
7399 .name = "NSACR",
7400 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7401 .access = PL3_RW | PL1_R,
7402 .resetvalue = 0,
7403 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
7404 };
7405 define_one_arm_cp_reg(cpu, &nsacr);
7406 }
7407 } else {
7408 if (arm_feature(env, ARM_FEATURE_V8)) {
7409 ARMCPRegInfo nsacr = {
7410 .name = "NSACR", .type = ARM_CP_CONST,
7411 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7412 .access = PL1_R,
7413 .resetvalue = 0xc00
7414 };
7415 define_one_arm_cp_reg(cpu, &nsacr);
7416 }
7417 }
7418
7419 if (arm_feature(env, ARM_FEATURE_PMSA)) {
7420 if (arm_feature(env, ARM_FEATURE_V6)) {
7421 /* PMSAv6 not implemented */
7422 assert(arm_feature(env, ARM_FEATURE_V7));
7423 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7424 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
7425 } else {
7426 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
7427 }
7428 } else {
7429 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7430 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
7431 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7432 if (cpu_isar_feature(aa32_hpd, cpu)) {
7433 define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
7434 }
7435 }
7436 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
7437 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
7438 }
7439 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
7440 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
7441 }
7442 if (arm_feature(env, ARM_FEATURE_VAPA)) {
7443 define_arm_cp_regs(cpu, vapa_cp_reginfo);
7444 }
7445 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
7446 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
7447 }
7448 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
7449 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
7450 }
7451 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
7452 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
7453 }
7454 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
7455 define_arm_cp_regs(cpu, omap_cp_reginfo);
7456 }
7457 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
7458 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
7459 }
7460 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
7461 define_arm_cp_regs(cpu, xscale_cp_reginfo);
7462 }
7463 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
7464 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
7465 }
7466 if (arm_feature(env, ARM_FEATURE_LPAE)) {
7467 define_arm_cp_regs(cpu, lpae_cp_reginfo);
7468 }
7469 if (cpu_isar_feature(aa32_jazelle, cpu)) {
7470 define_arm_cp_regs(cpu, jazelle_regs);
7471 }
7472 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7473 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7474 * be read-only (ie write causes UNDEF exception).
7475 */
7476 {
7477 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
7478 /* Pre-v8 MIDR space.
7479 * Note that the MIDR isn't a simple constant register because
7480 * of the TI925 behaviour where writes to another register can
7481 * cause the MIDR value to change.
7482 *
7483 * Unimplemented registers in the c15 0 0 0 space default to
7484 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7485 * and friends override accordingly.
7486 */
7487 { .name = "MIDR",
7488 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7489 .access = PL1_R, .resetvalue = cpu->midr,
7490 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
7491 .readfn = midr_read,
7492 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
7493 .type = ARM_CP_OVERRIDE },
7494 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7495 { .name = "DUMMY",
7496 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
7497 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7498 { .name = "DUMMY",
7499 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
7500 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7501 { .name = "DUMMY",
7502 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
7503 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7504 { .name = "DUMMY",
7505 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
7506 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7507 { .name = "DUMMY",
7508 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
7509 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7510 REGINFO_SENTINEL
7511 };
7512 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
7513 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
7514 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
7515 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
7516 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
7517 .readfn = midr_read },
7518 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7519 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
7520 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
7521 .access = PL1_R, .resetvalue = cpu->midr },
7522 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
7523 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
7524 .access = PL1_R, .resetvalue = cpu->midr },
7525 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
7526 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
7527 .access = PL1_R,
7528 .accessfn = access_aa64_tid1,
7529 .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
7530 REGINFO_SENTINEL
7531 };
7532 ARMCPRegInfo id_cp_reginfo[] = {
7533 /* These are common to v8 and pre-v8 */
7534 { .name = "CTR",
7535 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
7536 .access = PL1_R, .accessfn = ctr_el0_access,
7537 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
7538 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
7539 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
7540 .access = PL0_R, .accessfn = ctr_el0_access,
7541 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
7542 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7543 { .name = "TCMTR",
7544 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
7545 .access = PL1_R,
7546 .accessfn = access_aa32_tid1,
7547 .type = ARM_CP_CONST, .resetvalue = 0 },
7548 REGINFO_SENTINEL
7549 };
7550 /* TLBTR is specific to VMSA */
7551 ARMCPRegInfo id_tlbtr_reginfo = {
7552 .name = "TLBTR",
7553 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
7554 .access = PL1_R,
7555 .accessfn = access_aa32_tid1,
7556 .type = ARM_CP_CONST, .resetvalue = 0,
7557 };
7558 /* MPUIR is specific to PMSA V6+ */
7559 ARMCPRegInfo id_mpuir_reginfo = {
7560 .name = "MPUIR",
7561 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
7562 .access = PL1_R, .type = ARM_CP_CONST,
7563 .resetvalue = cpu->pmsav7_dregion << 8
7564 };
7565 ARMCPRegInfo crn0_wi_reginfo = {
7566 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
7567 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
7568 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
7569 };
7570 #ifdef CONFIG_USER_ONLY
7571 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
7572 { .name = "MIDR_EL1",
7573 .exported_bits = 0x00000000ffffffff },
7574 { .name = "REVIDR_EL1" },
7575 REGUSERINFO_SENTINEL
7576 };
7577 modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
7578 #endif
7579 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
7580 arm_feature(env, ARM_FEATURE_STRONGARM)) {
7581 ARMCPRegInfo *r;
7582 /* Register the blanket "writes ignored" value first to cover the
7583 * whole space. Then update the specific ID registers to allow write
7584 * access, so that they ignore writes rather than causing them to
7585 * UNDEF.
7586 */
7587 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
7588 for (r = id_pre_v8_midr_cp_reginfo;
7589 r->type != ARM_CP_SENTINEL; r++) {
7590 r->access = PL1_RW;
7591 }
7592 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
7593 r->access = PL1_RW;
7594 }
7595 id_mpuir_reginfo.access = PL1_RW;
7596 id_tlbtr_reginfo.access = PL1_RW;
7597 }
7598 if (arm_feature(env, ARM_FEATURE_V8)) {
7599 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
7600 } else {
7601 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
7602 }
7603 define_arm_cp_regs(cpu, id_cp_reginfo);
7604 if (!arm_feature(env, ARM_FEATURE_PMSA)) {
7605 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
7606 } else if (arm_feature(env, ARM_FEATURE_V7)) {
7607 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
7608 }
7609 }
7610
7611 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
7612 ARMCPRegInfo mpidr_cp_reginfo[] = {
7613 { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
7614 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
7615 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
7616 REGINFO_SENTINEL
7617 };
7618 #ifdef CONFIG_USER_ONLY
7619 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
7620 { .name = "MPIDR_EL1",
7621 .fixed_bits = 0x0000000080000000 },
7622 REGUSERINFO_SENTINEL
7623 };
7624 modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
7625 #endif
7626 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
7627 }
7628
7629 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
7630 ARMCPRegInfo auxcr_reginfo[] = {
7631 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
7632 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
7633 .access = PL1_RW, .type = ARM_CP_CONST,
7634 .resetvalue = cpu->reset_auxcr },
7635 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
7636 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
7637 .access = PL2_RW, .type = ARM_CP_CONST,
7638 .resetvalue = 0 },
7639 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
7640 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
7641 .access = PL3_RW, .type = ARM_CP_CONST,
7642 .resetvalue = 0 },
7643 REGINFO_SENTINEL
7644 };
7645 define_arm_cp_regs(cpu, auxcr_reginfo);
7646 if (cpu_isar_feature(aa32_ac2, cpu)) {
7647 define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo);
7648 }
7649 }
7650
7651 if (arm_feature(env, ARM_FEATURE_CBAR)) {
7652 /*
7653 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
7654 * There are two flavours:
7655 * (1) older 32-bit only cores have a simple 32-bit CBAR
7656 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
7657 * 32-bit register visible to AArch32 at a different encoding
7658 * to the "flavour 1" register and with the bits rearranged to
7659 * be able to squash a 64-bit address into the 32-bit view.
7660 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
7661 * in future if we support AArch32-only configs of some of the
7662 * AArch64 cores we might need to add a specific feature flag
7663 * to indicate cores with "flavour 2" CBAR.
7664 */
7665 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
7666 /* 32 bit view is [31:18] 0...0 [43:32]. */
7667 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
7668 | extract64(cpu->reset_cbar, 32, 12);
7669 ARMCPRegInfo cbar_reginfo[] = {
7670 { .name = "CBAR",
7671 .type = ARM_CP_CONST,
7672 .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
7673 .access = PL1_R, .resetvalue = cbar32 },
7674 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
7675 .type = ARM_CP_CONST,
7676 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
7677 .access = PL1_R, .resetvalue = cpu->reset_cbar },
7678 REGINFO_SENTINEL
7679 };
7680 /* We don't implement a r/w 64 bit CBAR currently */
7681 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
7682 define_arm_cp_regs(cpu, cbar_reginfo);
7683 } else {
7684 ARMCPRegInfo cbar = {
7685 .name = "CBAR",
7686 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
7687 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
7688 .fieldoffset = offsetof(CPUARMState,
7689 cp15.c15_config_base_address)
7690 };
7691 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
7692 cbar.access = PL1_R;
7693 cbar.fieldoffset = 0;
7694 cbar.type = ARM_CP_CONST;
7695 }
7696 define_one_arm_cp_reg(cpu, &cbar);
7697 }
7698 }
7699
7700 if (arm_feature(env, ARM_FEATURE_VBAR)) {
7701 ARMCPRegInfo vbar_cp_reginfo[] = {
7702 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
7703 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
7704 .access = PL1_RW, .writefn = vbar_write,
7705 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
7706 offsetof(CPUARMState, cp15.vbar_ns) },
7707 .resetvalue = 0 },
7708 REGINFO_SENTINEL
7709 };
7710 define_arm_cp_regs(cpu, vbar_cp_reginfo);
7711 }
7712
7713 /* Generic registers whose values depend on the implementation */
7714 {
7715 ARMCPRegInfo sctlr = {
7716 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
7717 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
7718 .access = PL1_RW,
7719 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
7720 offsetof(CPUARMState, cp15.sctlr_ns) },
7721 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
7722 .raw_writefn = raw_write,
7723 };
7724 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
7725 /* Normally we would always end the TB on an SCTLR write, but Linux
7726 * arch/arm/mach-pxa/sleep.S expects two instructions following
7727 * an MMU enable to execute from cache. Imitate this behaviour.
7728 */
7729 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
7730 }
7731 define_one_arm_cp_reg(cpu, &sctlr);
7732 }
7733
7734 if (cpu_isar_feature(aa64_lor, cpu)) {
7735 define_arm_cp_regs(cpu, lor_reginfo);
7736 }
7737 if (cpu_isar_feature(aa64_pan, cpu)) {
7738 define_one_arm_cp_reg(cpu, &pan_reginfo);
7739 }
7740 #ifndef CONFIG_USER_ONLY
7741 if (cpu_isar_feature(aa64_ats1e1, cpu)) {
7742 define_arm_cp_regs(cpu, ats1e1_reginfo);
7743 }
7744 if (cpu_isar_feature(aa32_ats1e1, cpu)) {
7745 define_arm_cp_regs(cpu, ats1cp_reginfo);
7746 }
7747 #endif
7748 if (cpu_isar_feature(aa64_uao, cpu)) {
7749 define_one_arm_cp_reg(cpu, &uao_reginfo);
7750 }
7751
7752 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
7753 define_arm_cp_regs(cpu, vhe_reginfo);
7754 }
7755
7756 if (cpu_isar_feature(aa64_sve, cpu)) {
7757 define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
7758 if (arm_feature(env, ARM_FEATURE_EL2)) {
7759 define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
7760 } else {
7761 define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
7762 }
7763 if (arm_feature(env, ARM_FEATURE_EL3)) {
7764 define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
7765 }
7766 }
7767
7768 #ifdef TARGET_AARCH64
7769 if (cpu_isar_feature(aa64_pauth, cpu)) {
7770 define_arm_cp_regs(cpu, pauth_reginfo);
7771 }
7772 if (cpu_isar_feature(aa64_rndr, cpu)) {
7773 define_arm_cp_regs(cpu, rndr_reginfo);
7774 }
7775 #ifndef CONFIG_USER_ONLY
7776 /* Data Cache clean instructions up to PoP */
7777 if (cpu_isar_feature(aa64_dcpop, cpu)) {
7778 define_one_arm_cp_reg(cpu, dcpop_reg);
7779
7780 if (cpu_isar_feature(aa64_dcpodp, cpu)) {
7781 define_one_arm_cp_reg(cpu, dcpodp_reg);
7782 }
7783 }
7784 #endif /*CONFIG_USER_ONLY*/
7785 #endif
7786
7787 if (cpu_isar_feature(any_predinv, cpu)) {
7788 define_arm_cp_regs(cpu, predinv_reginfo);
7789 }
7790
7791 #ifndef CONFIG_USER_ONLY
7792 /*
7793 * Register redirections and aliases must be done last,
7794 * after the registers from the other extensions have been defined.
7795 */
7796 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
7797 define_arm_vh_e2h_redirects_aliases(cpu);
7798 }
7799 #endif
7800 }
7801
7802 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
7803 {
7804 CPUState *cs = CPU(cpu);
7805 CPUARMState *env = &cpu->env;
7806
7807 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
7808 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
7809 aarch64_fpu_gdb_set_reg,
7810 34, "aarch64-fpu.xml", 0);
7811 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
7812 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
7813 51, "arm-neon.xml", 0);
7814 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
7815 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
7816 35, "arm-vfp3.xml", 0);
7817 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
7818 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
7819 19, "arm-vfp.xml", 0);
7820 }
7821 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
7822 arm_gen_dynamic_xml(cs),
7823 "system-registers.xml", 0);
7824 }
7825
7826 /* Sort alphabetically by type name, except for "any". */
7827 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
7828 {
7829 ObjectClass *class_a = (ObjectClass *)a;
7830 ObjectClass *class_b = (ObjectClass *)b;
7831 const char *name_a, *name_b;
7832
7833 name_a = object_class_get_name(class_a);
7834 name_b = object_class_get_name(class_b);
7835 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
7836 return 1;
7837 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
7838 return -1;
7839 } else {
7840 return strcmp(name_a, name_b);
7841 }
7842 }
7843
7844 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
7845 {
7846 ObjectClass *oc = data;
7847 const char *typename;
7848 char *name;
7849
7850 typename = object_class_get_name(oc);
7851 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
7852 qemu_printf(" %s\n", name);
7853 g_free(name);
7854 }
7855
7856 void arm_cpu_list(void)
7857 {
7858 GSList *list;
7859
7860 list = object_class_get_list(TYPE_ARM_CPU, false);
7861 list = g_slist_sort(list, arm_cpu_list_compare);
7862 qemu_printf("Available CPUs:\n");
7863 g_slist_foreach(list, arm_cpu_list_entry, NULL);
7864 g_slist_free(list);
7865 }
7866
7867 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
7868 {
7869 ObjectClass *oc = data;
7870 CpuDefinitionInfoList **cpu_list = user_data;
7871 CpuDefinitionInfoList *entry;
7872 CpuDefinitionInfo *info;
7873 const char *typename;
7874
7875 typename = object_class_get_name(oc);
7876 info = g_malloc0(sizeof(*info));
7877 info->name = g_strndup(typename,
7878 strlen(typename) - strlen("-" TYPE_ARM_CPU));
7879 info->q_typename = g_strdup(typename);
7880
7881 entry = g_malloc0(sizeof(*entry));
7882 entry->value = info;
7883 entry->next = *cpu_list;
7884 *cpu_list = entry;
7885 }
7886
7887 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7888 {
7889 CpuDefinitionInfoList *cpu_list = NULL;
7890 GSList *list;
7891
7892 list = object_class_get_list(TYPE_ARM_CPU, false);
7893 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
7894 g_slist_free(list);
7895
7896 return cpu_list;
7897 }
7898
7899 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
7900 void *opaque, int state, int secstate,
7901 int crm, int opc1, int opc2,
7902 const char *name)
7903 {
7904 /* Private utility function for define_one_arm_cp_reg_with_opaque():
7905 * add a single reginfo struct to the hash table.
7906 */
7907 uint32_t *key = g_new(uint32_t, 1);
7908 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
7909 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
7910 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
7911
7912 r2->name = g_strdup(name);
7913 /* Reset the secure state to the specific incoming state. This is
7914 * necessary as the register may have been defined with both states.
7915 */
7916 r2->secure = secstate;
7917
7918 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
7919 /* Register is banked (using both entries in array).
7920 * Overwriting fieldoffset as the array is only used to define
7921 * banked registers but later only fieldoffset is used.
7922 */
7923 r2->fieldoffset = r->bank_fieldoffsets[ns];
7924 }
7925
7926 if (state == ARM_CP_STATE_AA32) {
7927 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
7928 /* If the register is banked then we don't need to migrate or
7929 * reset the 32-bit instance in certain cases:
7930 *
7931 * 1) If the register has both 32-bit and 64-bit instances then we
7932 * can count on the 64-bit instance taking care of the
7933 * non-secure bank.
7934 * 2) If ARMv8 is enabled then we can count on a 64-bit version
7935 * taking care of the secure bank. This requires that separate
7936 * 32 and 64-bit definitions are provided.
7937 */
7938 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
7939 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
7940 r2->type |= ARM_CP_ALIAS;
7941 }
7942 } else if ((secstate != r->secure) && !ns) {
7943 /* The register is not banked so we only want to allow migration of
7944 * the non-secure instance.
7945 */
7946 r2->type |= ARM_CP_ALIAS;
7947 }
7948
7949 if (r->state == ARM_CP_STATE_BOTH) {
7950 /* We assume it is a cp15 register if the .cp field is left unset.
7951 */
7952 if (r2->cp == 0) {
7953 r2->cp = 15;
7954 }
7955
7956 #ifdef HOST_WORDS_BIGENDIAN
7957 if (r2->fieldoffset) {
7958 r2->fieldoffset += sizeof(uint32_t);
7959 }
7960 #endif
7961 }
7962 }
7963 if (state == ARM_CP_STATE_AA64) {
7964 /* To allow abbreviation of ARMCPRegInfo
7965 * definitions, we treat cp == 0 as equivalent to
7966 * the value for "standard guest-visible sysreg".
7967 * STATE_BOTH definitions are also always "standard
7968 * sysreg" in their AArch64 view (the .cp value may
7969 * be non-zero for the benefit of the AArch32 view).
7970 */
7971 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
7972 r2->cp = CP_REG_ARM64_SYSREG_CP;
7973 }
7974 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
7975 r2->opc0, opc1, opc2);
7976 } else {
7977 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
7978 }
7979 if (opaque) {
7980 r2->opaque = opaque;
7981 }
7982 /* reginfo passed to helpers is correct for the actual access,
7983 * and is never ARM_CP_STATE_BOTH:
7984 */
7985 r2->state = state;
7986 /* Make sure reginfo passed to helpers for wildcarded regs
7987 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
7988 */
7989 r2->crm = crm;
7990 r2->opc1 = opc1;
7991 r2->opc2 = opc2;
7992 /* By convention, for wildcarded registers only the first
7993 * entry is used for migration; the others are marked as
7994 * ALIAS so we don't try to transfer the register
7995 * multiple times. Special registers (ie NOP/WFI) are
7996 * never migratable and not even raw-accessible.
7997 */
7998 if ((r->type & ARM_CP_SPECIAL)) {
7999 r2->type |= ARM_CP_NO_RAW;
8000 }
8001 if (((r->crm == CP_ANY) && crm != 0) ||
8002 ((r->opc1 == CP_ANY) && opc1 != 0) ||
8003 ((r->opc2 == CP_ANY) && opc2 != 0)) {
8004 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
8005 }
8006
8007 /* Check that raw accesses are either forbidden or handled. Note that
8008 * we can't assert this earlier because the setup of fieldoffset for
8009 * banked registers has to be done first.
8010 */
8011 if (!(r2->type & ARM_CP_NO_RAW)) {
8012 assert(!raw_accessors_invalid(r2));
8013 }
8014
8015 /* Overriding of an existing definition must be explicitly
8016 * requested.
8017 */
8018 if (!(r->type & ARM_CP_OVERRIDE)) {
8019 ARMCPRegInfo *oldreg;
8020 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
8021 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
8022 fprintf(stderr, "Register redefined: cp=%d %d bit "
8023 "crn=%d crm=%d opc1=%d opc2=%d, "
8024 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
8025 r2->crn, r2->crm, r2->opc1, r2->opc2,
8026 oldreg->name, r2->name);
8027 g_assert_not_reached();
8028 }
8029 }
8030 g_hash_table_insert(cpu->cp_regs, key, r2);
8031 }
8032
8033
8034 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
8035 const ARMCPRegInfo *r, void *opaque)
8036 {
8037 /* Define implementations of coprocessor registers.
8038 * We store these in a hashtable because typically
8039 * there are less than 150 registers in a space which
8040 * is 16*16*16*8*8 = 262144 in size.
8041 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8042 * If a register is defined twice then the second definition is
8043 * used, so this can be used to define some generic registers and
8044 * then override them with implementation specific variations.
8045 * At least one of the original and the second definition should
8046 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8047 * against accidental use.
8048 *
8049 * The state field defines whether the register is to be
8050 * visible in the AArch32 or AArch64 execution state. If the
8051 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8052 * reginfo structure for the AArch32 view, which sees the lower
8053 * 32 bits of the 64 bit register.
8054 *
8055 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8056 * be wildcarded. AArch64 registers are always considered to be 64
8057 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8058 * the register, if any.
8059 */
8060 int crm, opc1, opc2, state;
8061 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
8062 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
8063 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
8064 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
8065 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
8066 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
8067 /* 64 bit registers have only CRm and Opc1 fields */
8068 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
8069 /* op0 only exists in the AArch64 encodings */
8070 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
8071 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8072 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
8073 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8074 * encodes a minimum access level for the register. We roll this
8075 * runtime check into our general permission check code, so check
8076 * here that the reginfo's specified permissions are strict enough
8077 * to encompass the generic architectural permission check.
8078 */
8079 if (r->state != ARM_CP_STATE_AA32) {
8080 int mask = 0;
8081 switch (r->opc1) {
8082 case 0:
8083 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8084 mask = PL0U_R | PL1_RW;
8085 break;
8086 case 1: case 2:
8087 /* min_EL EL1 */
8088 mask = PL1_RW;
8089 break;
8090 case 3:
8091 /* min_EL EL0 */
8092 mask = PL0_RW;
8093 break;
8094 case 4:
8095 case 5:
8096 /* min_EL EL2 */
8097 mask = PL2_RW;
8098 break;
8099 case 6:
8100 /* min_EL EL3 */
8101 mask = PL3_RW;
8102 break;
8103 case 7:
8104 /* min_EL EL1, secure mode only (we don't check the latter) */
8105 mask = PL1_RW;
8106 break;
8107 default:
8108 /* broken reginfo with out-of-range opc1 */
8109 assert(false);
8110 break;
8111 }
8112 /* assert our permissions are not too lax (stricter is fine) */
8113 assert((r->access & ~mask) == 0);
8114 }
8115
8116 /* Check that the register definition has enough info to handle
8117 * reads and writes if they are permitted.
8118 */
8119 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
8120 if (r->access & PL3_R) {
8121 assert((r->fieldoffset ||
8122 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8123 r->readfn);
8124 }
8125 if (r->access & PL3_W) {
8126 assert((r->fieldoffset ||
8127 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8128 r->writefn);
8129 }
8130 }
8131 /* Bad type field probably means missing sentinel at end of reg list */
8132 assert(cptype_valid(r->type));
8133 for (crm = crmmin; crm <= crmmax; crm++) {
8134 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
8135 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
8136 for (state = ARM_CP_STATE_AA32;
8137 state <= ARM_CP_STATE_AA64; state++) {
8138 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
8139 continue;
8140 }
8141 if (state == ARM_CP_STATE_AA32) {
8142 /* Under AArch32 CP registers can be common
8143 * (same for secure and non-secure world) or banked.
8144 */
8145 char *name;
8146
8147 switch (r->secure) {
8148 case ARM_CP_SECSTATE_S:
8149 case ARM_CP_SECSTATE_NS:
8150 add_cpreg_to_hashtable(cpu, r, opaque, state,
8151 r->secure, crm, opc1, opc2,
8152 r->name);
8153 break;
8154 default:
8155 name = g_strdup_printf("%s_S", r->name);
8156 add_cpreg_to_hashtable(cpu, r, opaque, state,
8157 ARM_CP_SECSTATE_S,
8158 crm, opc1, opc2, name);
8159 g_free(name);
8160 add_cpreg_to_hashtable(cpu, r, opaque, state,
8161 ARM_CP_SECSTATE_NS,
8162 crm, opc1, opc2, r->name);
8163 break;
8164 }
8165 } else {
8166 /* AArch64 registers get mapped to non-secure instance
8167 * of AArch32 */
8168 add_cpreg_to_hashtable(cpu, r, opaque, state,
8169 ARM_CP_SECSTATE_NS,
8170 crm, opc1, opc2, r->name);
8171 }
8172 }
8173 }
8174 }
8175 }
8176 }
8177
8178 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
8179 const ARMCPRegInfo *regs, void *opaque)
8180 {
8181 /* Define a whole list of registers */
8182 const ARMCPRegInfo *r;
8183 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8184 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
8185 }
8186 }
8187
8188 /*
8189 * Modify ARMCPRegInfo for access from userspace.
8190 *
8191 * This is a data driven modification directed by
8192 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8193 * user-space cannot alter any values and dynamic values pertaining to
8194 * execution state are hidden from user space view anyway.
8195 */
8196 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
8197 {
8198 const ARMCPRegUserSpaceInfo *m;
8199 ARMCPRegInfo *r;
8200
8201 for (m = mods; m->name; m++) {
8202 GPatternSpec *pat = NULL;
8203 if (m->is_glob) {
8204 pat = g_pattern_spec_new(m->name);
8205 }
8206 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8207 if (pat && g_pattern_match_string(pat, r->name)) {
8208 r->type = ARM_CP_CONST;
8209 r->access = PL0U_R;
8210 r->resetvalue = 0;
8211 /* continue */
8212 } else if (strcmp(r->name, m->name) == 0) {
8213 r->type = ARM_CP_CONST;
8214 r->access = PL0U_R;
8215 r->resetvalue &= m->exported_bits;
8216 r->resetvalue |= m->fixed_bits;
8217 break;
8218 }
8219 }
8220 if (pat) {
8221 g_pattern_spec_free(pat);
8222 }
8223 }
8224 }
8225
8226 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
8227 {
8228 return g_hash_table_lookup(cpregs, &encoded_cp);
8229 }
8230
8231 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
8232 uint64_t value)
8233 {
8234 /* Helper coprocessor write function for write-ignore registers */
8235 }
8236
8237 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
8238 {
8239 /* Helper coprocessor write function for read-as-zero registers */
8240 return 0;
8241 }
8242
8243 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
8244 {
8245 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8246 }
8247
8248 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
8249 {
8250 /* Return true if it is not valid for us to switch to
8251 * this CPU mode (ie all the UNPREDICTABLE cases in
8252 * the ARM ARM CPSRWriteByInstr pseudocode).
8253 */
8254
8255 /* Changes to or from Hyp via MSR and CPS are illegal. */
8256 if (write_type == CPSRWriteByInstr &&
8257 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
8258 mode == ARM_CPU_MODE_HYP)) {
8259 return 1;
8260 }
8261
8262 switch (mode) {
8263 case ARM_CPU_MODE_USR:
8264 return 0;
8265 case ARM_CPU_MODE_SYS:
8266 case ARM_CPU_MODE_SVC:
8267 case ARM_CPU_MODE_ABT:
8268 case ARM_CPU_MODE_UND:
8269 case ARM_CPU_MODE_IRQ:
8270 case ARM_CPU_MODE_FIQ:
8271 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8272 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8273 */
8274 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8275 * and CPS are treated as illegal mode changes.
8276 */
8277 if (write_type == CPSRWriteByInstr &&
8278 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
8279 (arm_hcr_el2_eff(env) & HCR_TGE)) {
8280 return 1;
8281 }
8282 return 0;
8283 case ARM_CPU_MODE_HYP:
8284 return !arm_feature(env, ARM_FEATURE_EL2)
8285 || arm_current_el(env) < 2 || arm_is_secure_below_el3(env);
8286 case ARM_CPU_MODE_MON:
8287 return arm_current_el(env) < 3;
8288 default:
8289 return 1;
8290 }
8291 }
8292
8293 uint32_t cpsr_read(CPUARMState *env)
8294 {
8295 int ZF;
8296 ZF = (env->ZF == 0);
8297 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
8298 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
8299 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
8300 | ((env->condexec_bits & 0xfc) << 8)
8301 | (env->GE << 16) | (env->daif & CPSR_AIF);
8302 }
8303
8304 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
8305 CPSRWriteType write_type)
8306 {
8307 uint32_t changed_daif;
8308
8309 if (mask & CPSR_NZCV) {
8310 env->ZF = (~val) & CPSR_Z;
8311 env->NF = val;
8312 env->CF = (val >> 29) & 1;
8313 env->VF = (val << 3) & 0x80000000;
8314 }
8315 if (mask & CPSR_Q)
8316 env->QF = ((val & CPSR_Q) != 0);
8317 if (mask & CPSR_T)
8318 env->thumb = ((val & CPSR_T) != 0);
8319 if (mask & CPSR_IT_0_1) {
8320 env->condexec_bits &= ~3;
8321 env->condexec_bits |= (val >> 25) & 3;
8322 }
8323 if (mask & CPSR_IT_2_7) {
8324 env->condexec_bits &= 3;
8325 env->condexec_bits |= (val >> 8) & 0xfc;
8326 }
8327 if (mask & CPSR_GE) {
8328 env->GE = (val >> 16) & 0xf;
8329 }
8330
8331 /* In a V7 implementation that includes the security extensions but does
8332 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8333 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8334 * bits respectively.
8335 *
8336 * In a V8 implementation, it is permitted for privileged software to
8337 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8338 */
8339 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
8340 arm_feature(env, ARM_FEATURE_EL3) &&
8341 !arm_feature(env, ARM_FEATURE_EL2) &&
8342 !arm_is_secure(env)) {
8343
8344 changed_daif = (env->daif ^ val) & mask;
8345
8346 if (changed_daif & CPSR_A) {
8347 /* Check to see if we are allowed to change the masking of async
8348 * abort exceptions from a non-secure state.
8349 */
8350 if (!(env->cp15.scr_el3 & SCR_AW)) {
8351 qemu_log_mask(LOG_GUEST_ERROR,
8352 "Ignoring attempt to switch CPSR_A flag from "
8353 "non-secure world with SCR.AW bit clear\n");
8354 mask &= ~CPSR_A;
8355 }
8356 }
8357
8358 if (changed_daif & CPSR_F) {
8359 /* Check to see if we are allowed to change the masking of FIQ
8360 * exceptions from a non-secure state.
8361 */
8362 if (!(env->cp15.scr_el3 & SCR_FW)) {
8363 qemu_log_mask(LOG_GUEST_ERROR,
8364 "Ignoring attempt to switch CPSR_F flag from "
8365 "non-secure world with SCR.FW bit clear\n");
8366 mask &= ~CPSR_F;
8367 }
8368
8369 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8370 * If this bit is set software is not allowed to mask
8371 * FIQs, but is allowed to set CPSR_F to 0.
8372 */
8373 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
8374 (val & CPSR_F)) {
8375 qemu_log_mask(LOG_GUEST_ERROR,
8376 "Ignoring attempt to enable CPSR_F flag "
8377 "(non-maskable FIQ [NMFI] support enabled)\n");
8378 mask &= ~CPSR_F;
8379 }
8380 }
8381 }
8382
8383 env->daif &= ~(CPSR_AIF & mask);
8384 env->daif |= val & CPSR_AIF & mask;
8385
8386 if (write_type != CPSRWriteRaw &&
8387 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
8388 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
8389 /* Note that we can only get here in USR mode if this is a
8390 * gdb stub write; for this case we follow the architectural
8391 * behaviour for guest writes in USR mode of ignoring an attempt
8392 * to switch mode. (Those are caught by translate.c for writes
8393 * triggered by guest instructions.)
8394 */
8395 mask &= ~CPSR_M;
8396 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
8397 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8398 * v7, and has defined behaviour in v8:
8399 * + leave CPSR.M untouched
8400 * + allow changes to the other CPSR fields
8401 * + set PSTATE.IL
8402 * For user changes via the GDB stub, we don't set PSTATE.IL,
8403 * as this would be unnecessarily harsh for a user error.
8404 */
8405 mask &= ~CPSR_M;
8406 if (write_type != CPSRWriteByGDBStub &&
8407 arm_feature(env, ARM_FEATURE_V8)) {
8408 mask |= CPSR_IL;
8409 val |= CPSR_IL;
8410 }
8411 qemu_log_mask(LOG_GUEST_ERROR,
8412 "Illegal AArch32 mode switch attempt from %s to %s\n",
8413 aarch32_mode_name(env->uncached_cpsr),
8414 aarch32_mode_name(val));
8415 } else {
8416 qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
8417 write_type == CPSRWriteExceptionReturn ?
8418 "Exception return from AArch32" :
8419 "AArch32 mode switch from",
8420 aarch32_mode_name(env->uncached_cpsr),
8421 aarch32_mode_name(val), env->regs[15]);
8422 switch_mode(env, val & CPSR_M);
8423 }
8424 }
8425 mask &= ~CACHED_CPSR_BITS;
8426 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
8427 }
8428
8429 /* Sign/zero extend */
8430 uint32_t HELPER(sxtb16)(uint32_t x)
8431 {
8432 uint32_t res;
8433 res = (uint16_t)(int8_t)x;
8434 res |= (uint32_t)(int8_t)(x >> 16) << 16;
8435 return res;
8436 }
8437
8438 uint32_t HELPER(uxtb16)(uint32_t x)
8439 {
8440 uint32_t res;
8441 res = (uint16_t)(uint8_t)x;
8442 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
8443 return res;
8444 }
8445
8446 int32_t HELPER(sdiv)(int32_t num, int32_t den)
8447 {
8448 if (den == 0)
8449 return 0;
8450 if (num == INT_MIN && den == -1)
8451 return INT_MIN;
8452 return num / den;
8453 }
8454
8455 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
8456 {
8457 if (den == 0)
8458 return 0;
8459 return num / den;
8460 }
8461
8462 uint32_t HELPER(rbit)(uint32_t x)
8463 {
8464 return revbit32(x);
8465 }
8466
8467 #ifdef CONFIG_USER_ONLY
8468
8469 static void switch_mode(CPUARMState *env, int mode)
8470 {
8471 ARMCPU *cpu = env_archcpu(env);
8472
8473 if (mode != ARM_CPU_MODE_USR) {
8474 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
8475 }
8476 }
8477
8478 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
8479 uint32_t cur_el, bool secure)
8480 {
8481 return 1;
8482 }
8483
8484 void aarch64_sync_64_to_32(CPUARMState *env)
8485 {
8486 g_assert_not_reached();
8487 }
8488
8489 #else
8490
8491 static void switch_mode(CPUARMState *env, int mode)
8492 {
8493 int old_mode;
8494 int i;
8495
8496 old_mode = env->uncached_cpsr & CPSR_M;
8497 if (mode == old_mode)
8498 return;
8499
8500 if (old_mode == ARM_CPU_MODE_FIQ) {
8501 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8502 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
8503 } else if (mode == ARM_CPU_MODE_FIQ) {
8504 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8505 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
8506 }
8507
8508 i = bank_number(old_mode);
8509 env->banked_r13[i] = env->regs[13];
8510 env->banked_spsr[i] = env->spsr;
8511
8512 i = bank_number(mode);
8513 env->regs[13] = env->banked_r13[i];
8514 env->spsr = env->banked_spsr[i];
8515
8516 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14];
8517 env->regs[14] = env->banked_r14[r14_bank_number(mode)];
8518 }
8519
8520 /* Physical Interrupt Target EL Lookup Table
8521 *
8522 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
8523 *
8524 * The below multi-dimensional table is used for looking up the target
8525 * exception level given numerous condition criteria. Specifically, the
8526 * target EL is based on SCR and HCR routing controls as well as the
8527 * currently executing EL and secure state.
8528 *
8529 * Dimensions:
8530 * target_el_table[2][2][2][2][2][4]
8531 * | | | | | +--- Current EL
8532 * | | | | +------ Non-secure(0)/Secure(1)
8533 * | | | +--------- HCR mask override
8534 * | | +------------ SCR exec state control
8535 * | +--------------- SCR mask override
8536 * +------------------ 32-bit(0)/64-bit(1) EL3
8537 *
8538 * The table values are as such:
8539 * 0-3 = EL0-EL3
8540 * -1 = Cannot occur
8541 *
8542 * The ARM ARM target EL table includes entries indicating that an "exception
8543 * is not taken". The two cases where this is applicable are:
8544 * 1) An exception is taken from EL3 but the SCR does not have the exception
8545 * routed to EL3.
8546 * 2) An exception is taken from EL2 but the HCR does not have the exception
8547 * routed to EL2.
8548 * In these two cases, the below table contain a target of EL1. This value is
8549 * returned as it is expected that the consumer of the table data will check
8550 * for "target EL >= current EL" to ensure the exception is not taken.
8551 *
8552 * SCR HCR
8553 * 64 EA AMO From
8554 * BIT IRQ IMO Non-secure Secure
8555 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
8556 */
8557 static const int8_t target_el_table[2][2][2][2][2][4] = {
8558 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8559 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
8560 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8561 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
8562 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8563 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
8564 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
8565 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
8566 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
8567 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
8568 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
8569 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
8570 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8571 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
8572 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
8573 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
8574 };
8575
8576 /*
8577 * Determine the target EL for physical exceptions
8578 */
8579 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
8580 uint32_t cur_el, bool secure)
8581 {
8582 CPUARMState *env = cs->env_ptr;
8583 bool rw;
8584 bool scr;
8585 bool hcr;
8586 int target_el;
8587 /* Is the highest EL AArch64? */
8588 bool is64 = arm_feature(env, ARM_FEATURE_AARCH64);
8589 uint64_t hcr_el2;
8590
8591 if (arm_feature(env, ARM_FEATURE_EL3)) {
8592 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
8593 } else {
8594 /* Either EL2 is the highest EL (and so the EL2 register width
8595 * is given by is64); or there is no EL2 or EL3, in which case
8596 * the value of 'rw' does not affect the table lookup anyway.
8597 */
8598 rw = is64;
8599 }
8600
8601 hcr_el2 = arm_hcr_el2_eff(env);
8602 switch (excp_idx) {
8603 case EXCP_IRQ:
8604 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
8605 hcr = hcr_el2 & HCR_IMO;
8606 break;
8607 case EXCP_FIQ:
8608 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
8609 hcr = hcr_el2 & HCR_FMO;
8610 break;
8611 default:
8612 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
8613 hcr = hcr_el2 & HCR_AMO;
8614 break;
8615 };
8616
8617 /*
8618 * For these purposes, TGE and AMO/IMO/FMO both force the
8619 * interrupt to EL2. Fold TGE into the bit extracted above.
8620 */
8621 hcr |= (hcr_el2 & HCR_TGE) != 0;
8622
8623 /* Perform a table-lookup for the target EL given the current state */
8624 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
8625
8626 assert(target_el > 0);
8627
8628 return target_el;
8629 }
8630
8631 void arm_log_exception(int idx)
8632 {
8633 if (qemu_loglevel_mask(CPU_LOG_INT)) {
8634 const char *exc = NULL;
8635 static const char * const excnames[] = {
8636 [EXCP_UDEF] = "Undefined Instruction",
8637 [EXCP_SWI] = "SVC",
8638 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
8639 [EXCP_DATA_ABORT] = "Data Abort",
8640 [EXCP_IRQ] = "IRQ",
8641 [EXCP_FIQ] = "FIQ",
8642 [EXCP_BKPT] = "Breakpoint",
8643 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
8644 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
8645 [EXCP_HVC] = "Hypervisor Call",
8646 [EXCP_HYP_TRAP] = "Hypervisor Trap",
8647 [EXCP_SMC] = "Secure Monitor Call",
8648 [EXCP_VIRQ] = "Virtual IRQ",
8649 [EXCP_VFIQ] = "Virtual FIQ",
8650 [EXCP_SEMIHOST] = "Semihosting call",
8651 [EXCP_NOCP] = "v7M NOCP UsageFault",
8652 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
8653 [EXCP_STKOF] = "v8M STKOF UsageFault",
8654 [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
8655 [EXCP_LSERR] = "v8M LSERR UsageFault",
8656 [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
8657 };
8658
8659 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
8660 exc = excnames[idx];
8661 }
8662 if (!exc) {
8663 exc = "unknown";
8664 }
8665 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
8666 }
8667 }
8668
8669 /*
8670 * Function used to synchronize QEMU's AArch64 register set with AArch32
8671 * register set. This is necessary when switching between AArch32 and AArch64
8672 * execution state.
8673 */
8674 void aarch64_sync_32_to_64(CPUARMState *env)
8675 {
8676 int i;
8677 uint32_t mode = env->uncached_cpsr & CPSR_M;
8678
8679 /* We can blanket copy R[0:7] to X[0:7] */
8680 for (i = 0; i < 8; i++) {
8681 env->xregs[i] = env->regs[i];
8682 }
8683
8684 /*
8685 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
8686 * Otherwise, they come from the banked user regs.
8687 */
8688 if (mode == ARM_CPU_MODE_FIQ) {
8689 for (i = 8; i < 13; i++) {
8690 env->xregs[i] = env->usr_regs[i - 8];
8691 }
8692 } else {
8693 for (i = 8; i < 13; i++) {
8694 env->xregs[i] = env->regs[i];
8695 }
8696 }
8697
8698 /*
8699 * Registers x13-x23 are the various mode SP and FP registers. Registers
8700 * r13 and r14 are only copied if we are in that mode, otherwise we copy
8701 * from the mode banked register.
8702 */
8703 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
8704 env->xregs[13] = env->regs[13];
8705 env->xregs[14] = env->regs[14];
8706 } else {
8707 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
8708 /* HYP is an exception in that it is copied from r14 */
8709 if (mode == ARM_CPU_MODE_HYP) {
8710 env->xregs[14] = env->regs[14];
8711 } else {
8712 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
8713 }
8714 }
8715
8716 if (mode == ARM_CPU_MODE_HYP) {
8717 env->xregs[15] = env->regs[13];
8718 } else {
8719 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
8720 }
8721
8722 if (mode == ARM_CPU_MODE_IRQ) {
8723 env->xregs[16] = env->regs[14];
8724 env->xregs[17] = env->regs[13];
8725 } else {
8726 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
8727 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
8728 }
8729
8730 if (mode == ARM_CPU_MODE_SVC) {
8731 env->xregs[18] = env->regs[14];
8732 env->xregs[19] = env->regs[13];
8733 } else {
8734 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
8735 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
8736 }
8737
8738 if (mode == ARM_CPU_MODE_ABT) {
8739 env->xregs[20] = env->regs[14];
8740 env->xregs[21] = env->regs[13];
8741 } else {
8742 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
8743 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
8744 }
8745
8746 if (mode == ARM_CPU_MODE_UND) {
8747 env->xregs[22] = env->regs[14];
8748 env->xregs[23] = env->regs[13];
8749 } else {
8750 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
8751 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
8752 }
8753
8754 /*
8755 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8756 * mode, then we can copy from r8-r14. Otherwise, we copy from the
8757 * FIQ bank for r8-r14.
8758 */
8759 if (mode == ARM_CPU_MODE_FIQ) {
8760 for (i = 24; i < 31; i++) {
8761 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
8762 }
8763 } else {
8764 for (i = 24; i < 29; i++) {
8765 env->xregs[i] = env->fiq_regs[i - 24];
8766 }
8767 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
8768 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
8769 }
8770
8771 env->pc = env->regs[15];
8772 }
8773
8774 /*
8775 * Function used to synchronize QEMU's AArch32 register set with AArch64
8776 * register set. This is necessary when switching between AArch32 and AArch64
8777 * execution state.
8778 */
8779 void aarch64_sync_64_to_32(CPUARMState *env)
8780 {
8781 int i;
8782 uint32_t mode = env->uncached_cpsr & CPSR_M;
8783
8784 /* We can blanket copy X[0:7] to R[0:7] */
8785 for (i = 0; i < 8; i++) {
8786 env->regs[i] = env->xregs[i];
8787 }
8788
8789 /*
8790 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
8791 * Otherwise, we copy x8-x12 into the banked user regs.
8792 */
8793 if (mode == ARM_CPU_MODE_FIQ) {
8794 for (i = 8; i < 13; i++) {
8795 env->usr_regs[i - 8] = env->xregs[i];
8796 }
8797 } else {
8798 for (i = 8; i < 13; i++) {
8799 env->regs[i] = env->xregs[i];
8800 }
8801 }
8802
8803 /*
8804 * Registers r13 & r14 depend on the current mode.
8805 * If we are in a given mode, we copy the corresponding x registers to r13
8806 * and r14. Otherwise, we copy the x register to the banked r13 and r14
8807 * for the mode.
8808 */
8809 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
8810 env->regs[13] = env->xregs[13];
8811 env->regs[14] = env->xregs[14];
8812 } else {
8813 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
8814
8815 /*
8816 * HYP is an exception in that it does not have its own banked r14 but
8817 * shares the USR r14
8818 */
8819 if (mode == ARM_CPU_MODE_HYP) {
8820 env->regs[14] = env->xregs[14];
8821 } else {
8822 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
8823 }
8824 }
8825
8826 if (mode == ARM_CPU_MODE_HYP) {
8827 env->regs[13] = env->xregs[15];
8828 } else {
8829 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
8830 }
8831
8832 if (mode == ARM_CPU_MODE_IRQ) {
8833 env->regs[14] = env->xregs[16];
8834 env->regs[13] = env->xregs[17];
8835 } else {
8836 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
8837 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
8838 }
8839
8840 if (mode == ARM_CPU_MODE_SVC) {
8841 env->regs[14] = env->xregs[18];
8842 env->regs[13] = env->xregs[19];
8843 } else {
8844 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
8845 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
8846 }
8847
8848 if (mode == ARM_CPU_MODE_ABT) {
8849 env->regs[14] = env->xregs[20];
8850 env->regs[13] = env->xregs[21];
8851 } else {
8852 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
8853 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
8854 }
8855
8856 if (mode == ARM_CPU_MODE_UND) {
8857 env->regs[14] = env->xregs[22];
8858 env->regs[13] = env->xregs[23];
8859 } else {
8860 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
8861 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
8862 }
8863
8864 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8865 * mode, then we can copy to r8-r14. Otherwise, we copy to the
8866 * FIQ bank for r8-r14.
8867 */
8868 if (mode == ARM_CPU_MODE_FIQ) {
8869 for (i = 24; i < 31; i++) {
8870 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
8871 }
8872 } else {
8873 for (i = 24; i < 29; i++) {
8874 env->fiq_regs[i - 24] = env->xregs[i];
8875 }
8876 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
8877 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
8878 }
8879
8880 env->regs[15] = env->pc;
8881 }
8882
8883 static void take_aarch32_exception(CPUARMState *env, int new_mode,
8884 uint32_t mask, uint32_t offset,
8885 uint32_t newpc)
8886 {
8887 int new_el;
8888
8889 /* Change the CPU state so as to actually take the exception. */
8890 switch_mode(env, new_mode);
8891 new_el = arm_current_el(env);
8892
8893 /*
8894 * For exceptions taken to AArch32 we must clear the SS bit in both
8895 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8896 */
8897 env->uncached_cpsr &= ~PSTATE_SS;
8898 env->spsr = cpsr_read(env);
8899 /* Clear IT bits. */
8900 env->condexec_bits = 0;
8901 /* Switch to the new mode, and to the correct instruction set. */
8902 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
8903 /* Set new mode endianness */
8904 env->uncached_cpsr &= ~CPSR_E;
8905 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
8906 env->uncached_cpsr |= CPSR_E;
8907 }
8908 /* J and IL must always be cleared for exception entry */
8909 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
8910 env->daif |= mask;
8911
8912 if (new_mode == ARM_CPU_MODE_HYP) {
8913 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
8914 env->elr_el[2] = env->regs[15];
8915 } else {
8916 /* CPSR.PAN is normally preserved preserved unless... */
8917 if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
8918 switch (new_el) {
8919 case 3:
8920 if (!arm_is_secure_below_el3(env)) {
8921 /* ... the target is EL3, from non-secure state. */
8922 env->uncached_cpsr &= ~CPSR_PAN;
8923 break;
8924 }
8925 /* ... the target is EL3, from secure state ... */
8926 /* fall through */
8927 case 1:
8928 /* ... the target is EL1 and SCTLR.SPAN is 0. */
8929 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) {
8930 env->uncached_cpsr |= CPSR_PAN;
8931 }
8932 break;
8933 }
8934 }
8935 /*
8936 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8937 * and we should just guard the thumb mode on V4
8938 */
8939 if (arm_feature(env, ARM_FEATURE_V4T)) {
8940 env->thumb =
8941 (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
8942 }
8943 env->regs[14] = env->regs[15] + offset;
8944 }
8945 env->regs[15] = newpc;
8946 arm_rebuild_hflags(env);
8947 }
8948
8949 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
8950 {
8951 /*
8952 * Handle exception entry to Hyp mode; this is sufficiently
8953 * different to entry to other AArch32 modes that we handle it
8954 * separately here.
8955 *
8956 * The vector table entry used is always the 0x14 Hyp mode entry point,
8957 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8958 * The offset applied to the preferred return address is always zero
8959 * (see DDI0487C.a section G1.12.3).
8960 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8961 */
8962 uint32_t addr, mask;
8963 ARMCPU *cpu = ARM_CPU(cs);
8964 CPUARMState *env = &cpu->env;
8965
8966 switch (cs->exception_index) {
8967 case EXCP_UDEF:
8968 addr = 0x04;
8969 break;
8970 case EXCP_SWI:
8971 addr = 0x14;
8972 break;
8973 case EXCP_BKPT:
8974 /* Fall through to prefetch abort. */
8975 case EXCP_PREFETCH_ABORT:
8976 env->cp15.ifar_s = env->exception.vaddress;
8977 qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n",
8978 (uint32_t)env->exception.vaddress);
8979 addr = 0x0c;
8980 break;
8981 case EXCP_DATA_ABORT:
8982 env->cp15.dfar_s = env->exception.vaddress;
8983 qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n",
8984 (uint32_t)env->exception.vaddress);
8985 addr = 0x10;
8986 break;
8987 case EXCP_IRQ:
8988 addr = 0x18;
8989 break;
8990 case EXCP_FIQ:
8991 addr = 0x1c;
8992 break;
8993 case EXCP_HVC:
8994 addr = 0x08;
8995 break;
8996 case EXCP_HYP_TRAP:
8997 addr = 0x14;
8998 break;
8999 default:
9000 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9001 }
9002
9003 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
9004 if (!arm_feature(env, ARM_FEATURE_V8)) {
9005 /*
9006 * QEMU syndrome values are v8-style. v7 has the IL bit
9007 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9008 * If this is a v7 CPU, squash the IL bit in those cases.
9009 */
9010 if (cs->exception_index == EXCP_PREFETCH_ABORT ||
9011 (cs->exception_index == EXCP_DATA_ABORT &&
9012 !(env->exception.syndrome & ARM_EL_ISV)) ||
9013 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) {
9014 env->exception.syndrome &= ~ARM_EL_IL;
9015 }
9016 }
9017 env->cp15.esr_el[2] = env->exception.syndrome;
9018 }
9019
9020 if (arm_current_el(env) != 2 && addr < 0x14) {
9021 addr = 0x14;
9022 }
9023
9024 mask = 0;
9025 if (!(env->cp15.scr_el3 & SCR_EA)) {
9026 mask |= CPSR_A;
9027 }
9028 if (!(env->cp15.scr_el3 & SCR_IRQ)) {
9029 mask |= CPSR_I;
9030 }
9031 if (!(env->cp15.scr_el3 & SCR_FIQ)) {
9032 mask |= CPSR_F;
9033 }
9034
9035 addr += env->cp15.hvbar;
9036
9037 take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr);
9038 }
9039
9040 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
9041 {
9042 ARMCPU *cpu = ARM_CPU(cs);
9043 CPUARMState *env = &cpu->env;
9044 uint32_t addr;
9045 uint32_t mask;
9046 int new_mode;
9047 uint32_t offset;
9048 uint32_t moe;
9049
9050 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9051 switch (syn_get_ec(env->exception.syndrome)) {
9052 case EC_BREAKPOINT:
9053 case EC_BREAKPOINT_SAME_EL:
9054 moe = 1;
9055 break;
9056 case EC_WATCHPOINT:
9057 case EC_WATCHPOINT_SAME_EL:
9058 moe = 10;
9059 break;
9060 case EC_AA32_BKPT:
9061 moe = 3;
9062 break;
9063 case EC_VECTORCATCH:
9064 moe = 5;
9065 break;
9066 default:
9067 moe = 0;
9068 break;
9069 }
9070
9071 if (moe) {
9072 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
9073 }
9074
9075 if (env->exception.target_el == 2) {
9076 arm_cpu_do_interrupt_aarch32_hyp(cs);
9077 return;
9078 }
9079
9080 switch (cs->exception_index) {
9081 case EXCP_UDEF:
9082 new_mode = ARM_CPU_MODE_UND;
9083 addr = 0x04;
9084 mask = CPSR_I;
9085 if (env->thumb)
9086 offset = 2;
9087 else
9088 offset = 4;
9089 break;
9090 case EXCP_SWI:
9091 new_mode = ARM_CPU_MODE_SVC;
9092 addr = 0x08;
9093 mask = CPSR_I;
9094 /* The PC already points to the next instruction. */
9095 offset = 0;
9096 break;
9097 case EXCP_BKPT:
9098 /* Fall through to prefetch abort. */
9099 case EXCP_PREFETCH_ABORT:
9100 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
9101 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
9102 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
9103 env->exception.fsr, (uint32_t)env->exception.vaddress);
9104 new_mode = ARM_CPU_MODE_ABT;
9105 addr = 0x0c;
9106 mask = CPSR_A | CPSR_I;
9107 offset = 4;
9108 break;
9109 case EXCP_DATA_ABORT:
9110 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
9111 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
9112 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
9113 env->exception.fsr,
9114 (uint32_t)env->exception.vaddress);
9115 new_mode = ARM_CPU_MODE_ABT;
9116 addr = 0x10;
9117 mask = CPSR_A | CPSR_I;
9118 offset = 8;
9119 break;
9120 case EXCP_IRQ:
9121 new_mode = ARM_CPU_MODE_IRQ;
9122 addr = 0x18;
9123 /* Disable IRQ and imprecise data aborts. */
9124 mask = CPSR_A | CPSR_I;
9125 offset = 4;
9126 if (env->cp15.scr_el3 & SCR_IRQ) {
9127 /* IRQ routed to monitor mode */
9128 new_mode = ARM_CPU_MODE_MON;
9129 mask |= CPSR_F;
9130 }
9131 break;
9132 case EXCP_FIQ:
9133 new_mode = ARM_CPU_MODE_FIQ;
9134 addr = 0x1c;
9135 /* Disable FIQ, IRQ and imprecise data aborts. */
9136 mask = CPSR_A | CPSR_I | CPSR_F;
9137 if (env->cp15.scr_el3 & SCR_FIQ) {
9138 /* FIQ routed to monitor mode */
9139 new_mode = ARM_CPU_MODE_MON;
9140 }
9141 offset = 4;
9142 break;
9143 case EXCP_VIRQ:
9144 new_mode = ARM_CPU_MODE_IRQ;
9145 addr = 0x18;
9146 /* Disable IRQ and imprecise data aborts. */
9147 mask = CPSR_A | CPSR_I;
9148 offset = 4;
9149 break;
9150 case EXCP_VFIQ:
9151 new_mode = ARM_CPU_MODE_FIQ;
9152 addr = 0x1c;
9153 /* Disable FIQ, IRQ and imprecise data aborts. */
9154 mask = CPSR_A | CPSR_I | CPSR_F;
9155 offset = 4;
9156 break;
9157 case EXCP_SMC:
9158 new_mode = ARM_CPU_MODE_MON;
9159 addr = 0x08;
9160 mask = CPSR_A | CPSR_I | CPSR_F;
9161 offset = 0;
9162 break;
9163 default:
9164 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9165 return; /* Never happens. Keep compiler happy. */
9166 }
9167
9168 if (new_mode == ARM_CPU_MODE_MON) {
9169 addr += env->cp15.mvbar;
9170 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
9171 /* High vectors. When enabled, base address cannot be remapped. */
9172 addr += 0xffff0000;
9173 } else {
9174 /* ARM v7 architectures provide a vector base address register to remap
9175 * the interrupt vector table.
9176 * This register is only followed in non-monitor mode, and is banked.
9177 * Note: only bits 31:5 are valid.
9178 */
9179 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
9180 }
9181
9182 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
9183 env->cp15.scr_el3 &= ~SCR_NS;
9184 }
9185
9186 take_aarch32_exception(env, new_mode, mask, offset, addr);
9187 }
9188
9189 /* Handle exception entry to a target EL which is using AArch64 */
9190 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
9191 {
9192 ARMCPU *cpu = ARM_CPU(cs);
9193 CPUARMState *env = &cpu->env;
9194 unsigned int new_el = env->exception.target_el;
9195 target_ulong addr = env->cp15.vbar_el[new_el];
9196 unsigned int new_mode = aarch64_pstate_mode(new_el, true);
9197 unsigned int old_mode;
9198 unsigned int cur_el = arm_current_el(env);
9199
9200 /*
9201 * Note that new_el can never be 0. If cur_el is 0, then
9202 * el0_a64 is is_a64(), else el0_a64 is ignored.
9203 */
9204 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
9205
9206 if (cur_el < new_el) {
9207 /* Entry vector offset depends on whether the implemented EL
9208 * immediately lower than the target level is using AArch32 or AArch64
9209 */
9210 bool is_aa64;
9211 uint64_t hcr;
9212
9213 switch (new_el) {
9214 case 3:
9215 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
9216 break;
9217 case 2:
9218 hcr = arm_hcr_el2_eff(env);
9219 if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
9220 is_aa64 = (hcr & HCR_RW) != 0;
9221 break;
9222 }
9223 /* fall through */
9224 case 1:
9225 is_aa64 = is_a64(env);
9226 break;
9227 default:
9228 g_assert_not_reached();
9229 }
9230
9231 if (is_aa64) {
9232 addr += 0x400;
9233 } else {
9234 addr += 0x600;
9235 }
9236 } else if (pstate_read(env) & PSTATE_SP) {
9237 addr += 0x200;
9238 }
9239
9240 switch (cs->exception_index) {
9241 case EXCP_PREFETCH_ABORT:
9242 case EXCP_DATA_ABORT:
9243 env->cp15.far_el[new_el] = env->exception.vaddress;
9244 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
9245 env->cp15.far_el[new_el]);
9246 /* fall through */
9247 case EXCP_BKPT:
9248 case EXCP_UDEF:
9249 case EXCP_SWI:
9250 case EXCP_HVC:
9251 case EXCP_HYP_TRAP:
9252 case EXCP_SMC:
9253 if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) {
9254 /*
9255 * QEMU internal FP/SIMD syndromes from AArch32 include the
9256 * TA and coproc fields which are only exposed if the exception
9257 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9258 * AArch64 format syndrome.
9259 */
9260 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20);
9261 }
9262 env->cp15.esr_el[new_el] = env->exception.syndrome;
9263 break;
9264 case EXCP_IRQ:
9265 case EXCP_VIRQ:
9266 addr += 0x80;
9267 break;
9268 case EXCP_FIQ:
9269 case EXCP_VFIQ:
9270 addr += 0x100;
9271 break;
9272 default:
9273 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9274 }
9275
9276 if (is_a64(env)) {
9277 old_mode = pstate_read(env);
9278 aarch64_save_sp(env, arm_current_el(env));
9279 env->elr_el[new_el] = env->pc;
9280 } else {
9281 old_mode = cpsr_read(env);
9282 env->elr_el[new_el] = env->regs[15];
9283
9284 aarch64_sync_32_to_64(env);
9285
9286 env->condexec_bits = 0;
9287 }
9288 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
9289
9290 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
9291 env->elr_el[new_el]);
9292
9293 if (cpu_isar_feature(aa64_pan, cpu)) {
9294 /* The value of PSTATE.PAN is normally preserved, except when ... */
9295 new_mode |= old_mode & PSTATE_PAN;
9296 switch (new_el) {
9297 case 2:
9298 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9299 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE))
9300 != (HCR_E2H | HCR_TGE)) {
9301 break;
9302 }
9303 /* fall through */
9304 case 1:
9305 /* ... the target is EL1 ... */
9306 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9307 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) {
9308 new_mode |= PSTATE_PAN;
9309 }
9310 break;
9311 }
9312 }
9313
9314 pstate_write(env, PSTATE_DAIF | new_mode);
9315 env->aarch64 = 1;
9316 aarch64_restore_sp(env, new_el);
9317 helper_rebuild_hflags_a64(env, new_el);
9318
9319 env->pc = addr;
9320
9321 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
9322 new_el, env->pc, pstate_read(env));
9323 }
9324
9325 /*
9326 * Do semihosting call and set the appropriate return value. All the
9327 * permission and validity checks have been done at translate time.
9328 *
9329 * We only see semihosting exceptions in TCG only as they are not
9330 * trapped to the hypervisor in KVM.
9331 */
9332 #ifdef CONFIG_TCG
9333 static void handle_semihosting(CPUState *cs)
9334 {
9335 ARMCPU *cpu = ARM_CPU(cs);
9336 CPUARMState *env = &cpu->env;
9337
9338 if (is_a64(env)) {
9339 qemu_log_mask(CPU_LOG_INT,
9340 "...handling as semihosting call 0x%" PRIx64 "\n",
9341 env->xregs[0]);
9342 env->xregs[0] = do_arm_semihosting(env);
9343 env->pc += 4;
9344 } else {
9345 qemu_log_mask(CPU_LOG_INT,
9346 "...handling as semihosting call 0x%x\n",
9347 env->regs[0]);
9348 env->regs[0] = do_arm_semihosting(env);
9349 env->regs[15] += env->thumb ? 2 : 4;
9350 }
9351 }
9352 #endif
9353
9354 /* Handle a CPU exception for A and R profile CPUs.
9355 * Do any appropriate logging, handle PSCI calls, and then hand off
9356 * to the AArch64-entry or AArch32-entry function depending on the
9357 * target exception level's register width.
9358 */
9359 void arm_cpu_do_interrupt(CPUState *cs)
9360 {
9361 ARMCPU *cpu = ARM_CPU(cs);
9362 CPUARMState *env = &cpu->env;
9363 unsigned int new_el = env->exception.target_el;
9364
9365 assert(!arm_feature(env, ARM_FEATURE_M));
9366
9367 arm_log_exception(cs->exception_index);
9368 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
9369 new_el);
9370 if (qemu_loglevel_mask(CPU_LOG_INT)
9371 && !excp_is_internal(cs->exception_index)) {
9372 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
9373 syn_get_ec(env->exception.syndrome),
9374 env->exception.syndrome);
9375 }
9376
9377 if (arm_is_psci_call(cpu, cs->exception_index)) {
9378 arm_handle_psci_call(cpu);
9379 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
9380 return;
9381 }
9382
9383 /*
9384 * Semihosting semantics depend on the register width of the code
9385 * that caused the exception, not the target exception level, so
9386 * must be handled here.
9387 */
9388 #ifdef CONFIG_TCG
9389 if (cs->exception_index == EXCP_SEMIHOST) {
9390 handle_semihosting(cs);
9391 return;
9392 }
9393 #endif
9394
9395 /* Hooks may change global state so BQL should be held, also the
9396 * BQL needs to be held for any modification of
9397 * cs->interrupt_request.
9398 */
9399 g_assert(qemu_mutex_iothread_locked());
9400
9401 arm_call_pre_el_change_hook(cpu);
9402
9403 assert(!excp_is_internal(cs->exception_index));
9404 if (arm_el_is_aa64(env, new_el)) {
9405 arm_cpu_do_interrupt_aarch64(cs);
9406 } else {
9407 arm_cpu_do_interrupt_aarch32(cs);
9408 }
9409
9410 arm_call_el_change_hook(cpu);
9411
9412 if (!kvm_enabled()) {
9413 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
9414 }
9415 }
9416 #endif /* !CONFIG_USER_ONLY */
9417
9418 /* Return the exception level which controls this address translation regime */
9419 static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
9420 {
9421 switch (mmu_idx) {
9422 case ARMMMUIdx_E20_0:
9423 case ARMMMUIdx_E20_2:
9424 case ARMMMUIdx_E20_2_PAN:
9425 case ARMMMUIdx_Stage2:
9426 case ARMMMUIdx_E2:
9427 return 2;
9428 case ARMMMUIdx_SE3:
9429 return 3;
9430 case ARMMMUIdx_SE10_0:
9431 return arm_el_is_aa64(env, 3) ? 1 : 3;
9432 case ARMMMUIdx_SE10_1:
9433 case ARMMMUIdx_SE10_1_PAN:
9434 case ARMMMUIdx_Stage1_E0:
9435 case ARMMMUIdx_Stage1_E1:
9436 case ARMMMUIdx_Stage1_E1_PAN:
9437 case ARMMMUIdx_E10_0:
9438 case ARMMMUIdx_E10_1:
9439 case ARMMMUIdx_E10_1_PAN:
9440 case ARMMMUIdx_MPrivNegPri:
9441 case ARMMMUIdx_MUserNegPri:
9442 case ARMMMUIdx_MPriv:
9443 case ARMMMUIdx_MUser:
9444 case ARMMMUIdx_MSPrivNegPri:
9445 case ARMMMUIdx_MSUserNegPri:
9446 case ARMMMUIdx_MSPriv:
9447 case ARMMMUIdx_MSUser:
9448 return 1;
9449 default:
9450 g_assert_not_reached();
9451 }
9452 }
9453
9454 uint64_t arm_sctlr(CPUARMState *env, int el)
9455 {
9456 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
9457 if (el == 0) {
9458 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
9459 el = (mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1);
9460 }
9461 return env->cp15.sctlr_el[el];
9462 }
9463
9464 /* Return the SCTLR value which controls this address translation regime */
9465 static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
9466 {
9467 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
9468 }
9469
9470 #ifndef CONFIG_USER_ONLY
9471
9472 /* Return true if the specified stage of address translation is disabled */
9473 static inline bool regime_translation_disabled(CPUARMState *env,
9474 ARMMMUIdx mmu_idx)
9475 {
9476 if (arm_feature(env, ARM_FEATURE_M)) {
9477 switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
9478 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
9479 case R_V7M_MPU_CTRL_ENABLE_MASK:
9480 /* Enabled, but not for HardFault and NMI */
9481 return mmu_idx & ARM_MMU_IDX_M_NEGPRI;
9482 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
9483 /* Enabled for all cases */
9484 return false;
9485 case 0:
9486 default:
9487 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9488 * we warned about that in armv7m_nvic.c when the guest set it.
9489 */
9490 return true;
9491 }
9492 }
9493
9494 if (mmu_idx == ARMMMUIdx_Stage2) {
9495 /* HCR.DC means HCR.VM behaves as 1 */
9496 return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
9497 }
9498
9499 if (env->cp15.hcr_el2 & HCR_TGE) {
9500 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
9501 if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
9502 return true;
9503 }
9504 }
9505
9506 if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
9507 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
9508 return true;
9509 }
9510
9511 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
9512 }
9513
9514 static inline bool regime_translation_big_endian(CPUARMState *env,
9515 ARMMMUIdx mmu_idx)
9516 {
9517 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
9518 }
9519
9520 /* Return the TTBR associated with this translation regime */
9521 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
9522 int ttbrn)
9523 {
9524 if (mmu_idx == ARMMMUIdx_Stage2) {
9525 return env->cp15.vttbr_el2;
9526 }
9527 if (ttbrn == 0) {
9528 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
9529 } else {
9530 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
9531 }
9532 }
9533
9534 #endif /* !CONFIG_USER_ONLY */
9535
9536 /* Return the TCR controlling this translation regime */
9537 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
9538 {
9539 if (mmu_idx == ARMMMUIdx_Stage2) {
9540 return &env->cp15.vtcr_el2;
9541 }
9542 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
9543 }
9544
9545 /* Convert a possible stage1+2 MMU index into the appropriate
9546 * stage 1 MMU index
9547 */
9548 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
9549 {
9550 switch (mmu_idx) {
9551 case ARMMMUIdx_E10_0:
9552 return ARMMMUIdx_Stage1_E0;
9553 case ARMMMUIdx_E10_1:
9554 return ARMMMUIdx_Stage1_E1;
9555 case ARMMMUIdx_E10_1_PAN:
9556 return ARMMMUIdx_Stage1_E1_PAN;
9557 default:
9558 return mmu_idx;
9559 }
9560 }
9561
9562 /* Return true if the translation regime is using LPAE format page tables */
9563 static inline bool regime_using_lpae_format(CPUARMState *env,
9564 ARMMMUIdx mmu_idx)
9565 {
9566 int el = regime_el(env, mmu_idx);
9567 if (el == 2 || arm_el_is_aa64(env, el)) {
9568 return true;
9569 }
9570 if (arm_feature(env, ARM_FEATURE_LPAE)
9571 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
9572 return true;
9573 }
9574 return false;
9575 }
9576
9577 /* Returns true if the stage 1 translation regime is using LPAE format page
9578 * tables. Used when raising alignment exceptions, whose FSR changes depending
9579 * on whether the long or short descriptor format is in use. */
9580 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
9581 {
9582 mmu_idx = stage_1_mmu_idx(mmu_idx);
9583
9584 return regime_using_lpae_format(env, mmu_idx);
9585 }
9586
9587 #ifndef CONFIG_USER_ONLY
9588 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
9589 {
9590 switch (mmu_idx) {
9591 case ARMMMUIdx_SE10_0:
9592 case ARMMMUIdx_E20_0:
9593 case ARMMMUIdx_Stage1_E0:
9594 case ARMMMUIdx_MUser:
9595 case ARMMMUIdx_MSUser:
9596 case ARMMMUIdx_MUserNegPri:
9597 case ARMMMUIdx_MSUserNegPri:
9598 return true;
9599 default:
9600 return false;
9601 case ARMMMUIdx_E10_0:
9602 case ARMMMUIdx_E10_1:
9603 case ARMMMUIdx_E10_1_PAN:
9604 g_assert_not_reached();
9605 }
9606 }
9607
9608 /* Translate section/page access permissions to page
9609 * R/W protection flags
9610 *
9611 * @env: CPUARMState
9612 * @mmu_idx: MMU index indicating required translation regime
9613 * @ap: The 3-bit access permissions (AP[2:0])
9614 * @domain_prot: The 2-bit domain access permissions
9615 */
9616 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
9617 int ap, int domain_prot)
9618 {
9619 bool is_user = regime_is_user(env, mmu_idx);
9620
9621 if (domain_prot == 3) {
9622 return PAGE_READ | PAGE_WRITE;
9623 }
9624
9625 switch (ap) {
9626 case 0:
9627 if (arm_feature(env, ARM_FEATURE_V7)) {
9628 return 0;
9629 }
9630 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
9631 case SCTLR_S:
9632 return is_user ? 0 : PAGE_READ;
9633 case SCTLR_R:
9634 return PAGE_READ;
9635 default:
9636 return 0;
9637 }
9638 case 1:
9639 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
9640 case 2:
9641 if (is_user) {
9642 return PAGE_READ;
9643 } else {
9644 return PAGE_READ | PAGE_WRITE;
9645 }
9646 case 3:
9647 return PAGE_READ | PAGE_WRITE;
9648 case 4: /* Reserved. */
9649 return 0;
9650 case 5:
9651 return is_user ? 0 : PAGE_READ;
9652 case 6:
9653 return PAGE_READ;
9654 case 7:
9655 if (!arm_feature(env, ARM_FEATURE_V6K)) {
9656 return 0;
9657 }
9658 return PAGE_READ;
9659 default:
9660 g_assert_not_reached();
9661 }
9662 }
9663
9664 /* Translate section/page access permissions to page
9665 * R/W protection flags.
9666 *
9667 * @ap: The 2-bit simple AP (AP[2:1])
9668 * @is_user: TRUE if accessing from PL0
9669 */
9670 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
9671 {
9672 switch (ap) {
9673 case 0:
9674 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
9675 case 1:
9676 return PAGE_READ | PAGE_WRITE;
9677 case 2:
9678 return is_user ? 0 : PAGE_READ;
9679 case 3:
9680 return PAGE_READ;
9681 default:
9682 g_assert_not_reached();
9683 }
9684 }
9685
9686 static inline int
9687 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
9688 {
9689 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
9690 }
9691
9692 /* Translate S2 section/page access permissions to protection flags
9693 *
9694 * @env: CPUARMState
9695 * @s2ap: The 2-bit stage2 access permissions (S2AP)
9696 * @xn: XN (execute-never) bit
9697 */
9698 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
9699 {
9700 int prot = 0;
9701
9702 if (s2ap & 1) {
9703 prot |= PAGE_READ;
9704 }
9705 if (s2ap & 2) {
9706 prot |= PAGE_WRITE;
9707 }
9708 if (!xn) {
9709 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
9710 prot |= PAGE_EXEC;
9711 }
9712 }
9713 return prot;
9714 }
9715
9716 /* Translate section/page access permissions to protection flags
9717 *
9718 * @env: CPUARMState
9719 * @mmu_idx: MMU index indicating required translation regime
9720 * @is_aa64: TRUE if AArch64
9721 * @ap: The 2-bit simple AP (AP[2:1])
9722 * @ns: NS (non-secure) bit
9723 * @xn: XN (execute-never) bit
9724 * @pxn: PXN (privileged execute-never) bit
9725 */
9726 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
9727 int ap, int ns, int xn, int pxn)
9728 {
9729 bool is_user = regime_is_user(env, mmu_idx);
9730 int prot_rw, user_rw;
9731 bool have_wxn;
9732 int wxn = 0;
9733
9734 assert(mmu_idx != ARMMMUIdx_Stage2);
9735
9736 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
9737 if (is_user) {
9738 prot_rw = user_rw;
9739 } else {
9740 if (user_rw && regime_is_pan(env, mmu_idx)) {
9741 return 0;
9742 }
9743 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
9744 }
9745
9746 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
9747 return prot_rw;
9748 }
9749
9750 /* TODO have_wxn should be replaced with
9751 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
9752 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
9753 * compatible processors have EL2, which is required for [U]WXN.
9754 */
9755 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
9756
9757 if (have_wxn) {
9758 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
9759 }
9760
9761 if (is_aa64) {
9762 if (regime_has_2_ranges(mmu_idx) && !is_user) {
9763 xn = pxn || (user_rw & PAGE_WRITE);
9764 }
9765 } else if (arm_feature(env, ARM_FEATURE_V7)) {
9766 switch (regime_el(env, mmu_idx)) {
9767 case 1:
9768 case 3:
9769 if (is_user) {
9770 xn = xn || !(user_rw & PAGE_READ);
9771 } else {
9772 int uwxn = 0;
9773 if (have_wxn) {
9774 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
9775 }
9776 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
9777 (uwxn && (user_rw & PAGE_WRITE));
9778 }
9779 break;
9780 case 2:
9781 break;
9782 }
9783 } else {
9784 xn = wxn = 0;
9785 }
9786
9787 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
9788 return prot_rw;
9789 }
9790 return prot_rw | PAGE_EXEC;
9791 }
9792
9793 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
9794 uint32_t *table, uint32_t address)
9795 {
9796 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
9797 TCR *tcr = regime_tcr(env, mmu_idx);
9798
9799 if (address & tcr->mask) {
9800 if (tcr->raw_tcr & TTBCR_PD1) {
9801 /* Translation table walk disabled for TTBR1 */
9802 return false;
9803 }
9804 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
9805 } else {
9806 if (tcr->raw_tcr & TTBCR_PD0) {
9807 /* Translation table walk disabled for TTBR0 */
9808 return false;
9809 }
9810 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
9811 }
9812 *table |= (address >> 18) & 0x3ffc;
9813 return true;
9814 }
9815
9816 /* Translate a S1 pagetable walk through S2 if needed. */
9817 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
9818 hwaddr addr, MemTxAttrs txattrs,
9819 ARMMMUFaultInfo *fi)
9820 {
9821 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
9822 !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
9823 target_ulong s2size;
9824 hwaddr s2pa;
9825 int s2prot;
9826 int ret;
9827 ARMCacheAttrs cacheattrs = {};
9828 ARMCacheAttrs *pcacheattrs = NULL;
9829
9830 if (env->cp15.hcr_el2 & HCR_PTW) {
9831 /*
9832 * PTW means we must fault if this S1 walk touches S2 Device
9833 * memory; otherwise we don't care about the attributes and can
9834 * save the S2 translation the effort of computing them.
9835 */
9836 pcacheattrs = &cacheattrs;
9837 }
9838
9839 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
9840 &txattrs, &s2prot, &s2size, fi, pcacheattrs);
9841 if (ret) {
9842 assert(fi->type != ARMFault_None);
9843 fi->s2addr = addr;
9844 fi->stage2 = true;
9845 fi->s1ptw = true;
9846 return ~0;
9847 }
9848 if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
9849 /* Access was to Device memory: generate Permission fault */
9850 fi->type = ARMFault_Permission;
9851 fi->s2addr = addr;
9852 fi->stage2 = true;
9853 fi->s1ptw = true;
9854 return ~0;
9855 }
9856 addr = s2pa;
9857 }
9858 return addr;
9859 }
9860
9861 /* All loads done in the course of a page table walk go through here. */
9862 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
9863 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
9864 {
9865 ARMCPU *cpu = ARM_CPU(cs);
9866 CPUARMState *env = &cpu->env;
9867 MemTxAttrs attrs = {};
9868 MemTxResult result = MEMTX_OK;
9869 AddressSpace *as;
9870 uint32_t data;
9871
9872 attrs.secure = is_secure;
9873 as = arm_addressspace(cs, attrs);
9874 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
9875 if (fi->s1ptw) {
9876 return 0;
9877 }
9878 if (regime_translation_big_endian(env, mmu_idx)) {
9879 data = address_space_ldl_be(as, addr, attrs, &result);
9880 } else {
9881 data = address_space_ldl_le(as, addr, attrs, &result);
9882 }
9883 if (result == MEMTX_OK) {
9884 return data;
9885 }
9886 fi->type = ARMFault_SyncExternalOnWalk;
9887 fi->ea = arm_extabort_type(result);
9888 return 0;
9889 }
9890
9891 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
9892 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
9893 {
9894 ARMCPU *cpu = ARM_CPU(cs);
9895 CPUARMState *env = &cpu->env;
9896 MemTxAttrs attrs = {};
9897 MemTxResult result = MEMTX_OK;
9898 AddressSpace *as;
9899 uint64_t data;
9900
9901 attrs.secure = is_secure;
9902 as = arm_addressspace(cs, attrs);
9903 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
9904 if (fi->s1ptw) {
9905 return 0;
9906 }
9907 if (regime_translation_big_endian(env, mmu_idx)) {
9908 data = address_space_ldq_be(as, addr, attrs, &result);
9909 } else {
9910 data = address_space_ldq_le(as, addr, attrs, &result);
9911 }
9912 if (result == MEMTX_OK) {
9913 return data;
9914 }
9915 fi->type = ARMFault_SyncExternalOnWalk;
9916 fi->ea = arm_extabort_type(result);
9917 return 0;
9918 }
9919
9920 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
9921 MMUAccessType access_type, ARMMMUIdx mmu_idx,
9922 hwaddr *phys_ptr, int *prot,
9923 target_ulong *page_size,
9924 ARMMMUFaultInfo *fi)
9925 {
9926 CPUState *cs = env_cpu(env);
9927 int level = 1;
9928 uint32_t table;
9929 uint32_t desc;
9930 int type;
9931 int ap;
9932 int domain = 0;
9933 int domain_prot;
9934 hwaddr phys_addr;
9935 uint32_t dacr;
9936
9937 /* Pagetable walk. */
9938 /* Lookup l1 descriptor. */
9939 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
9940 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9941 fi->type = ARMFault_Translation;
9942 goto do_fault;
9943 }
9944 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
9945 mmu_idx, fi);
9946 if (fi->type != ARMFault_None) {
9947 goto do_fault;
9948 }
9949 type = (desc & 3);
9950 domain = (desc >> 5) & 0x0f;
9951 if (regime_el(env, mmu_idx) == 1) {
9952 dacr = env->cp15.dacr_ns;
9953 } else {
9954 dacr = env->cp15.dacr_s;
9955 }
9956 domain_prot = (dacr >> (domain * 2)) & 3;
9957 if (type == 0) {
9958 /* Section translation fault. */
9959 fi->type = ARMFault_Translation;
9960 goto do_fault;
9961 }
9962 if (type != 2) {
9963 level = 2;
9964 }
9965 if (domain_prot == 0 || domain_prot == 2) {
9966 fi->type = ARMFault_Domain;
9967 goto do_fault;
9968 }
9969 if (type == 2) {
9970 /* 1Mb section. */
9971 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
9972 ap = (desc >> 10) & 3;
9973 *page_size = 1024 * 1024;
9974 } else {
9975 /* Lookup l2 entry. */
9976 if (type == 1) {
9977 /* Coarse pagetable. */
9978 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
9979 } else {
9980 /* Fine pagetable. */
9981 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
9982 }
9983 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
9984 mmu_idx, fi);
9985 if (fi->type != ARMFault_None) {
9986 goto do_fault;
9987 }
9988 switch (desc & 3) {
9989 case 0: /* Page translation fault. */
9990 fi->type = ARMFault_Translation;
9991 goto do_fault;
9992 case 1: /* 64k page. */
9993 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
9994 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
9995 *page_size = 0x10000;
9996 break;
9997 case 2: /* 4k page. */
9998 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
9999 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
10000 *page_size = 0x1000;
10001 break;
10002 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10003 if (type == 1) {
10004 /* ARMv6/XScale extended small page format */
10005 if (arm_feature(env, ARM_FEATURE_XSCALE)
10006 || arm_feature(env, ARM_FEATURE_V6)) {
10007 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10008 *page_size = 0x1000;
10009 } else {
10010 /* UNPREDICTABLE in ARMv5; we choose to take a
10011 * page translation fault.
10012 */
10013 fi->type = ARMFault_Translation;
10014 goto do_fault;
10015 }
10016 } else {
10017 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
10018 *page_size = 0x400;
10019 }
10020 ap = (desc >> 4) & 3;
10021 break;
10022 default:
10023 /* Never happens, but compiler isn't smart enough to tell. */
10024 abort();
10025 }
10026 }
10027 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10028 *prot |= *prot ? PAGE_EXEC : 0;
10029 if (!(*prot & (1 << access_type))) {
10030 /* Access permission fault. */
10031 fi->type = ARMFault_Permission;
10032 goto do_fault;
10033 }
10034 *phys_ptr = phys_addr;
10035 return false;
10036 do_fault:
10037 fi->domain = domain;
10038 fi->level = level;
10039 return true;
10040 }
10041
10042 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
10043 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10044 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
10045 target_ulong *page_size, ARMMMUFaultInfo *fi)
10046 {
10047 CPUState *cs = env_cpu(env);
10048 int level = 1;
10049 uint32_t table;
10050 uint32_t desc;
10051 uint32_t xn;
10052 uint32_t pxn = 0;
10053 int type;
10054 int ap;
10055 int domain = 0;
10056 int domain_prot;
10057 hwaddr phys_addr;
10058 uint32_t dacr;
10059 bool ns;
10060
10061 /* Pagetable walk. */
10062 /* Lookup l1 descriptor. */
10063 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
10064 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10065 fi->type = ARMFault_Translation;
10066 goto do_fault;
10067 }
10068 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10069 mmu_idx, fi);
10070 if (fi->type != ARMFault_None) {
10071 goto do_fault;
10072 }
10073 type = (desc & 3);
10074 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
10075 /* Section translation fault, or attempt to use the encoding
10076 * which is Reserved on implementations without PXN.
10077 */
10078 fi->type = ARMFault_Translation;
10079 goto do_fault;
10080 }
10081 if ((type == 1) || !(desc & (1 << 18))) {
10082 /* Page or Section. */
10083 domain = (desc >> 5) & 0x0f;
10084 }
10085 if (regime_el(env, mmu_idx) == 1) {
10086 dacr = env->cp15.dacr_ns;
10087 } else {
10088 dacr = env->cp15.dacr_s;
10089 }
10090 if (type == 1) {
10091 level = 2;
10092 }
10093 domain_prot = (dacr >> (domain * 2)) & 3;
10094 if (domain_prot == 0 || domain_prot == 2) {
10095 /* Section or Page domain fault */
10096 fi->type = ARMFault_Domain;
10097 goto do_fault;
10098 }
10099 if (type != 1) {
10100 if (desc & (1 << 18)) {
10101 /* Supersection. */
10102 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
10103 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
10104 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
10105 *page_size = 0x1000000;
10106 } else {
10107 /* Section. */
10108 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
10109 *page_size = 0x100000;
10110 }
10111 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
10112 xn = desc & (1 << 4);
10113 pxn = desc & 1;
10114 ns = extract32(desc, 19, 1);
10115 } else {
10116 if (arm_feature(env, ARM_FEATURE_PXN)) {
10117 pxn = (desc >> 2) & 1;
10118 }
10119 ns = extract32(desc, 3, 1);
10120 /* Lookup l2 entry. */
10121 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
10122 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10123 mmu_idx, fi);
10124 if (fi->type != ARMFault_None) {
10125 goto do_fault;
10126 }
10127 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
10128 switch (desc & 3) {
10129 case 0: /* Page translation fault. */
10130 fi->type = ARMFault_Translation;
10131 goto do_fault;
10132 case 1: /* 64k page. */
10133 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10134 xn = desc & (1 << 15);
10135 *page_size = 0x10000;
10136 break;
10137 case 2: case 3: /* 4k page. */
10138 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10139 xn = desc & 1;
10140 *page_size = 0x1000;
10141 break;
10142 default:
10143 /* Never happens, but compiler isn't smart enough to tell. */
10144 abort();
10145 }
10146 }
10147 if (domain_prot == 3) {
10148 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10149 } else {
10150 if (pxn && !regime_is_user(env, mmu_idx)) {
10151 xn = 1;
10152 }
10153 if (xn && access_type == MMU_INST_FETCH) {
10154 fi->type = ARMFault_Permission;
10155 goto do_fault;
10156 }
10157
10158 if (arm_feature(env, ARM_FEATURE_V6K) &&
10159 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
10160 /* The simplified model uses AP[0] as an access control bit. */
10161 if ((ap & 1) == 0) {
10162 /* Access flag fault. */
10163 fi->type = ARMFault_AccessFlag;
10164 goto do_fault;
10165 }
10166 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
10167 } else {
10168 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10169 }
10170 if (*prot && !xn) {
10171 *prot |= PAGE_EXEC;
10172 }
10173 if (!(*prot & (1 << access_type))) {
10174 /* Access permission fault. */
10175 fi->type = ARMFault_Permission;
10176 goto do_fault;
10177 }
10178 }
10179 if (ns) {
10180 /* The NS bit will (as required by the architecture) have no effect if
10181 * the CPU doesn't support TZ or this is a non-secure translation
10182 * regime, because the attribute will already be non-secure.
10183 */
10184 attrs->secure = false;
10185 }
10186 *phys_ptr = phys_addr;
10187 return false;
10188 do_fault:
10189 fi->domain = domain;
10190 fi->level = level;
10191 return true;
10192 }
10193
10194 /*
10195 * check_s2_mmu_setup
10196 * @cpu: ARMCPU
10197 * @is_aa64: True if the translation regime is in AArch64 state
10198 * @startlevel: Suggested starting level
10199 * @inputsize: Bitsize of IPAs
10200 * @stride: Page-table stride (See the ARM ARM)
10201 *
10202 * Returns true if the suggested S2 translation parameters are OK and
10203 * false otherwise.
10204 */
10205 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
10206 int inputsize, int stride)
10207 {
10208 const int grainsize = stride + 3;
10209 int startsizecheck;
10210
10211 /* Negative levels are never allowed. */
10212 if (level < 0) {
10213 return false;
10214 }
10215
10216 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
10217 if (startsizecheck < 1 || startsizecheck > stride + 4) {
10218 return false;
10219 }
10220
10221 if (is_aa64) {
10222 CPUARMState *env = &cpu->env;
10223 unsigned int pamax = arm_pamax(cpu);
10224
10225 switch (stride) {
10226 case 13: /* 64KB Pages. */
10227 if (level == 0 || (level == 1 && pamax <= 42)) {
10228 return false;
10229 }
10230 break;
10231 case 11: /* 16KB Pages. */
10232 if (level == 0 || (level == 1 && pamax <= 40)) {
10233 return false;
10234 }
10235 break;
10236 case 9: /* 4KB Pages. */
10237 if (level == 0 && pamax <= 42) {
10238 return false;
10239 }
10240 break;
10241 default:
10242 g_assert_not_reached();
10243 }
10244
10245 /* Inputsize checks. */
10246 if (inputsize > pamax &&
10247 (arm_el_is_aa64(env, 1) || inputsize > 40)) {
10248 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10249 return false;
10250 }
10251 } else {
10252 /* AArch32 only supports 4KB pages. Assert on that. */
10253 assert(stride == 9);
10254
10255 if (level == 0) {
10256 return false;
10257 }
10258 }
10259 return true;
10260 }
10261
10262 /* Translate from the 4-bit stage 2 representation of
10263 * memory attributes (without cache-allocation hints) to
10264 * the 8-bit representation of the stage 1 MAIR registers
10265 * (which includes allocation hints).
10266 *
10267 * ref: shared/translation/attrs/S2AttrDecode()
10268 * .../S2ConvertAttrsHints()
10269 */
10270 static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
10271 {
10272 uint8_t hiattr = extract32(s2attrs, 2, 2);
10273 uint8_t loattr = extract32(s2attrs, 0, 2);
10274 uint8_t hihint = 0, lohint = 0;
10275
10276 if (hiattr != 0) { /* normal memory */
10277 if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */
10278 hiattr = loattr = 1; /* non-cacheable */
10279 } else {
10280 if (hiattr != 1) { /* Write-through or write-back */
10281 hihint = 3; /* RW allocate */
10282 }
10283 if (loattr != 1) { /* Write-through or write-back */
10284 lohint = 3; /* RW allocate */
10285 }
10286 }
10287 }
10288
10289 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
10290 }
10291 #endif /* !CONFIG_USER_ONLY */
10292
10293 static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
10294 {
10295 if (regime_has_2_ranges(mmu_idx)) {
10296 return extract64(tcr, 37, 2);
10297 } else if (mmu_idx == ARMMMUIdx_Stage2) {
10298 return 0; /* VTCR_EL2 */
10299 } else {
10300 return extract32(tcr, 20, 1);
10301 }
10302 }
10303
10304 static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
10305 {
10306 if (regime_has_2_ranges(mmu_idx)) {
10307 return extract64(tcr, 51, 2);
10308 } else if (mmu_idx == ARMMMUIdx_Stage2) {
10309 return 0; /* VTCR_EL2 */
10310 } else {
10311 return extract32(tcr, 29, 1);
10312 }
10313 }
10314
10315 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
10316 ARMMMUIdx mmu_idx, bool data)
10317 {
10318 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
10319 bool epd, hpd, using16k, using64k;
10320 int select, tsz, tbi;
10321
10322 if (!regime_has_2_ranges(mmu_idx)) {
10323 select = 0;
10324 tsz = extract32(tcr, 0, 6);
10325 using64k = extract32(tcr, 14, 1);
10326 using16k = extract32(tcr, 15, 1);
10327 if (mmu_idx == ARMMMUIdx_Stage2) {
10328 /* VTCR_EL2 */
10329 hpd = false;
10330 } else {
10331 hpd = extract32(tcr, 24, 1);
10332 }
10333 epd = false;
10334 } else {
10335 /*
10336 * Bit 55 is always between the two regions, and is canonical for
10337 * determining if address tagging is enabled.
10338 */
10339 select = extract64(va, 55, 1);
10340 if (!select) {
10341 tsz = extract32(tcr, 0, 6);
10342 epd = extract32(tcr, 7, 1);
10343 using64k = extract32(tcr, 14, 1);
10344 using16k = extract32(tcr, 15, 1);
10345 hpd = extract64(tcr, 41, 1);
10346 } else {
10347 int tg = extract32(tcr, 30, 2);
10348 using16k = tg == 1;
10349 using64k = tg == 3;
10350 tsz = extract32(tcr, 16, 6);
10351 epd = extract32(tcr, 23, 1);
10352 hpd = extract64(tcr, 42, 1);
10353 }
10354 }
10355 tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
10356 tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
10357
10358 /* Present TBI as a composite with TBID. */
10359 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
10360 if (!data) {
10361 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
10362 }
10363 tbi = (tbi >> select) & 1;
10364
10365 return (ARMVAParameters) {
10366 .tsz = tsz,
10367 .select = select,
10368 .tbi = tbi,
10369 .epd = epd,
10370 .hpd = hpd,
10371 .using16k = using16k,
10372 .using64k = using64k,
10373 };
10374 }
10375
10376 #ifndef CONFIG_USER_ONLY
10377 static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
10378 ARMMMUIdx mmu_idx)
10379 {
10380 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
10381 uint32_t el = regime_el(env, mmu_idx);
10382 int select, tsz;
10383 bool epd, hpd;
10384
10385 if (mmu_idx == ARMMMUIdx_Stage2) {
10386 /* VTCR */
10387 bool sext = extract32(tcr, 4, 1);
10388 bool sign = extract32(tcr, 3, 1);
10389
10390 /*
10391 * If the sign-extend bit is not the same as t0sz[3], the result
10392 * is unpredictable. Flag this as a guest error.
10393 */
10394 if (sign != sext) {
10395 qemu_log_mask(LOG_GUEST_ERROR,
10396 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10397 }
10398 tsz = sextract32(tcr, 0, 4) + 8;
10399 select = 0;
10400 hpd = false;
10401 epd = false;
10402 } else if (el == 2) {
10403 /* HTCR */
10404 tsz = extract32(tcr, 0, 3);
10405 select = 0;
10406 hpd = extract64(tcr, 24, 1);
10407 epd = false;
10408 } else {
10409 int t0sz = extract32(tcr, 0, 3);
10410 int t1sz = extract32(tcr, 16, 3);
10411
10412 if (t1sz == 0) {
10413 select = va > (0xffffffffu >> t0sz);
10414 } else {
10415 /* Note that we will detect errors later. */
10416 select = va >= ~(0xffffffffu >> t1sz);
10417 }
10418 if (!select) {
10419 tsz = t0sz;
10420 epd = extract32(tcr, 7, 1);
10421 hpd = extract64(tcr, 41, 1);
10422 } else {
10423 tsz = t1sz;
10424 epd = extract32(tcr, 23, 1);
10425 hpd = extract64(tcr, 42, 1);
10426 }
10427 /* For aarch32, hpd0 is not enabled without t2e as well. */
10428 hpd &= extract32(tcr, 6, 1);
10429 }
10430
10431 return (ARMVAParameters) {
10432 .tsz = tsz,
10433 .select = select,
10434 .epd = epd,
10435 .hpd = hpd,
10436 };
10437 }
10438
10439 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
10440 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10441 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
10442 target_ulong *page_size_ptr,
10443 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
10444 {
10445 ARMCPU *cpu = env_archcpu(env);
10446 CPUState *cs = CPU(cpu);
10447 /* Read an LPAE long-descriptor translation table. */
10448 ARMFaultType fault_type = ARMFault_Translation;
10449 uint32_t level;
10450 ARMVAParameters param;
10451 uint64_t ttbr;
10452 hwaddr descaddr, indexmask, indexmask_grainsize;
10453 uint32_t tableattrs;
10454 target_ulong page_size;
10455 uint32_t attrs;
10456 int32_t stride;
10457 int addrsize, inputsize;
10458 TCR *tcr = regime_tcr(env, mmu_idx);
10459 int ap, ns, xn, pxn;
10460 uint32_t el = regime_el(env, mmu_idx);
10461 uint64_t descaddrmask;
10462 bool aarch64 = arm_el_is_aa64(env, el);
10463 bool guarded = false;
10464
10465 /* TODO:
10466 * This code does not handle the different format TCR for VTCR_EL2.
10467 * This code also does not support shareability levels.
10468 * Attribute and permission bit handling should also be checked when adding
10469 * support for those page table walks.
10470 */
10471 if (aarch64) {
10472 param = aa64_va_parameters(env, address, mmu_idx,
10473 access_type != MMU_INST_FETCH);
10474 level = 0;
10475 addrsize = 64 - 8 * param.tbi;
10476 inputsize = 64 - param.tsz;
10477 } else {
10478 param = aa32_va_parameters(env, address, mmu_idx);
10479 level = 1;
10480 addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
10481 inputsize = addrsize - param.tsz;
10482 }
10483
10484 /*
10485 * We determined the region when collecting the parameters, but we
10486 * have not yet validated that the address is valid for the region.
10487 * Extract the top bits and verify that they all match select.
10488 *
10489 * For aa32, if inputsize == addrsize, then we have selected the
10490 * region by exclusion in aa32_va_parameters and there is no more
10491 * validation to do here.
10492 */
10493 if (inputsize < addrsize) {
10494 target_ulong top_bits = sextract64(address, inputsize,
10495 addrsize - inputsize);
10496 if (-top_bits != param.select) {
10497 /* The gap between the two regions is a Translation fault */
10498 fault_type = ARMFault_Translation;
10499 goto do_fault;
10500 }
10501 }
10502
10503 if (param.using64k) {
10504 stride = 13;
10505 } else if (param.using16k) {
10506 stride = 11;
10507 } else {
10508 stride = 9;
10509 }
10510
10511 /* Note that QEMU ignores shareability and cacheability attributes,
10512 * so we don't need to do anything with the SH, ORGN, IRGN fields
10513 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
10514 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
10515 * implement any ASID-like capability so we can ignore it (instead
10516 * we will always flush the TLB any time the ASID is changed).
10517 */
10518 ttbr = regime_ttbr(env, mmu_idx, param.select);
10519
10520 /* Here we should have set up all the parameters for the translation:
10521 * inputsize, ttbr, epd, stride, tbi
10522 */
10523
10524 if (param.epd) {
10525 /* Translation table walk disabled => Translation fault on TLB miss
10526 * Note: This is always 0 on 64-bit EL2 and EL3.
10527 */
10528 goto do_fault;
10529 }
10530
10531 if (mmu_idx != ARMMMUIdx_Stage2) {
10532 /* The starting level depends on the virtual address size (which can
10533 * be up to 48 bits) and the translation granule size. It indicates
10534 * the number of strides (stride bits at a time) needed to
10535 * consume the bits of the input address. In the pseudocode this is:
10536 * level = 4 - RoundUp((inputsize - grainsize) / stride)
10537 * where their 'inputsize' is our 'inputsize', 'grainsize' is
10538 * our 'stride + 3' and 'stride' is our 'stride'.
10539 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
10540 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
10541 * = 4 - (inputsize - 4) / stride;
10542 */
10543 level = 4 - (inputsize - 4) / stride;
10544 } else {
10545 /* For stage 2 translations the starting level is specified by the
10546 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
10547 */
10548 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
10549 uint32_t startlevel;
10550 bool ok;
10551
10552 if (!aarch64 || stride == 9) {
10553 /* AArch32 or 4KB pages */
10554 startlevel = 2 - sl0;
10555 } else {
10556 /* 16KB or 64KB pages */
10557 startlevel = 3 - sl0;
10558 }
10559
10560 /* Check that the starting level is valid. */
10561 ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
10562 inputsize, stride);
10563 if (!ok) {
10564 fault_type = ARMFault_Translation;
10565 goto do_fault;
10566 }
10567 level = startlevel;
10568 }
10569
10570 indexmask_grainsize = (1ULL << (stride + 3)) - 1;
10571 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
10572
10573 /* Now we can extract the actual base address from the TTBR */
10574 descaddr = extract64(ttbr, 0, 48);
10575 descaddr &= ~indexmask;
10576
10577 /* The address field in the descriptor goes up to bit 39 for ARMv7
10578 * but up to bit 47 for ARMv8, but we use the descaddrmask
10579 * up to bit 39 for AArch32, because we don't need other bits in that case
10580 * to construct next descriptor address (anyway they should be all zeroes).
10581 */
10582 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
10583 ~indexmask_grainsize;
10584
10585 /* Secure accesses start with the page table in secure memory and
10586 * can be downgraded to non-secure at any step. Non-secure accesses
10587 * remain non-secure. We implement this by just ORing in the NSTable/NS
10588 * bits at each step.
10589 */
10590 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
10591 for (;;) {
10592 uint64_t descriptor;
10593 bool nstable;
10594
10595 descaddr |= (address >> (stride * (4 - level))) & indexmask;
10596 descaddr &= ~7ULL;
10597 nstable = extract32(tableattrs, 4, 1);
10598 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
10599 if (fi->type != ARMFault_None) {
10600 goto do_fault;
10601 }
10602
10603 if (!(descriptor & 1) ||
10604 (!(descriptor & 2) && (level == 3))) {
10605 /* Invalid, or the Reserved level 3 encoding */
10606 goto do_fault;
10607 }
10608 descaddr = descriptor & descaddrmask;
10609
10610 if ((descriptor & 2) && (level < 3)) {
10611 /* Table entry. The top five bits are attributes which may
10612 * propagate down through lower levels of the table (and
10613 * which are all arranged so that 0 means "no effect", so
10614 * we can gather them up by ORing in the bits at each level).
10615 */
10616 tableattrs |= extract64(descriptor, 59, 5);
10617 level++;
10618 indexmask = indexmask_grainsize;
10619 continue;
10620 }
10621 /* Block entry at level 1 or 2, or page entry at level 3.
10622 * These are basically the same thing, although the number
10623 * of bits we pull in from the vaddr varies.
10624 */
10625 page_size = (1ULL << ((stride * (4 - level)) + 3));
10626 descaddr |= (address & (page_size - 1));
10627 /* Extract attributes from the descriptor */
10628 attrs = extract64(descriptor, 2, 10)
10629 | (extract64(descriptor, 52, 12) << 10);
10630
10631 if (mmu_idx == ARMMMUIdx_Stage2) {
10632 /* Stage 2 table descriptors do not include any attribute fields */
10633 break;
10634 }
10635 /* Merge in attributes from table descriptors */
10636 attrs |= nstable << 3; /* NS */
10637 guarded = extract64(descriptor, 50, 1); /* GP */
10638 if (param.hpd) {
10639 /* HPD disables all the table attributes except NSTable. */
10640 break;
10641 }
10642 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
10643 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
10644 * means "force PL1 access only", which means forcing AP[1] to 0.
10645 */
10646 attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
10647 attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
10648 break;
10649 }
10650 /* Here descaddr is the final physical address, and attributes
10651 * are all in attrs.
10652 */
10653 fault_type = ARMFault_AccessFlag;
10654 if ((attrs & (1 << 8)) == 0) {
10655 /* Access flag */
10656 goto do_fault;
10657 }
10658
10659 ap = extract32(attrs, 4, 2);
10660 xn = extract32(attrs, 12, 1);
10661
10662 if (mmu_idx == ARMMMUIdx_Stage2) {
10663 ns = true;
10664 *prot = get_S2prot(env, ap, xn);
10665 } else {
10666 ns = extract32(attrs, 3, 1);
10667 pxn = extract32(attrs, 11, 1);
10668 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
10669 }
10670
10671 fault_type = ARMFault_Permission;
10672 if (!(*prot & (1 << access_type))) {
10673 goto do_fault;
10674 }
10675
10676 if (ns) {
10677 /* The NS bit will (as required by the architecture) have no effect if
10678 * the CPU doesn't support TZ or this is a non-secure translation
10679 * regime, because the attribute will already be non-secure.
10680 */
10681 txattrs->secure = false;
10682 }
10683 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
10684 if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
10685 txattrs->target_tlb_bit0 = true;
10686 }
10687
10688 if (cacheattrs != NULL) {
10689 if (mmu_idx == ARMMMUIdx_Stage2) {
10690 cacheattrs->attrs = convert_stage2_attrs(env,
10691 extract32(attrs, 0, 4));
10692 } else {
10693 /* Index into MAIR registers for cache attributes */
10694 uint8_t attrindx = extract32(attrs, 0, 3);
10695 uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
10696 assert(attrindx <= 7);
10697 cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
10698 }
10699 cacheattrs->shareability = extract32(attrs, 6, 2);
10700 }
10701
10702 *phys_ptr = descaddr;
10703 *page_size_ptr = page_size;
10704 return false;
10705
10706 do_fault:
10707 fi->type = fault_type;
10708 fi->level = level;
10709 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
10710 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2);
10711 return true;
10712 }
10713
10714 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
10715 ARMMMUIdx mmu_idx,
10716 int32_t address, int *prot)
10717 {
10718 if (!arm_feature(env, ARM_FEATURE_M)) {
10719 *prot = PAGE_READ | PAGE_WRITE;
10720 switch (address) {
10721 case 0xF0000000 ... 0xFFFFFFFF:
10722 if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
10723 /* hivecs execing is ok */
10724 *prot |= PAGE_EXEC;
10725 }
10726 break;
10727 case 0x00000000 ... 0x7FFFFFFF:
10728 *prot |= PAGE_EXEC;
10729 break;
10730 }
10731 } else {
10732 /* Default system address map for M profile cores.
10733 * The architecture specifies which regions are execute-never;
10734 * at the MPU level no other checks are defined.
10735 */
10736 switch (address) {
10737 case 0x00000000 ... 0x1fffffff: /* ROM */
10738 case 0x20000000 ... 0x3fffffff: /* SRAM */
10739 case 0x60000000 ... 0x7fffffff: /* RAM */
10740 case 0x80000000 ... 0x9fffffff: /* RAM */
10741 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10742 break;
10743 case 0x40000000 ... 0x5fffffff: /* Peripheral */
10744 case 0xa0000000 ... 0xbfffffff: /* Device */
10745 case 0xc0000000 ... 0xdfffffff: /* Device */
10746 case 0xe0000000 ... 0xffffffff: /* System */
10747 *prot = PAGE_READ | PAGE_WRITE;
10748 break;
10749 default:
10750 g_assert_not_reached();
10751 }
10752 }
10753 }
10754
10755 static bool pmsav7_use_background_region(ARMCPU *cpu,
10756 ARMMMUIdx mmu_idx, bool is_user)
10757 {
10758 /* Return true if we should use the default memory map as a
10759 * "background" region if there are no hits against any MPU regions.
10760 */
10761 CPUARMState *env = &cpu->env;
10762
10763 if (is_user) {
10764 return false;
10765 }
10766
10767 if (arm_feature(env, ARM_FEATURE_M)) {
10768 return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
10769 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
10770 } else {
10771 return regime_sctlr(env, mmu_idx) & SCTLR_BR;
10772 }
10773 }
10774
10775 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
10776 {
10777 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
10778 return arm_feature(env, ARM_FEATURE_M) &&
10779 extract32(address, 20, 12) == 0xe00;
10780 }
10781
10782 static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
10783 {
10784 /* True if address is in the M profile system region
10785 * 0xe0000000 - 0xffffffff
10786 */
10787 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
10788 }
10789
10790 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
10791 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10792 hwaddr *phys_ptr, int *prot,
10793 target_ulong *page_size,
10794 ARMMMUFaultInfo *fi)
10795 {
10796 ARMCPU *cpu = env_archcpu(env);
10797 int n;
10798 bool is_user = regime_is_user(env, mmu_idx);
10799
10800 *phys_ptr = address;
10801 *page_size = TARGET_PAGE_SIZE;
10802 *prot = 0;
10803
10804 if (regime_translation_disabled(env, mmu_idx) ||
10805 m_is_ppb_region(env, address)) {
10806 /* MPU disabled or M profile PPB access: use default memory map.
10807 * The other case which uses the default memory map in the
10808 * v7M ARM ARM pseudocode is exception vector reads from the vector
10809 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
10810 * which always does a direct read using address_space_ldl(), rather
10811 * than going via this function, so we don't need to check that here.
10812 */
10813 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
10814 } else { /* MPU enabled */
10815 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
10816 /* region search */
10817 uint32_t base = env->pmsav7.drbar[n];
10818 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
10819 uint32_t rmask;
10820 bool srdis = false;
10821
10822 if (!(env->pmsav7.drsr[n] & 0x1)) {
10823 continue;
10824 }
10825
10826 if (!rsize) {
10827 qemu_log_mask(LOG_GUEST_ERROR,
10828 "DRSR[%d]: Rsize field cannot be 0\n", n);
10829 continue;
10830 }
10831 rsize++;
10832 rmask = (1ull << rsize) - 1;
10833
10834 if (base & rmask) {
10835 qemu_log_mask(LOG_GUEST_ERROR,
10836 "DRBAR[%d]: 0x%" PRIx32 " misaligned "
10837 "to DRSR region size, mask = 0x%" PRIx32 "\n",
10838 n, base, rmask);
10839 continue;
10840 }
10841
10842 if (address < base || address > base + rmask) {
10843 /*
10844 * Address not in this region. We must check whether the
10845 * region covers addresses in the same page as our address.
10846 * In that case we must not report a size that covers the
10847 * whole page for a subsequent hit against a different MPU
10848 * region or the background region, because it would result in
10849 * incorrect TLB hits for subsequent accesses to addresses that
10850 * are in this MPU region.
10851 */
10852 if (ranges_overlap(base, rmask,
10853 address & TARGET_PAGE_MASK,
10854 TARGET_PAGE_SIZE)) {
10855 *page_size = 1;
10856 }
10857 continue;
10858 }
10859
10860 /* Region matched */
10861
10862 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
10863 int i, snd;
10864 uint32_t srdis_mask;
10865
10866 rsize -= 3; /* sub region size (power of 2) */
10867 snd = ((address - base) >> rsize) & 0x7;
10868 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
10869
10870 srdis_mask = srdis ? 0x3 : 0x0;
10871 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
10872 /* This will check in groups of 2, 4 and then 8, whether
10873 * the subregion bits are consistent. rsize is incremented
10874 * back up to give the region size, considering consistent
10875 * adjacent subregions as one region. Stop testing if rsize
10876 * is already big enough for an entire QEMU page.
10877 */
10878 int snd_rounded = snd & ~(i - 1);
10879 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
10880 snd_rounded + 8, i);
10881 if (srdis_mask ^ srdis_multi) {
10882 break;
10883 }
10884 srdis_mask = (srdis_mask << i) | srdis_mask;
10885 rsize++;
10886 }
10887 }
10888 if (srdis) {
10889 continue;
10890 }
10891 if (rsize < TARGET_PAGE_BITS) {
10892 *page_size = 1 << rsize;
10893 }
10894 break;
10895 }
10896
10897 if (n == -1) { /* no hits */
10898 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
10899 /* background fault */
10900 fi->type = ARMFault_Background;
10901 return true;
10902 }
10903 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
10904 } else { /* a MPU hit! */
10905 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
10906 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
10907
10908 if (m_is_system_region(env, address)) {
10909 /* System space is always execute never */
10910 xn = 1;
10911 }
10912
10913 if (is_user) { /* User mode AP bit decoding */
10914 switch (ap) {
10915 case 0:
10916 case 1:
10917 case 5:
10918 break; /* no access */
10919 case 3:
10920 *prot |= PAGE_WRITE;
10921 /* fall through */
10922 case 2:
10923 case 6:
10924 *prot |= PAGE_READ | PAGE_EXEC;
10925 break;
10926 case 7:
10927 /* for v7M, same as 6; for R profile a reserved value */
10928 if (arm_feature(env, ARM_FEATURE_M)) {
10929 *prot |= PAGE_READ | PAGE_EXEC;
10930 break;
10931 }
10932 /* fall through */
10933 default:
10934 qemu_log_mask(LOG_GUEST_ERROR,
10935 "DRACR[%d]: Bad value for AP bits: 0x%"
10936 PRIx32 "\n", n, ap);
10937 }
10938 } else { /* Priv. mode AP bits decoding */
10939 switch (ap) {
10940 case 0:
10941 break; /* no access */
10942 case 1:
10943 case 2:
10944 case 3:
10945 *prot |= PAGE_WRITE;
10946 /* fall through */
10947 case 5:
10948 case 6:
10949 *prot |= PAGE_READ | PAGE_EXEC;
10950 break;
10951 case 7:
10952 /* for v7M, same as 6; for R profile a reserved value */
10953 if (arm_feature(env, ARM_FEATURE_M)) {
10954 *prot |= PAGE_READ | PAGE_EXEC;
10955 break;
10956 }
10957 /* fall through */
10958 default:
10959 qemu_log_mask(LOG_GUEST_ERROR,
10960 "DRACR[%d]: Bad value for AP bits: 0x%"
10961 PRIx32 "\n", n, ap);
10962 }
10963 }
10964
10965 /* execute never */
10966 if (xn) {
10967 *prot &= ~PAGE_EXEC;
10968 }
10969 }
10970 }
10971
10972 fi->type = ARMFault_Permission;
10973 fi->level = 1;
10974 return !(*prot & (1 << access_type));
10975 }
10976
10977 static bool v8m_is_sau_exempt(CPUARMState *env,
10978 uint32_t address, MMUAccessType access_type)
10979 {
10980 /* The architecture specifies that certain address ranges are
10981 * exempt from v8M SAU/IDAU checks.
10982 */
10983 return
10984 (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
10985 (address >= 0xe0000000 && address <= 0xe0002fff) ||
10986 (address >= 0xe000e000 && address <= 0xe000efff) ||
10987 (address >= 0xe002e000 && address <= 0xe002efff) ||
10988 (address >= 0xe0040000 && address <= 0xe0041fff) ||
10989 (address >= 0xe00ff000 && address <= 0xe00fffff);
10990 }
10991
10992 void v8m_security_lookup(CPUARMState *env, uint32_t address,
10993 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10994 V8M_SAttributes *sattrs)
10995 {
10996 /* Look up the security attributes for this address. Compare the
10997 * pseudocode SecurityCheck() function.
10998 * We assume the caller has zero-initialized *sattrs.
10999 */
11000 ARMCPU *cpu = env_archcpu(env);
11001 int r;
11002 bool idau_exempt = false, idau_ns = true, idau_nsc = true;
11003 int idau_region = IREGION_NOTVALID;
11004 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11005 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
11006
11007 if (cpu->idau) {
11008 IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
11009 IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
11010
11011 iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
11012 &idau_nsc);
11013 }
11014
11015 if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
11016 /* 0xf0000000..0xffffffff is always S for insn fetches */
11017 return;
11018 }
11019
11020 if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
11021 sattrs->ns = !regime_is_secure(env, mmu_idx);
11022 return;
11023 }
11024
11025 if (idau_region != IREGION_NOTVALID) {
11026 sattrs->irvalid = true;
11027 sattrs->iregion = idau_region;
11028 }
11029
11030 switch (env->sau.ctrl & 3) {
11031 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11032 break;
11033 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11034 sattrs->ns = true;
11035 break;
11036 default: /* SAU.ENABLE == 1 */
11037 for (r = 0; r < cpu->sau_sregion; r++) {
11038 if (env->sau.rlar[r] & 1) {
11039 uint32_t base = env->sau.rbar[r] & ~0x1f;
11040 uint32_t limit = env->sau.rlar[r] | 0x1f;
11041
11042 if (base <= address && limit >= address) {
11043 if (base > addr_page_base || limit < addr_page_limit) {
11044 sattrs->subpage = true;
11045 }
11046 if (sattrs->srvalid) {
11047 /* If we hit in more than one region then we must report
11048 * as Secure, not NS-Callable, with no valid region
11049 * number info.
11050 */
11051 sattrs->ns = false;
11052 sattrs->nsc = false;
11053 sattrs->sregion = 0;
11054 sattrs->srvalid = false;
11055 break;
11056 } else {
11057 if (env->sau.rlar[r] & 2) {
11058 sattrs->nsc = true;
11059 } else {
11060 sattrs->ns = true;
11061 }
11062 sattrs->srvalid = true;
11063 sattrs->sregion = r;
11064 }
11065 } else {
11066 /*
11067 * Address not in this region. We must check whether the
11068 * region covers addresses in the same page as our address.
11069 * In that case we must not report a size that covers the
11070 * whole page for a subsequent hit against a different MPU
11071 * region or the background region, because it would result
11072 * in incorrect TLB hits for subsequent accesses to
11073 * addresses that are in this MPU region.
11074 */
11075 if (limit >= base &&
11076 ranges_overlap(base, limit - base + 1,
11077 addr_page_base,
11078 TARGET_PAGE_SIZE)) {
11079 sattrs->subpage = true;
11080 }
11081 }
11082 }
11083 }
11084 break;
11085 }
11086
11087 /*
11088 * The IDAU will override the SAU lookup results if it specifies
11089 * higher security than the SAU does.
11090 */
11091 if (!idau_ns) {
11092 if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
11093 sattrs->ns = false;
11094 sattrs->nsc = idau_nsc;
11095 }
11096 }
11097 }
11098
11099 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
11100 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11101 hwaddr *phys_ptr, MemTxAttrs *txattrs,
11102 int *prot, bool *is_subpage,
11103 ARMMMUFaultInfo *fi, uint32_t *mregion)
11104 {
11105 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11106 * that a full phys-to-virt translation does).
11107 * mregion is (if not NULL) set to the region number which matched,
11108 * or -1 if no region number is returned (MPU off, address did not
11109 * hit a region, address hit in multiple regions).
11110 * We set is_subpage to true if the region hit doesn't cover the
11111 * entire TARGET_PAGE the address is within.
11112 */
11113 ARMCPU *cpu = env_archcpu(env);
11114 bool is_user = regime_is_user(env, mmu_idx);
11115 uint32_t secure = regime_is_secure(env, mmu_idx);
11116 int n;
11117 int matchregion = -1;
11118 bool hit = false;
11119 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11120 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
11121
11122 *is_subpage = false;
11123 *phys_ptr = address;
11124 *prot = 0;
11125 if (mregion) {
11126 *mregion = -1;
11127 }
11128
11129 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11130 * was an exception vector read from the vector table (which is always
11131 * done using the default system address map), because those accesses
11132 * are done in arm_v7m_load_vector(), which always does a direct
11133 * read using address_space_ldl(), rather than going via this function.
11134 */
11135 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
11136 hit = true;
11137 } else if (m_is_ppb_region(env, address)) {
11138 hit = true;
11139 } else {
11140 if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
11141 hit = true;
11142 }
11143
11144 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11145 /* region search */
11146 /* Note that the base address is bits [31:5] from the register
11147 * with bits [4:0] all zeroes, but the limit address is bits
11148 * [31:5] from the register with bits [4:0] all ones.
11149 */
11150 uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
11151 uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
11152
11153 if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
11154 /* Region disabled */
11155 continue;
11156 }
11157
11158 if (address < base || address > limit) {
11159 /*
11160 * Address not in this region. We must check whether the
11161 * region covers addresses in the same page as our address.
11162 * In that case we must not report a size that covers the
11163 * whole page for a subsequent hit against a different MPU
11164 * region or the background region, because it would result in
11165 * incorrect TLB hits for subsequent accesses to addresses that
11166 * are in this MPU region.
11167 */
11168 if (limit >= base &&
11169 ranges_overlap(base, limit - base + 1,
11170 addr_page_base,
11171 TARGET_PAGE_SIZE)) {
11172 *is_subpage = true;
11173 }
11174 continue;
11175 }
11176
11177 if (base > addr_page_base || limit < addr_page_limit) {
11178 *is_subpage = true;
11179 }
11180
11181 if (matchregion != -1) {
11182 /* Multiple regions match -- always a failure (unlike
11183 * PMSAv7 where highest-numbered-region wins)
11184 */
11185 fi->type = ARMFault_Permission;
11186 fi->level = 1;
11187 return true;
11188 }
11189
11190 matchregion = n;
11191 hit = true;
11192 }
11193 }
11194
11195 if (!hit) {
11196 /* background fault */
11197 fi->type = ARMFault_Background;
11198 return true;
11199 }
11200
11201 if (matchregion == -1) {
11202 /* hit using the background region */
11203 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11204 } else {
11205 uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
11206 uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
11207
11208 if (m_is_system_region(env, address)) {
11209 /* System space is always execute never */
11210 xn = 1;
11211 }
11212
11213 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
11214 if (*prot && !xn) {
11215 *prot |= PAGE_EXEC;
11216 }
11217 /* We don't need to look the attribute up in the MAIR0/MAIR1
11218 * registers because that only tells us about cacheability.
11219 */
11220 if (mregion) {
11221 *mregion = matchregion;
11222 }
11223 }
11224
11225 fi->type = ARMFault_Permission;
11226 fi->level = 1;
11227 return !(*prot & (1 << access_type));
11228 }
11229
11230
11231 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
11232 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11233 hwaddr *phys_ptr, MemTxAttrs *txattrs,
11234 int *prot, target_ulong *page_size,
11235 ARMMMUFaultInfo *fi)
11236 {
11237 uint32_t secure = regime_is_secure(env, mmu_idx);
11238 V8M_SAttributes sattrs = {};
11239 bool ret;
11240 bool mpu_is_subpage;
11241
11242 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
11243 v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
11244 if (access_type == MMU_INST_FETCH) {
11245 /* Instruction fetches always use the MMU bank and the
11246 * transaction attribute determined by the fetch address,
11247 * regardless of CPU state. This is painful for QEMU
11248 * to handle, because it would mean we need to encode
11249 * into the mmu_idx not just the (user, negpri) information
11250 * for the current security state but also that for the
11251 * other security state, which would balloon the number
11252 * of mmu_idx values needed alarmingly.
11253 * Fortunately we can avoid this because it's not actually
11254 * possible to arbitrarily execute code from memory with
11255 * the wrong security attribute: it will always generate
11256 * an exception of some kind or another, apart from the
11257 * special case of an NS CPU executing an SG instruction
11258 * in S&NSC memory. So we always just fail the translation
11259 * here and sort things out in the exception handler
11260 * (including possibly emulating an SG instruction).
11261 */
11262 if (sattrs.ns != !secure) {
11263 if (sattrs.nsc) {
11264 fi->type = ARMFault_QEMU_NSCExec;
11265 } else {
11266 fi->type = ARMFault_QEMU_SFault;
11267 }
11268 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
11269 *phys_ptr = address;
11270 *prot = 0;
11271 return true;
11272 }
11273 } else {
11274 /* For data accesses we always use the MMU bank indicated
11275 * by the current CPU state, but the security attributes
11276 * might downgrade a secure access to nonsecure.
11277 */
11278 if (sattrs.ns) {
11279 txattrs->secure = false;
11280 } else if (!secure) {
11281 /* NS access to S memory must fault.
11282 * Architecturally we should first check whether the
11283 * MPU information for this address indicates that we
11284 * are doing an unaligned access to Device memory, which
11285 * should generate a UsageFault instead. QEMU does not
11286 * currently check for that kind of unaligned access though.
11287 * If we added it we would need to do so as a special case
11288 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11289 */
11290 fi->type = ARMFault_QEMU_SFault;
11291 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
11292 *phys_ptr = address;
11293 *prot = 0;
11294 return true;
11295 }
11296 }
11297 }
11298
11299 ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
11300 txattrs, prot, &mpu_is_subpage, fi, NULL);
11301 *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
11302 return ret;
11303 }
11304
11305 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
11306 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11307 hwaddr *phys_ptr, int *prot,
11308 ARMMMUFaultInfo *fi)
11309 {
11310 int n;
11311 uint32_t mask;
11312 uint32_t base;
11313 bool is_user = regime_is_user(env, mmu_idx);
11314
11315 if (regime_translation_disabled(env, mmu_idx)) {
11316 /* MPU disabled. */
11317 *phys_ptr = address;
11318 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11319 return false;
11320 }
11321
11322 *phys_ptr = address;
11323 for (n = 7; n >= 0; n--) {
11324 base = env->cp15.c6_region[n];
11325 if ((base & 1) == 0) {
11326 continue;
11327 }
11328 mask = 1 << ((base >> 1) & 0x1f);
11329 /* Keep this shift separate from the above to avoid an
11330 (undefined) << 32. */
11331 mask = (mask << 1) - 1;
11332 if (((base ^ address) & ~mask) == 0) {
11333 break;
11334 }
11335 }
11336 if (n < 0) {
11337 fi->type = ARMFault_Background;
11338 return true;
11339 }
11340
11341 if (access_type == MMU_INST_FETCH) {
11342 mask = env->cp15.pmsav5_insn_ap;
11343 } else {
11344 mask = env->cp15.pmsav5_data_ap;
11345 }
11346 mask = (mask >> (n * 4)) & 0xf;
11347 switch (mask) {
11348 case 0:
11349 fi->type = ARMFault_Permission;
11350 fi->level = 1;
11351 return true;
11352 case 1:
11353 if (is_user) {
11354 fi->type = ARMFault_Permission;
11355 fi->level = 1;
11356 return true;
11357 }
11358 *prot = PAGE_READ | PAGE_WRITE;
11359 break;
11360 case 2:
11361 *prot = PAGE_READ;
11362 if (!is_user) {
11363 *prot |= PAGE_WRITE;
11364 }
11365 break;
11366 case 3:
11367 *prot = PAGE_READ | PAGE_WRITE;
11368 break;
11369 case 5:
11370 if (is_user) {
11371 fi->type = ARMFault_Permission;
11372 fi->level = 1;
11373 return true;
11374 }
11375 *prot = PAGE_READ;
11376 break;
11377 case 6:
11378 *prot = PAGE_READ;
11379 break;
11380 default:
11381 /* Bad permission. */
11382 fi->type = ARMFault_Permission;
11383 fi->level = 1;
11384 return true;
11385 }
11386 *prot |= PAGE_EXEC;
11387 return false;
11388 }
11389
11390 /* Combine either inner or outer cacheability attributes for normal
11391 * memory, according to table D4-42 and pseudocode procedure
11392 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11393 *
11394 * NB: only stage 1 includes allocation hints (RW bits), leading to
11395 * some asymmetry.
11396 */
11397 static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
11398 {
11399 if (s1 == 4 || s2 == 4) {
11400 /* non-cacheable has precedence */
11401 return 4;
11402 } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
11403 /* stage 1 write-through takes precedence */
11404 return s1;
11405 } else if (extract32(s2, 2, 2) == 2) {
11406 /* stage 2 write-through takes precedence, but the allocation hint
11407 * is still taken from stage 1
11408 */
11409 return (2 << 2) | extract32(s1, 0, 2);
11410 } else { /* write-back */
11411 return s1;
11412 }
11413 }
11414
11415 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11416 * and CombineS1S2Desc()
11417 *
11418 * @s1: Attributes from stage 1 walk
11419 * @s2: Attributes from stage 2 walk
11420 */
11421 static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
11422 {
11423 uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4);
11424 uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4);
11425 ARMCacheAttrs ret;
11426
11427 /* Combine shareability attributes (table D4-43) */
11428 if (s1.shareability == 2 || s2.shareability == 2) {
11429 /* if either are outer-shareable, the result is outer-shareable */
11430 ret.shareability = 2;
11431 } else if (s1.shareability == 3 || s2.shareability == 3) {
11432 /* if either are inner-shareable, the result is inner-shareable */
11433 ret.shareability = 3;
11434 } else {
11435 /* both non-shareable */
11436 ret.shareability = 0;
11437 }
11438
11439 /* Combine memory type and cacheability attributes */
11440 if (s1hi == 0 || s2hi == 0) {
11441 /* Device has precedence over normal */
11442 if (s1lo == 0 || s2lo == 0) {
11443 /* nGnRnE has precedence over anything */
11444 ret.attrs = 0;
11445 } else if (s1lo == 4 || s2lo == 4) {
11446 /* non-Reordering has precedence over Reordering */
11447 ret.attrs = 4; /* nGnRE */
11448 } else if (s1lo == 8 || s2lo == 8) {
11449 /* non-Gathering has precedence over Gathering */
11450 ret.attrs = 8; /* nGRE */
11451 } else {
11452 ret.attrs = 0xc; /* GRE */
11453 }
11454
11455 /* Any location for which the resultant memory type is any
11456 * type of Device memory is always treated as Outer Shareable.
11457 */
11458 ret.shareability = 2;
11459 } else { /* Normal memory */
11460 /* Outer/inner cacheability combine independently */
11461 ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
11462 | combine_cacheattr_nibble(s1lo, s2lo);
11463
11464 if (ret.attrs == 0x44) {
11465 /* Any location for which the resultant memory type is Normal
11466 * Inner Non-cacheable, Outer Non-cacheable is always treated
11467 * as Outer Shareable.
11468 */
11469 ret.shareability = 2;
11470 }
11471 }
11472
11473 return ret;
11474 }
11475
11476
11477 /* get_phys_addr - get the physical address for this virtual address
11478 *
11479 * Find the physical address corresponding to the given virtual address,
11480 * by doing a translation table walk on MMU based systems or using the
11481 * MPU state on MPU based systems.
11482 *
11483 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11484 * prot and page_size may not be filled in, and the populated fsr value provides
11485 * information on why the translation aborted, in the format of a
11486 * DFSR/IFSR fault register, with the following caveats:
11487 * * we honour the short vs long DFSR format differences.
11488 * * the WnR bit is never set (the caller must do this).
11489 * * for PSMAv5 based systems we don't bother to return a full FSR format
11490 * value.
11491 *
11492 * @env: CPUARMState
11493 * @address: virtual address to get physical address for
11494 * @access_type: 0 for read, 1 for write, 2 for execute
11495 * @mmu_idx: MMU index indicating required translation regime
11496 * @phys_ptr: set to the physical address corresponding to the virtual address
11497 * @attrs: set to the memory transaction attributes to use
11498 * @prot: set to the permissions for the page containing phys_ptr
11499 * @page_size: set to the size of the page containing phys_ptr
11500 * @fi: set to fault info if the translation fails
11501 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11502 */
11503 bool get_phys_addr(CPUARMState *env, target_ulong address,
11504 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11505 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
11506 target_ulong *page_size,
11507 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
11508 {
11509 if (mmu_idx == ARMMMUIdx_E10_0 ||
11510 mmu_idx == ARMMMUIdx_E10_1 ||
11511 mmu_idx == ARMMMUIdx_E10_1_PAN) {
11512 /* Call ourselves recursively to do the stage 1 and then stage 2
11513 * translations.
11514 */
11515 if (arm_feature(env, ARM_FEATURE_EL2)) {
11516 hwaddr ipa;
11517 int s2_prot;
11518 int ret;
11519 ARMCacheAttrs cacheattrs2 = {};
11520
11521 ret = get_phys_addr(env, address, access_type,
11522 stage_1_mmu_idx(mmu_idx), &ipa, attrs,
11523 prot, page_size, fi, cacheattrs);
11524
11525 /* If S1 fails or S2 is disabled, return early. */
11526 if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
11527 *phys_ptr = ipa;
11528 return ret;
11529 }
11530
11531 /* S1 is done. Now do S2 translation. */
11532 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
11533 phys_ptr, attrs, &s2_prot,
11534 page_size, fi,
11535 cacheattrs != NULL ? &cacheattrs2 : NULL);
11536 fi->s2addr = ipa;
11537 /* Combine the S1 and S2 perms. */
11538 *prot &= s2_prot;
11539
11540 /* Combine the S1 and S2 cache attributes, if needed */
11541 if (!ret && cacheattrs != NULL) {
11542 if (env->cp15.hcr_el2 & HCR_DC) {
11543 /*
11544 * HCR.DC forces the first stage attributes to
11545 * Normal Non-Shareable,
11546 * Inner Write-Back Read-Allocate Write-Allocate,
11547 * Outer Write-Back Read-Allocate Write-Allocate.
11548 */
11549 cacheattrs->attrs = 0xff;
11550 cacheattrs->shareability = 0;
11551 }
11552 *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
11553 }
11554
11555 return ret;
11556 } else {
11557 /*
11558 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
11559 */
11560 mmu_idx = stage_1_mmu_idx(mmu_idx);
11561 }
11562 }
11563
11564 /* The page table entries may downgrade secure to non-secure, but
11565 * cannot upgrade an non-secure translation regime's attributes
11566 * to secure.
11567 */
11568 attrs->secure = regime_is_secure(env, mmu_idx);
11569 attrs->user = regime_is_user(env, mmu_idx);
11570
11571 /* Fast Context Switch Extension. This doesn't exist at all in v8.
11572 * In v7 and earlier it affects all stage 1 translations.
11573 */
11574 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2
11575 && !arm_feature(env, ARM_FEATURE_V8)) {
11576 if (regime_el(env, mmu_idx) == 3) {
11577 address += env->cp15.fcseidr_s;
11578 } else {
11579 address += env->cp15.fcseidr_ns;
11580 }
11581 }
11582
11583 if (arm_feature(env, ARM_FEATURE_PMSA)) {
11584 bool ret;
11585 *page_size = TARGET_PAGE_SIZE;
11586
11587 if (arm_feature(env, ARM_FEATURE_V8)) {
11588 /* PMSAv8 */
11589 ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
11590 phys_ptr, attrs, prot, page_size, fi);
11591 } else if (arm_feature(env, ARM_FEATURE_V7)) {
11592 /* PMSAv7 */
11593 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
11594 phys_ptr, prot, page_size, fi);
11595 } else {
11596 /* Pre-v7 MPU */
11597 ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
11598 phys_ptr, prot, fi);
11599 }
11600 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
11601 " mmu_idx %u -> %s (prot %c%c%c)\n",
11602 access_type == MMU_DATA_LOAD ? "reading" :
11603 (access_type == MMU_DATA_STORE ? "writing" : "execute"),
11604 (uint32_t)address, mmu_idx,
11605 ret ? "Miss" : "Hit",
11606 *prot & PAGE_READ ? 'r' : '-',
11607 *prot & PAGE_WRITE ? 'w' : '-',
11608 *prot & PAGE_EXEC ? 'x' : '-');
11609
11610 return ret;
11611 }
11612
11613 /* Definitely a real MMU, not an MPU */
11614
11615 if (regime_translation_disabled(env, mmu_idx)) {
11616 /* MMU disabled. */
11617 *phys_ptr = address;
11618 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11619 *page_size = TARGET_PAGE_SIZE;
11620 return 0;
11621 }
11622
11623 if (regime_using_lpae_format(env, mmu_idx)) {
11624 return get_phys_addr_lpae(env, address, access_type, mmu_idx,
11625 phys_ptr, attrs, prot, page_size,
11626 fi, cacheattrs);
11627 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
11628 return get_phys_addr_v6(env, address, access_type, mmu_idx,
11629 phys_ptr, attrs, prot, page_size, fi);
11630 } else {
11631 return get_phys_addr_v5(env, address, access_type, mmu_idx,
11632 phys_ptr, prot, page_size, fi);
11633 }
11634 }
11635
11636 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
11637 MemTxAttrs *attrs)
11638 {
11639 ARMCPU *cpu = ARM_CPU(cs);
11640 CPUARMState *env = &cpu->env;
11641 hwaddr phys_addr;
11642 target_ulong page_size;
11643 int prot;
11644 bool ret;
11645 ARMMMUFaultInfo fi = {};
11646 ARMMMUIdx mmu_idx = arm_mmu_idx(env);
11647
11648 *attrs = (MemTxAttrs) {};
11649
11650 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
11651 attrs, &prot, &page_size, &fi, NULL);
11652
11653 if (ret) {
11654 return -1;
11655 }
11656 return phys_addr;
11657 }
11658
11659 #endif
11660
11661 /* Note that signed overflow is undefined in C. The following routines are
11662 careful to use unsigned types where modulo arithmetic is required.
11663 Failure to do so _will_ break on newer gcc. */
11664
11665 /* Signed saturating arithmetic. */
11666
11667 /* Perform 16-bit signed saturating addition. */
11668 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
11669 {
11670 uint16_t res;
11671
11672 res = a + b;
11673 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
11674 if (a & 0x8000)
11675 res = 0x8000;
11676 else
11677 res = 0x7fff;
11678 }
11679 return res;
11680 }
11681
11682 /* Perform 8-bit signed saturating addition. */
11683 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
11684 {
11685 uint8_t res;
11686
11687 res = a + b;
11688 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
11689 if (a & 0x80)
11690 res = 0x80;
11691 else
11692 res = 0x7f;
11693 }
11694 return res;
11695 }
11696
11697 /* Perform 16-bit signed saturating subtraction. */
11698 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
11699 {
11700 uint16_t res;
11701
11702 res = a - b;
11703 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
11704 if (a & 0x8000)
11705 res = 0x8000;
11706 else
11707 res = 0x7fff;
11708 }
11709 return res;
11710 }
11711
11712 /* Perform 8-bit signed saturating subtraction. */
11713 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
11714 {
11715 uint8_t res;
11716
11717 res = a - b;
11718 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
11719 if (a & 0x80)
11720 res = 0x80;
11721 else
11722 res = 0x7f;
11723 }
11724 return res;
11725 }
11726
11727 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11728 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11729 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11730 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11731 #define PFX q
11732
11733 #include "op_addsub.h"
11734
11735 /* Unsigned saturating arithmetic. */
11736 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
11737 {
11738 uint16_t res;
11739 res = a + b;
11740 if (res < a)
11741 res = 0xffff;
11742 return res;
11743 }
11744
11745 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
11746 {
11747 if (a > b)
11748 return a - b;
11749 else
11750 return 0;
11751 }
11752
11753 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
11754 {
11755 uint8_t res;
11756 res = a + b;
11757 if (res < a)
11758 res = 0xff;
11759 return res;
11760 }
11761
11762 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
11763 {
11764 if (a > b)
11765 return a - b;
11766 else
11767 return 0;
11768 }
11769
11770 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11771 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11772 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11773 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11774 #define PFX uq
11775
11776 #include "op_addsub.h"
11777
11778 /* Signed modulo arithmetic. */
11779 #define SARITH16(a, b, n, op) do { \
11780 int32_t sum; \
11781 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11782 RESULT(sum, n, 16); \
11783 if (sum >= 0) \
11784 ge |= 3 << (n * 2); \
11785 } while(0)
11786
11787 #define SARITH8(a, b, n, op) do { \
11788 int32_t sum; \
11789 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11790 RESULT(sum, n, 8); \
11791 if (sum >= 0) \
11792 ge |= 1 << n; \
11793 } while(0)
11794
11795
11796 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11797 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11798 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11799 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11800 #define PFX s
11801 #define ARITH_GE
11802
11803 #include "op_addsub.h"
11804
11805 /* Unsigned modulo arithmetic. */
11806 #define ADD16(a, b, n) do { \
11807 uint32_t sum; \
11808 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11809 RESULT(sum, n, 16); \
11810 if ((sum >> 16) == 1) \
11811 ge |= 3 << (n * 2); \
11812 } while(0)
11813
11814 #define ADD8(a, b, n) do { \
11815 uint32_t sum; \
11816 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11817 RESULT(sum, n, 8); \
11818 if ((sum >> 8) == 1) \
11819 ge |= 1 << n; \
11820 } while(0)
11821
11822 #define SUB16(a, b, n) do { \
11823 uint32_t sum; \
11824 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11825 RESULT(sum, n, 16); \
11826 if ((sum >> 16) == 0) \
11827 ge |= 3 << (n * 2); \
11828 } while(0)
11829
11830 #define SUB8(a, b, n) do { \
11831 uint32_t sum; \
11832 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11833 RESULT(sum, n, 8); \
11834 if ((sum >> 8) == 0) \
11835 ge |= 1 << n; \
11836 } while(0)
11837
11838 #define PFX u
11839 #define ARITH_GE
11840
11841 #include "op_addsub.h"
11842
11843 /* Halved signed arithmetic. */
11844 #define ADD16(a, b, n) \
11845 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11846 #define SUB16(a, b, n) \
11847 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11848 #define ADD8(a, b, n) \
11849 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11850 #define SUB8(a, b, n) \
11851 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11852 #define PFX sh
11853
11854 #include "op_addsub.h"
11855
11856 /* Halved unsigned arithmetic. */
11857 #define ADD16(a, b, n) \
11858 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11859 #define SUB16(a, b, n) \
11860 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11861 #define ADD8(a, b, n) \
11862 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11863 #define SUB8(a, b, n) \
11864 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11865 #define PFX uh
11866
11867 #include "op_addsub.h"
11868
11869 static inline uint8_t do_usad(uint8_t a, uint8_t b)
11870 {
11871 if (a > b)
11872 return a - b;
11873 else
11874 return b - a;
11875 }
11876
11877 /* Unsigned sum of absolute byte differences. */
11878 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
11879 {
11880 uint32_t sum;
11881 sum = do_usad(a, b);
11882 sum += do_usad(a >> 8, b >> 8);
11883 sum += do_usad(a >> 16, b >>16);
11884 sum += do_usad(a >> 24, b >> 24);
11885 return sum;
11886 }
11887
11888 /* For ARMv6 SEL instruction. */
11889 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
11890 {
11891 uint32_t mask;
11892
11893 mask = 0;
11894 if (flags & 1)
11895 mask |= 0xff;
11896 if (flags & 2)
11897 mask |= 0xff00;
11898 if (flags & 4)
11899 mask |= 0xff0000;
11900 if (flags & 8)
11901 mask |= 0xff000000;
11902 return (a & mask) | (b & ~mask);
11903 }
11904
11905 /* CRC helpers.
11906 * The upper bytes of val (above the number specified by 'bytes') must have
11907 * been zeroed out by the caller.
11908 */
11909 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
11910 {
11911 uint8_t buf[4];
11912
11913 stl_le_p(buf, val);
11914
11915 /* zlib crc32 converts the accumulator and output to one's complement. */
11916 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
11917 }
11918
11919 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
11920 {
11921 uint8_t buf[4];
11922
11923 stl_le_p(buf, val);
11924
11925 /* Linux crc32c converts the output to one's complement. */
11926 return crc32c(acc, buf, bytes) ^ 0xffffffff;
11927 }
11928
11929 /* Return the exception level to which FP-disabled exceptions should
11930 * be taken, or 0 if FP is enabled.
11931 */
11932 int fp_exception_el(CPUARMState *env, int cur_el)
11933 {
11934 #ifndef CONFIG_USER_ONLY
11935 /* CPACR and the CPTR registers don't exist before v6, so FP is
11936 * always accessible
11937 */
11938 if (!arm_feature(env, ARM_FEATURE_V6)) {
11939 return 0;
11940 }
11941
11942 if (arm_feature(env, ARM_FEATURE_M)) {
11943 /* CPACR can cause a NOCP UsageFault taken to current security state */
11944 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) {
11945 return 1;
11946 }
11947
11948 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) {
11949 if (!extract32(env->v7m.nsacr, 10, 1)) {
11950 /* FP insns cause a NOCP UsageFault taken to Secure */
11951 return 3;
11952 }
11953 }
11954
11955 return 0;
11956 }
11957
11958 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11959 * 0, 2 : trap EL0 and EL1/PL1 accesses
11960 * 1 : trap only EL0 accesses
11961 * 3 : trap no accesses
11962 * This register is ignored if E2H+TGE are both set.
11963 */
11964 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
11965 int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
11966
11967 switch (fpen) {
11968 case 0:
11969 case 2:
11970 if (cur_el == 0 || cur_el == 1) {
11971 /* Trap to PL1, which might be EL1 or EL3 */
11972 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
11973 return 3;
11974 }
11975 return 1;
11976 }
11977 if (cur_el == 3 && !is_a64(env)) {
11978 /* Secure PL1 running at EL3 */
11979 return 3;
11980 }
11981 break;
11982 case 1:
11983 if (cur_el == 0) {
11984 return 1;
11985 }
11986 break;
11987 case 3:
11988 break;
11989 }
11990 }
11991
11992 /*
11993 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11994 * to control non-secure access to the FPU. It doesn't have any
11995 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11996 */
11997 if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
11998 cur_el <= 2 && !arm_is_secure_below_el3(env))) {
11999 if (!extract32(env->cp15.nsacr, 10, 1)) {
12000 /* FP insns act as UNDEF */
12001 return cur_el == 2 ? 2 : 1;
12002 }
12003 }
12004
12005 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12006 * check because zero bits in the registers mean "don't trap".
12007 */
12008
12009 /* CPTR_EL2 : present in v7VE or v8 */
12010 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
12011 && !arm_is_secure_below_el3(env)) {
12012 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12013 return 2;
12014 }
12015
12016 /* CPTR_EL3 : present in v8 */
12017 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
12018 /* Trap all FP ops to EL3 */
12019 return 3;
12020 }
12021 #endif
12022 return 0;
12023 }
12024
12025 /* Return the exception level we're running at if this is our mmu_idx */
12026 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
12027 {
12028 if (mmu_idx & ARM_MMU_IDX_M) {
12029 return mmu_idx & ARM_MMU_IDX_M_PRIV;
12030 }
12031
12032 switch (mmu_idx) {
12033 case ARMMMUIdx_E10_0:
12034 case ARMMMUIdx_E20_0:
12035 case ARMMMUIdx_SE10_0:
12036 return 0;
12037 case ARMMMUIdx_E10_1:
12038 case ARMMMUIdx_E10_1_PAN:
12039 case ARMMMUIdx_SE10_1:
12040 case ARMMMUIdx_SE10_1_PAN:
12041 return 1;
12042 case ARMMMUIdx_E2:
12043 case ARMMMUIdx_E20_2:
12044 case ARMMMUIdx_E20_2_PAN:
12045 return 2;
12046 case ARMMMUIdx_SE3:
12047 return 3;
12048 default:
12049 g_assert_not_reached();
12050 }
12051 }
12052
12053 #ifndef CONFIG_TCG
12054 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
12055 {
12056 g_assert_not_reached();
12057 }
12058 #endif
12059
12060 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
12061 {
12062 if (arm_feature(env, ARM_FEATURE_M)) {
12063 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
12064 }
12065
12066 /* See ARM pseudo-function ELIsInHost. */
12067 switch (el) {
12068 case 0:
12069 if (arm_is_secure_below_el3(env)) {
12070 return ARMMMUIdx_SE10_0;
12071 }
12072 if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)
12073 && arm_el_is_aa64(env, 2)) {
12074 return ARMMMUIdx_E20_0;
12075 }
12076 return ARMMMUIdx_E10_0;
12077 case 1:
12078 if (arm_is_secure_below_el3(env)) {
12079 if (env->pstate & PSTATE_PAN) {
12080 return ARMMMUIdx_SE10_1_PAN;
12081 }
12082 return ARMMMUIdx_SE10_1;
12083 }
12084 if (env->pstate & PSTATE_PAN) {
12085 return ARMMMUIdx_E10_1_PAN;
12086 }
12087 return ARMMMUIdx_E10_1;
12088 case 2:
12089 /* TODO: ARMv8.4-SecEL2 */
12090 /* Note that TGE does not apply at EL2. */
12091 if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) {
12092 if (env->pstate & PSTATE_PAN) {
12093 return ARMMMUIdx_E20_2_PAN;
12094 }
12095 return ARMMMUIdx_E20_2;
12096 }
12097 return ARMMMUIdx_E2;
12098 case 3:
12099 return ARMMMUIdx_SE3;
12100 default:
12101 g_assert_not_reached();
12102 }
12103 }
12104
12105 ARMMMUIdx arm_mmu_idx(CPUARMState *env)
12106 {
12107 return arm_mmu_idx_el(env, arm_current_el(env));
12108 }
12109
12110 int cpu_mmu_index(CPUARMState *env, bool ifetch)
12111 {
12112 return arm_to_core_mmu_idx(arm_mmu_idx(env));
12113 }
12114
12115 #ifndef CONFIG_USER_ONLY
12116 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
12117 {
12118 return stage_1_mmu_idx(arm_mmu_idx(env));
12119 }
12120 #endif
12121
12122 static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
12123 ARMMMUIdx mmu_idx, uint32_t flags)
12124 {
12125 flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
12126 flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
12127 arm_to_core_mmu_idx(mmu_idx));
12128
12129 if (arm_singlestep_active(env)) {
12130 flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
12131 }
12132 return flags;
12133 }
12134
12135 static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
12136 ARMMMUIdx mmu_idx, uint32_t flags)
12137 {
12138 bool sctlr_b = arm_sctlr_b(env);
12139
12140 if (sctlr_b) {
12141 flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
12142 }
12143 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
12144 flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
12145 }
12146 flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
12147
12148 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
12149 }
12150
12151 static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
12152 ARMMMUIdx mmu_idx)
12153 {
12154 uint32_t flags = 0;
12155
12156 if (arm_v7m_is_handler_mode(env)) {
12157 flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
12158 }
12159
12160 /*
12161 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
12162 * is suppressing them because the requested execution priority
12163 * is less than 0.
12164 */
12165 if (arm_feature(env, ARM_FEATURE_V8) &&
12166 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
12167 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
12168 flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
12169 }
12170
12171 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
12172 }
12173
12174 static uint32_t rebuild_hflags_aprofile(CPUARMState *env)
12175 {
12176 int flags = 0;
12177
12178 flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL,
12179 arm_debug_target_el(env));
12180 return flags;
12181 }
12182
12183 static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
12184 ARMMMUIdx mmu_idx)
12185 {
12186 uint32_t flags = rebuild_hflags_aprofile(env);
12187
12188 if (arm_el_is_aa64(env, 1)) {
12189 flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
12190 }
12191
12192 if (arm_current_el(env) < 2 && env->cp15.hstr_el2 &&
12193 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
12194 flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1);
12195 }
12196
12197 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
12198 }
12199
12200 static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
12201 ARMMMUIdx mmu_idx)
12202 {
12203 uint32_t flags = rebuild_hflags_aprofile(env);
12204 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
12205 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
12206 uint64_t sctlr;
12207 int tbii, tbid;
12208
12209 flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
12210
12211 /* Get control bits for tagged addresses. */
12212 tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
12213 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
12214
12215 flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
12216 flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
12217
12218 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
12219 int sve_el = sve_exception_el(env, el);
12220 uint32_t zcr_len;
12221
12222 /*
12223 * If SVE is disabled, but FP is enabled,
12224 * then the effective len is 0.
12225 */
12226 if (sve_el != 0 && fp_el == 0) {
12227 zcr_len = 0;
12228 } else {
12229 zcr_len = sve_zcr_len_for_el(env, el);
12230 }
12231 flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
12232 flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
12233 }
12234
12235 sctlr = regime_sctlr(env, stage1);
12236
12237 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
12238 flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
12239 }
12240
12241 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
12242 /*
12243 * In order to save space in flags, we record only whether
12244 * pauth is "inactive", meaning all insns are implemented as
12245 * a nop, or "active" when some action must be performed.
12246 * The decision of which action to take is left to a helper.
12247 */
12248 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
12249 flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
12250 }
12251 }
12252
12253 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
12254 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12255 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
12256 flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
12257 }
12258 }
12259
12260 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12261 if (!(env->pstate & PSTATE_UAO)) {
12262 switch (mmu_idx) {
12263 case ARMMMUIdx_E10_1:
12264 case ARMMMUIdx_E10_1_PAN:
12265 case ARMMMUIdx_SE10_1:
12266 case ARMMMUIdx_SE10_1_PAN:
12267 /* TODO: ARMv8.3-NV */
12268 flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
12269 break;
12270 case ARMMMUIdx_E20_2:
12271 case ARMMMUIdx_E20_2_PAN:
12272 /* TODO: ARMv8.4-SecEL2 */
12273 /*
12274 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12275 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12276 */
12277 if (env->cp15.hcr_el2 & HCR_TGE) {
12278 flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
12279 }
12280 break;
12281 default:
12282 break;
12283 }
12284 }
12285
12286 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
12287 }
12288
12289 static uint32_t rebuild_hflags_internal(CPUARMState *env)
12290 {
12291 int el = arm_current_el(env);
12292 int fp_el = fp_exception_el(env, el);
12293 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12294
12295 if (is_a64(env)) {
12296 return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
12297 } else if (arm_feature(env, ARM_FEATURE_M)) {
12298 return rebuild_hflags_m32(env, fp_el, mmu_idx);
12299 } else {
12300 return rebuild_hflags_a32(env, fp_el, mmu_idx);
12301 }
12302 }
12303
12304 void arm_rebuild_hflags(CPUARMState *env)
12305 {
12306 env->hflags = rebuild_hflags_internal(env);
12307 }
12308
12309 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
12310 {
12311 int fp_el = fp_exception_el(env, el);
12312 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12313
12314 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
12315 }
12316
12317 /*
12318 * If we have triggered a EL state change we can't rely on the
12319 * translator having passed it too us, we need to recompute.
12320 */
12321 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
12322 {
12323 int el = arm_current_el(env);
12324 int fp_el = fp_exception_el(env, el);
12325 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12326 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
12327 }
12328
12329 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
12330 {
12331 int fp_el = fp_exception_el(env, el);
12332 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12333
12334 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
12335 }
12336
12337 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
12338 {
12339 int fp_el = fp_exception_el(env, el);
12340 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12341
12342 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
12343 }
12344
12345 static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
12346 {
12347 #ifdef CONFIG_DEBUG_TCG
12348 uint32_t env_flags_current = env->hflags;
12349 uint32_t env_flags_rebuilt = rebuild_hflags_internal(env);
12350
12351 if (unlikely(env_flags_current != env_flags_rebuilt)) {
12352 fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
12353 env_flags_current, env_flags_rebuilt);
12354 abort();
12355 }
12356 #endif
12357 }
12358
12359 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
12360 target_ulong *cs_base, uint32_t *pflags)
12361 {
12362 uint32_t flags = env->hflags;
12363 uint32_t pstate_for_ss;
12364
12365 *cs_base = 0;
12366 assert_hflags_rebuild_correctly(env);
12367
12368 if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) {
12369 *pc = env->pc;
12370 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
12371 flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
12372 }
12373 pstate_for_ss = env->pstate;
12374 } else {
12375 *pc = env->regs[15];
12376
12377 if (arm_feature(env, ARM_FEATURE_M)) {
12378 if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
12379 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
12380 != env->v7m.secure) {
12381 flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
12382 }
12383
12384 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
12385 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
12386 (env->v7m.secure &&
12387 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
12388 /*
12389 * ASPEN is set, but FPCA/SFPA indicate that there is no
12390 * active FP context; we must create a new FP context before
12391 * executing any FP insn.
12392 */
12393 flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1);
12394 }
12395
12396 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
12397 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
12398 flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
12399 }
12400 } else {
12401 /*
12402 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12403 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12404 */
12405 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
12406 flags = FIELD_DP32(flags, TBFLAG_A32,
12407 XSCALE_CPAR, env->cp15.c15_cpar);
12408 } else {
12409 flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN,
12410 env->vfp.vec_len);
12411 flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
12412 env->vfp.vec_stride);
12413 }
12414 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
12415 flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
12416 }
12417 }
12418
12419 flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
12420 flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
12421 pstate_for_ss = env->uncached_cpsr;
12422 }
12423
12424 /*
12425 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12426 * states defined in the ARM ARM for software singlestep:
12427 * SS_ACTIVE PSTATE.SS State
12428 * 0 x Inactive (the TB flag for SS is always 0)
12429 * 1 0 Active-pending
12430 * 1 1 Active-not-pending
12431 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
12432 */
12433 if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
12434 (pstate_for_ss & PSTATE_SS)) {
12435 flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
12436 }
12437
12438 *pflags = flags;
12439 }
12440
12441 #ifdef TARGET_AARCH64
12442 /*
12443 * The manual says that when SVE is enabled and VQ is widened the
12444 * implementation is allowed to zero the previously inaccessible
12445 * portion of the registers. The corollary to that is that when
12446 * SVE is enabled and VQ is narrowed we are also allowed to zero
12447 * the now inaccessible portion of the registers.
12448 *
12449 * The intent of this is that no predicate bit beyond VQ is ever set.
12450 * Which means that some operations on predicate registers themselves
12451 * may operate on full uint64_t or even unrolled across the maximum
12452 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12453 * may well be cheaper than conditionals to restrict the operation
12454 * to the relevant portion of a uint16_t[16].
12455 */
12456 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
12457 {
12458 int i, j;
12459 uint64_t pmask;
12460
12461 assert(vq >= 1 && vq <= ARM_MAX_VQ);
12462 assert(vq <= env_archcpu(env)->sve_max_vq);
12463
12464 /* Zap the high bits of the zregs. */
12465 for (i = 0; i < 32; i++) {
12466 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
12467 }
12468
12469 /* Zap the high bits of the pregs and ffr. */
12470 pmask = 0;
12471 if (vq & 3) {
12472 pmask = ~(-1ULL << (16 * (vq & 3)));
12473 }
12474 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
12475 for (i = 0; i < 17; ++i) {
12476 env->vfp.pregs[i].p[j] &= pmask;
12477 }
12478 pmask = 0;
12479 }
12480 }
12481
12482 /*
12483 * Notice a change in SVE vector size when changing EL.
12484 */
12485 void aarch64_sve_change_el(CPUARMState *env, int old_el,
12486 int new_el, bool el0_a64)
12487 {
12488 ARMCPU *cpu = env_archcpu(env);
12489 int old_len, new_len;
12490 bool old_a64, new_a64;
12491
12492 /* Nothing to do if no SVE. */
12493 if (!cpu_isar_feature(aa64_sve, cpu)) {
12494 return;
12495 }
12496
12497 /* Nothing to do if FP is disabled in either EL. */
12498 if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
12499 return;
12500 }
12501
12502 /*
12503 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12504 * at ELx, or not available because the EL is in AArch32 state, then
12505 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12506 * has an effective value of 0".
12507 *
12508 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12509 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12510 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12511 * we already have the correct register contents when encountering the
12512 * vq0->vq0 transition between EL0->EL1.
12513 */
12514 old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
12515 old_len = (old_a64 && !sve_exception_el(env, old_el)
12516 ? sve_zcr_len_for_el(env, old_el) : 0);
12517 new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
12518 new_len = (new_a64 && !sve_exception_el(env, new_el)
12519 ? sve_zcr_len_for_el(env, new_el) : 0);
12520
12521 /* When changing vector length, clear inaccessible state. */
12522 if (new_len < old_len) {
12523 aarch64_sve_narrow_vq(env, new_len + 1);
12524 }
12525 }
12526 #endif
AR7 emulation for QEMU