target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7
   8 #define CPUArchState struct CPUMIPSState
   9
  10 #include "config.h"
  11 #include "qemu-common.h"
  12 #include "mips-defs.h"
  13 #include "exec/cpu-defs.h"
  14 #include "fpu/softfloat.h"
  15
  16 struct CPUMIPSState;
  17
  18 typedef struct r4k_tlb_t r4k_tlb_t;
  19 struct r4k_tlb_t {
  20     target_ulong VPN;
  21     uint32_t PageMask;
  22     uint_fast8_t ASID;
  23     uint_fast16_t G:1;
  24     uint_fast16_t C0:3;
  25     uint_fast16_t C1:3;
  26     uint_fast16_t V0:1;
  27     uint_fast16_t V1:1;
  28     uint_fast16_t D0:1;
  29     uint_fast16_t D1:1;
  30     uint_fast16_t XI0:1;
  31     uint_fast16_t XI1:1;
  32     uint_fast16_t RI0:1;
  33     uint_fast16_t RI1:1;
  34     uint_fast16_t EHINV:1;
  35     uint64_t PFN[2];
  36 };
  37
  38 #if !defined(CONFIG_USER_ONLY)
  39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  40 struct CPUMIPSTLBContext {
  41     uint32_t nb_tlb;
  42     uint32_t tlb_in_use;
  43     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  44     void (*helper_tlbwi)(struct CPUMIPSState *env);
  45     void (*helper_tlbwr)(struct CPUMIPSState *env);
  46     void (*helper_tlbp)(struct CPUMIPSState *env);
  47     void (*helper_tlbr)(struct CPUMIPSState *env);
  48     void (*helper_tlbinv)(struct CPUMIPSState *env);
  49     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  50     union {
  51         struct {
  52             r4k_tlb_t tlb[MIPS_TLB_MAX];
  53         } r4k;
  54     } mmu;
  55 };
  56 #endif
  57
  58 /* MSA Context */
  59 #define MSA_WRLEN (128)
  60
  61 enum CPUMIPSMSADataFormat {
  62     DF_BYTE = 0,
  63     DF_HALF,
  64     DF_WORD,
  65     DF_DOUBLE
  66 };
  67
  68 typedef union wr_t wr_t;
  69 union wr_t {
  70     int8_t  b[MSA_WRLEN/8];
  71     int16_t h[MSA_WRLEN/16];
  72     int32_t w[MSA_WRLEN/32];
  73     int64_t d[MSA_WRLEN/64];
  74 };
  75
  76 typedef union fpr_t fpr_t;
  77 union fpr_t {
  78     float64  fd;   /* ieee double precision */
  79     float32  fs[2];/* ieee single precision */
  80     uint64_t d;    /* binary double fixed-point */
  81     uint32_t w[2]; /* binary single fixed-point */
  82 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  83     wr_t     wr;   /* vector data */
  84 };
  85 /* define FP_ENDIAN_IDX to access the same location
  86  * in the fpr_t union regardless of the host endianness
  87  */
  88 #if defined(HOST_WORDS_BIGENDIAN)
  89 #  define FP_ENDIAN_IDX 1
  90 #else
  91 #  define FP_ENDIAN_IDX 0
  92 #endif
  93
  94 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  95 struct CPUMIPSFPUContext {
  96     /* Floating point registers */
  97     fpr_t fpr[32];
  98     float_status fp_status;
  99     /* fpu implementation/revision register (fir) */
 100     uint32_t fcr0;
 101 #define FCR0_FREP 29
 102 #define FCR0_UFRP 28
 103 #define FCR0_F64 22
 104 #define FCR0_L 21
 105 #define FCR0_W 20
 106 #define FCR0_3D 19
 107 #define FCR0_PS 18
 108 #define FCR0_D 17
 109 #define FCR0_S 16
 110 #define FCR0_PRID 8
 111 #define FCR0_REV 0
 112     /* fcsr */
 113     uint32_t fcr31;
 114 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 115 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 116 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 117 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 118 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 119 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 120 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 121 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 122 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 123 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 124 #define FP_INEXACT        1
 125 #define FP_UNDERFLOW      2
 126 #define FP_OVERFLOW       4
 127 #define FP_DIV0           8
 128 #define FP_INVALID        16
 129 #define FP_UNIMPLEMENTED  32
 130 };
 131
 132 #define NB_MMU_MODES 3
 133
 134 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 135 struct CPUMIPSMVPContext {
 136     int32_t CP0_MVPControl;
 137 #define CP0MVPCo_CPA    3
 138 #define CP0MVPCo_STLB   2
 139 #define CP0MVPCo_VPC    1
 140 #define CP0MVPCo_EVP    0
 141     int32_t CP0_MVPConf0;
 142 #define CP0MVPC0_M      31
 143 #define CP0MVPC0_TLBS   29
 144 #define CP0MVPC0_GS     28
 145 #define CP0MVPC0_PCP    27
 146 #define CP0MVPC0_PTLBE  16
 147 #define CP0MVPC0_TCA    15
 148 #define CP0MVPC0_PVPE   10
 149 #define CP0MVPC0_PTC    0
 150     int32_t CP0_MVPConf1;
 151 #define CP0MVPC1_CIM    31
 152 #define CP0MVPC1_CIF    30
 153 #define CP0MVPC1_PCX    20
 154 #define CP0MVPC1_PCP2   10
 155 #define CP0MVPC1_PCP1   0
 156 };
 157
 158 typedef struct mips_def_t mips_def_t;
 159
 160 #define MIPS_SHADOW_SET_MAX 16
 161 #define MIPS_TC_MAX 5
 162 #define MIPS_FPU_MAX 1
 163 #define MIPS_DSP_ACC 4
 164 #define MIPS_KSCRATCH_NUM 6
 165
 166 typedef struct TCState TCState;
 167 struct TCState {
 168     target_ulong gpr[32];
 169     target_ulong PC;
 170     target_ulong HI[MIPS_DSP_ACC];
 171     target_ulong LO[MIPS_DSP_ACC];
 172     target_ulong ACX[MIPS_DSP_ACC];
 173     target_ulong DSPControl;
 174     int32_t CP0_TCStatus;
 175 #define CP0TCSt_TCU3    31
 176 #define CP0TCSt_TCU2    30
 177 #define CP0TCSt_TCU1    29
 178 #define CP0TCSt_TCU0    28
 179 #define CP0TCSt_TMX     27
 180 #define CP0TCSt_RNST    23
 181 #define CP0TCSt_TDS     21
 182 #define CP0TCSt_DT      20
 183 #define CP0TCSt_DA      15
 184 #define CP0TCSt_A       13
 185 #define CP0TCSt_TKSU    11
 186 #define CP0TCSt_IXMT    10
 187 #define CP0TCSt_TASID   0
 188     int32_t CP0_TCBind;
 189 #define CP0TCBd_CurTC   21
 190 #define CP0TCBd_TBE     17
 191 #define CP0TCBd_CurVPE  0
 192     target_ulong CP0_TCHalt;
 193     target_ulong CP0_TCContext;
 194     target_ulong CP0_TCSchedule;
 195     target_ulong CP0_TCScheFBack;
 196     int32_t CP0_Debug_tcstatus;
 197     target_ulong CP0_UserLocal;
 198
 199     int32_t msacsr;
 200
 201 #define MSACSR_FS       24
 202 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 203 #define MSACSR_NX       18
 204 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 205 #define MSACSR_CEF      2
 206 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 207 #define MSACSR_RM       0
 208 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 209 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 210         MSACSR_FS_MASK)
 211
 212     float_status msa_fp_status;
 213 };
 214
 215 typedef struct CPUMIPSState CPUMIPSState;
 216 struct CPUMIPSState {
 217     TCState active_tc;
 218     CPUMIPSFPUContext active_fpu;
 219
 220     uint32_t current_tc;
 221     uint32_t current_fpu;
 222
 223     uint32_t SEGBITS;
 224     uint32_t PABITS;
 225 #if defined(TARGET_MIPS64)
 226 # define PABITS_BASE 36
 227 #else
 228 # define PABITS_BASE 32
 229 #endif
 230     target_ulong SEGMask;
 231     uint64_t PAMask;
 232 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 233
 234     int32_t msair;
 235 #define MSAIR_ProcID    8
 236 #define MSAIR_Rev       0
 237
 238     int32_t CP0_Index;
 239     /* CP0_MVP* are per MVP registers. */
 240     int32_t CP0_Random;
 241     int32_t CP0_VPEControl;
 242 #define CP0VPECo_YSI    21
 243 #define CP0VPECo_GSI    20
 244 #define CP0VPECo_EXCPT  16
 245 #define CP0VPECo_TE     15
 246 #define CP0VPECo_TargTC 0
 247     int32_t CP0_VPEConf0;
 248 #define CP0VPEC0_M      31
 249 #define CP0VPEC0_XTC    21
 250 #define CP0VPEC0_TCS    19
 251 #define CP0VPEC0_SCS    18
 252 #define CP0VPEC0_DSC    17
 253 #define CP0VPEC0_ICS    16
 254 #define CP0VPEC0_MVP    1
 255 #define CP0VPEC0_VPA    0
 256     int32_t CP0_VPEConf1;
 257 #define CP0VPEC1_NCX    20
 258 #define CP0VPEC1_NCP2   10
 259 #define CP0VPEC1_NCP1   0
 260     target_ulong CP0_YQMask;
 261     target_ulong CP0_VPESchedule;
 262     target_ulong CP0_VPEScheFBack;
 263     int32_t CP0_VPEOpt;
 264 #define CP0VPEOpt_IWX7  15
 265 #define CP0VPEOpt_IWX6  14
 266 #define CP0VPEOpt_IWX5  13
 267 #define CP0VPEOpt_IWX4  12
 268 #define CP0VPEOpt_IWX3  11
 269 #define CP0VPEOpt_IWX2  10
 270 #define CP0VPEOpt_IWX1  9
 271 #define CP0VPEOpt_IWX0  8
 272 #define CP0VPEOpt_DWX7  7
 273 #define CP0VPEOpt_DWX6  6
 274 #define CP0VPEOpt_DWX5  5
 275 #define CP0VPEOpt_DWX4  4
 276 #define CP0VPEOpt_DWX3  3
 277 #define CP0VPEOpt_DWX2  2
 278 #define CP0VPEOpt_DWX1  1
 279 #define CP0VPEOpt_DWX0  0
 280     uint64_t CP0_EntryLo0;
 281     uint64_t CP0_EntryLo1;
 282 #if defined(TARGET_MIPS64)
 283 # define CP0EnLo_RI 63
 284 # define CP0EnLo_XI 62
 285 #else
 286 # define CP0EnLo_RI 31
 287 # define CP0EnLo_XI 30
 288 #endif
 289     target_ulong CP0_Context;
 290     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 291     int32_t CP0_PageMask;
 292     int32_t CP0_PageGrain_rw_bitmask;
 293     int32_t CP0_PageGrain;
 294 #define CP0PG_RIE 31
 295 #define CP0PG_XIE 30
 296 #define CP0PG_ELPA 29
 297 #define CP0PG_IEC 27
 298     int32_t CP0_Wired;
 299     int32_t CP0_SRSConf0_rw_bitmask;
 300     int32_t CP0_SRSConf0;
 301 #define CP0SRSC0_M      31
 302 #define CP0SRSC0_SRS3   20
 303 #define CP0SRSC0_SRS2   10
 304 #define CP0SRSC0_SRS1   0
 305     int32_t CP0_SRSConf1_rw_bitmask;
 306     int32_t CP0_SRSConf1;
 307 #define CP0SRSC1_M      31
 308 #define CP0SRSC1_SRS6   20
 309 #define CP0SRSC1_SRS5   10
 310 #define CP0SRSC1_SRS4   0
 311     int32_t CP0_SRSConf2_rw_bitmask;
 312     int32_t CP0_SRSConf2;
 313 #define CP0SRSC2_M      31
 314 #define CP0SRSC2_SRS9   20
 315 #define CP0SRSC2_SRS8   10
 316 #define CP0SRSC2_SRS7   0
 317     int32_t CP0_SRSConf3_rw_bitmask;
 318     int32_t CP0_SRSConf3;
 319 #define CP0SRSC3_M      31
 320 #define CP0SRSC3_SRS12  20
 321 #define CP0SRSC3_SRS11  10
 322 #define CP0SRSC3_SRS10  0
 323     int32_t CP0_SRSConf4_rw_bitmask;
 324     int32_t CP0_SRSConf4;
 325 #define CP0SRSC4_SRS15  20
 326 #define CP0SRSC4_SRS14  10
 327 #define CP0SRSC4_SRS13  0
 328     int32_t CP0_HWREna;
 329     target_ulong CP0_BadVAddr;
 330     uint32_t CP0_BadInstr;
 331     uint32_t CP0_BadInstrP;
 332     int32_t CP0_Count;
 333     target_ulong CP0_EntryHi;
 334 #define CP0EnHi_EHINV 10
 335     int32_t CP0_Compare;
 336     int32_t CP0_Status;
 337 #define CP0St_CU3   31
 338 #define CP0St_CU2   30
 339 #define CP0St_CU1   29
 340 #define CP0St_CU0   28
 341 #define CP0St_RP    27
 342 #define CP0St_FR    26
 343 #define CP0St_RE    25
 344 #define CP0St_MX    24
 345 #define CP0St_PX    23
 346 #define CP0St_BEV   22
 347 #define CP0St_TS    21
 348 #define CP0St_SR    20
 349 #define CP0St_NMI   19
 350 #define CP0St_IM    8
 351 #define CP0St_KX    7
 352 #define CP0St_SX    6
 353 #define CP0St_UX    5
 354 #define CP0St_KSU   3
 355 #define CP0St_ERL   2
 356 #define CP0St_EXL   1
 357 #define CP0St_IE    0
 358     int32_t CP0_IntCtl;
 359 #define CP0IntCtl_IPTI 29
 360 #define CP0IntCtl_IPPC1 26
 361 #define CP0IntCtl_VS 5
 362     int32_t CP0_SRSCtl;
 363 #define CP0SRSCtl_HSS 26
 364 #define CP0SRSCtl_EICSS 18
 365 #define CP0SRSCtl_ESS 12
 366 #define CP0SRSCtl_PSS 6
 367 #define CP0SRSCtl_CSS 0
 368     int32_t CP0_SRSMap;
 369 #define CP0SRSMap_SSV7 28
 370 #define CP0SRSMap_SSV6 24
 371 #define CP0SRSMap_SSV5 20
 372 #define CP0SRSMap_SSV4 16
 373 #define CP0SRSMap_SSV3 12
 374 #define CP0SRSMap_SSV2 8
 375 #define CP0SRSMap_SSV1 4
 376 #define CP0SRSMap_SSV0 0
 377     int32_t CP0_Cause;
 378 #define CP0Ca_BD   31
 379 #define CP0Ca_TI   30
 380 #define CP0Ca_CE   28
 381 #define CP0Ca_DC   27
 382 #define CP0Ca_PCI  26
 383 #define CP0Ca_IV   23
 384 #define CP0Ca_WP   22
 385 #define CP0Ca_IP    8
 386 #define CP0Ca_IP_mask 0x0000FF00
 387 #define CP0Ca_EC    2
 388     target_ulong CP0_EPC;
 389     int32_t CP0_PRid;
 390     int32_t CP0_EBase;
 391     int32_t CP0_Config0;
 392 #define CP0C0_M    31
 393 #define CP0C0_K23  28
 394 #define CP0C0_KU   25
 395 #define CP0C0_MDU  20
 396 #define CP0C0_MM   18
 397 #define CP0C0_BM   16
 398 #define CP0C0_BE   15
 399 #define CP0C0_AT   13
 400 #define CP0C0_AR   10
 401 #define CP0C0_MT   7
 402 #define CP0C0_VI   3
 403 #define CP0C0_K0   0
 404     int32_t CP0_Config1;
 405 #define CP0C1_M    31
 406 #define CP0C1_MMU  25
 407 #define CP0C1_IS   22
 408 #define CP0C1_IL   19
 409 #define CP0C1_IA   16
 410 #define CP0C1_DS   13
 411 #define CP0C1_DL   10
 412 #define CP0C1_DA   7
 413 #define CP0C1_C2   6
 414 #define CP0C1_MD   5
 415 #define CP0C1_PC   4
 416 #define CP0C1_WR   3
 417 #define CP0C1_CA   2
 418 #define CP0C1_EP   1
 419 #define CP0C1_FP   0
 420     int32_t CP0_Config2;
 421 #define CP0C2_M    31
 422 #define CP0C2_TU   28
 423 #define CP0C2_TS   24
 424 #define CP0C2_TL   20
 425 #define CP0C2_TA   16
 426 #define CP0C2_SU   12
 427 #define CP0C2_SS   8
 428 #define CP0C2_SL   4
 429 #define CP0C2_SA   0
 430     int32_t CP0_Config3;
 431 #define CP0C3_M    31
 432 #define CP0C3_BPG  30
 433 #define CP0C3_CMCGR 29
 434 #define CP0C3_MSAP  28
 435 #define CP0C3_BP 27
 436 #define CP0C3_BI 26
 437 #define CP0C3_IPLW 21
 438 #define CP0C3_MMAR 18
 439 #define CP0C3_MCU  17
 440 #define CP0C3_ISA_ON_EXC 16
 441 #define CP0C3_ISA  14
 442 #define CP0C3_ULRI 13
 443 #define CP0C3_RXI  12
 444 #define CP0C3_DSP2P 11
 445 #define CP0C3_DSPP 10
 446 #define CP0C3_LPA  7
 447 #define CP0C3_VEIC 6
 448 #define CP0C3_VInt 5
 449 #define CP0C3_SP   4
 450 #define CP0C3_CDMM 3
 451 #define CP0C3_MT   2
 452 #define CP0C3_SM   1
 453 #define CP0C3_TL   0
 454     int32_t CP0_Config4;
 455     int32_t CP0_Config4_rw_bitmask;
 456 #define CP0C4_M    31
 457 #define CP0C4_IE   29
 458 #define CP0C4_KScrExist 16
 459 #define CP0C4_MMUExtDef 14
 460 #define CP0C4_FTLBPageSize 8
 461 #define CP0C4_FTLBWays 4
 462 #define CP0C4_FTLBSets 0
 463 #define CP0C4_MMUSizeExt 0
 464     int32_t CP0_Config5;
 465     int32_t CP0_Config5_rw_bitmask;
 466 #define CP0C5_M          31
 467 #define CP0C5_K          30
 468 #define CP0C5_CV         29
 469 #define CP0C5_EVA        28
 470 #define CP0C5_MSAEn      27
 471 #define CP0C5_UFE        9
 472 #define CP0C5_FRE        8
 473 #define CP0C5_SBRI       6
 474 #define CP0C5_MVH        5
 475 #define CP0C5_LLB        4
 476 #define CP0C5_UFR        2
 477 #define CP0C5_NFExists   0
 478     int32_t CP0_Config6;
 479     int32_t CP0_Config7;
 480     /* XXX: Maybe make LLAddr per-TC? */
 481     uint64_t lladdr;
 482     target_ulong llval;
 483     target_ulong llnewval;
 484     target_ulong llreg;
 485     uint64_t CP0_LLAddr_rw_bitmask;
 486     int CP0_LLAddr_shift;
 487     target_ulong CP0_WatchLo[8];
 488     int32_t CP0_WatchHi[8];
 489     target_ulong CP0_XContext;
 490     int32_t CP0_Framemask;
 491     int32_t CP0_Debug;
 492 #define CP0DB_DBD  31
 493 #define CP0DB_DM   30
 494 #define CP0DB_LSNM 28
 495 #define CP0DB_Doze 27
 496 #define CP0DB_Halt 26
 497 #define CP0DB_CNT  25
 498 #define CP0DB_IBEP 24
 499 #define CP0DB_DBEP 21
 500 #define CP0DB_IEXI 20
 501 #define CP0DB_VER  15
 502 #define CP0DB_DEC  10
 503 #define CP0DB_SSt  8
 504 #define CP0DB_DINT 5
 505 #define CP0DB_DIB  4
 506 #define CP0DB_DDBS 3
 507 #define CP0DB_DDBL 2
 508 #define CP0DB_DBp  1
 509 #define CP0DB_DSS  0
 510     target_ulong CP0_DEPC;
 511     int32_t CP0_Performance0;
 512     uint64_t CP0_TagLo;
 513     int32_t CP0_DataLo;
 514     int32_t CP0_TagHi;
 515     int32_t CP0_DataHi;
 516     target_ulong CP0_ErrorEPC;
 517     int32_t CP0_DESAVE;
 518     /* We waste some space so we can handle shadow registers like TCs. */
 519     TCState tcs[MIPS_SHADOW_SET_MAX];
 520     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 521     /* QEMU */
 522     int error_code;
 523 #define EXCP_TLB_NOMATCH   0x1
 524 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 525     uint32_t hflags;    /* CPU State */
 526     /* TMASK defines different execution modes */
 527 #define MIPS_HFLAG_TMASK  0x75807FF
 528 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 529     /* The KSU flags must be the lowest bits in hflags. The flag order
 530        must be the same as defined for CP0 Status. This allows to use
 531        the bits as the value of mmu_idx. */
 532 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 533 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 534 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 535 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 536 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 537 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 538 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 539 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 540 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 541     /* True if the MIPS IV COP1X instructions can be used.  This also
 542        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 543        and RSQRT.D.  */
 544 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 545 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 546 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 547 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 548 #define MIPS_HFLAG_M16_SHIFT 10
 549     /* If translation is interrupted between the branch instruction and
 550      * the delay slot, record what type of branch it is so that we can
 551      * resume translation properly.  It might be possible to reduce
 552      * this from three bits to two.  */
 553 #define MIPS_HFLAG_BMASK_BASE  0x803800
 554 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 555 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 556 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 557 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 558     /* Extra flags about the current pending branch.  */
 559 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 560 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 561 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 562 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 563 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 564 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 565 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 566     /* MIPS DSP resources access. */
 567 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 568 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 569     /* Extra flag about HWREna register. */
 570 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 571 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 572 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 573 #define MIPS_HFLAG_MSA   0x1000000
 574 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 575 #define MIPS_HFLAG_ELPA  0x4000000
 576     target_ulong btarget;        /* Jump / branch target               */
 577     target_ulong bcond;          /* Branch condition (if needed)       */
 578
 579     int SYNCI_Step; /* Address step size for SYNCI */
 580     int CCRes; /* Cycle count resolution/divisor */
 581     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 582     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 583     int insn_flags; /* Supported instruction set */
 584
 585     CPU_COMMON
 586
 587     /* Fields from here on are preserved across CPU reset. */
 588     CPUMIPSMVPContext *mvp;
 589 #if !defined(CONFIG_USER_ONLY)
 590     CPUMIPSTLBContext *tlb;
 591 #endif
 592
 593     const mips_def_t *cpu_model;
 594     void *irq[8];
 595     QEMUTimer *timer; /* Internal timer */
 596 };
 597
 598 #include "cpu-qom.h"
 599
 600 #if !defined(CONFIG_USER_ONLY)
 601 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 602                         target_ulong address, int rw, int access_type);
 603 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 604                            target_ulong address, int rw, int access_type);
 605 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 606                      target_ulong address, int rw, int access_type);
 607 void r4k_helper_tlbwi(CPUMIPSState *env);
 608 void r4k_helper_tlbwr(CPUMIPSState *env);
 609 void r4k_helper_tlbp(CPUMIPSState *env);
 610 void r4k_helper_tlbr(CPUMIPSState *env);
 611 void r4k_helper_tlbinv(CPUMIPSState *env);
 612 void r4k_helper_tlbinvf(CPUMIPSState *env);
 613
 614 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 615                                 bool is_write, bool is_exec, int unused,
 616                                 unsigned size);
 617 #endif
 618
 619 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 620
 621 #define cpu_exec cpu_mips_exec
 622 #define cpu_gen_code cpu_mips_gen_code
 623 #define cpu_signal_handler cpu_mips_signal_handler
 624 #define cpu_list mips_cpu_list
 625
 626 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 627 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 628
 629 /* MMU modes definitions. We carefully match the indices with our
 630    hflags layout. */
 631 #define MMU_MODE0_SUFFIX _kernel
 632 #define MMU_MODE1_SUFFIX _super
 633 #define MMU_MODE2_SUFFIX _user
 634 #define MMU_USER_IDX 2
 635 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 636 {
 637     return env->hflags & MIPS_HFLAG_KSU;
 638 }
 639
 640 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 641 {
 642     int32_t pending;
 643     int32_t status;
 644     int r;
 645
 646     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
 647         (env->CP0_Status & (1 << CP0St_EXL)) ||
 648         (env->CP0_Status & (1 << CP0St_ERL)) ||
 649         /* Note that the TCStatus IXMT field is initialized to zero,
 650            and only MT capable cores can set it to one. So we don't
 651            need to check for MT capabilities here.  */
 652         (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
 653         (env->hflags & MIPS_HFLAG_DM)) {
 654         /* Interrupts are disabled */
 655         return 0;
 656     }
 657
 658     pending = env->CP0_Cause & CP0Ca_IP_mask;
 659     status = env->CP0_Status & CP0Ca_IP_mask;
 660
 661     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 662         /* A MIPS configured with a vectorizing external interrupt controller
 663            will feed a vector into the Cause pending lines. The core treats
 664            the status lines as a vector level, not as indiviual masks.  */
 665         r = pending > status;
 666     } else {
 667         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 668            treats the pending lines as individual interrupt lines, the status
 669            lines are individual masks.  */
 670         r = pending & status;
 671     }
 672     return r;
 673 }
 674
 675 #include "exec/cpu-all.h"
 676
 677 /* Memory access type :
 678  * may be needed for precise access rights control and precise exceptions.
 679  */
 680 enum {
 681     /* 1 bit to define user level / supervisor access */
 682     ACCESS_USER  = 0x00,
 683     ACCESS_SUPER = 0x01,
 684     /* 1 bit to indicate direction */
 685     ACCESS_STORE = 0x02,
 686     /* Type of instruction that generated the access */
 687     ACCESS_CODE  = 0x10, /* Code fetch access                */
 688     ACCESS_INT   = 0x20, /* Integer load/store access        */
 689     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 690 };
 691
 692 /* Exceptions */
 693 enum {
 694     EXCP_NONE          = -1,
 695     EXCP_RESET         = 0,
 696     EXCP_SRESET,
 697     EXCP_DSS,
 698     EXCP_DINT,
 699     EXCP_DDBL,
 700     EXCP_DDBS,
 701     EXCP_NMI,
 702     EXCP_MCHECK,
 703     EXCP_EXT_INTERRUPT, /* 8 */
 704     EXCP_DFWATCH,
 705     EXCP_DIB,
 706     EXCP_IWATCH,
 707     EXCP_AdEL,
 708     EXCP_AdES,
 709     EXCP_TLBF,
 710     EXCP_IBE,
 711     EXCP_DBp, /* 16 */
 712     EXCP_SYSCALL,
 713     EXCP_BREAK,
 714     EXCP_CpU,
 715     EXCP_RI,
 716     EXCP_OVERFLOW,
 717     EXCP_TRAP,
 718     EXCP_FPE,
 719     EXCP_DWATCH, /* 24 */
 720     EXCP_LTLBL,
 721     EXCP_TLBL,
 722     EXCP_TLBS,
 723     EXCP_DBE,
 724     EXCP_THREAD,
 725     EXCP_MDMX,
 726     EXCP_C2E,
 727     EXCP_CACHE, /* 32 */
 728     EXCP_DSPDIS,
 729     EXCP_MSADIS,
 730     EXCP_MSAFPE,
 731     EXCP_TLBXI,
 732     EXCP_TLBRI,
 733
 734     EXCP_LAST = EXCP_TLBRI,
 735 };
 736 /* Dummy exception for conditional stores.  */
 737 #define EXCP_SC 0x100
 738
 739 /*
 740  * This is an interrnally generated WAKE request line.
 741  * It is driven by the CPU itself. Raised when the MT
 742  * block wants to wake a VPE from an inactive state and
 743  * cleared when VPE goes from active to inactive.
 744  */
 745 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 746
 747 int cpu_mips_exec(CPUState *cpu);
 748 void mips_tcg_init(void);
 749 MIPSCPU *cpu_mips_init(const char *cpu_model);
 750 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 751
 752 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 753
 754 /* TODO QOM'ify CPU reset and remove */
 755 void cpu_state_reset(CPUMIPSState *s);
 756
 757 /* mips_timer.c */
 758 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 759 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 760 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 761 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 762 void cpu_mips_start_count(CPUMIPSState *env);
 763 void cpu_mips_stop_count(CPUMIPSState *env);
 764
 765 /* mips_int.c */
 766 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 767
 768 /* helper.c */
 769 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 770                               int mmu_idx);
 771 #if !defined(CONFIG_USER_ONLY)
 772 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 773 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 774                                                int rw);
 775 #endif
 776 target_ulong exception_resume_pc (CPUMIPSState *env);
 777
 778 /* op_helper.c */
 779 extern unsigned int ieee_rm[];
 780 int ieee_ex_to_mips(int xcpt);
 781
 782 static inline void restore_rounding_mode(CPUMIPSState *env)
 783 {
 784     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 785                             &env->active_fpu.fp_status);
 786 }
 787
 788 static inline void restore_flush_mode(CPUMIPSState *env)
 789 {
 790     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
 791                       &env->active_fpu.fp_status);
 792 }
 793
 794 static inline void restore_fp_status(CPUMIPSState *env)
 795 {
 796     restore_rounding_mode(env);
 797     restore_flush_mode(env);
 798 }
 799
 800 static inline void restore_msa_fp_status(CPUMIPSState *env)
 801 {
 802     float_status *status = &env->active_tc.msa_fp_status;
 803     int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 804     bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 805
 806     set_float_rounding_mode(ieee_rm[rounding_mode], status);
 807     set_flush_to_zero(flush_to_zero, status);
 808     set_flush_inputs_to_zero(flush_to_zero, status);
 809 }
 810
 811 static inline void restore_pamask(CPUMIPSState *env)
 812 {
 813     if (env->hflags & MIPS_HFLAG_ELPA) {
 814         env->PAMask = (1ULL << env->PABITS) - 1;
 815     } else {
 816         env->PAMask = PAMASK_BASE;
 817     }
 818 }
 819
 820 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 821                                         target_ulong *cs_base, int *flags)
 822 {
 823     *pc = env->active_tc.PC;
 824     *cs_base = 0;
 825     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 826                             MIPS_HFLAG_HWRENA_ULR);
 827 }
 828
 829 static inline int mips_vpe_active(CPUMIPSState *env)
 830 {
 831     int active = 1;
 832
 833     /* Check that the VPE is enabled.  */
 834     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 835         active = 0;
 836     }
 837     /* Check that the VPE is activated.  */
 838     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 839         active = 0;
 840     }
 841
 842     /* Now verify that there are active thread contexts in the VPE.
 843
 844        This assumes the CPU model will internally reschedule threads
 845        if the active one goes to sleep. If there are no threads available
 846        the active one will be in a sleeping state, and we can turn off
 847        the entire VPE.  */
 848     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 849         /* TC is not activated.  */
 850         active = 0;
 851     }
 852     if (env->active_tc.CP0_TCHalt & 1) {
 853         /* TC is in halt state.  */
 854         active = 0;
 855     }
 856
 857     return active;
 858 }
 859
 860 #include "exec/exec-all.h"
 861
 862 static inline void compute_hflags(CPUMIPSState *env)
 863 {
 864     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 865                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 866                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 867                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 868                      MIPS_HFLAG_ELPA);
 869     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 870         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 871         !(env->hflags & MIPS_HFLAG_DM)) {
 872         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 873     }
 874 #if defined(TARGET_MIPS64)
 875     if ((env->insn_flags & ISA_MIPS3) &&
 876         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 877          (env->CP0_Status & (1 << CP0St_PX)) ||
 878          (env->CP0_Status & (1 << CP0St_UX)))) {
 879         env->hflags |= MIPS_HFLAG_64;
 880     }
 881
 882     if (!(env->insn_flags & ISA_MIPS3)) {
 883         env->hflags |= MIPS_HFLAG_AWRAP;
 884     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 885                !(env->CP0_Status & (1 << CP0St_UX))) {
 886         env->hflags |= MIPS_HFLAG_AWRAP;
 887     } else if (env->insn_flags & ISA_MIPS64R6) {
 888         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 889         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 890              !(env->CP0_Status & (1 << CP0St_SX))) ||
 891             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 892              !(env->CP0_Status & (1 << CP0St_KX)))) {
 893             env->hflags |= MIPS_HFLAG_AWRAP;
 894         }
 895     }
 896 #endif
 897     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 898          !(env->insn_flags & ISA_MIPS32R6)) ||
 899         !(env->hflags & MIPS_HFLAG_KSU)) {
 900         env->hflags |= MIPS_HFLAG_CP0;
 901     }
 902     if (env->CP0_Status & (1 << CP0St_CU1)) {
 903         env->hflags |= MIPS_HFLAG_FPU;
 904     }
 905     if (env->CP0_Status & (1 << CP0St_FR)) {
 906         env->hflags |= MIPS_HFLAG_F64;
 907     }
 908     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 909         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 910         env->hflags |= MIPS_HFLAG_SBRI;
 911     }
 912     if (env->insn_flags & ASE_DSPR2) {
 913         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 914            so enable to access DSPR2 resources. */
 915         if (env->CP0_Status & (1 << CP0St_MX)) {
 916             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 917         }
 918
 919     } else if (env->insn_flags & ASE_DSP) {
 920         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 921            so enable to access DSP resources. */
 922         if (env->CP0_Status & (1 << CP0St_MX)) {
 923             env->hflags |= MIPS_HFLAG_DSP;
 924         }
 925
 926     }
 927     if (env->insn_flags & ISA_MIPS32R2) {
 928         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 929             env->hflags |= MIPS_HFLAG_COP1X;
 930         }
 931     } else if (env->insn_flags & ISA_MIPS32) {
 932         if (env->hflags & MIPS_HFLAG_64) {
 933             env->hflags |= MIPS_HFLAG_COP1X;
 934         }
 935     } else if (env->insn_flags & ISA_MIPS4) {
 936         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 937            and disable the MIPS IV extensions to the MIPS III ISA.
 938            Some other MIPS IV CPUs ignore the bit, so the check here
 939            would be too restrictive for them.  */
 940         if (env->CP0_Status & (1U << CP0St_CU3)) {
 941             env->hflags |= MIPS_HFLAG_COP1X;
 942         }
 943     }
 944     if (env->insn_flags & ASE_MSA) {
 945         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 946             env->hflags |= MIPS_HFLAG_MSA;
 947         }
 948     }
 949     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 950         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 951             env->hflags |= MIPS_HFLAG_FRE;
 952         }
 953     }
 954     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 955         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 956             env->hflags |= MIPS_HFLAG_ELPA;
 957         }
 958     }
 959 }
 960
 961 #ifndef CONFIG_USER_ONLY
 962 /* Called for updates to CP0_Status.  */
 963 static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 964 {
 965     int32_t tcstatus, *tcst;
 966     uint32_t v = cpu->CP0_Status;
 967     uint32_t cu, mx, asid, ksu;
 968     uint32_t mask = ((1 << CP0TCSt_TCU3)
 969                        | (1 << CP0TCSt_TCU2)
 970                        | (1 << CP0TCSt_TCU1)
 971                        | (1 << CP0TCSt_TCU0)
 972                        | (1 << CP0TCSt_TMX)
 973                        | (3 << CP0TCSt_TKSU)
 974                        | (0xff << CP0TCSt_TASID));
 975
 976     cu = (v >> CP0St_CU0) & 0xf;
 977     mx = (v >> CP0St_MX) & 0x1;
 978     ksu = (v >> CP0St_KSU) & 0x3;
 979     asid = env->CP0_EntryHi & 0xff;
 980
 981     tcstatus = cu << CP0TCSt_TCU0;
 982     tcstatus |= mx << CP0TCSt_TMX;
 983     tcstatus |= ksu << CP0TCSt_TKSU;
 984     tcstatus |= asid;
 985
 986     if (tc == cpu->current_tc) {
 987         tcst = &cpu->active_tc.CP0_TCStatus;
 988     } else {
 989         tcst = &cpu->tcs[tc].CP0_TCStatus;
 990     }
 991
 992     *tcst &= ~mask;
 993     *tcst |= tcstatus;
 994     compute_hflags(cpu);
 995 }
 996
 997 static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 998 {
 999     uint32_t mask = env->CP0_Status_rw_bitmask;
1000
1001     if (env->insn_flags & ISA_MIPS32R6) {
1002         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
1003
1004         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
1005             mask &= ~(3 << CP0St_KSU);
1006         }
1007         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
1008     }
1009
1010     env->CP0_Status = (env->CP0_Status & ~mask) | (val & mask);
1011     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1012         sync_c0_status(env, env, env->current_tc);
1013     } else {
1014         compute_hflags(env);
1015     }
1016 }
1017
1018 static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
1019 {
1020     uint32_t mask = 0x00C00300;
1021     uint32_t old = env->CP0_Cause;
1022     int i;
1023
1024     if (env->insn_flags & ISA_MIPS32R2) {
1025         mask |= 1 << CP0Ca_DC;
1026     }
1027     if (env->insn_flags & ISA_MIPS32R6) {
1028         mask &= ~((1 << CP0Ca_WP) & val);
1029     }
1030
1031     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
1032
1033     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1034         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
1035             cpu_mips_stop_count(env);
1036         } else {
1037             cpu_mips_start_count(env);
1038         }
1039     }
1040
1041     /* Set/reset software interrupts */
1042     for (i = 0 ; i < 2 ; i++) {
1043         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1044             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
1045         }
1046     }
1047 }
1048 #endif
1049
1050 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1051                                                         uint32_t exception,
1052                                                         int error_code,
1053                                                         uintptr_t pc)
1054 {
1055     CPUState *cs = CPU(mips_env_get_cpu(env));
1056
1057     if (exception < EXCP_SC) {
1058         qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
1059                       __func__, exception, error_code);
1060     }
1061     cs->exception_index = exception;
1062     env->error_code = error_code;
1063
1064     cpu_loop_exit_restore(cs, pc);
1065 }
1066
1067 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1068                                                     uint32_t exception,
1069                                                     uintptr_t pc)
1070 {
1071     do_raise_exception_err(env, exception, 0, pc);
1072 }
1073
1074 #endif /* !defined (__MIPS_CPU_H__) */