hw/i2c/imx_i2c.c

   1 /*
   2  *  i.MX I2C Bus Serial Interface Emulation
   3  *
   4  *  Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "hw/i2c/imx_i2c.h"
  22 #include "hw/i2c/i2c.h"
  23
  24 #ifndef IMX_I2C_DEBUG
  25 #define IMX_I2C_DEBUG                 0
  26 #endif
  27
  28 #if IMX_I2C_DEBUG
  29 #define DPRINT(fmt, args...)              \
  30     do { fprintf(stderr, "%s: "fmt, __func__, ## args); } while (0)
  31
  32 static const char *imx_i2c_get_regname(unsigned offset)
  33 {
  34     switch (offset) {
  35     case IADR_ADDR:
  36         return "IADR";
  37     case IFDR_ADDR:
  38         return "IFDR";
  39     case I2CR_ADDR:
  40         return "I2CR";
  41     case I2SR_ADDR:
  42         return "I2SR";
  43     case I2DR_ADDR:
  44         return "I2DR";
  45     default:
  46         return "[?]";
  47     }
  48 }
  49 #else
  50 #define DPRINT(fmt, args...)              do { } while (0)
  51 #endif
  52
  53 static inline bool imx_i2c_is_enabled(IMXI2CState *s)
  54 {
  55     return s->i2cr & I2CR_IEN;
  56 }
  57
  58 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
  59 {
  60     return s->i2cr & I2CR_IIEN;
  61 }
  62
  63 static inline bool imx_i2c_is_master(IMXI2CState *s)
  64 {
  65     return s->i2cr & I2CR_MSTA;
  66 }
  67
  68 static void imx_i2c_reset(DeviceState *dev)
  69 {
  70     IMXI2CState *s = IMX_I2C(dev);
  71
  72     if (s->address != ADDR_RESET) {
  73         i2c_end_transfer(s->bus);
  74     }
  75
  76     s->address    = ADDR_RESET;
  77     s->iadr       = IADR_RESET;
  78     s->ifdr       = IFDR_RESET;
  79     s->i2cr       = I2CR_RESET;
  80     s->i2sr       = I2SR_RESET;
  81     s->i2dr_read  = I2DR_RESET;
  82     s->i2dr_write = I2DR_RESET;
  83 }
  84
  85 static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
  86 {
  87     /*
  88      * raise an interrupt if the device is enabled and it is configured
  89      * to generate some interrupts.
  90      */
  91     if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
  92         s->i2sr |= I2SR_IIF;
  93         qemu_irq_raise(s->irq);
  94     }
  95 }
  96
  97 static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
  98                              unsigned size)
  99 {
 100     uint16_t value;
 101     IMXI2CState *s = IMX_I2C(opaque);
 102
 103     switch (offset) {
 104     case IADR_ADDR:
 105         value = s->iadr;
 106         break;
 107     case IFDR_ADDR:
 108         value = s->ifdr;
 109         break;
 110     case I2CR_ADDR:
 111         value = s->i2cr;
 112         break;
 113     case I2SR_ADDR:
 114         value = s->i2sr;
 115         break;
 116     case I2DR_ADDR:
 117         value = s->i2dr_read;
 118
 119         if (imx_i2c_is_master(s)) {
 120             int ret = 0xff;
 121
 122             if (s->address == ADDR_RESET) {
 123                 /* something is wrong as the address is not set */
 124                 qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Trying to read "
 125                               "without specifying the slave address\n",
 126                               TYPE_IMX_I2C, __func__);
 127             } else if (s->i2cr & I2CR_MTX) {
 128                 qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Trying to read "
 129                               "but MTX is set\n", TYPE_IMX_I2C, __func__);
 130             } else {
 131                 /* get the next byte */
 132                 ret = i2c_recv(s->bus);
 133
 134                 if (ret >= 0) {
 135                     imx_i2c_raise_interrupt(s);
 136                 } else {
 137                     qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: read failed "
 138                                   "for device 0x%02x\n", TYPE_IMX_I2C,
 139                                   __func__, s->address);
 140                     ret = 0xff;
 141                 }
 142             }
 143
 144             s->i2dr_read = ret;
 145         } else {
 146             qemu_log_mask(LOG_UNIMP, "%s[%s]: slave mode not implemented\n",
 147                           TYPE_IMX_I2C, __func__);
 148         }
 149         break;
 150     default:
 151         qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
 152                       TYPE_IMX_I2C, __func__, s->address);
 153         value = 0;
 154         break;
 155     }
 156
 157     DPRINT("read %s [0x%02x] -> 0x%02x\n", imx_i2c_get_regname(offset),
 158            (unsigned int)offset, value);
 159
 160     return (uint64_t)value;
 161 }
 162
 163 static void imx_i2c_write(void *opaque, hwaddr offset,
 164                           uint64_t value, unsigned size)
 165 {
 166     IMXI2CState *s = IMX_I2C(opaque);
 167
 168     DPRINT("write %s [0x%02x] <- 0x%02x\n", imx_i2c_get_regname(offset),
 169            (unsigned int)offset, (int)value);
 170
 171     value &= 0xff;
 172
 173     switch (offset) {
 174     case IADR_ADDR:
 175         s->iadr = value & IADR_MASK;
 176         /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
 177         break;
 178     case IFDR_ADDR:
 179         s->ifdr = value & IFDR_MASK;
 180         break;
 181     case I2CR_ADDR:
 182         if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
 183             /* This is a soft reset. IADR is preserved during soft resets */
 184             uint16_t iadr = s->iadr;
 185             imx_i2c_reset(DEVICE(s));
 186             s->iadr = iadr;
 187         } else { /* normal write */
 188             s->i2cr = value & I2CR_MASK;
 189
 190             if (imx_i2c_is_master(s)) {
 191                 /* set the bus to busy */
 192                 s->i2sr |= I2SR_IBB;
 193             } else { /* slave mode */
 194                 /* bus is not busy anymore */
 195                 s->i2sr &= ~I2SR_IBB;
 196
 197                 /*
 198                  * if we unset the master mode then it ends the ongoing
 199                  * transfer if any
 200                  */
 201                 if (s->address != ADDR_RESET) {
 202                     i2c_end_transfer(s->bus);
 203                     s->address = ADDR_RESET;
 204                 }
 205             }
 206
 207             if (s->i2cr & I2CR_RSTA) { /* Restart */
 208                 /* if this is a restart then it ends the ongoing transfer */
 209                 if (s->address != ADDR_RESET) {
 210                     i2c_end_transfer(s->bus);
 211                     s->address = ADDR_RESET;
 212                     s->i2cr &= ~I2CR_RSTA;
 213                 }
 214             }
 215         }
 216         break;
 217     case I2SR_ADDR:
 218         /*
 219          * if the user writes 0 to IIF then lower the interrupt and
 220          * reset the bit
 221          */
 222         if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
 223             s->i2sr &= ~I2SR_IIF;
 224             qemu_irq_lower(s->irq);
 225         }
 226
 227         /*
 228          * if the user writes 0 to IAL, reset the bit
 229          */
 230         if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
 231             s->i2sr &= ~I2SR_IAL;
 232         }
 233
 234         break;
 235     case I2DR_ADDR:
 236         /* if the device is not enabled, nothing to do */
 237         if (!imx_i2c_is_enabled(s)) {
 238             break;
 239         }
 240
 241         s->i2dr_write = value & I2DR_MASK;
 242
 243         if (imx_i2c_is_master(s)) {
 244             /* If this is the first write cycle then it is the slave addr */
 245             if (s->address == ADDR_RESET) {
 246                 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
 247                                        extract32(s->i2dr_write, 0, 1))) {
 248                     /* if non zero is returned, the adress is not valid */
 249                     s->i2sr |= I2SR_RXAK;
 250                 } else {
 251                     s->address = s->i2dr_write;
 252                     s->i2sr &= ~I2SR_RXAK;
 253                     imx_i2c_raise_interrupt(s);
 254                 }
 255             } else { /* This is a normal data write */
 256                 if (i2c_send(s->bus, s->i2dr_write)) {
 257                     /* if the target return non zero then end the transfer */
 258                     s->i2sr |= I2SR_RXAK;
 259                     s->address = ADDR_RESET;
 260                     i2c_end_transfer(s->bus);
 261                 } else {
 262                     s->i2sr &= ~I2SR_RXAK;
 263                     imx_i2c_raise_interrupt(s);
 264                 }
 265             }
 266         } else {
 267             qemu_log_mask(LOG_UNIMP, "%s[%s]: slave mode not implemented\n",
 268                           TYPE_IMX_I2C, __func__);
 269         }
 270         break;
 271     default:
 272         qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
 273                       TYPE_IMX_I2C, __func__, s->address);
 274         break;
 275     }
 276 }
 277
 278 static const MemoryRegionOps imx_i2c_ops = {
 279     .read = imx_i2c_read,
 280     .write = imx_i2c_write,
 281     .valid.min_access_size = 1,
 282     .valid.max_access_size = 2,
 283     .endianness = DEVICE_NATIVE_ENDIAN,
 284 };
 285
 286 static const VMStateDescription imx_i2c_vmstate = {
 287     .name = TYPE_IMX_I2C,
 288     .version_id = 1,
 289     .minimum_version_id = 1,
 290     .fields = (VMStateField[]) {
 291         VMSTATE_UINT16(address, IMXI2CState),
 292         VMSTATE_UINT16(iadr, IMXI2CState),
 293         VMSTATE_UINT16(ifdr, IMXI2CState),
 294         VMSTATE_UINT16(i2cr, IMXI2CState),
 295         VMSTATE_UINT16(i2sr, IMXI2CState),
 296         VMSTATE_UINT16(i2dr_read, IMXI2CState),
 297         VMSTATE_UINT16(i2dr_write, IMXI2CState),
 298         VMSTATE_END_OF_LIST()
 299     }
 300 };
 301
 302 static void imx_i2c_realize(DeviceState *dev, Error **errp)
 303 {
 304     IMXI2CState *s = IMX_I2C(dev);
 305
 306     memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
 307                           IMX_I2C_MEM_SIZE);
 308     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 309     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 310     s->bus = i2c_init_bus(DEVICE(dev), "i2c");
 311 }
 312
 313 static void imx_i2c_class_init(ObjectClass *klass, void *data)
 314 {
 315     DeviceClass *dc = DEVICE_CLASS(klass);
 316
 317     dc->vmsd = &imx_i2c_vmstate;
 318     dc->reset = imx_i2c_reset;
 319     dc->realize = imx_i2c_realize;
 320 }
 321
 322 static const TypeInfo imx_i2c_type_info = {
 323     .name = TYPE_IMX_I2C,
 324     .parent = TYPE_SYS_BUS_DEVICE,
 325     .instance_size = sizeof(IMXI2CState),
 326     .class_init = imx_i2c_class_init,
 327 };
 328
 329 static void imx_i2c_register_types(void)
 330 {
 331     type_register_static(&imx_i2c_type_info);
 332 }
 333
 334 type_init(imx_i2c_register_types)