2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * - See TODO comments in code.
29 /* Marker for missing code. */
32 fprintf(stderr, "TODO %s:%u: %s()\n", \
33 __FILE__, __LINE__, __func__); \
37 /* Bitfield n...m (in 32 bit value). */
38 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
40 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
43 case INDEX_op_ld8u_i32:
44 case INDEX_op_ld8s_i32:
45 case INDEX_op_ld16u_i32:
46 case INDEX_op_ld16s_i32:
48 case INDEX_op_ld8u_i64:
49 case INDEX_op_ld8s_i64:
50 case INDEX_op_ld16u_i64:
51 case INDEX_op_ld16s_i64:
52 case INDEX_op_ld32u_i64:
53 case INDEX_op_ld32s_i64:
55 case INDEX_op_not_i32:
56 case INDEX_op_not_i64:
57 case INDEX_op_neg_i32:
58 case INDEX_op_neg_i64:
59 case INDEX_op_ext8s_i32:
60 case INDEX_op_ext8s_i64:
61 case INDEX_op_ext16s_i32:
62 case INDEX_op_ext16s_i64:
63 case INDEX_op_ext8u_i32:
64 case INDEX_op_ext8u_i64:
65 case INDEX_op_ext16u_i32:
66 case INDEX_op_ext16u_i64:
67 case INDEX_op_ext32s_i64:
68 case INDEX_op_ext32u_i64:
69 case INDEX_op_ext_i32_i64:
70 case INDEX_op_extu_i32_i64:
71 case INDEX_op_bswap16_i32:
72 case INDEX_op_bswap16_i64:
73 case INDEX_op_bswap32_i32:
74 case INDEX_op_bswap32_i64:
75 case INDEX_op_bswap64_i64:
78 case INDEX_op_st8_i32:
79 case INDEX_op_st16_i32:
81 case INDEX_op_st8_i64:
82 case INDEX_op_st16_i64:
83 case INDEX_op_st32_i64:
87 case INDEX_op_div_i32:
88 case INDEX_op_div_i64:
89 case INDEX_op_divu_i32:
90 case INDEX_op_divu_i64:
91 case INDEX_op_rem_i32:
92 case INDEX_op_rem_i64:
93 case INDEX_op_remu_i32:
94 case INDEX_op_remu_i64:
95 case INDEX_op_add_i32:
96 case INDEX_op_add_i64:
97 case INDEX_op_sub_i32:
98 case INDEX_op_sub_i64:
99 case INDEX_op_mul_i32:
100 case INDEX_op_mul_i64:
101 case INDEX_op_and_i32:
102 case INDEX_op_and_i64:
103 case INDEX_op_andc_i32:
104 case INDEX_op_andc_i64:
105 case INDEX_op_eqv_i32:
106 case INDEX_op_eqv_i64:
107 case INDEX_op_nand_i32:
108 case INDEX_op_nand_i64:
109 case INDEX_op_nor_i32:
110 case INDEX_op_nor_i64:
111 case INDEX_op_or_i32:
112 case INDEX_op_or_i64:
113 case INDEX_op_orc_i32:
114 case INDEX_op_orc_i64:
115 case INDEX_op_xor_i32:
116 case INDEX_op_xor_i64:
117 case INDEX_op_shl_i32:
118 case INDEX_op_shl_i64:
119 case INDEX_op_shr_i32:
120 case INDEX_op_shr_i64:
121 case INDEX_op_sar_i32:
122 case INDEX_op_sar_i64:
123 case INDEX_op_rotl_i32:
124 case INDEX_op_rotl_i64:
125 case INDEX_op_rotr_i32:
126 case INDEX_op_rotr_i64:
127 case INDEX_op_setcond_i32:
128 case INDEX_op_setcond_i64:
129 case INDEX_op_deposit_i32:
130 case INDEX_op_deposit_i64:
131 return C_O1_I2(r, r, r);
133 case INDEX_op_brcond_i32:
134 case INDEX_op_brcond_i64:
135 return C_O0_I2(r, r);
137 #if TCG_TARGET_REG_BITS == 32
138 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
139 case INDEX_op_add2_i32:
140 case INDEX_op_sub2_i32:
141 return C_O2_I4(r, r, r, r, r, r);
142 case INDEX_op_brcond2_i32:
143 return C_O0_I4(r, r, r, r);
144 case INDEX_op_mulu2_i32:
145 return C_O2_I2(r, r, r, r);
146 case INDEX_op_setcond2_i32:
147 return C_O1_I4(r, r, r, r, r);
150 case INDEX_op_qemu_ld_i32:
151 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
154 case INDEX_op_qemu_ld_i64:
155 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
156 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r)
157 : C_O2_I2(r, r, r, r));
158 case INDEX_op_qemu_st_i32:
159 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
162 case INDEX_op_qemu_st_i64:
163 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
164 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r)
165 : C_O0_I4(r, r, r, r));
168 g_assert_not_reached();
172 static const int tcg_target_reg_alloc_order[] = {
191 #if MAX_OPC_PARAM_IARGS != 6
192 # error Fix needed, number of supported input arguments changed!
195 static const int tcg_target_call_iarg_regs[] = {
202 #if TCG_TARGET_REG_BITS == 32
203 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
213 static const int tcg_target_call_oarg_regs[] = {
215 #if TCG_TARGET_REG_BITS == 32
220 #ifdef CONFIG_DEBUG_TCG
221 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
241 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
242 intptr_t value, intptr_t addend)
244 /* tcg_out_reloc always uses the same type, addend. */
245 tcg_debug_assert(type == sizeof(tcg_target_long));
246 tcg_debug_assert(addend == 0);
247 tcg_debug_assert(value != 0);
248 if (TCG_TARGET_REG_BITS == 32) {
249 tcg_patch32(code_ptr, value);
251 tcg_patch64(code_ptr, value);
256 /* Write value (native size). */
257 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
259 if (TCG_TARGET_REG_BITS == 32) {
267 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
273 /* Write register. */
274 static void tcg_out_r(TCGContext *s, TCGArg t0)
276 tcg_debug_assert(t0 < TCG_TARGET_NB_REGS);
281 static void tci_out_label(TCGContext *s, TCGLabel *label)
283 if (label->has_value) {
284 tcg_out_i(s, label->u.value);
285 tcg_debug_assert(label->u.value);
287 tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
288 s->code_ptr += sizeof(tcg_target_ulong);
292 static void stack_bounds_check(TCGReg base, target_long offset)
294 if (base == TCG_REG_CALL_STACK) {
295 tcg_debug_assert(offset < 0);
296 tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long)));
300 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0)
302 uint8_t *old_code_ptr = s->code_ptr;
305 tci_out_label(s, l0);
307 old_code_ptr[1] = s->code_ptr - old_code_ptr;
310 static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
312 uint8_t *old_code_ptr = s->code_ptr;
315 tcg_out_i(s, (uintptr_t)p0);
317 old_code_ptr[1] = s->code_ptr - old_code_ptr;
320 static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
322 uint8_t *old_code_ptr = s->code_ptr;
326 old_code_ptr[1] = s->code_ptr - old_code_ptr;
329 static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1)
331 uint8_t *old_code_ptr = s->code_ptr;
337 old_code_ptr[1] = s->code_ptr - old_code_ptr;
340 #if TCG_TARGET_REG_BITS == 64
341 static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
342 TCGReg r0, uint64_t i1)
344 uint8_t *old_code_ptr = s->code_ptr;
350 old_code_ptr[1] = s->code_ptr - old_code_ptr;
354 static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
356 uint8_t *old_code_ptr = s->code_ptr;
362 old_code_ptr[1] = s->code_ptr - old_code_ptr;
365 static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op,
366 TCGReg r0, TCGReg r1, TCGArg m2)
368 uint8_t *old_code_ptr = s->code_ptr;
375 old_code_ptr[1] = s->code_ptr - old_code_ptr;
378 static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op,
379 TCGReg r0, TCGReg r1, TCGReg r2)
381 uint8_t *old_code_ptr = s->code_ptr;
388 old_code_ptr[1] = s->code_ptr - old_code_ptr;
391 static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
392 TCGReg r0, TCGReg r1, intptr_t i2)
394 uint8_t *old_code_ptr = s->code_ptr;
399 tcg_debug_assert(i2 == (int32_t)i2);
402 old_code_ptr[1] = s->code_ptr - old_code_ptr;
405 static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op,
406 TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3)
408 uint8_t *old_code_ptr = s->code_ptr;
414 tci_out_label(s, l3);
416 old_code_ptr[1] = s->code_ptr - old_code_ptr;
419 static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
420 TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
422 uint8_t *old_code_ptr = s->code_ptr;
430 old_code_ptr[1] = s->code_ptr - old_code_ptr;
433 static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op,
434 TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3)
436 uint8_t *old_code_ptr = s->code_ptr;
444 old_code_ptr[1] = s->code_ptr - old_code_ptr;
447 static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
448 TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
450 uint8_t *old_code_ptr = s->code_ptr;
459 old_code_ptr[1] = s->code_ptr - old_code_ptr;
462 static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0,
463 TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4)
465 uint8_t *old_code_ptr = s->code_ptr;
474 old_code_ptr[1] = s->code_ptr - old_code_ptr;
477 #if TCG_TARGET_REG_BITS == 32
478 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
479 TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
481 uint8_t *old_code_ptr = s->code_ptr;
489 old_code_ptr[1] = s->code_ptr - old_code_ptr;
492 static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op,
493 TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3,
494 TCGCond c4, TCGLabel *l5)
496 uint8_t *old_code_ptr = s->code_ptr;
504 tci_out_label(s, l5);
506 old_code_ptr[1] = s->code_ptr - old_code_ptr;
509 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
510 TCGReg r0, TCGReg r1, TCGReg r2,
511 TCGReg r3, TCGReg r4, TCGCond c5)
513 uint8_t *old_code_ptr = s->code_ptr;
523 old_code_ptr[1] = s->code_ptr - old_code_ptr;
526 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
527 TCGReg r0, TCGReg r1, TCGReg r2,
528 TCGReg r3, TCGReg r4, TCGReg r5)
530 uint8_t *old_code_ptr = s->code_ptr;
540 old_code_ptr[1] = s->code_ptr - old_code_ptr;
544 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
547 stack_bounds_check(base, offset);
550 tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset);
552 #if TCG_TARGET_REG_BITS == 64
554 tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset);
558 g_assert_not_reached();
562 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
566 tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg);
568 #if TCG_TARGET_REG_BITS == 64
570 tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg);
574 g_assert_not_reached();
579 static void tcg_out_movi(TCGContext *s, TCGType type,
580 TCGReg ret, tcg_target_long arg)
584 tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg);
586 #if TCG_TARGET_REG_BITS == 64
588 tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg);
592 g_assert_not_reached();
596 static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
598 uint8_t *old_code_ptr = s->code_ptr;
599 tcg_out_op_t(s, INDEX_op_call);
600 tcg_out_i(s, (uintptr_t)arg);
601 old_code_ptr[1] = s->code_ptr - old_code_ptr;
604 #if TCG_TARGET_REG_BITS == 64
605 # define CASE_32_64(x) \
606 case glue(glue(INDEX_op_, x), _i64): \
607 case glue(glue(INDEX_op_, x), _i32):
608 # define CASE_64(x) \
609 case glue(glue(INDEX_op_, x), _i64):
611 # define CASE_32_64(x) \
612 case glue(glue(INDEX_op_, x), _i32):
616 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
617 const TCGArg args[TCG_MAX_OP_ARGS],
618 const int const_args[TCG_MAX_OP_ARGS])
621 case INDEX_op_exit_tb:
622 tcg_out_op_p(s, opc, (void *)args[0]);
625 case INDEX_op_goto_tb:
626 tcg_debug_assert(s->tb_jmp_insn_offset == 0);
627 /* indirect jump method. */
628 tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]);
629 set_jmp_reset_offset(s, args[0]);
633 tcg_out_op_l(s, opc, arg_label(args[0]));
637 tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]);
640 #if TCG_TARGET_REG_BITS == 32
641 case INDEX_op_setcond2_i32:
642 tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2],
643 args[3], args[4], args[5]);
651 case INDEX_op_ld_i32:
657 case INDEX_op_st_i32:
660 stack_bounds_check(args[1], args[2]);
661 tcg_out_op_rrs(s, opc, args[0], args[1], args[2]);
670 CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */
671 CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
672 CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
673 CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
674 CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */
678 CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */
679 CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */
680 CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */
681 CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
682 CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
683 CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
684 tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
687 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
689 TCGArg pos = args[3], len = args[4];
690 TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64;
692 tcg_debug_assert(pos < max);
693 tcg_debug_assert(pos + len <= max);
695 tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len);
700 tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3]));
703 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
704 CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
705 CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */
706 CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */
707 CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */
708 CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */
709 CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */
710 CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */
713 CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
714 CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
715 CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
716 tcg_out_op_rr(s, opc, args[0], args[1]);
719 #if TCG_TARGET_REG_BITS == 32
720 case INDEX_op_add2_i32:
721 case INDEX_op_sub2_i32:
722 tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
723 args[3], args[4], args[5]);
725 case INDEX_op_brcond2_i32:
726 tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2],
727 args[3], args[4], arg_label(args[5]));
729 case INDEX_op_mulu2_i32:
730 tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
734 case INDEX_op_qemu_ld_i32:
735 case INDEX_op_qemu_st_i32:
736 if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
737 tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
739 tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
743 case INDEX_op_qemu_ld_i64:
744 case INDEX_op_qemu_st_i64:
745 if (TCG_TARGET_REG_BITS == 64) {
746 tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
747 } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
748 tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
750 tcg_out_op_rrrrm(s, opc, args[0], args[1],
751 args[2], args[3], args[4]);
756 tcg_out_op_v(s, opc);
759 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
760 case INDEX_op_mov_i64:
761 case INDEX_op_call: /* Always emitted via tcg_out_call. */
767 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
770 stack_bounds_check(base, offset);
773 tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset);
775 #if TCG_TARGET_REG_BITS == 64
777 tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset);
781 g_assert_not_reached();
785 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
786 TCGReg base, intptr_t ofs)
791 /* Test if a constant matches the constraint. */
792 static int tcg_target_const_match(tcg_target_long val, TCGType type,
793 const TCGArgConstraint *arg_ct)
795 /* No need to return 0 or 1, 0 or != 0 is good enough. */
796 return arg_ct->ct & TCG_CT_CONST;
799 static void tcg_target_init(TCGContext *s)
801 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
802 const char *envval = getenv("DEBUG_TCG");
804 qemu_set_log(strtol(envval, NULL, 0));
808 /* The current code uses uint8_t for tcg operations. */
809 tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX);
811 /* Registers available for 32 bit operations. */
812 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
813 /* Registers available for 64 bit operations. */
814 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
815 /* TODO: Which registers should be set here? */
816 tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;
818 s->reserved_regs = 0;
819 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
821 /* We use negative offsets from "sp" so that we can distinguish
822 stores that might pretend to be call arguments. */
823 tcg_set_frame(s, TCG_REG_CALL_STACK,
824 -CPU_TEMP_BUF_NLONGS * sizeof(long),
825 CPU_TEMP_BUF_NLONGS * sizeof(long));
828 /* Generate global QEMU prologue and epilogue code. */
829 static inline void tcg_target_qemu_prologue(TCGContext *s)