spapr: Simplify error handling in spapr_cpu_core_realize()
[qemu/ar7.git] / hw / intc / ompic.c
blob1731a1068385c66bf6a37f5bfafba249f653a6e9
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Authors: Stafford Horne <shorne@gmail.com>
7 */
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "qemu/module.h"
12 #include "qapi/error.h"
13 #include "hw/irq.h"
14 #include "hw/qdev-properties.h"
15 #include "hw/sysbus.h"
16 #include "migration/vmstate.h"
17 #include "exec/memory.h"
18 #include "qom/object.h"
20 #define TYPE_OR1K_OMPIC "or1k-ompic"
21 OBJECT_DECLARE_SIMPLE_TYPE(OR1KOMPICState, OR1K_OMPIC)
23 #define OMPIC_CTRL_IRQ_ACK (1 << 31)
24 #define OMPIC_CTRL_IRQ_GEN (1 << 30)
25 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff)
27 #define OMPIC_REG(addr) (((addr) >> 2) & 0x1)
28 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f)
29 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f)
31 #define OMPIC_STATUS_IRQ_PENDING (1 << 30)
32 #define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16)
33 #define OMPIC_STATUS_DATA(data) ((data) & 0xffff)
35 #define OMPIC_CONTROL 0
36 #define OMPIC_STATUS 1
38 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */
39 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */
41 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState;
43 struct OR1KOMPICCPUState {
44 qemu_irq irq;
45 uint32_t status;
46 uint32_t control;
49 struct OR1KOMPICState {
50 SysBusDevice parent_obj;
51 MemoryRegion mr;
53 OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS];
55 uint32_t num_cpus;
58 static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size)
60 OR1KOMPICState *s = opaque;
61 int src_cpu = OMPIC_SRC_CPU(addr);
63 /* We can only write to control control, write control + update status */
64 if (OMPIC_REG(addr) == OMPIC_CONTROL) {
65 return s->cpus[src_cpu].control;
66 } else {
67 return s->cpus[src_cpu].status;
72 static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
74 OR1KOMPICState *s = opaque;
75 /* We can only write to control control, write control + update status */
76 if (OMPIC_REG(addr) == OMPIC_CONTROL) {
77 int src_cpu = OMPIC_SRC_CPU(addr);
79 s->cpus[src_cpu].control = data;
81 if (data & OMPIC_CTRL_IRQ_GEN) {
82 int dst_cpu = OMPIC_CTRL_DST(data);
84 s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING |
85 OMPIC_STATUS_SRC(src_cpu) |
86 OMPIC_STATUS_DATA(data);
88 qemu_irq_raise(s->cpus[dst_cpu].irq);
90 if (data & OMPIC_CTRL_IRQ_ACK) {
91 s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING;
92 qemu_irq_lower(s->cpus[src_cpu].irq);
97 static const MemoryRegionOps ompic_ops = {
98 .read = ompic_read,
99 .write = ompic_write,
100 .endianness = DEVICE_NATIVE_ENDIAN,
101 .impl = {
102 .max_access_size = 8,
106 static void or1k_ompic_init(Object *obj)
108 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
109 OR1KOMPICState *s = OR1K_OMPIC(obj);
111 memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s,
112 "or1k-ompic", OMPIC_ADDRSPACE_SZ);
113 sysbus_init_mmio(sbd, &s->mr);
116 static void or1k_ompic_realize(DeviceState *dev, Error **errp)
118 OR1KOMPICState *s = OR1K_OMPIC(dev);
119 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
120 int i;
122 if (s->num_cpus > OMPIC_MAX_CPUS) {
123 error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus);
124 return;
126 /* Init IRQ sources for all CPUs */
127 for (i = 0; i < s->num_cpus; i++) {
128 sysbus_init_irq(sbd, &s->cpus[i].irq);
132 static Property or1k_ompic_properties[] = {
133 DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1),
134 DEFINE_PROP_END_OF_LIST(),
137 static const VMStateDescription vmstate_or1k_ompic_cpu = {
138 .name = "or1k_ompic_cpu",
139 .version_id = 1,
140 .minimum_version_id = 1,
141 .fields = (VMStateField[]) {
142 VMSTATE_UINT32(status, OR1KOMPICCPUState),
143 VMSTATE_UINT32(control, OR1KOMPICCPUState),
144 VMSTATE_END_OF_LIST()
148 static const VMStateDescription vmstate_or1k_ompic = {
149 .name = TYPE_OR1K_OMPIC,
150 .version_id = 1,
151 .minimum_version_id = 1,
152 .fields = (VMStateField[]) {
153 VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1,
154 vmstate_or1k_ompic_cpu, OR1KOMPICCPUState),
155 VMSTATE_UINT32(num_cpus, OR1KOMPICState),
156 VMSTATE_END_OF_LIST()
160 static void or1k_ompic_class_init(ObjectClass *klass, void *data)
162 DeviceClass *dc = DEVICE_CLASS(klass);
164 device_class_set_props(dc, or1k_ompic_properties);
165 dc->realize = or1k_ompic_realize;
166 dc->vmsd = &vmstate_or1k_ompic;
169 static const TypeInfo or1k_ompic_info = {
170 .name = TYPE_OR1K_OMPIC,
171 .parent = TYPE_SYS_BUS_DEVICE,
172 .instance_size = sizeof(OR1KOMPICState),
173 .instance_init = or1k_ompic_init,
174 .class_init = or1k_ompic_class_init,
177 static void or1k_ompic_register_types(void)
179 type_register_static(&or1k_ompic_info);
182 type_init(or1k_ompic_register_types)