2 * Faraday FTGMAC100 Gigabit Ethernet
4 * Copyright (C) 2016-2017, IBM Corporation.
6 * Based on Coldfire Fast Ethernet Controller emulation.
8 * Copyright (c) 2007 CodeSourcery.
10 * This code is licensed under the GPL version 2 or later. See the
11 * COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
15 #include "hw/net/ftgmac100.h"
16 #include "sysemu/dma.h"
18 #include "qemu/module.h"
19 #include "net/checksum.h"
21 #include "hw/net/mii.h"
29 #define FTGMAC100_ISR 0x00
30 #define FTGMAC100_IER 0x04
31 #define FTGMAC100_MAC_MADR 0x08
32 #define FTGMAC100_MAC_LADR 0x0c
33 #define FTGMAC100_MATH0 0x10
34 #define FTGMAC100_MATH1 0x14
35 #define FTGMAC100_NPTXPD 0x18
36 #define FTGMAC100_RXPD 0x1C
37 #define FTGMAC100_NPTXR_BADR 0x20
38 #define FTGMAC100_RXR_BADR 0x24
39 #define FTGMAC100_HPTXPD 0x28
40 #define FTGMAC100_HPTXR_BADR 0x2c
41 #define FTGMAC100_ITC 0x30
42 #define FTGMAC100_APTC 0x34
43 #define FTGMAC100_DBLAC 0x38
44 #define FTGMAC100_REVR 0x40
45 #define FTGMAC100_FEAR1 0x44
46 #define FTGMAC100_RBSR 0x4c
47 #define FTGMAC100_TPAFCR 0x48
49 #define FTGMAC100_MACCR 0x50
50 #define FTGMAC100_MACSR 0x54
51 #define FTGMAC100_PHYCR 0x60
52 #define FTGMAC100_PHYDATA 0x64
53 #define FTGMAC100_FCR 0x68
56 * Interrupt status register & interrupt enable register
58 #define FTGMAC100_INT_RPKT_BUF (1 << 0)
59 #define FTGMAC100_INT_RPKT_FIFO (1 << 1)
60 #define FTGMAC100_INT_NO_RXBUF (1 << 2)
61 #define FTGMAC100_INT_RPKT_LOST (1 << 3)
62 #define FTGMAC100_INT_XPKT_ETH (1 << 4)
63 #define FTGMAC100_INT_XPKT_FIFO (1 << 5)
64 #define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
65 #define FTGMAC100_INT_XPKT_LOST (1 << 7)
66 #define FTGMAC100_INT_AHB_ERR (1 << 8)
67 #define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
68 #define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
71 * Automatic polling timer control register
73 #define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf)
74 #define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
75 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf)
76 #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
79 * PHY control register
81 #define FTGMAC100_PHYCR_MIIRD (1 << 26)
82 #define FTGMAC100_PHYCR_MIIWR (1 << 27)
84 #define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f)
85 #define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f)
90 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
91 #define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff)
94 * PHY control register - New MDC/MDIO interface
96 #define FTGMAC100_PHYCR_NEW_DATA(x) (((x) >> 16) & 0xffff)
97 #define FTGMAC100_PHYCR_NEW_FIRE (1 << 15)
98 #define FTGMAC100_PHYCR_NEW_ST_22 (1 << 12)
99 #define FTGMAC100_PHYCR_NEW_OP(x) (((x) >> 10) & 3)
100 #define FTGMAC100_PHYCR_NEW_OP_WRITE 0x1
101 #define FTGMAC100_PHYCR_NEW_OP_READ 0x2
102 #define FTGMAC100_PHYCR_NEW_DEV(x) (((x) >> 5) & 0x1f)
103 #define FTGMAC100_PHYCR_NEW_REG(x) ((x) & 0x1f)
108 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31)
111 * MAC control register
113 #define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
114 #define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
115 #define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
116 #define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
117 #define FTGMAC100_MACCR_RM_VLAN (1 << 4)
118 #define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
119 #define FTGMAC100_MACCR_LOOP_EN (1 << 6)
120 #define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
121 #define FTGMAC100_MACCR_FULLDUP (1 << 8)
122 #define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
123 #define FTGMAC100_MACCR_CRC_APD (1 << 10) /* not needed */
124 #define FTGMAC100_MACCR_RX_RUNT (1 << 12)
125 #define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
126 #define FTGMAC100_MACCR_RX_ALL (1 << 14)
127 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
128 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
129 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
130 #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
131 #define FTGMAC100_MACCR_FAST_MODE (1 << 19)
132 #define FTGMAC100_MACCR_SW_RST (1 << 31)
135 * Transmit descriptor
137 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
138 #define FTGMAC100_TXDES0_EDOTR (1 << 15)
139 #define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
140 #define FTGMAC100_TXDES0_LTS (1 << 28)
141 #define FTGMAC100_TXDES0_FTS (1 << 29)
142 #define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30)
143 #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
145 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
146 #define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
147 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
148 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
149 #define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
150 #define FTGMAC100_TXDES1_LLC (1 << 22)
151 #define FTGMAC100_TXDES1_TX2FIC (1 << 30)
152 #define FTGMAC100_TXDES1_TXIC (1 << 31)
157 #define FTGMAC100_RXDES0_VDBC 0x3fff
158 #define FTGMAC100_RXDES0_EDORR (1 << 15)
159 #define FTGMAC100_RXDES0_MULTICAST (1 << 16)
160 #define FTGMAC100_RXDES0_BROADCAST (1 << 17)
161 #define FTGMAC100_RXDES0_RX_ERR (1 << 18)
162 #define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
163 #define FTGMAC100_RXDES0_FTL (1 << 20)
164 #define FTGMAC100_RXDES0_RUNT (1 << 21)
165 #define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
166 #define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
167 #define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
168 #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
169 #define FTGMAC100_RXDES0_LRS (1 << 28)
170 #define FTGMAC100_RXDES0_FRS (1 << 29)
171 #define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30)
172 #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
174 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
175 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
176 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
177 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
178 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
179 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
180 #define FTGMAC100_RXDES1_LLC (1 << 22)
181 #define FTGMAC100_RXDES1_DF (1 << 23)
182 #define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
183 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
184 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
185 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
188 * Receive and transmit Buffer Descriptor
193 uint32_t des2
; /* not used by HW */
198 * Specific RTL8211E MII Registers
200 #define RTL8211E_MII_PHYCR 16 /* PHY Specific Control */
201 #define RTL8211E_MII_PHYSR 17 /* PHY Specific Status */
202 #define RTL8211E_MII_INER 18 /* Interrupt Enable */
203 #define RTL8211E_MII_INSR 19 /* Interrupt Status */
204 #define RTL8211E_MII_RXERC 24 /* Receive Error Counter */
205 #define RTL8211E_MII_LDPSR 27 /* Link Down Power Saving */
206 #define RTL8211E_MII_EPAGSR 30 /* Extension Page Select */
207 #define RTL8211E_MII_PAGSEL 31 /* Page Select */
210 * RTL8211E Interrupt Status
212 #define PHY_INT_AUTONEG_ERROR (1 << 15)
213 #define PHY_INT_PAGE_RECV (1 << 12)
214 #define PHY_INT_AUTONEG_COMPLETE (1 << 11)
215 #define PHY_INT_LINK_STATUS (1 << 10)
216 #define PHY_INT_ERROR (1 << 9)
217 #define PHY_INT_DOWN (1 << 8)
218 #define PHY_INT_JABBER (1 << 0)
221 * Max frame size for the receiving buffer
223 #define FTGMAC100_MAX_FRAME_SIZE 9220
225 /* Limits depending on the type of the frame
227 * 9216 for Jumbo frames (+ 4 for VLAN)
228 * 1518 for other frames (+ 4 for VLAN)
230 static int ftgmac100_max_frame_size(FTGMAC100State
*s
, uint16_t proto
)
232 int max
= (s
->maccr
& FTGMAC100_MACCR_JUMBO_LF
? 9216 : 1518);
234 return max
+ (proto
== ETH_P_VLAN
? 4 : 0);
237 static void ftgmac100_update_irq(FTGMAC100State
*s
)
239 qemu_set_irq(s
->irq
, s
->isr
& s
->ier
);
243 * The MII phy could raise a GPIO to the processor which in turn
244 * could be handled as an interrpt by the OS.
245 * For now we don't handle any GPIO/interrupt line, so the OS will
246 * have to poll for the PHY status.
248 static void phy_update_irq(FTGMAC100State
*s
)
250 ftgmac100_update_irq(s
);
253 static void phy_update_link(FTGMAC100State
*s
)
255 /* Autonegotiation status mirrors link status. */
256 if (qemu_get_queue(s
->nic
)->link_down
) {
257 s
->phy_status
&= ~(MII_BMSR_LINK_ST
| MII_BMSR_AN_COMP
);
258 s
->phy_int
|= PHY_INT_DOWN
;
260 s
->phy_status
|= (MII_BMSR_LINK_ST
| MII_BMSR_AN_COMP
);
261 s
->phy_int
|= PHY_INT_AUTONEG_COMPLETE
;
266 static void ftgmac100_set_link(NetClientState
*nc
)
268 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc
)));
271 static void phy_reset(FTGMAC100State
*s
)
273 s
->phy_status
= (MII_BMSR_100TX_FD
| MII_BMSR_100TX_HD
| MII_BMSR_10T_FD
|
274 MII_BMSR_10T_HD
| MII_BMSR_EXTSTAT
| MII_BMSR_MFPS
|
275 MII_BMSR_AN_COMP
| MII_BMSR_AUTONEG
| MII_BMSR_LINK_ST
|
277 s
->phy_control
= (MII_BMCR_AUTOEN
| MII_BMCR_FD
| MII_BMCR_SPEED1000
);
278 s
->phy_advertise
= (MII_ANAR_PAUSE_ASYM
| MII_ANAR_PAUSE
| MII_ANAR_TXFD
|
279 MII_ANAR_TX
| MII_ANAR_10FD
| MII_ANAR_10
|
285 static uint16_t do_phy_read(FTGMAC100State
*s
, uint8_t reg
)
290 case MII_BMCR
: /* Basic Control */
291 val
= s
->phy_control
;
293 case MII_BMSR
: /* Basic Status */
296 case MII_PHYID1
: /* ID1 */
297 val
= RTL8211E_PHYID1
;
299 case MII_PHYID2
: /* ID2 */
300 val
= RTL8211E_PHYID2
;
302 case MII_ANAR
: /* Auto-neg advertisement */
303 val
= s
->phy_advertise
;
305 case MII_ANLPAR
: /* Auto-neg Link Partner Ability */
306 val
= (MII_ANLPAR_ACK
| MII_ANLPAR_PAUSE
| MII_ANLPAR_TXFD
|
307 MII_ANLPAR_TX
| MII_ANLPAR_10FD
| MII_ANLPAR_10
|
310 case MII_ANER
: /* Auto-neg Expansion */
313 case MII_CTRL1000
: /* 1000BASE-T control */
314 val
= (MII_CTRL1000_HALF
| MII_CTRL1000_FULL
);
316 case MII_STAT1000
: /* 1000BASE-T status */
317 val
= MII_STAT1000_FULL
;
319 case RTL8211E_MII_INSR
: /* Interrupt status. */
324 case RTL8211E_MII_INER
: /* Interrupt enable */
325 val
= s
->phy_int_mask
;
327 case RTL8211E_MII_PHYCR
:
328 case RTL8211E_MII_PHYSR
:
329 case RTL8211E_MII_RXERC
:
330 case RTL8211E_MII_LDPSR
:
331 case RTL8211E_MII_EPAGSR
:
332 case RTL8211E_MII_PAGSEL
:
333 qemu_log_mask(LOG_UNIMP
, "%s: reg %d not implemented\n",
338 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset %d\n",
347 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \
348 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
349 MII_BMCR_FD | MII_BMCR_CTST)
350 #define MII_ANAR_MASK 0x2d7f
352 static void do_phy_write(FTGMAC100State
*s
, uint8_t reg
, uint16_t val
)
355 case MII_BMCR
: /* Basic Control */
356 if (val
& MII_BMCR_RESET
) {
359 s
->phy_control
= val
& MII_BMCR_MASK
;
360 /* Complete autonegotiation immediately. */
361 if (val
& MII_BMCR_AUTOEN
) {
362 s
->phy_status
|= MII_BMSR_AN_COMP
;
366 case MII_ANAR
: /* Auto-neg advertisement */
367 s
->phy_advertise
= (val
& MII_ANAR_MASK
) | MII_ANAR_TX
;
369 case RTL8211E_MII_INER
: /* Interrupt enable */
370 s
->phy_int_mask
= val
& 0xff;
373 case RTL8211E_MII_PHYCR
:
374 case RTL8211E_MII_PHYSR
:
375 case RTL8211E_MII_RXERC
:
376 case RTL8211E_MII_LDPSR
:
377 case RTL8211E_MII_EPAGSR
:
378 case RTL8211E_MII_PAGSEL
:
379 qemu_log_mask(LOG_UNIMP
, "%s: reg %d not implemented\n",
383 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset %d\n",
389 static void do_phy_new_ctl(FTGMAC100State
*s
)
394 if (!(s
->phycr
& FTGMAC100_PHYCR_NEW_ST_22
)) {
395 qemu_log_mask(LOG_UNIMP
, "%s: unsupported ST code\n", __func__
);
400 if (!(s
->phycr
& FTGMAC100_PHYCR_NEW_FIRE
)) {
404 reg
= FTGMAC100_PHYCR_NEW_REG(s
->phycr
);
405 data
= FTGMAC100_PHYCR_NEW_DATA(s
->phycr
);
407 switch (FTGMAC100_PHYCR_NEW_OP(s
->phycr
)) {
408 case FTGMAC100_PHYCR_NEW_OP_WRITE
:
409 do_phy_write(s
, reg
, data
);
411 case FTGMAC100_PHYCR_NEW_OP_READ
:
412 s
->phydata
= do_phy_read(s
, reg
) & 0xffff;
415 qemu_log_mask(LOG_GUEST_ERROR
, "%s: invalid OP code %08x\n",
419 s
->phycr
&= ~FTGMAC100_PHYCR_NEW_FIRE
;
422 static void do_phy_ctl(FTGMAC100State
*s
)
424 uint8_t reg
= FTGMAC100_PHYCR_REG(s
->phycr
);
426 if (s
->phycr
& FTGMAC100_PHYCR_MIIWR
) {
427 do_phy_write(s
, reg
, s
->phydata
& 0xffff);
428 s
->phycr
&= ~FTGMAC100_PHYCR_MIIWR
;
429 } else if (s
->phycr
& FTGMAC100_PHYCR_MIIRD
) {
430 s
->phydata
= do_phy_read(s
, reg
) << 16;
431 s
->phycr
&= ~FTGMAC100_PHYCR_MIIRD
;
433 qemu_log_mask(LOG_GUEST_ERROR
, "%s: no OP code %08x\n",
438 static int ftgmac100_read_bd(FTGMAC100Desc
*bd
, dma_addr_t addr
)
440 if (dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
))) {
441 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to read descriptor @ 0x%"
442 HWADDR_PRIx
"\n", __func__
, addr
);
445 bd
->des0
= le32_to_cpu(bd
->des0
);
446 bd
->des1
= le32_to_cpu(bd
->des1
);
447 bd
->des2
= le32_to_cpu(bd
->des2
);
448 bd
->des3
= le32_to_cpu(bd
->des3
);
452 static int ftgmac100_write_bd(FTGMAC100Desc
*bd
, dma_addr_t addr
)
456 lebd
.des0
= cpu_to_le32(bd
->des0
);
457 lebd
.des1
= cpu_to_le32(bd
->des1
);
458 lebd
.des2
= cpu_to_le32(bd
->des2
);
459 lebd
.des3
= cpu_to_le32(bd
->des3
);
460 if (dma_memory_write(&address_space_memory
, addr
, &lebd
, sizeof(lebd
))) {
461 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to write descriptor @ 0x%"
462 HWADDR_PRIx
"\n", __func__
, addr
);
468 static void ftgmac100_do_tx(FTGMAC100State
*s
, uint32_t tx_ring
,
469 uint32_t tx_descriptor
)
472 uint8_t *ptr
= s
->frame
;
473 uint32_t addr
= tx_descriptor
;
480 if (ftgmac100_read_bd(&bd
, addr
) ||
481 ((bd
.des0
& FTGMAC100_TXDES0_TXDMA_OWN
) == 0)) {
482 /* Run out of descriptors to transmit. */
483 s
->isr
|= FTGMAC100_INT_NO_NPTXBUF
;
487 /* record transmit flags as they are valid only on the first
489 if (bd
.des0
& FTGMAC100_TXDES0_FTS
) {
493 len
= FTGMAC100_TXDES0_TXBUF_SIZE(bd
.des0
);
494 if (frame_size
+ len
> sizeof(s
->frame
)) {
495 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %d bytes\n",
497 s
->isr
|= FTGMAC100_INT_XPKT_LOST
;
498 len
= sizeof(s
->frame
) - frame_size
;
501 if (dma_memory_read(&address_space_memory
, bd
.des3
, ptr
, len
)) {
502 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to read packet @ 0x%x\n",
504 s
->isr
|= FTGMAC100_INT_NO_NPTXBUF
;
509 if (bd
.des0
& FTGMAC100_TXDES0_FTS
&&
510 bd
.des1
& FTGMAC100_TXDES1_INS_VLANTAG
&&
511 be16_to_cpu(PKT_GET_ETH_HDR(ptr
)->h_proto
) != ETH_P_VLAN
) {
512 if (frame_size
+ len
+ 4 > sizeof(s
->frame
)) {
513 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %d bytes\n",
515 s
->isr
|= FTGMAC100_INT_XPKT_LOST
;
516 len
= sizeof(s
->frame
) - frame_size
- 4;
518 memmove(ptr
+ 16, ptr
+ 12, len
- 12);
519 stw_be_p(ptr
+ 12, ETH_P_VLAN
);
520 stw_be_p(ptr
+ 14, bd
.des1
);
526 if (bd
.des0
& FTGMAC100_TXDES0_LTS
) {
527 if (flags
& FTGMAC100_TXDES1_IP_CHKSUM
) {
528 net_checksum_calculate(s
->frame
, frame_size
);
530 /* Last buffer in frame. */
531 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
534 if (flags
& FTGMAC100_TXDES1_TXIC
) {
535 s
->isr
|= FTGMAC100_INT_XPKT_ETH
;
539 if (flags
& FTGMAC100_TXDES1_TX2FIC
) {
540 s
->isr
|= FTGMAC100_INT_XPKT_FIFO
;
542 bd
.des0
&= ~FTGMAC100_TXDES0_TXDMA_OWN
;
544 /* Write back the modified descriptor. */
545 ftgmac100_write_bd(&bd
, addr
);
546 /* Advance to the next descriptor. */
547 if (bd
.des0
& s
->txdes0_edotr
) {
550 addr
+= sizeof(FTGMAC100Desc
);
554 s
->tx_descriptor
= addr
;
556 ftgmac100_update_irq(s
);
559 static int ftgmac100_can_receive(NetClientState
*nc
)
561 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
564 if ((s
->maccr
& (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
))
565 != (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
)) {
569 if (ftgmac100_read_bd(&bd
, s
->rx_descriptor
)) {
572 return !(bd
.des0
& FTGMAC100_RXDES0_RXPKT_RDY
);
576 * This is purely informative. The HW can poll the RW (and RX) ring
577 * buffers for available descriptors but we don't need to trigger a
578 * timer for that in qemu.
580 static uint32_t ftgmac100_rxpoll(FTGMAC100State
*s
)
584 * Speed TIME_SEL=0 TIME_SEL=1
586 * 10 51.2 ms 819.2 ms
587 * 100 5.12 ms 81.92 ms
588 * 1000 1.024 ms 16.384 ms
590 static const int div
[] = { 20, 200, 1000 };
592 uint32_t cnt
= 1024 * FTGMAC100_APTC_RXPOLL_CNT(s
->aptcr
);
593 uint32_t speed
= (s
->maccr
& FTGMAC100_MACCR_FAST_MODE
) ? 1 : 0;
595 if (s
->aptcr
& FTGMAC100_APTC_RXPOLL_TIME_SEL
) {
599 if (s
->maccr
& FTGMAC100_MACCR_GIGA_MODE
) {
603 return cnt
/ div
[speed
];
606 static void ftgmac100_reset(DeviceState
*d
)
608 FTGMAC100State
*s
= FTGMAC100(d
);
610 /* Reset the FTGMAC100 */
616 s
->rx_descriptor
= 0;
618 s
->tx_descriptor
= 0;
623 s
->dblac
= 0x00022f00;
637 static uint64_t ftgmac100_read(void *opaque
, hwaddr addr
, unsigned size
)
639 FTGMAC100State
*s
= FTGMAC100(opaque
);
641 switch (addr
& 0xff) {
646 case FTGMAC100_MAC_MADR
:
647 return (s
->conf
.macaddr
.a
[0] << 8) | s
->conf
.macaddr
.a
[1];
648 case FTGMAC100_MAC_LADR
:
649 return ((uint32_t) s
->conf
.macaddr
.a
[2] << 24) |
650 (s
->conf
.macaddr
.a
[3] << 16) | (s
->conf
.macaddr
.a
[4] << 8) |
651 s
->conf
.macaddr
.a
[5];
652 case FTGMAC100_MATH0
:
654 case FTGMAC100_MATH1
:
658 case FTGMAC100_DBLAC
:
662 case FTGMAC100_FEAR1
:
664 case FTGMAC100_TPAFCR
:
668 case FTGMAC100_MACCR
:
670 case FTGMAC100_PHYCR
:
672 case FTGMAC100_PHYDATA
:
675 /* We might want to support these one day */
676 case FTGMAC100_HPTXPD
: /* High Priority Transmit Poll Demand */
677 case FTGMAC100_HPTXR_BADR
: /* High Priority Transmit Ring Base Address */
678 case FTGMAC100_MACSR
: /* MAC Status Register (MACSR) */
679 qemu_log_mask(LOG_UNIMP
, "%s: read to unimplemented register 0x%"
680 HWADDR_PRIx
"\n", __func__
, addr
);
683 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset 0x%"
684 HWADDR_PRIx
"\n", __func__
, addr
);
689 static void ftgmac100_write(void *opaque
, hwaddr addr
,
690 uint64_t value
, unsigned size
)
692 FTGMAC100State
*s
= FTGMAC100(opaque
);
694 switch (addr
& 0xff) {
695 case FTGMAC100_ISR
: /* Interrupt status */
698 case FTGMAC100_IER
: /* Interrupt control */
701 case FTGMAC100_MAC_MADR
: /* MAC */
702 s
->conf
.macaddr
.a
[0] = value
>> 8;
703 s
->conf
.macaddr
.a
[1] = value
;
705 case FTGMAC100_MAC_LADR
:
706 s
->conf
.macaddr
.a
[2] = value
>> 24;
707 s
->conf
.macaddr
.a
[3] = value
>> 16;
708 s
->conf
.macaddr
.a
[4] = value
>> 8;
709 s
->conf
.macaddr
.a
[5] = value
;
711 case FTGMAC100_MATH0
: /* Multicast Address Hash Table 0 */
714 case FTGMAC100_MATH1
: /* Multicast Address Hash Table 1 */
717 case FTGMAC100_ITC
: /* TODO: Interrupt Timer Control */
720 case FTGMAC100_RXR_BADR
: /* Ring buffer address */
722 s
->rx_descriptor
= s
->rx_ring
;
725 case FTGMAC100_RBSR
: /* DMA buffer size */
729 case FTGMAC100_NPTXR_BADR
: /* Transmit buffer address */
731 s
->tx_descriptor
= s
->tx_ring
;
734 case FTGMAC100_NPTXPD
: /* Trigger transmit */
735 if ((s
->maccr
& (FTGMAC100_MACCR_TXDMA_EN
| FTGMAC100_MACCR_TXMAC_EN
))
736 == (FTGMAC100_MACCR_TXDMA_EN
| FTGMAC100_MACCR_TXMAC_EN
)) {
737 /* TODO: high priority tx ring */
738 ftgmac100_do_tx(s
, s
->tx_ring
, s
->tx_descriptor
);
740 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
741 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
745 case FTGMAC100_RXPD
: /* Receive Poll Demand Register */
746 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
747 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
751 case FTGMAC100_APTC
: /* Automatic polling */
754 if (FTGMAC100_APTC_RXPOLL_CNT(s
->aptcr
)) {
758 if (FTGMAC100_APTC_TXPOLL_CNT(s
->aptcr
)) {
759 qemu_log_mask(LOG_UNIMP
, "%s: no transmit polling\n", __func__
);
763 case FTGMAC100_MACCR
: /* MAC Device control */
765 if (value
& FTGMAC100_MACCR_SW_RST
) {
766 ftgmac100_reset(DEVICE(s
));
769 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
770 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
774 case FTGMAC100_PHYCR
: /* PHY Device control */
776 if (s
->revr
& FTGMAC100_REVR_NEW_MDIO_INTERFACE
) {
782 case FTGMAC100_PHYDATA
:
783 s
->phydata
= value
& 0xffff;
785 case FTGMAC100_DBLAC
: /* DMA Burst Length and Arbitration Control */
788 case FTGMAC100_REVR
: /* Feature Register */
791 case FTGMAC100_FEAR1
: /* Feature Register 1 */
794 case FTGMAC100_TPAFCR
: /* Transmit Priority Arbitration and FIFO Control */
797 case FTGMAC100_FCR
: /* Flow Control */
801 case FTGMAC100_HPTXPD
: /* High Priority Transmit Poll Demand */
802 case FTGMAC100_HPTXR_BADR
: /* High Priority Transmit Ring Base Address */
803 case FTGMAC100_MACSR
: /* MAC Status Register (MACSR) */
804 qemu_log_mask(LOG_UNIMP
, "%s: write to unimplemented register 0x%"
805 HWADDR_PRIx
"\n", __func__
, addr
);
808 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset 0x%"
809 HWADDR_PRIx
"\n", __func__
, addr
);
813 ftgmac100_update_irq(s
);
816 static int ftgmac100_filter(FTGMAC100State
*s
, const uint8_t *buf
, size_t len
)
820 if (s
->maccr
& FTGMAC100_MACCR_RX_ALL
) {
824 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf
))) {
826 if (!(s
->maccr
& FTGMAC100_MACCR_RX_BROADPKT
)) {
831 if (!(s
->maccr
& FTGMAC100_MACCR_RX_MULTIPKT
)) {
832 if (!(s
->maccr
& FTGMAC100_MACCR_HT_MULTI_EN
)) {
836 mcast_idx
= net_crc32_le(buf
, ETH_ALEN
);
837 mcast_idx
= (~(mcast_idx
>> 2)) & 0x3f;
838 if (!(s
->math
[mcast_idx
/ 32] & (1 << (mcast_idx
% 32)))) {
844 if (memcmp(s
->conf
.macaddr
.a
, buf
, 6)) {
853 static ssize_t
ftgmac100_receive(NetClientState
*nc
, const uint8_t *buf
,
856 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
865 uint32_t first
= FTGMAC100_RXDES0_FRS
;
866 uint16_t proto
= be16_to_cpu(PKT_GET_ETH_HDR(buf
)->h_proto
);
867 int max_frame_size
= ftgmac100_max_frame_size(s
, proto
);
869 if ((s
->maccr
& (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
))
870 != (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
)) {
874 /* TODO : Pad to minimum Ethernet frame length */
875 /* handle small packets. */
877 qemu_log_mask(LOG_GUEST_ERROR
, "%s: dropped frame of %zd bytes\n",
882 if (!ftgmac100_filter(s
, buf
, size
)) {
886 /* 4 bytes for the CRC. */
888 crc
= cpu_to_be32(crc32(~0, buf
, size
));
889 crc_ptr
= (uint8_t *) &crc
;
891 /* Huge frames are truncated. */
892 if (size
> max_frame_size
) {
893 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %zd bytes\n",
895 size
= max_frame_size
;
896 flags
|= FTGMAC100_RXDES0_FTL
;
899 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf
))) {
901 flags
|= FTGMAC100_RXDES0_BROADCAST
;
904 flags
|= FTGMAC100_RXDES0_MULTICAST
;
910 addr
= s
->rx_descriptor
;
912 if (!ftgmac100_can_receive(nc
)) {
913 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Unexpected packet\n", __func__
);
917 if (ftgmac100_read_bd(&bd
, addr
) ||
918 (bd
.des0
& FTGMAC100_RXDES0_RXPKT_RDY
)) {
919 /* No descriptors available. Bail out. */
920 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Lost end of frame\n",
922 s
->isr
|= FTGMAC100_INT_NO_RXBUF
;
925 buf_len
= (size
<= s
->rbsr
) ? size
: s
->rbsr
;
926 bd
.des0
|= buf_len
& 0x3fff;
929 /* The last 4 bytes are the CRC. */
934 if (first
&& proto
== ETH_P_VLAN
&& buf_len
>= 18) {
935 bd
.des1
= lduw_be_p(buf
+ 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL
;
937 if (s
->maccr
& FTGMAC100_MACCR_RM_VLAN
) {
938 dma_memory_write(&address_space_memory
, buf_addr
, buf
, 12);
939 dma_memory_write(&address_space_memory
, buf_addr
+ 12, buf
+ 16,
942 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
946 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
950 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
955 bd
.des0
|= first
| FTGMAC100_RXDES0_RXPKT_RDY
;
958 /* Last buffer in frame. */
959 bd
.des0
|= flags
| FTGMAC100_RXDES0_LRS
;
960 s
->isr
|= FTGMAC100_INT_RPKT_BUF
;
962 s
->isr
|= FTGMAC100_INT_RPKT_FIFO
;
964 ftgmac100_write_bd(&bd
, addr
);
965 if (bd
.des0
& s
->rxdes0_edorr
) {
968 addr
+= sizeof(FTGMAC100Desc
);
971 s
->rx_descriptor
= addr
;
973 ftgmac100_update_irq(s
);
977 static const MemoryRegionOps ftgmac100_ops
= {
978 .read
= ftgmac100_read
,
979 .write
= ftgmac100_write
,
980 .valid
.min_access_size
= 4,
981 .valid
.max_access_size
= 4,
982 .endianness
= DEVICE_LITTLE_ENDIAN
,
985 static void ftgmac100_cleanup(NetClientState
*nc
)
987 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
992 static NetClientInfo net_ftgmac100_info
= {
993 .type
= NET_CLIENT_DRIVER_NIC
,
994 .size
= sizeof(NICState
),
995 .can_receive
= ftgmac100_can_receive
,
996 .receive
= ftgmac100_receive
,
997 .cleanup
= ftgmac100_cleanup
,
998 .link_status_changed
= ftgmac100_set_link
,
1001 static void ftgmac100_realize(DeviceState
*dev
, Error
**errp
)
1003 FTGMAC100State
*s
= FTGMAC100(dev
);
1004 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1007 s
->txdes0_edotr
= FTGMAC100_TXDES0_EDOTR_ASPEED
;
1008 s
->rxdes0_edorr
= FTGMAC100_RXDES0_EDORR_ASPEED
;
1010 s
->txdes0_edotr
= FTGMAC100_TXDES0_EDOTR
;
1011 s
->rxdes0_edorr
= FTGMAC100_RXDES0_EDORR
;
1014 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &ftgmac100_ops
, s
,
1015 TYPE_FTGMAC100
, 0x2000);
1016 sysbus_init_mmio(sbd
, &s
->iomem
);
1017 sysbus_init_irq(sbd
, &s
->irq
);
1018 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1020 s
->nic
= qemu_new_nic(&net_ftgmac100_info
, &s
->conf
,
1021 object_get_typename(OBJECT(dev
)), DEVICE(dev
)->id
,
1023 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1026 static const VMStateDescription vmstate_ftgmac100
= {
1027 .name
= TYPE_FTGMAC100
,
1029 .minimum_version_id
= 1,
1030 .fields
= (VMStateField
[]) {
1031 VMSTATE_UINT32(irq_state
, FTGMAC100State
),
1032 VMSTATE_UINT32(isr
, FTGMAC100State
),
1033 VMSTATE_UINT32(ier
, FTGMAC100State
),
1034 VMSTATE_UINT32(rx_enabled
, FTGMAC100State
),
1035 VMSTATE_UINT32(rx_ring
, FTGMAC100State
),
1036 VMSTATE_UINT32(rbsr
, FTGMAC100State
),
1037 VMSTATE_UINT32(tx_ring
, FTGMAC100State
),
1038 VMSTATE_UINT32(rx_descriptor
, FTGMAC100State
),
1039 VMSTATE_UINT32(tx_descriptor
, FTGMAC100State
),
1040 VMSTATE_UINT32_ARRAY(math
, FTGMAC100State
, 2),
1041 VMSTATE_UINT32(itc
, FTGMAC100State
),
1042 VMSTATE_UINT32(aptcr
, FTGMAC100State
),
1043 VMSTATE_UINT32(dblac
, FTGMAC100State
),
1044 VMSTATE_UINT32(revr
, FTGMAC100State
),
1045 VMSTATE_UINT32(fear1
, FTGMAC100State
),
1046 VMSTATE_UINT32(tpafcr
, FTGMAC100State
),
1047 VMSTATE_UINT32(maccr
, FTGMAC100State
),
1048 VMSTATE_UINT32(phycr
, FTGMAC100State
),
1049 VMSTATE_UINT32(phydata
, FTGMAC100State
),
1050 VMSTATE_UINT32(fcr
, FTGMAC100State
),
1051 VMSTATE_UINT32(phy_status
, FTGMAC100State
),
1052 VMSTATE_UINT32(phy_control
, FTGMAC100State
),
1053 VMSTATE_UINT32(phy_advertise
, FTGMAC100State
),
1054 VMSTATE_UINT32(phy_int
, FTGMAC100State
),
1055 VMSTATE_UINT32(phy_int_mask
, FTGMAC100State
),
1056 VMSTATE_UINT32(txdes0_edotr
, FTGMAC100State
),
1057 VMSTATE_UINT32(rxdes0_edorr
, FTGMAC100State
),
1058 VMSTATE_END_OF_LIST()
1062 static Property ftgmac100_properties
[] = {
1063 DEFINE_PROP_BOOL("aspeed", FTGMAC100State
, aspeed
, false),
1064 DEFINE_NIC_PROPERTIES(FTGMAC100State
, conf
),
1065 DEFINE_PROP_END_OF_LIST(),
1068 static void ftgmac100_class_init(ObjectClass
*klass
, void *data
)
1070 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1072 dc
->vmsd
= &vmstate_ftgmac100
;
1073 dc
->reset
= ftgmac100_reset
;
1074 dc
->props
= ftgmac100_properties
;
1075 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
1076 dc
->realize
= ftgmac100_realize
;
1077 dc
->desc
= "Faraday FTGMAC100 Gigabit Ethernet emulation";
1080 static const TypeInfo ftgmac100_info
= {
1081 .name
= TYPE_FTGMAC100
,
1082 .parent
= TYPE_SYS_BUS_DEVICE
,
1083 .instance_size
= sizeof(FTGMAC100State
),
1084 .class_init
= ftgmac100_class_init
,
1087 static void ftgmac100_register_types(void)
1089 type_register_static(&ftgmac100_info
);
1092 type_init(ftgmac100_register_types
)