hw/net/e1000e.c

   1 /*
   2 * QEMU INTEL 82574 GbE NIC emulation
   3 *
   4 * Software developer's manuals:
   5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
   6 *
   7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   8 * Developed by Daynix Computing LTD (http://www.daynix.com)
   9 *
  10 * Authors:
  11 * Dmitry Fleytman <dmitry@daynix.com>
  12 * Leonid Bloch <leonid@daynix.com>
  13 * Yan Vugenfirer <yan@daynix.com>
  14 *
  15 * Based on work done by:
  16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  17 * Copyright (c) 2008 Qumranet
  18 * Based on work done by:
  19 * Copyright (c) 2007 Dan Aloni
  20 * Copyright (c) 2004 Antony T Curtis
  21 *
  22 * This library is free software; you can redistribute it and/or
  23 * modify it under the terms of the GNU Lesser General Public
  24 * License as published by the Free Software Foundation; either
  25 * version 2 of the License, or (at your option) any later version.
  26 *
  27 * This library is distributed in the hope that it will be useful,
  28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  30 * Lesser General Public License for more details.
  31 *
  32 * You should have received a copy of the GNU Lesser General Public
  33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  34 */
  35
  36 #include "qemu/osdep.h"
  37 #include "qemu/units.h"
  38 #include "net/net.h"
  39 #include "net/tap.h"
  40 #include "qemu/module.h"
  41 #include "qemu/range.h"
  42 #include "sysemu/sysemu.h"
  43 #include "hw/pci/msi.h"
  44 #include "hw/pci/msix.h"
  45
  46 #include "e1000_regs.h"
  47
  48 #include "e1000x_common.h"
  49 #include "e1000e_core.h"
  50
  51 #include "trace.h"
  52 #include "qapi/error.h"
  53
  54 #define TYPE_E1000E "e1000e"
  55 #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
  56
  57 typedef struct E1000EState {
  58     PCIDevice parent_obj;
  59     NICState *nic;
  60     NICConf conf;
  61
  62     MemoryRegion mmio;
  63     MemoryRegion flash;
  64     MemoryRegion io;
  65     MemoryRegion msix;
  66
  67     uint32_t ioaddr;
  68
  69     uint16_t subsys_ven;
  70     uint16_t subsys;
  71
  72     uint16_t subsys_ven_used;
  73     uint16_t subsys_used;
  74
  75     bool disable_vnet;
  76
  77     E1000ECore core;
  78
  79 } E1000EState;
  80
  81 #define E1000E_MMIO_IDX     0
  82 #define E1000E_FLASH_IDX    1
  83 #define E1000E_IO_IDX       2
  84 #define E1000E_MSIX_IDX     3
  85
  86 #define E1000E_MMIO_SIZE    (128 * KiB)
  87 #define E1000E_FLASH_SIZE   (128 * KiB)
  88 #define E1000E_IO_SIZE      (32)
  89 #define E1000E_MSIX_SIZE    (16 * KiB)
  90
  91 #define E1000E_MSIX_TABLE   (0x0000)
  92 #define E1000E_MSIX_PBA     (0x2000)
  93
  94 static uint64_t
  95 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
  96 {
  97     E1000EState *s = opaque;
  98     return e1000e_core_read(&s->core, addr, size);
  99 }
 100
 101 static void
 102 e1000e_mmio_write(void *opaque, hwaddr addr,
 103                    uint64_t val, unsigned size)
 104 {
 105     E1000EState *s = opaque;
 106     e1000e_core_write(&s->core, addr, val, size);
 107 }
 108
 109 static bool
 110 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
 111 {
 112     if (s->ioaddr < 0x1FFFF) {
 113         *idx = s->ioaddr;
 114         return true;
 115     }
 116
 117     if (s->ioaddr < 0x7FFFF) {
 118         trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
 119         return false;
 120     }
 121
 122     if (s->ioaddr < 0xFFFFF) {
 123         trace_e1000e_wrn_io_addr_flash(s->ioaddr);
 124         return false;
 125     }
 126
 127     trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
 128     return false;
 129 }
 130
 131 static uint64_t
 132 e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
 133 {
 134     E1000EState *s = opaque;
 135     uint32_t idx = 0;
 136     uint64_t val;
 137
 138     switch (addr) {
 139     case E1000_IOADDR:
 140         trace_e1000e_io_read_addr(s->ioaddr);
 141         return s->ioaddr;
 142     case E1000_IODATA:
 143         if (e1000e_io_get_reg_index(s, &idx)) {
 144             val = e1000e_core_read(&s->core, idx, sizeof(val));
 145             trace_e1000e_io_read_data(idx, val);
 146             return val;
 147         }
 148         return 0;
 149     default:
 150         trace_e1000e_wrn_io_read_unknown(addr);
 151         return 0;
 152     }
 153 }
 154
 155 static void
 156 e1000e_io_write(void *opaque, hwaddr addr,
 157                 uint64_t val, unsigned size)
 158 {
 159     E1000EState *s = opaque;
 160     uint32_t idx = 0;
 161
 162     switch (addr) {
 163     case E1000_IOADDR:
 164         trace_e1000e_io_write_addr(val);
 165         s->ioaddr = (uint32_t) val;
 166         return;
 167     case E1000_IODATA:
 168         if (e1000e_io_get_reg_index(s, &idx)) {
 169             trace_e1000e_io_write_data(idx, val);
 170             e1000e_core_write(&s->core, idx, val, sizeof(val));
 171         }
 172         return;
 173     default:
 174         trace_e1000e_wrn_io_write_unknown(addr);
 175         return;
 176     }
 177 }
 178
 179 static const MemoryRegionOps mmio_ops = {
 180     .read = e1000e_mmio_read,
 181     .write = e1000e_mmio_write,
 182     .endianness = DEVICE_LITTLE_ENDIAN,
 183     .impl = {
 184         .min_access_size = 4,
 185         .max_access_size = 4,
 186     },
 187 };
 188
 189 static const MemoryRegionOps io_ops = {
 190     .read = e1000e_io_read,
 191     .write = e1000e_io_write,
 192     .endianness = DEVICE_LITTLE_ENDIAN,
 193     .impl = {
 194         .min_access_size = 4,
 195         .max_access_size = 4,
 196     },
 197 };
 198
 199 static int
 200 e1000e_nc_can_receive(NetClientState *nc)
 201 {
 202     E1000EState *s = qemu_get_nic_opaque(nc);
 203     return e1000e_can_receive(&s->core);
 204 }
 205
 206 static ssize_t
 207 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
 208 {
 209     E1000EState *s = qemu_get_nic_opaque(nc);
 210     return e1000e_receive_iov(&s->core, iov, iovcnt);
 211 }
 212
 213 static ssize_t
 214 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 215 {
 216     E1000EState *s = qemu_get_nic_opaque(nc);
 217     return e1000e_receive(&s->core, buf, size);
 218 }
 219
 220 static void
 221 e1000e_set_link_status(NetClientState *nc)
 222 {
 223     E1000EState *s = qemu_get_nic_opaque(nc);
 224     e1000e_core_set_link_status(&s->core);
 225 }
 226
 227 static NetClientInfo net_e1000e_info = {
 228     .type = NET_CLIENT_DRIVER_NIC,
 229     .size = sizeof(NICState),
 230     .can_receive = e1000e_nc_can_receive,
 231     .receive = e1000e_nc_receive,
 232     .receive_iov = e1000e_nc_receive_iov,
 233     .link_status_changed = e1000e_set_link_status,
 234 };
 235
 236 /*
 237 * EEPROM (NVM) contents documented in Table 36, section 6.1
 238 * and generally 6.1.2 Software accessed words.
 239 */
 240 static const uint16_t e1000e_eeprom_template[64] = {
 241   /*        Address        |    Compat.    | ImVer |   Compat.     */
 242     0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
 243   /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
 244     0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
 245   /*    NVM words 1,2,3    |-------------------------------|PCI-EID*/
 246     0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
 247   /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
 248     0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
 249   /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
 250     0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
 251   /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP  */
 252     0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
 253   /*                            SW Section                         */
 254     0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
 255   /*                      SW Section                       |CHKSUM */
 256     0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
 257 };
 258
 259 static void e1000e_core_realize(E1000EState *s)
 260 {
 261     s->core.owner = &s->parent_obj;
 262     s->core.owner_nic = s->nic;
 263 }
 264
 265 static void
 266 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
 267 {
 268     int i;
 269     for (i = 0; i < num_vectors; i++) {
 270         msix_vector_unuse(PCI_DEVICE(s), i);
 271     }
 272 }
 273
 274 static bool
 275 e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
 276 {
 277     int i;
 278     for (i = 0; i < num_vectors; i++) {
 279         int res = msix_vector_use(PCI_DEVICE(s), i);
 280         if (res < 0) {
 281             trace_e1000e_msix_use_vector_fail(i, res);
 282             e1000e_unuse_msix_vectors(s, i);
 283             return false;
 284         }
 285     }
 286     return true;
 287 }
 288
 289 static void
 290 e1000e_init_msix(E1000EState *s)
 291 {
 292     PCIDevice *d = PCI_DEVICE(s);
 293     int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
 294                         &s->msix,
 295                         E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
 296                         &s->msix,
 297                         E1000E_MSIX_IDX, E1000E_MSIX_PBA,
 298                         0xA0, NULL);
 299
 300     if (res < 0) {
 301         trace_e1000e_msix_init_fail(res);
 302     } else {
 303         if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
 304             msix_uninit(d, &s->msix, &s->msix);
 305         }
 306     }
 307 }
 308
 309 static void
 310 e1000e_cleanup_msix(E1000EState *s)
 311 {
 312     if (msix_present(PCI_DEVICE(s))) {
 313         e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
 314         msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
 315     }
 316 }
 317
 318 static void
 319 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
 320 {
 321     DeviceState *dev = DEVICE(pci_dev);
 322     NetClientState *nc;
 323     int i;
 324
 325     s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
 326         object_get_typename(OBJECT(s)), dev->id, s);
 327
 328     s->core.max_queue_num = s->conf.peers.queues - 1;
 329
 330     trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
 331     memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
 332
 333     qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
 334
 335     /* Setup virtio headers */
 336     if (s->disable_vnet) {
 337         s->core.has_vnet = false;
 338         trace_e1000e_cfg_support_virtio(false);
 339         return;
 340     } else {
 341         s->core.has_vnet = true;
 342     }
 343
 344     for (i = 0; i < s->conf.peers.queues; i++) {
 345         nc = qemu_get_subqueue(s->nic, i);
 346         if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
 347             s->core.has_vnet = false;
 348             trace_e1000e_cfg_support_virtio(false);
 349             return;
 350         }
 351     }
 352
 353     trace_e1000e_cfg_support_virtio(true);
 354
 355     for (i = 0; i < s->conf.peers.queues; i++) {
 356         nc = qemu_get_subqueue(s->nic, i);
 357         qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
 358         qemu_using_vnet_hdr(nc->peer, true);
 359     }
 360 }
 361
 362 static inline uint64_t
 363 e1000e_gen_dsn(uint8_t *mac)
 364 {
 365     return (uint64_t)(mac[5])        |
 366            (uint64_t)(mac[4])  << 8  |
 367            (uint64_t)(mac[3])  << 16 |
 368            (uint64_t)(0x00FF)  << 24 |
 369            (uint64_t)(0x00FF)  << 32 |
 370            (uint64_t)(mac[2])  << 40 |
 371            (uint64_t)(mac[1])  << 48 |
 372            (uint64_t)(mac[0])  << 56;
 373 }
 374
 375 static int
 376 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
 377 {
 378     Error *local_err = NULL;
 379     int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
 380                                  PCI_PM_SIZEOF, &local_err);
 381
 382     if (local_err) {
 383         error_report_err(local_err);
 384         return ret;
 385     }
 386
 387     pci_set_word(pdev->config + offset + PCI_PM_PMC,
 388                  PCI_PM_CAP_VER_1_1 |
 389                  pmc);
 390
 391     pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
 392                  PCI_PM_CTRL_STATE_MASK |
 393                  PCI_PM_CTRL_PME_ENABLE |
 394                  PCI_PM_CTRL_DATA_SEL_MASK);
 395
 396     pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
 397                  PCI_PM_CTRL_PME_STATUS);
 398
 399     return ret;
 400 }
 401
 402 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
 403                                 uint32_t val, int len)
 404 {
 405     E1000EState *s = E1000E(pci_dev);
 406
 407     pci_default_write_config(pci_dev, address, val, len);
 408
 409     if (range_covers_byte(address, len, PCI_COMMAND) &&
 410         (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
 411         e1000e_start_recv(&s->core);
 412     }
 413 }
 414
 415 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
 416 {
 417     static const uint16_t e1000e_pmrb_offset = 0x0C8;
 418     static const uint16_t e1000e_pcie_offset = 0x0E0;
 419     static const uint16_t e1000e_aer_offset =  0x100;
 420     static const uint16_t e1000e_dsn_offset =  0x140;
 421     E1000EState *s = E1000E(pci_dev);
 422     uint8_t *macaddr;
 423     int ret;
 424
 425     trace_e1000e_cb_pci_realize();
 426
 427     pci_dev->config_write = e1000e_write_config;
 428
 429     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
 430     pci_dev->config[PCI_INTERRUPT_PIN] = 1;
 431
 432     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
 433     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
 434
 435     s->subsys_ven_used = s->subsys_ven;
 436     s->subsys_used = s->subsys;
 437
 438     /* Define IO/MMIO regions */
 439     memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
 440                           "e1000e-mmio", E1000E_MMIO_SIZE);
 441     pci_register_bar(pci_dev, E1000E_MMIO_IDX,
 442                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 443
 444     /*
 445      * We provide a dummy implementation for the flash BAR
 446      * for drivers that may theoretically probe for its presence.
 447      */
 448     memory_region_init(&s->flash, OBJECT(s),
 449                        "e1000e-flash", E1000E_FLASH_SIZE);
 450     pci_register_bar(pci_dev, E1000E_FLASH_IDX,
 451                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
 452
 453     memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
 454                           "e1000e-io", E1000E_IO_SIZE);
 455     pci_register_bar(pci_dev, E1000E_IO_IDX,
 456                      PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 457
 458     memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
 459                        E1000E_MSIX_SIZE);
 460     pci_register_bar(pci_dev, E1000E_MSIX_IDX,
 461                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
 462
 463     /* Create networking backend */
 464     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 465     macaddr = s->conf.macaddr.a;
 466
 467     e1000e_init_msix(s);
 468
 469     if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
 470         hw_error("Failed to initialize PCIe capability");
 471     }
 472
 473     ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
 474     if (ret) {
 475         trace_e1000e_msi_init_fail(ret);
 476     }
 477
 478     if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
 479                                   PCI_PM_CAP_DSI) < 0) {
 480         hw_error("Failed to initialize PM capability");
 481     }
 482
 483     if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
 484                       PCI_ERR_SIZEOF, NULL) < 0) {
 485         hw_error("Failed to initialize AER capability");
 486     }
 487
 488     pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
 489                           e1000e_gen_dsn(macaddr));
 490
 491     e1000e_init_net_peer(s, pci_dev, macaddr);
 492
 493     /* Initialize core */
 494     e1000e_core_realize(s);
 495
 496     e1000e_core_pci_realize(&s->core,
 497                             e1000e_eeprom_template,
 498                             sizeof(e1000e_eeprom_template),
 499                             macaddr);
 500 }
 501
 502 static void e1000e_pci_uninit(PCIDevice *pci_dev)
 503 {
 504     E1000EState *s = E1000E(pci_dev);
 505
 506     trace_e1000e_cb_pci_uninit();
 507
 508     e1000e_core_pci_uninit(&s->core);
 509
 510     pcie_aer_exit(pci_dev);
 511     pcie_cap_exit(pci_dev);
 512
 513     qemu_del_nic(s->nic);
 514
 515     e1000e_cleanup_msix(s);
 516     msi_uninit(pci_dev);
 517 }
 518
 519 static void e1000e_qdev_reset(DeviceState *dev)
 520 {
 521     E1000EState *s = E1000E(dev);
 522
 523     trace_e1000e_cb_qdev_reset();
 524
 525     e1000e_core_reset(&s->core);
 526 }
 527
 528 static int e1000e_pre_save(void *opaque)
 529 {
 530     E1000EState *s = opaque;
 531
 532     trace_e1000e_cb_pre_save();
 533
 534     e1000e_core_pre_save(&s->core);
 535
 536     return 0;
 537 }
 538
 539 static int e1000e_post_load(void *opaque, int version_id)
 540 {
 541     E1000EState *s = opaque;
 542
 543     trace_e1000e_cb_post_load();
 544
 545     if ((s->subsys != s->subsys_used) ||
 546         (s->subsys_ven != s->subsys_ven_used)) {
 547         fprintf(stderr,
 548             "ERROR: Cannot migrate while device properties "
 549             "(subsys/subsys_ven) differ");
 550         return -1;
 551     }
 552
 553     return e1000e_core_post_load(&s->core);
 554 }
 555
 556 static const VMStateDescription e1000e_vmstate_tx = {
 557     .name = "e1000e-tx",
 558     .version_id = 1,
 559     .minimum_version_id = 1,
 560     .fields = (VMStateField[]) {
 561         VMSTATE_UINT8(sum_needed, struct e1000e_tx),
 562         VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
 563         VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
 564         VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
 565         VMSTATE_UINT8(props.tucss, struct e1000e_tx),
 566         VMSTATE_UINT8(props.tucso, struct e1000e_tx),
 567         VMSTATE_UINT16(props.tucse, struct e1000e_tx),
 568         VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
 569         VMSTATE_UINT16(props.mss, struct e1000e_tx),
 570         VMSTATE_UINT32(props.paylen, struct e1000e_tx),
 571         VMSTATE_INT8(props.ip, struct e1000e_tx),
 572         VMSTATE_INT8(props.tcp, struct e1000e_tx),
 573         VMSTATE_BOOL(props.tse, struct e1000e_tx),
 574         VMSTATE_BOOL(cptse, struct e1000e_tx),
 575         VMSTATE_BOOL(skip_cp, struct e1000e_tx),
 576         VMSTATE_END_OF_LIST()
 577     }
 578 };
 579
 580 static const VMStateDescription e1000e_vmstate_intr_timer = {
 581     .name = "e1000e-intr-timer",
 582     .version_id = 1,
 583     .minimum_version_id = 1,
 584     .fields = (VMStateField[]) {
 585         VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
 586         VMSTATE_BOOL(running, E1000IntrDelayTimer),
 587         VMSTATE_END_OF_LIST()
 588     }
 589 };
 590
 591 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s)                     \
 592     VMSTATE_STRUCT(_f, _s, 0,                                       \
 593                    e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 594
 595 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)         \
 596     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
 597                          e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 598
 599 static const VMStateDescription e1000e_vmstate = {
 600     .name = "e1000e",
 601     .version_id = 1,
 602     .minimum_version_id = 1,
 603     .pre_save = e1000e_pre_save,
 604     .post_load = e1000e_post_load,
 605     .fields = (VMStateField[]) {
 606         VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
 607         VMSTATE_MSIX(parent_obj, E1000EState),
 608
 609         VMSTATE_UINT32(ioaddr, E1000EState),
 610         VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
 611         VMSTATE_UINT8(core.rx_desc_len, E1000EState),
 612         VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
 613                              E1000_PSRCTL_BUFFS_PER_DESC),
 614         VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
 615         VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
 616         VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
 617                                E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
 618         VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
 619         VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
 620
 621         VMSTATE_UINT32(core.delayed_causes, E1000EState),
 622
 623         VMSTATE_UINT16(subsys, E1000EState),
 624         VMSTATE_UINT16(subsys_ven, E1000EState),
 625
 626         VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
 627         VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
 628         VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
 629         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
 630         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
 631
 632         VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
 633         VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
 634
 635         VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
 636                                               E1000E_MSIX_VEC_NUM),
 637         VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
 638                            E1000E_MSIX_VEC_NUM),
 639
 640         VMSTATE_UINT32(core.itr_guest_value, E1000EState),
 641         VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
 642                              E1000E_MSIX_VEC_NUM),
 643
 644         VMSTATE_UINT16(core.vet, E1000EState),
 645
 646         VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
 647                              e1000e_vmstate_tx, struct e1000e_tx),
 648         VMSTATE_END_OF_LIST()
 649     }
 650 };
 651
 652 static PropertyInfo e1000e_prop_disable_vnet,
 653                     e1000e_prop_subsys_ven,
 654                     e1000e_prop_subsys;
 655
 656 static Property e1000e_properties[] = {
 657     DEFINE_NIC_PROPERTIES(E1000EState, conf),
 658     DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
 659                         e1000e_prop_disable_vnet, bool),
 660     DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
 661                         PCI_VENDOR_ID_INTEL,
 662                         e1000e_prop_subsys_ven, uint16_t),
 663     DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
 664                         e1000e_prop_subsys, uint16_t),
 665     DEFINE_PROP_END_OF_LIST(),
 666 };
 667
 668 static void e1000e_class_init(ObjectClass *class, void *data)
 669 {
 670     DeviceClass *dc = DEVICE_CLASS(class);
 671     PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
 672
 673     c->realize = e1000e_pci_realize;
 674     c->exit = e1000e_pci_uninit;
 675     c->vendor_id = PCI_VENDOR_ID_INTEL;
 676     c->device_id = E1000_DEV_ID_82574L;
 677     c->revision = 0;
 678     c->romfile = "efi-e1000e.rom";
 679     c->class_id = PCI_CLASS_NETWORK_ETHERNET;
 680
 681     dc->desc = "Intel 82574L GbE Controller";
 682     dc->reset = e1000e_qdev_reset;
 683     dc->vmsd = &e1000e_vmstate;
 684     dc->props = e1000e_properties;
 685
 686     e1000e_prop_disable_vnet = qdev_prop_uint8;
 687     e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
 688                                            "perform SW offloads emulation "
 689                                            "instead";
 690
 691     e1000e_prop_subsys_ven = qdev_prop_uint16;
 692     e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
 693
 694     e1000e_prop_subsys = qdev_prop_uint16;
 695     e1000e_prop_subsys.description = "PCI device Subsystem ID";
 696
 697     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 698 }
 699
 700 static void e1000e_instance_init(Object *obj)
 701 {
 702     E1000EState *s = E1000E(obj);
 703     device_add_bootindex_property(obj, &s->conf.bootindex,
 704                                   "bootindex", "/ethernet-phy@0",
 705                                   DEVICE(obj), NULL);
 706 }
 707
 708 static const TypeInfo e1000e_info = {
 709     .name = TYPE_E1000E,
 710     .parent = TYPE_PCI_DEVICE,
 711     .instance_size = sizeof(E1000EState),
 712     .class_init = e1000e_class_init,
 713     .instance_init = e1000e_instance_init,
 714     .interfaces = (InterfaceInfo[]) {
 715         { INTERFACE_PCIE_DEVICE },
 716         { }
 717     },
 718 };
 719
 720 static void e1000e_register_types(void)
 721 {
 722     type_register_static(&e1000e_info);
 723 }
 724
 725 type_init(e1000e_register_types)