include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  66
  67 #include "qemu/log.h"
  68
  69 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  70 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  71                           target_ulong *data);
  72
  73 void cpu_gen_init(void);
  74 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  75
  76 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  77 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  78 TranslationBlock *tb_gen_code(CPUState *cpu,
  79                               target_ulong pc, target_ulong cs_base, int flags,
  80                               int cflags);
  81 void cpu_exec_init(CPUState *cpu, Error **errp);
  82 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  83 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  84
  85 #if !defined(CONFIG_USER_ONLY)
  86 void cpu_reloading_memory_map(void);
  87 /**
  88  * cpu_address_space_init:
  89  * @cpu: CPU to add this address space to
  90  * @as: address space to add
  91  * @asidx: integer index of this address space
  92  *
  93  * Add the specified address space to the CPU's cpu_ases list.
  94  * The address space added with @asidx 0 is the one used for the
  95  * convenience pointer cpu->as.
  96  * The target-specific code which registers ASes is responsible
  97  * for defining what semantics address space 0, 1, 2, etc have.
  98  *
  99  * Before the first call to this function, the caller must set
 100  * cpu->num_ases to the total number of address spaces it needs
 101  * to support.
 102  *
 103  * Note that with KVM only one address space is supported.
 104  */
 105 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx);
 106 /* cputlb.c */
 107 /**
 108  * tlb_flush_page:
 109  * @cpu: CPU whose TLB should be flushed
 110  * @addr: virtual address of page to be flushed
 111  *
 112  * Flush one page from the TLB of the specified CPU, for all
 113  * MMU indexes.
 114  */
 115 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 116 /**
 117  * tlb_flush:
 118  * @cpu: CPU whose TLB should be flushed
 119  * @flush_global: ignored
 120  *
 121  * Flush the entire TLB for the specified CPU.
 122  * The flush_global flag is in theory an indicator of whether the whole
 123  * TLB should be flushed, or only those entries not marked global.
 124  * In practice QEMU does not implement any global/not global flag for
 125  * TLB entries, and the argument is ignored.
 126  */
 127 void tlb_flush(CPUState *cpu, int flush_global);
 128 /**
 129  * tlb_flush_page_by_mmuidx:
 130  * @cpu: CPU whose TLB should be flushed
 131  * @addr: virtual address of page to be flushed
 132  * @...: list of MMU indexes to flush, terminated by a negative value
 133  *
 134  * Flush one page from the TLB of the specified CPU, for the specified
 135  * MMU indexes.
 136  */
 137 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
 138 /**
 139  * tlb_flush_by_mmuidx:
 140  * @cpu: CPU whose TLB should be flushed
 141  * @...: list of MMU indexes to flush, terminated by a negative value
 142  *
 143  * Flush all entries from the TLB of the specified CPU, for the specified
 144  * MMU indexes.
 145  */
 146 void tlb_flush_by_mmuidx(CPUState *cpu, ...);
 147 /**
 148  * tlb_set_page_with_attrs:
 149  * @cpu: CPU to add this TLB entry for
 150  * @vaddr: virtual address of page to add entry for
 151  * @paddr: physical address of the page
 152  * @attrs: memory transaction attributes
 153  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 154  * @mmu_idx: MMU index to insert TLB entry for
 155  * @size: size of the page in bytes
 156  *
 157  * Add an entry to this CPU's TLB (a mapping from virtual address
 158  * @vaddr to physical address @paddr) with the specified memory
 159  * transaction attributes. This is generally called by the target CPU
 160  * specific code after it has been called through the tlb_fill()
 161  * entry point and performed a successful page table walk to find
 162  * the physical address and attributes for the virtual address
 163  * which provoked the TLB miss.
 164  *
 165  * At most one entry for a given virtual address is permitted. Only a
 166  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 167  * used by tlb_flush_page.
 168  */
 169 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 170                              hwaddr paddr, MemTxAttrs attrs,
 171                              int prot, int mmu_idx, target_ulong size);
 172 /* tlb_set_page:
 173  *
 174  * This function is equivalent to calling tlb_set_page_with_attrs()
 175  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 176  * as a convenience for CPUs which don't use memory transaction attributes.
 177  */
 178 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 179                   hwaddr paddr, int prot,
 180                   int mmu_idx, target_ulong size);
 181 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 182 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 183                  uintptr_t retaddr);
 184 #else
 185 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 186 {
 187 }
 188
 189 static inline void tlb_flush(CPUState *cpu, int flush_global)
 190 {
 191 }
 192
 193 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 194                                             target_ulong addr, ...)
 195 {
 196 }
 197
 198 static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...)
 199 {
 200 }
 201 #endif
 202
 203 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 204
 205 #define CODE_GEN_PHYS_HASH_BITS     15
 206 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 207
 208 /* Estimated block size for TB allocation.  */
 209 /* ??? The following is based on a 2015 survey of x86_64 host output.
 210    Better would seem to be some sort of dynamically sized TB array,
 211    adapting to the block sizes actually being produced.  */
 212 #if defined(CONFIG_SOFTMMU)
 213 #define CODE_GEN_AVG_BLOCK_SIZE 400
 214 #else
 215 #define CODE_GEN_AVG_BLOCK_SIZE 150
 216 #endif
 217
 218 #if defined(__arm__) || defined(_ARCH_PPC) \
 219     || defined(__x86_64__) || defined(__i386__) \
 220     || defined(__sparc__) || defined(__aarch64__) \
 221     || defined(__s390x__) || defined(__mips__) \
 222     || defined(CONFIG_TCG_INTERPRETER)
 223 #define USE_DIRECT_JUMP
 224 #endif
 225
 226 struct TranslationBlock {
 227     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 228     target_ulong cs_base; /* CS base for this block */
 229     uint64_t flags; /* flags defining in which context the code was generated */
 230     uint16_t size;      /* size of target code for this block (1 <=
 231                            size <= TARGET_PAGE_SIZE) */
 232     uint16_t icount;
 233     uint32_t cflags;    /* compile flags */
 234 #define CF_COUNT_MASK  0x7fff
 235 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 236 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 237 #define CF_USE_ICOUNT  0x20000
 238 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
 239
 240     void *tc_ptr;    /* pointer to the translated code */
 241     uint8_t *tc_search;  /* pointer to search data */
 242     /* next matching tb for physical address. */
 243     struct TranslationBlock *phys_hash_next;
 244     /* original tb when cflags has CF_NOCACHE */
 245     struct TranslationBlock *orig_tb;
 246     /* first and second physical page containing code. The lower bit
 247        of the pointer tells the index in page_next[] */
 248     struct TranslationBlock *page_next[2];
 249     tb_page_addr_t page_addr[2];
 250
 251     /* the following data are used to directly call another TB from
 252        the code of this one. */
 253     uint16_t tb_next_offset[2]; /* offset of original jump target */
 254 #ifdef USE_DIRECT_JUMP
 255     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 256 #else
 257     uintptr_t tb_next[2]; /* address of jump generated code */
 258 #endif
 259     /* list of TBs jumping to this one. This is a circular list using
 260        the two least significant bits of the pointers to tell what is
 261        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 262        jmp_first */
 263     struct TranslationBlock *jmp_next[2];
 264     struct TranslationBlock *jmp_first;
 265 };
 266
 267 #include "qemu/thread.h"
 268
 269 typedef struct TBContext TBContext;
 270
 271 struct TBContext {
 272
 273     TranslationBlock *tbs;
 274     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 275     int nb_tbs;
 276     /* any access to the tbs or the page table must use this lock */
 277     QemuMutex tb_lock;
 278
 279     /* statistics */
 280     int tb_flush_count;
 281     int tb_phys_invalidate_count;
 282
 283     int tb_invalidated_flag;
 284 };
 285
 286 void tb_free(TranslationBlock *tb);
 287 void tb_flush(CPUState *cpu);
 288 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 289
 290 #if defined(USE_DIRECT_JUMP)
 291
 292 #if defined(CONFIG_TCG_INTERPRETER)
 293 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 294 {
 295     /* patch the branch destination */
 296     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 297     /* no need to flush icache explicitly */
 298 }
 299 #elif defined(_ARCH_PPC)
 300 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 301 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 302 #elif defined(__i386__) || defined(__x86_64__)
 303 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 304 {
 305     /* patch the branch destination */
 306     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 307     /* no need to flush icache explicitly */
 308 }
 309 #elif defined(__s390x__)
 310 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 311 {
 312     /* patch the branch destination */
 313     intptr_t disp = addr - (jmp_addr - 2);
 314     stl_be_p((void*)jmp_addr, disp / 2);
 315     /* no need to flush icache explicitly */
 316 }
 317 #elif defined(__aarch64__)
 318 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 319 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 320 #elif defined(__arm__)
 321 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 322 {
 323 #if !QEMU_GNUC_PREREQ(4, 1)
 324     register unsigned long _beg __asm ("a1");
 325     register unsigned long _end __asm ("a2");
 326     register unsigned long _flg __asm ("a3");
 327 #endif
 328
 329     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 330     *(uint32_t *)jmp_addr =
 331         (*(uint32_t *)jmp_addr & ~0xffffff)
 332         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 333
 334 #if QEMU_GNUC_PREREQ(4, 1)
 335     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 336 #else
 337     /* flush icache */
 338     _beg = jmp_addr;
 339     _end = jmp_addr + 4;
 340     _flg = 0;
 341     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 342 #endif
 343 }
 344 #elif defined(__sparc__) || defined(__mips__)
 345 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 346 #else
 347 #error tb_set_jmp_target1 is missing
 348 #endif
 349
 350 static inline void tb_set_jmp_target(TranslationBlock *tb,
 351                                      int n, uintptr_t addr)
 352 {
 353     uint16_t offset = tb->tb_jmp_offset[n];
 354     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 355 }
 356
 357 #else
 358
 359 /* set the jump target */
 360 static inline void tb_set_jmp_target(TranslationBlock *tb,
 361                                      int n, uintptr_t addr)
 362 {
 363     tb->tb_next[n] = addr;
 364 }
 365
 366 #endif
 367
 368 static inline void tb_add_jump(TranslationBlock *tb, int n,
 369                                TranslationBlock *tb_next)
 370 {
 371     /* NOTE: this test is only needed for thread safety */
 372     if (!tb->jmp_next[n]) {
 373         /* patch the native jump address */
 374         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 375
 376         /* add in TB jmp circular list */
 377         tb->jmp_next[n] = tb_next->jmp_first;
 378         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 379     }
 380 }
 381
 382 /* GETRA is the true target of the return instruction that we'll execute,
 383    defined here for simplicity of defining the follow-up macros.  */
 384 #if defined(CONFIG_TCG_INTERPRETER)
 385 extern uintptr_t tci_tb_ptr;
 386 # define GETRA() tci_tb_ptr
 387 #else
 388 # define GETRA() \
 389     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 390 #endif
 391
 392 /* The true return address will often point to a host insn that is part of
 393    the next translated guest insn.  Adjust the address backward to point to
 394    the middle of the call insn.  Subtracting one would do the job except for
 395    several compressed mode architectures (arm, mips) which set the low bit
 396    to indicate the compressed mode; subtracting two works around that.  It
 397    is also the case that there are no host isas that contain a call insn
 398    smaller than 4 bytes, so we don't worry about special-casing this.  */
 399 #define GETPC_ADJ   2
 400
 401 #define GETPC()  (GETRA() - GETPC_ADJ)
 402
 403 #if !defined(CONFIG_USER_ONLY)
 404
 405 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 406                                      hwaddr index, MemTxAttrs attrs);
 407
 408 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 409               uintptr_t retaddr);
 410
 411 #endif
 412
 413 #if defined(CONFIG_USER_ONLY)
 414 void mmap_lock(void);
 415 void mmap_unlock(void);
 416
 417 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 418 {
 419     return addr;
 420 }
 421 #else
 422 static inline void mmap_lock(void) {}
 423 static inline void mmap_unlock(void) {}
 424
 425 /* cputlb.c */
 426 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 427
 428 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 429 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 430
 431 /* exec.c */
 432 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
 433
 434 MemoryRegionSection *
 435 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 436                                   hwaddr *xlat, hwaddr *plen);
 437 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 438                                        MemoryRegionSection *section,
 439                                        target_ulong vaddr,
 440                                        hwaddr paddr, hwaddr xlat,
 441                                        int prot,
 442                                        target_ulong *address);
 443 bool memory_region_is_unassigned(MemoryRegion *mr);
 444
 445 #endif
 446
 447 /* vl.c */
 448 extern int singlestep;
 449
 450 /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */
 451 extern CPUState *tcg_current_cpu;
 452 extern bool exit_request;
 453
 454 #endif