hw/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-timer.h"
  27 #include "ptimer.h"
  28
  29 #define D(x)
  30
  31 #define R_TCSR     0
  32 #define R_TLR      1
  33 #define R_TCR      2
  34 #define R_MAX      4
  35
  36 #define TCSR_MDT        (1<<0)
  37 #define TCSR_UDT        (1<<1)
  38 #define TCSR_GENT       (1<<2)
  39 #define TCSR_CAPT       (1<<3)
  40 #define TCSR_ARHT       (1<<4)
  41 #define TCSR_LOAD       (1<<5)
  42 #define TCSR_ENIT       (1<<6)
  43 #define TCSR_ENT        (1<<7)
  44 #define TCSR_TINT       (1<<8)
  45 #define TCSR_PWMA       (1<<9)
  46 #define TCSR_ENALL      (1<<10)
  47
  48 struct xlx_timer
  49 {
  50     QEMUBH *bh;
  51     ptimer_state *ptimer;
  52     void *parent;
  53     int nr; /* for debug.  */
  54
  55     unsigned long timer_div;
  56
  57     uint32_t regs[R_MAX];
  58 };
  59
  60 struct timerblock
  61 {
  62     SysBusDevice busdev;
  63     MemoryRegion mmio;
  64     qemu_irq irq;
  65     uint32_t nr_timers;
  66     uint32_t freq_hz;
  67     struct xlx_timer *timers;
  68 };
  69
  70 static inline unsigned int timer_from_addr(target_phys_addr_t addr)
  71 {
  72     /* Timers get a 4x32bit control reg area each.  */
  73     return addr >> 2;
  74 }
  75
  76 static void timer_update_irq(struct timerblock *t)
  77 {
  78     unsigned int i, irq = 0;
  79     uint32_t csr;
  80
  81     for (i = 0; i < t->nr_timers; i++) {
  82         csr = t->timers[i].regs[R_TCSR];
  83         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  84     }
  85
  86     /* All timers within the same slave share a single IRQ line.  */
  87     qemu_set_irq(t->irq, !!irq);
  88 }
  89
  90 static uint64_t
  91 timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
  92 {
  93     struct timerblock *t = opaque;
  94     struct xlx_timer *xt;
  95     uint32_t r = 0;
  96     unsigned int timer;
  97
  98     addr >>= 2;
  99     timer = timer_from_addr(addr);
 100     xt = &t->timers[timer];
 101     /* Further decoding to address a specific timers reg.  */
 102     addr &= 0x3;
 103     switch (addr)
 104     {
 105         case R_TCR:
 106                 r = ptimer_get_count(xt->ptimer);
 107                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 108                     r = ~r;
 109                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 110                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 111             break;
 112         default:
 113             if (addr < ARRAY_SIZE(xt->regs))
 114                 r = xt->regs[addr];
 115             break;
 116
 117     }
 118     D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 119     return r;
 120 }
 121
 122 static void timer_enable(struct xlx_timer *xt)
 123 {
 124     uint64_t count;
 125
 126     D(printf("%s timer=%d down=%d\n", __func__,
 127               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 128
 129     ptimer_stop(xt->ptimer);
 130
 131     if (xt->regs[R_TCSR] & TCSR_UDT)
 132         count = xt->regs[R_TLR];
 133     else
 134         count = ~0 - xt->regs[R_TLR];
 135     ptimer_set_count(xt->ptimer, count);
 136     ptimer_run(xt->ptimer, 1);
 137 }
 138
 139 static void
 140 timer_write(void *opaque, target_phys_addr_t addr,
 141             uint64_t val64, unsigned int size)
 142 {
 143     struct timerblock *t = opaque;
 144     struct xlx_timer *xt;
 145     unsigned int timer;
 146     uint32_t value = val64;
 147
 148     addr >>= 2;
 149     timer = timer_from_addr(addr);
 150     xt = &t->timers[timer];
 151     D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
 152              __func__, addr * 4, value, timer, addr & 3));
 153     /* Further decoding to address a specific timers reg.  */
 154     addr &= 3;
 155     switch (addr)
 156     {
 157         case R_TCSR:
 158             if (value & TCSR_TINT)
 159                 value &= ~TCSR_TINT;
 160
 161             xt->regs[addr] = value;
 162             if (value & TCSR_ENT)
 163                 timer_enable(xt);
 164             break;
 165
 166         default:
 167             if (addr < ARRAY_SIZE(xt->regs))
 168                 xt->regs[addr] = value;
 169             break;
 170     }
 171     timer_update_irq(t);
 172 }
 173
 174 static const MemoryRegionOps timer_ops = {
 175     .read = timer_read,
 176     .write = timer_write,
 177     .endianness = DEVICE_NATIVE_ENDIAN,
 178     .valid = {
 179         .min_access_size = 4,
 180         .max_access_size = 4
 181     }
 182 };
 183
 184 static void timer_hit(void *opaque)
 185 {
 186     struct xlx_timer *xt = opaque;
 187     struct timerblock *t = xt->parent;
 188     D(printf("%s %d\n", __func__, timer));
 189     xt->regs[R_TCSR] |= TCSR_TINT;
 190
 191     if (xt->regs[R_TCSR] & TCSR_ARHT)
 192         timer_enable(xt);
 193     timer_update_irq(t);
 194 }
 195
 196 static int xilinx_timer_init(SysBusDevice *dev)
 197 {
 198     struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
 199     unsigned int i;
 200
 201     /* All timers share a single irq line.  */
 202     sysbus_init_irq(dev, &t->irq);
 203
 204     /* Init all the ptimers.  */
 205     t->timers = g_malloc0(sizeof t->timers[0] * t->nr_timers);
 206     for (i = 0; i < t->nr_timers; i++) {
 207         struct xlx_timer *xt = &t->timers[i];
 208
 209         xt->parent = t;
 210         xt->nr = i;
 211         xt->bh = qemu_bh_new(timer_hit, xt);
 212         xt->ptimer = ptimer_init(xt->bh);
 213         ptimer_set_freq(xt->ptimer, t->freq_hz);
 214     }
 215
 216     memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
 217                           R_MAX * 4 * t->nr_timers);
 218     sysbus_init_mmio(dev, &t->mmio);
 219     return 0;
 220 }
 221
 222 static Property xilinx_timer_properties[] = {
 223     DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
 224     DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
 225     DEFINE_PROP_END_OF_LIST(),
 226 };
 227
 228 static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 229 {
 230     DeviceClass *dc = DEVICE_CLASS(klass);
 231     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 232
 233     k->init = xilinx_timer_init;
 234     dc->props = xilinx_timer_properties;
 235 }
 236
 237 static TypeInfo xilinx_timer_info = {
 238     .name          = "xilinx,timer",
 239     .parent        = TYPE_SYS_BUS_DEVICE,
 240     .instance_size = sizeof(struct timerblock),
 241     .class_init    = xilinx_timer_class_init,
 242 };
 243
 244 static void xilinx_timer_register(void)
 245 {
 246     type_register_static(&xilinx_timer_info);
 247 }
 248
 249 device_init(xilinx_timer_register)