4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 void raise_exception(CPUARMState
*env
, uint32_t excp
,
32 uint32_t syndrome
, uint32_t target_el
)
34 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
36 if (target_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
38 * Redirect NS EL1 exceptions to NS EL2. These are reported with
39 * their original syndrome register value, with the exception of
40 * SIMD/FP access traps, which are reported as uncategorized
41 * (see DDI0478C.a D1.10.4)
44 if (syn_get_ec(syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
45 syndrome
= syn_uncategorized();
49 assert(!excp_is_internal(excp
));
50 cs
->exception_index
= excp
;
51 env
->exception
.syndrome
= syndrome
;
52 env
->exception
.target_el
= target_el
;
56 static int exception_target_el(CPUARMState
*env
)
58 int target_el
= MAX(1, arm_current_el(env
));
60 /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
61 * to EL3 in this case.
63 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
70 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
77 for (shift
= 0; shift
< 32; shift
+= 8) {
78 uint32_t index
= (ireg
>> shift
) & 0xff;
79 if (index
< maxindex
) {
80 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
83 val
|= def
& (0xff << shift
);
89 #if !defined(CONFIG_USER_ONLY)
91 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
92 unsigned int target_el
,
93 bool same_el
, bool ea
,
94 bool s1ptw
, bool is_write
,
99 /* ISV is only set for data aborts routed to EL2 and
100 * never for stage-1 page table walks faulting on stage 2.
102 * Furthermore, ISV is only set for certain kinds of load/stores.
103 * If the template syndrome does not have ISV set, we should leave
106 * See ARMv8 specs, D7-1974:
107 * ISS encoding for an exception from a Data Abort, the
110 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
111 syn
= syn_data_abort_no_iss(same_el
,
112 ea
, 0, s1ptw
, is_write
, fsc
);
114 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
115 * syndrome created at translation time.
116 * Now we create the runtime syndrome with the remaining fields.
118 syn
= syn_data_abort_with_iss(same_el
,
120 ea
, 0, s1ptw
, is_write
, fsc
,
122 /* Merge the runtime syndrome with the template syndrome. */
128 static void deliver_fault(ARMCPU
*cpu
, vaddr addr
, MMUAccessType access_type
,
129 int mmu_idx
, ARMMMUFaultInfo
*fi
)
131 CPUARMState
*env
= &cpu
->env
;
134 uint32_t syn
, exc
, fsr
, fsc
;
135 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
137 target_el
= exception_target_el(env
);
140 env
->cp15
.hpfar_el2
= extract64(fi
->s2addr
, 12, 47) << 4;
142 same_el
= (arm_current_el(env
) == target_el
);
144 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
145 arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
146 /* LPAE format fault status register : bottom 6 bits are
147 * status code in the same form as needed for syndrome
149 fsr
= arm_fi_to_lfsc(fi
);
150 fsc
= extract32(fsr
, 0, 6);
152 fsr
= arm_fi_to_sfsc(fi
);
153 /* Short format FSR : this fault will never actually be reported
154 * to an EL that uses a syndrome register. Use a (currently)
155 * reserved FSR code in case the constructed syndrome does leak
156 * into the guest somehow.
161 if (access_type
== MMU_INST_FETCH
) {
162 syn
= syn_insn_abort(same_el
, fi
->ea
, fi
->s1ptw
, fsc
);
163 exc
= EXCP_PREFETCH_ABORT
;
165 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
166 same_el
, fi
->ea
, fi
->s1ptw
,
167 access_type
== MMU_DATA_STORE
,
169 if (access_type
== MMU_DATA_STORE
170 && arm_feature(env
, ARM_FEATURE_V6
)) {
173 exc
= EXCP_DATA_ABORT
;
176 env
->exception
.vaddress
= addr
;
177 env
->exception
.fsr
= fsr
;
178 raise_exception(env
, exc
, syn
, target_el
);
181 /* try to fill the TLB and return an exception if error. If retaddr is
182 * NULL, it means that the function was called in C code (i.e. not
183 * from generated code or from helper.c)
185 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
186 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
189 ARMMMUFaultInfo fi
= {};
191 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fi
);
193 ARMCPU
*cpu
= ARM_CPU(cs
);
195 /* now we have a real cpu fault */
196 cpu_restore_state(cs
, retaddr
, true);
198 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
202 /* Raise a data fault alignment exception for the specified virtual address */
203 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
204 MMUAccessType access_type
,
205 int mmu_idx
, uintptr_t retaddr
)
207 ARMCPU
*cpu
= ARM_CPU(cs
);
208 ARMMMUFaultInfo fi
= {};
210 /* now we have a real cpu fault */
211 cpu_restore_state(cs
, retaddr
, true);
213 fi
.type
= ARMFault_Alignment
;
214 deliver_fault(cpu
, vaddr
, access_type
, mmu_idx
, &fi
);
217 /* arm_cpu_do_transaction_failed: handle a memory system error response
218 * (eg "no device/memory present at address") by raising an external abort
221 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
222 vaddr addr
, unsigned size
,
223 MMUAccessType access_type
,
224 int mmu_idx
, MemTxAttrs attrs
,
225 MemTxResult response
, uintptr_t retaddr
)
227 ARMCPU
*cpu
= ARM_CPU(cs
);
228 ARMMMUFaultInfo fi
= {};
230 /* now we have a real cpu fault */
231 cpu_restore_state(cs
, retaddr
, true);
233 fi
.ea
= arm_extabort_type(response
);
234 fi
.type
= ARMFault_SyncExternal
;
235 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
238 #endif /* !defined(CONFIG_USER_ONLY) */
240 void HELPER(v8m_stackcheck
)(CPUARMState
*env
, uint32_t newvalue
)
243 * Perform the v8M stack limit check for SP updates from translated code,
244 * raising an exception if the limit is breached.
246 if (newvalue
< v7m_sp_limit(env
)) {
247 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
250 * Stack limit exceptions are a rare case, so rather than syncing
251 * PC/condbits before the call, we use cpu_restore_state() to
252 * get them right before raising the exception.
254 cpu_restore_state(cs
, GETPC(), true);
255 raise_exception(env
, EXCP_STKOF
, 0, 1);
259 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
261 uint32_t res
= a
+ b
;
262 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
267 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
269 uint32_t res
= a
+ b
;
270 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
272 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
277 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
279 uint32_t res
= a
- b
;
280 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
282 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
287 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
290 if (val
>= 0x40000000) {
293 } else if (val
<= (int32_t)0xc0000000) {
302 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
304 uint32_t res
= a
+ b
;
312 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
314 uint32_t res
= a
- b
;
322 /* Signed saturation. */
323 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
329 mask
= (1u << shift
) - 1;
333 } else if (top
< -1) {
340 /* Unsigned saturation. */
341 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
345 max
= (1u << shift
) - 1;
349 } else if (val
> max
) {
356 /* Signed saturate. */
357 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
359 return do_ssat(env
, x
, shift
);
362 /* Dual halfword signed saturate. */
363 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
367 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
368 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
372 /* Unsigned saturate. */
373 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
375 return do_usat(env
, x
, shift
);
378 /* Dual halfword unsigned saturate. */
379 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
383 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
384 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
388 void HELPER(setend
)(CPUARMState
*env
)
390 env
->uncached_cpsr
^= CPSR_E
;
393 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
394 * The function returns the target EL (1-3) if the instruction is to be trapped;
395 * otherwise it returns 0 indicating it is not trapped.
397 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
399 int cur_el
= arm_current_el(env
);
402 if (arm_feature(env
, ARM_FEATURE_M
)) {
403 /* M profile cores can never trap WFI/WFE. */
407 /* If we are currently in EL0 then we need to check if SCTLR is set up for
408 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
410 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
413 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
414 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
415 /* Secure EL0 and Secure PL1 is at EL3 */
421 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
426 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
427 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
428 * bits will be zero indicating no trap.
431 mask
= is_wfe
? HCR_TWE
: HCR_TWI
;
432 if (arm_hcr_el2_eff(env
) & mask
) {
437 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
439 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
440 if (env
->cp15
.scr_el3
& mask
) {
448 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
450 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
451 int target_el
= check_wfx_trap(env
, false);
453 if (cpu_has_work(cs
)) {
454 /* Don't bother to go into our "low power state" if
455 * we would just wake up immediately.
462 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
466 cs
->exception_index
= EXCP_HLT
;
471 void HELPER(wfe
)(CPUARMState
*env
)
473 /* This is a hint instruction that is semantically different
474 * from YIELD even though we currently implement it identically.
475 * Don't actually halt the CPU, just yield back to top
476 * level loop. This is not going into a "low power state"
477 * (ie halting until some event occurs), so we never take
478 * a configurable trap to a different exception level.
483 void HELPER(yield
)(CPUARMState
*env
)
485 ARMCPU
*cpu
= arm_env_get_cpu(env
);
486 CPUState
*cs
= CPU(cpu
);
488 /* This is a non-trappable hint instruction that generally indicates
489 * that the guest is currently busy-looping. Yield control back to the
490 * top level loop so that a more deserving VCPU has a chance to run.
492 cs
->exception_index
= EXCP_YIELD
;
496 /* Raise an internal-to-QEMU exception. This is limited to only
497 * those EXCP values which are special cases for QEMU to interrupt
498 * execution and not to be used for exceptions which are passed to
499 * the guest (those must all have syndrome information and thus should
500 * use exception_with_syndrome).
502 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
504 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
506 assert(excp_is_internal(excp
));
507 cs
->exception_index
= excp
;
511 /* Raise an exception with the specified syndrome register value */
512 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
513 uint32_t syndrome
, uint32_t target_el
)
515 raise_exception(env
, excp
, syndrome
, target_el
);
518 /* Raise an EXCP_BKPT with the specified syndrome register value,
519 * targeting the correct exception level for debug exceptions.
521 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
523 /* FSR will only be used if the debug target EL is AArch32. */
524 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
525 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
526 * values to the guest that it shouldn't be able to see at its
527 * exception/security level.
529 env
->exception
.vaddress
= 0;
530 raise_exception(env
, EXCP_BKPT
, syndrome
, arm_debug_target_el(env
));
533 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
535 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
538 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
540 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
543 /* Write the CPSR for a 32-bit exception return */
544 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
546 qemu_mutex_lock_iothread();
547 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
548 qemu_mutex_unlock_iothread();
550 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
552 /* Generated code has already stored the new PC value, but
553 * without masking out its low bits, because which bits need
554 * masking depends on whether we're returning to Thumb or ARM
555 * state. Do the masking now.
557 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
559 qemu_mutex_lock_iothread();
560 arm_call_el_change_hook(arm_env_get_cpu(env
));
561 qemu_mutex_unlock_iothread();
564 /* Access to user mode registers from privileged modes. */
565 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
570 val
= env
->banked_r13
[BANK_USRSYS
];
571 } else if (regno
== 14) {
572 val
= env
->banked_r14
[BANK_USRSYS
];
573 } else if (regno
>= 8
574 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
575 val
= env
->usr_regs
[regno
- 8];
577 val
= env
->regs
[regno
];
582 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
585 env
->banked_r13
[BANK_USRSYS
] = val
;
586 } else if (regno
== 14) {
587 env
->banked_r14
[BANK_USRSYS
] = val
;
588 } else if (regno
>= 8
589 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
590 env
->usr_regs
[regno
- 8] = val
;
592 env
->regs
[regno
] = val
;
596 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
598 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
601 env
->banked_r13
[bank_number(mode
)] = val
;
605 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
607 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
608 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
609 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
611 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
612 exception_target_el(env
));
615 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
616 return env
->regs
[13];
618 return env
->banked_r13
[bank_number(mode
)];
622 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
625 /* Raise an exception if the requested access is one of the UNPREDICTABLE
626 * cases; otherwise return. This broadly corresponds to the pseudocode
627 * BankedRegisterAccessValid() and SPSRAccessValid(),
628 * except that we have already handled some cases at translate time.
630 int curmode
= env
->uncached_cpsr
& CPSR_M
;
633 /* ELR_Hyp: a special case because access from tgtmode is OK */
634 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
640 if (curmode
== tgtmode
) {
644 if (tgtmode
== ARM_CPU_MODE_USR
) {
647 if (curmode
!= ARM_CPU_MODE_FIQ
) {
652 if (curmode
== ARM_CPU_MODE_SYS
) {
657 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
666 if (tgtmode
== ARM_CPU_MODE_HYP
) {
667 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
668 if (curmode
!= ARM_CPU_MODE_MON
) {
676 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
677 exception_target_el(env
));
680 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
683 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
687 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
689 case 17: /* ELR_Hyp */
690 env
->elr_el
[2] = value
;
693 env
->banked_r13
[bank_number(tgtmode
)] = value
;
696 env
->banked_r14
[r14_bank_number(tgtmode
)] = value
;
700 case ARM_CPU_MODE_USR
:
701 env
->usr_regs
[regno
- 8] = value
;
703 case ARM_CPU_MODE_FIQ
:
704 env
->fiq_regs
[regno
- 8] = value
;
707 g_assert_not_reached();
711 g_assert_not_reached();
715 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
717 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
721 return env
->banked_spsr
[bank_number(tgtmode
)];
722 case 17: /* ELR_Hyp */
723 return env
->elr_el
[2];
725 return env
->banked_r13
[bank_number(tgtmode
)];
727 return env
->banked_r14
[r14_bank_number(tgtmode
)];
730 case ARM_CPU_MODE_USR
:
731 return env
->usr_regs
[regno
- 8];
732 case ARM_CPU_MODE_FIQ
:
733 return env
->fiq_regs
[regno
- 8];
735 g_assert_not_reached();
738 g_assert_not_reached();
742 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
745 const ARMCPRegInfo
*ri
= rip
;
748 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
749 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
750 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
757 switch (ri
->accessfn(env
, ri
, isread
)) {
761 target_el
= exception_target_el(env
);
763 case CP_ACCESS_TRAP_EL2
:
764 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
765 * a bug in the access function.
767 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
770 case CP_ACCESS_TRAP_EL3
:
773 case CP_ACCESS_TRAP_UNCATEGORIZED
:
774 target_el
= exception_target_el(env
);
775 syndrome
= syn_uncategorized();
777 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
779 syndrome
= syn_uncategorized();
781 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
783 syndrome
= syn_uncategorized();
785 case CP_ACCESS_TRAP_FP_EL2
:
787 /* Since we are an implementation that takes exceptions on a trapped
788 * conditional insn only if the insn has passed its condition code
789 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
790 * (which is also the required value for AArch64 traps).
792 syndrome
= syn_fp_access_trap(1, 0xe, false);
794 case CP_ACCESS_TRAP_FP_EL3
:
796 syndrome
= syn_fp_access_trap(1, 0xe, false);
799 g_assert_not_reached();
802 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
805 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
807 const ARMCPRegInfo
*ri
= rip
;
809 if (ri
->type
& ARM_CP_IO
) {
810 qemu_mutex_lock_iothread();
811 ri
->writefn(env
, ri
, value
);
812 qemu_mutex_unlock_iothread();
814 ri
->writefn(env
, ri
, value
);
818 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
820 const ARMCPRegInfo
*ri
= rip
;
823 if (ri
->type
& ARM_CP_IO
) {
824 qemu_mutex_lock_iothread();
825 res
= ri
->readfn(env
, ri
);
826 qemu_mutex_unlock_iothread();
828 res
= ri
->readfn(env
, ri
);
834 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
836 const ARMCPRegInfo
*ri
= rip
;
838 if (ri
->type
& ARM_CP_IO
) {
839 qemu_mutex_lock_iothread();
840 ri
->writefn(env
, ri
, value
);
841 qemu_mutex_unlock_iothread();
843 ri
->writefn(env
, ri
, value
);
847 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
849 const ARMCPRegInfo
*ri
= rip
;
852 if (ri
->type
& ARM_CP_IO
) {
853 qemu_mutex_lock_iothread();
854 res
= ri
->readfn(env
, ri
);
855 qemu_mutex_unlock_iothread();
857 res
= ri
->readfn(env
, ri
);
863 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
865 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
866 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
867 * to catch that case at translate time.
869 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
870 uint32_t syndrome
= syn_aa64_sysregtrap(0, extract32(op
, 0, 3),
871 extract32(op
, 3, 3), 4,
873 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
877 case 0x05: /* SPSel */
878 update_spsel(env
, imm
);
880 case 0x1e: /* DAIFSet */
881 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
883 case 0x1f: /* DAIFClear */
884 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
887 g_assert_not_reached();
891 void HELPER(clear_pstate_ss
)(CPUARMState
*env
)
893 env
->pstate
&= ~PSTATE_SS
;
896 void HELPER(pre_hvc
)(CPUARMState
*env
)
898 ARMCPU
*cpu
= arm_env_get_cpu(env
);
899 int cur_el
= arm_current_el(env
);
900 /* FIXME: Use actual secure state. */
904 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
905 /* If PSCI is enabled and this looks like a valid PSCI call then
906 * that overrides the architecturally mandated HVC behaviour.
911 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
912 /* If EL2 doesn't exist, HVC always UNDEFs */
914 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
915 /* EL3.HCE has priority over EL2.HCD. */
916 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
918 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
921 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
922 * For ARMv8/AArch64, HVC is allowed in EL3.
923 * Note that we've already trapped HVC from EL0 at translation
926 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
931 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
932 exception_target_el(env
));
936 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
938 ARMCPU
*cpu
= arm_env_get_cpu(env
);
939 int cur_el
= arm_current_el(env
);
940 bool secure
= arm_is_secure(env
);
941 bool smd_flag
= env
->cp15
.scr_el3
& SCR_SMD
;
944 * SMC behaviour is summarized in the following table.
945 * This helper handles the "Trap to EL2" and "Undef insn" cases.
946 * The "Trap to EL3" and "PSCI call" cases are handled in the exception
949 * -> ARM_FEATURE_EL3 and !SMD
950 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
952 * Conduit SMC, valid call Trap to EL2 PSCI Call
953 * Conduit SMC, inval call Trap to EL2 Trap to EL3
954 * Conduit not SMC Trap to EL2 Trap to EL3
957 * -> ARM_FEATURE_EL3 and SMD
958 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
960 * Conduit SMC, valid call Trap to EL2 PSCI Call
961 * Conduit SMC, inval call Trap to EL2 Undef insn
962 * Conduit not SMC Trap to EL2 Undef insn
965 * -> !ARM_FEATURE_EL3
966 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
968 * Conduit SMC, valid call Trap to EL2 PSCI Call
969 * Conduit SMC, inval call Trap to EL2 Undef insn
970 * Conduit not SMC Undef insn Undef insn
973 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
974 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
975 * extensions, SMD only applies to NS state.
976 * On ARMv7 without the Virtualization extensions, the SMD bit
977 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
978 * so we need not special case this here.
980 bool smd
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd_flag
981 : smd_flag
&& !secure
;
983 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
984 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
985 /* If we have no EL3 then SMC always UNDEFs and can't be
986 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
987 * firmware within QEMU, and we want an EL2 guest to be able
988 * to forbid its EL1 from making PSCI calls into QEMU's
989 * "firmware" via HCR.TSC, so for these purposes treat
990 * PSCI-via-SMC as implying an EL3.
991 * This handles the very last line of the previous table.
993 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
994 exception_target_el(env
));
997 if (cur_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TSC
)) {
998 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
999 * We also want an EL2 guest to be able to forbid its EL1 from
1000 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
1001 * This handles all the "Trap to EL2" cases of the previous table.
1003 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
1006 /* Catch the two remaining "Undef insn" cases of the previous table:
1007 * - PSCI conduit is SMC but we don't have a valid PCSI call,
1008 * - We don't have EL3 or SMD is set.
1010 if (!arm_is_psci_call(cpu
, EXCP_SMC
) &&
1011 (smd
|| !arm_feature(env
, ARM_FEATURE_EL3
))) {
1012 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
1013 exception_target_el(env
));
1017 static int el_from_spsr(uint32_t spsr
)
1019 /* Return the exception level that this SPSR is requesting a return to,
1020 * or -1 if it is invalid (an illegal return)
1022 if (spsr
& PSTATE_nRW
) {
1023 switch (spsr
& CPSR_M
) {
1024 case ARM_CPU_MODE_USR
:
1026 case ARM_CPU_MODE_HYP
:
1028 case ARM_CPU_MODE_FIQ
:
1029 case ARM_CPU_MODE_IRQ
:
1030 case ARM_CPU_MODE_SVC
:
1031 case ARM_CPU_MODE_ABT
:
1032 case ARM_CPU_MODE_UND
:
1033 case ARM_CPU_MODE_SYS
:
1035 case ARM_CPU_MODE_MON
:
1036 /* Returning to Mon from AArch64 is never possible,
1037 * so this is an illegal return.
1043 if (extract32(spsr
, 1, 1)) {
1044 /* Return with reserved M[1] bit set */
1047 if (extract32(spsr
, 0, 4) == 1) {
1048 /* return to EL0 with M[0] bit set */
1051 return extract32(spsr
, 2, 2);
1055 void HELPER(exception_return
)(CPUARMState
*env
)
1057 int cur_el
= arm_current_el(env
);
1058 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
1059 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
1061 bool return_to_aa64
= (spsr
& PSTATE_nRW
) == 0;
1063 aarch64_save_sp(env
, cur_el
);
1065 arm_clear_exclusive(env
);
1067 /* We must squash the PSTATE.SS bit to zero unless both of the
1069 * 1. debug exceptions are currently disabled
1070 * 2. singlestep will be active in the EL we return to
1071 * We check 1 here and 2 after we've done the pstate/cpsr write() to
1072 * transition to the EL we're going to.
1074 if (arm_generate_debug_exceptions(env
)) {
1078 new_el
= el_from_spsr(spsr
);
1080 goto illegal_return
;
1083 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
1084 /* Disallow return to an EL which is unimplemented or higher
1085 * than the current one.
1087 goto illegal_return
;
1090 if (new_el
!= 0 && arm_el_is_aa64(env
, new_el
) != return_to_aa64
) {
1091 /* Return to an EL which is configured for a different register width */
1092 goto illegal_return
;
1095 if (new_el
== 2 && arm_is_secure_below_el3(env
)) {
1096 /* Return to the non-existent secure-EL2 */
1097 goto illegal_return
;
1100 if (new_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
1101 goto illegal_return
;
1104 qemu_mutex_lock_iothread();
1105 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
1106 qemu_mutex_unlock_iothread();
1108 if (!return_to_aa64
) {
1110 /* We do a raw CPSR write because aarch64_sync_64_to_32()
1111 * will sort the register banks out for us, and we've already
1112 * caught all the bad-mode cases in el_from_spsr().
1114 cpsr_write(env
, spsr
, ~0, CPSRWriteRaw
);
1115 if (!arm_singlestep_active(env
)) {
1116 env
->uncached_cpsr
&= ~PSTATE_SS
;
1118 aarch64_sync_64_to_32(env
);
1120 if (spsr
& CPSR_T
) {
1121 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x1;
1123 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x3;
1125 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1126 "AArch32 EL%d PC 0x%" PRIx32
"\n",
1127 cur_el
, new_el
, env
->regs
[15]);
1130 pstate_write(env
, spsr
);
1131 if (!arm_singlestep_active(env
)) {
1132 env
->pstate
&= ~PSTATE_SS
;
1134 aarch64_restore_sp(env
, new_el
);
1135 env
->pc
= env
->elr_el
[cur_el
];
1136 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1137 "AArch64 EL%d PC 0x%" PRIx64
"\n",
1138 cur_el
, new_el
, env
->pc
);
1141 * Note that cur_el can never be 0. If new_el is 0, then
1142 * el0_a64 is return_to_aa64, else el0_a64 is ignored.
1144 aarch64_sve_change_el(env
, cur_el
, new_el
, return_to_aa64
);
1146 qemu_mutex_lock_iothread();
1147 arm_call_el_change_hook(arm_env_get_cpu(env
));
1148 qemu_mutex_unlock_iothread();
1153 /* Illegal return events of various kinds have architecturally
1154 * mandated behaviour:
1155 * restore NZCV and DAIF from SPSR_ELx
1157 * restore PC from ELR_ELx
1158 * no change to exception level, execution state or stack pointer
1160 env
->pstate
|= PSTATE_IL
;
1161 env
->pc
= env
->elr_el
[cur_el
];
1162 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
1163 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
1164 pstate_write(env
, spsr
);
1165 if (!arm_singlestep_active(env
)) {
1166 env
->pstate
&= ~PSTATE_SS
;
1168 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal exception return at EL%d: "
1169 "resuming execution at 0x%" PRIx64
"\n", cur_el
, env
->pc
);
1172 /* Return true if the linked breakpoint entry lbn passes its checks */
1173 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
1175 CPUARMState
*env
= &cpu
->env
;
1176 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
1177 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
1178 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
1180 uint32_t contextidr
;
1182 /* Links to unimplemented or non-context aware breakpoints are
1183 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
1184 * as if linked to an UNKNOWN context-aware breakpoint (in which
1185 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
1186 * We choose the former.
1188 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1192 bcr
= env
->cp15
.dbgbcr
[lbn
];
1194 if (extract64(bcr
, 0, 1) == 0) {
1195 /* Linked breakpoint disabled : generate no events */
1199 bt
= extract64(bcr
, 20, 4);
1201 /* We match the whole register even if this is AArch32 using the
1202 * short descriptor format (in which case it holds both PROCID and ASID),
1203 * since we don't implement the optional v7 context ID masking.
1205 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1208 case 3: /* linked context ID match */
1209 if (arm_current_el(env
) > 1) {
1210 /* Context matches never fire in EL2 or (AArch64) EL3 */
1213 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1214 case 5: /* linked address mismatch (reserved in AArch64) */
1215 case 9: /* linked VMID match (reserved if no EL2) */
1216 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1218 /* Links to Unlinked context breakpoints must generate no
1219 * events; we choose to do the same for reserved values too.
1227 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1229 CPUARMState
*env
= &cpu
->env
;
1231 int pac
, hmc
, ssc
, wt
, lbn
;
1232 /* Note that for watchpoints the check is against the CPU security
1233 * state, not the S/NS attribute on the offending data access.
1235 bool is_secure
= arm_is_secure(env
);
1236 int access_el
= arm_current_el(env
);
1239 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1241 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1244 cr
= env
->cp15
.dbgwcr
[n
];
1245 if (wp
->hitattrs
.user
) {
1246 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1247 * match watchpoints as if they were accesses done at EL0, even if
1248 * the CPU is at EL1 or higher.
1253 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1255 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1258 cr
= env
->cp15
.dbgbcr
[n
];
1260 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1261 * enabled and that the address and access type match; for breakpoints
1262 * we know the address matched; check the remaining fields, including
1263 * linked breakpoints. We rely on WCR and BCR having the same layout
1264 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1265 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1266 * must act either like some valid combination or as if the watchpoint
1267 * were disabled. We choose the former, and use this together with
1268 * the fact that EL3 must always be Secure and EL2 must always be
1269 * Non-Secure to simplify the code slightly compared to the full
1270 * table in the ARM ARM.
1272 pac
= extract64(cr
, 1, 2);
1273 hmc
= extract64(cr
, 13, 1);
1274 ssc
= extract64(cr
, 14, 2);
1292 switch (access_el
) {
1300 if (extract32(pac
, 0, 1) == 0) {
1305 if (extract32(pac
, 1, 1) == 0) {
1310 g_assert_not_reached();
1313 wt
= extract64(cr
, 20, 1);
1314 lbn
= extract64(cr
, 16, 4);
1316 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1323 static bool check_watchpoints(ARMCPU
*cpu
)
1325 CPUARMState
*env
= &cpu
->env
;
1328 /* If watchpoints are disabled globally or we can't take debug
1329 * exceptions here then watchpoint firings are ignored.
1331 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1332 || !arm_generate_debug_exceptions(env
)) {
1336 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1337 if (bp_wp_matches(cpu
, n
, true)) {
1344 static bool check_breakpoints(ARMCPU
*cpu
)
1346 CPUARMState
*env
= &cpu
->env
;
1349 /* If breakpoints are disabled globally or we can't take debug
1350 * exceptions here then breakpoint firings are ignored.
1352 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1353 || !arm_generate_debug_exceptions(env
)) {
1357 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1358 if (bp_wp_matches(cpu
, n
, false)) {
1365 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1367 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1369 if (check_breakpoints(cpu
)) {
1370 HELPER(exception_internal(env
, EXCP_DEBUG
));
1374 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1376 /* Called by core code when a CPU watchpoint fires; need to check if this
1377 * is also an architectural watchpoint match.
1379 ARMCPU
*cpu
= ARM_CPU(cs
);
1381 return check_watchpoints(cpu
);
1384 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1386 ARMCPU
*cpu
= ARM_CPU(cs
);
1387 CPUARMState
*env
= &cpu
->env
;
1389 /* In BE32 system mode, target memory is stored byteswapped (on a
1390 * little-endian host system), and by the time we reach here (via an
1391 * opcode helper) the addresses of subword accesses have been adjusted
1392 * to account for that, which means that watchpoints will not match.
1393 * Undo the adjustment here.
1395 if (arm_sctlr_b(env
)) {
1398 } else if (len
== 2) {
1406 void arm_debug_excp_handler(CPUState
*cs
)
1408 /* Called by core code when a watchpoint or breakpoint fires;
1409 * need to check which one and raise the appropriate exception.
1411 ARMCPU
*cpu
= ARM_CPU(cs
);
1412 CPUARMState
*env
= &cpu
->env
;
1413 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1416 if (wp_hit
->flags
& BP_CPU
) {
1417 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1418 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1420 cs
->watchpoint_hit
= NULL
;
1422 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1423 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1424 raise_exception(env
, EXCP_DATA_ABORT
,
1425 syn_watchpoint(same_el
, 0, wnr
),
1426 arm_debug_target_el(env
));
1429 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1430 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1432 /* (1) GDB breakpoints should be handled first.
1433 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1434 * since singlestep is also done by generating a debug internal
1437 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1438 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1442 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1443 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
1444 * values to the guest that it shouldn't be able to see at its
1445 * exception/security level.
1447 env
->exception
.vaddress
= 0;
1448 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1449 syn_breakpoint(same_el
),
1450 arm_debug_target_el(env
));
1454 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1455 The only way to do that in TCG is a conditional branch, which clobbers
1456 all our temporaries. For now implement these as helper functions. */
1458 /* Similarly for variable shift instructions. */
1460 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1462 int shift
= i
& 0xff;
1469 } else if (shift
!= 0) {
1470 env
->CF
= (x
>> (32 - shift
)) & 1;
1476 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1478 int shift
= i
& 0xff;
1481 env
->CF
= (x
>> 31) & 1;
1485 } else if (shift
!= 0) {
1486 env
->CF
= (x
>> (shift
- 1)) & 1;
1492 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1494 int shift
= i
& 0xff;
1496 env
->CF
= (x
>> 31) & 1;
1497 return (int32_t)x
>> 31;
1498 } else if (shift
!= 0) {
1499 env
->CF
= (x
>> (shift
- 1)) & 1;
1500 return (int32_t)x
>> shift
;
1505 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1509 shift
= shift1
& 0x1f;
1512 env
->CF
= (x
>> 31) & 1;
1515 env
->CF
= (x
>> (shift
- 1)) & 1;
1516 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));