hw/arm/virt-acpi-build.c

   1 /* Support for generating ACPI tables and passing them to Guests
   2  *
   3  * ARM virt ACPI generation
   4  *
   5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
   6  * Copyright (C) 2006 Fabrice Bellard
   7  * Copyright (C) 2013 Red Hat Inc
   8  *
   9  * Author: Michael S. Tsirkin <mst@redhat.com>
  10  *
  11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  12  *
  13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24
  25  * You should have received a copy of the GNU General Public License along
  26  * with this program; if not, see <http://www.gnu.org/licenses/>.
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "qemu-common.h"
  31 #include "hw/arm/virt-acpi-build.h"
  32 #include "qemu/bitmap.h"
  33 #include "trace.h"
  34 #include "qom/cpu.h"
  35 #include "target-arm/cpu.h"
  36 #include "hw/acpi/acpi-defs.h"
  37 #include "hw/acpi/acpi.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/acpi/bios-linker-loader.h"
  40 #include "hw/loader.h"
  41 #include "hw/hw.h"
  42 #include "hw/acpi/aml-build.h"
  43 #include "hw/pci/pcie_host.h"
  44 #include "hw/pci/pci.h"
  45
  46 #define ARM_SPI_BASE 32
  47 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
  48
  49 typedef struct VirtAcpiCpuInfo {
  50     DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
  51 } VirtAcpiCpuInfo;
  52
  53 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
  54 {
  55     CPUState *cpu;
  56
  57     memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
  58     CPU_FOREACH(cpu) {
  59         set_bit(cpu->cpu_index, cpuinfo->found_cpus);
  60     }
  61 }
  62
  63 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
  64 {
  65     uint16_t i;
  66
  67     for (i = 0; i < smp_cpus; i++) {
  68         Aml *dev = aml_device("C%03x", i);
  69         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
  70         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
  71         aml_append(scope, dev);
  72     }
  73 }
  74
  75 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
  76                                            uint32_t uart_irq)
  77 {
  78     Aml *dev = aml_device("COM0");
  79     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
  80     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
  81
  82     Aml *crs = aml_resource_template();
  83     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
  84                                        uart_memmap->size, AML_READ_WRITE));
  85     aml_append(crs,
  86                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  87                              AML_EXCLUSIVE, &uart_irq, 1));
  88     aml_append(dev, aml_name_decl("_CRS", crs));
  89
  90     /* The _ADR entry is used to link this device to the UART described
  91      * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
  92      */
  93     aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
  94
  95     aml_append(scope, dev);
  96 }
  97
  98 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
  99 {
 100     Aml *dev, *crs;
 101     hwaddr base = flash_memmap->base;
 102     hwaddr size = flash_memmap->size / 2;
 103
 104     dev = aml_device("FLS0");
 105     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 106     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 107
 108     crs = aml_resource_template();
 109     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 110     aml_append(dev, aml_name_decl("_CRS", crs));
 111     aml_append(scope, dev);
 112
 113     dev = aml_device("FLS1");
 114     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 115     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
 116     crs = aml_resource_template();
 117     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
 118     aml_append(dev, aml_name_decl("_CRS", crs));
 119     aml_append(scope, dev);
 120 }
 121
 122 static void acpi_dsdt_add_virtio(Aml *scope,
 123                                  const MemMapEntry *virtio_mmio_memmap,
 124                                  uint32_t mmio_irq, int num)
 125 {
 126     hwaddr base = virtio_mmio_memmap->base;
 127     hwaddr size = virtio_mmio_memmap->size;
 128     int i;
 129
 130     for (i = 0; i < num; i++) {
 131         uint32_t irq = mmio_irq + i;
 132         Aml *dev = aml_device("VR%02u", i);
 133         aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
 134         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
 135
 136         Aml *crs = aml_resource_template();
 137         aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 138         aml_append(crs,
 139                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 140                                  AML_EXCLUSIVE, &irq, 1));
 141         aml_append(dev, aml_name_decl("_CRS", crs));
 142         aml_append(scope, dev);
 143         base += size;
 144     }
 145 }
 146
 147 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
 148                               uint32_t irq, bool use_highmem)
 149 {
 150     Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
 151     int i, bus_no;
 152     hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
 153     hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
 154     hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
 155     hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
 156     hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
 157     hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
 158     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
 159
 160     Aml *dev = aml_device("%s", "PCI0");
 161     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 162     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 163     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 164     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 165     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 166     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
 167     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 168     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 169
 170     /* Declare the PCI Routing Table. */
 171     Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
 172     for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
 173         for (i = 0; i < PCI_NUM_PINS; i++) {
 174             int gsi = (i + bus_no) % PCI_NUM_PINS;
 175             Aml *pkg = aml_package(4);
 176             aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
 177             aml_append(pkg, aml_int(i));
 178             aml_append(pkg, aml_name("GSI%d", gsi));
 179             aml_append(pkg, aml_int(0));
 180             aml_append(rt_pkg, pkg);
 181         }
 182     }
 183     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
 184
 185     /* Create GSI link device */
 186     for (i = 0; i < PCI_NUM_PINS; i++) {
 187         uint32_t irqs =  irq + i;
 188         Aml *dev_gsi = aml_device("GSI%d", i);
 189         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
 190         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
 191         crs = aml_resource_template();
 192         aml_append(crs,
 193                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 194                                  AML_EXCLUSIVE, &irqs, 1));
 195         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
 196         crs = aml_resource_template();
 197         aml_append(crs,
 198                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 199                                  AML_EXCLUSIVE, &irqs, 1));
 200         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
 201         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
 202         aml_append(dev_gsi, method);
 203         aml_append(dev, dev_gsi);
 204     }
 205
 206     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 207     aml_append(method, aml_return(aml_int(base_ecam)));
 208     aml_append(dev, method);
 209
 210     method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
 211     Aml *rbuf = aml_resource_template();
 212     aml_append(rbuf,
 213         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 214                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 215                             nr_pcie_buses));
 216     aml_append(rbuf,
 217         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 218                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
 219                          base_mmio + size_mmio - 1, 0x0000, size_mmio));
 220     aml_append(rbuf,
 221         aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 222                      AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
 223                      size_pio));
 224
 225     if (use_highmem) {
 226         hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
 227         hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
 228
 229         aml_append(rbuf,
 230             aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 231                              AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 232                              base_mmio_high, base_mmio_high, 0x0000,
 233                              size_mmio_high));
 234     }
 235
 236     aml_append(method, aml_name_decl("RBUF", rbuf));
 237     aml_append(method, aml_return(rbuf));
 238     aml_append(dev, method);
 239
 240     /* Declare an _OSC (OS Control Handoff) method */
 241     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
 242     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
 243     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
 244     aml_append(method,
 245         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
 246
 247     /* PCI Firmware Specification 3.0
 248      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
 249      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
 250      * identified by the Universal Unique IDentifier (UUID)
 251      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
 252      */
 253     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
 254     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 255     aml_append(ifctx,
 256         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
 257     aml_append(ifctx,
 258         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
 259     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
 260     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
 261     aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
 262                                 aml_name("CTRL")));
 263
 264     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
 265     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
 266                                  aml_name("CDW1")));
 267     aml_append(ifctx, ifctx1);
 268
 269     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
 270     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
 271                                  aml_name("CDW1")));
 272     aml_append(ifctx, ifctx1);
 273
 274     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
 275     aml_append(ifctx, aml_return(aml_arg(3)));
 276     aml_append(method, ifctx);
 277
 278     elsectx = aml_else();
 279     aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
 280                                   aml_name("CDW1")));
 281     aml_append(elsectx, aml_return(aml_arg(3)));
 282     aml_append(method, elsectx);
 283     aml_append(dev, method);
 284
 285     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 286
 287     /* PCI Firmware Specification 3.0
 288      * 4.6.1. _DSM for PCI Express Slot Information
 289      * The UUID in _DSM in this context is
 290      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 291      */
 292     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 293     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 294     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 295     uint8_t byte_list[1] = {1};
 296     buf = aml_buffer(1, byte_list);
 297     aml_append(ifctx1, aml_return(buf));
 298     aml_append(ifctx, ifctx1);
 299     aml_append(method, ifctx);
 300
 301     byte_list[0] = 0;
 302     buf = aml_buffer(1, byte_list);
 303     aml_append(method, aml_return(buf));
 304     aml_append(dev, method);
 305
 306     Aml *dev_rp0 = aml_device("%s", "RP0");
 307     aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
 308     aml_append(dev, dev_rp0);
 309     aml_append(scope, dev);
 310 }
 311
 312 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
 313                                            uint32_t gpio_irq)
 314 {
 315     Aml *dev = aml_device("GPO0");
 316     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
 317     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 318     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 319
 320     Aml *crs = aml_resource_template();
 321     aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
 322                                        AML_READ_WRITE));
 323     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 324                                   AML_EXCLUSIVE, &gpio_irq, 1));
 325     aml_append(dev, aml_name_decl("_CRS", crs));
 326
 327     Aml *aei = aml_resource_template();
 328     /* Pin 3 for power button */
 329     const uint32_t pin_list[1] = {3};
 330     aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
 331                                  AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
 332                                  "GPO0", NULL, 0));
 333     aml_append(dev, aml_name_decl("_AEI", aei));
 334
 335     /* _E03 is handle for power button */
 336     Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
 337     aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
 338                                   aml_int(0x80)));
 339     aml_append(dev, method);
 340     aml_append(scope, dev);
 341 }
 342
 343 static void acpi_dsdt_add_power_button(Aml *scope)
 344 {
 345     Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
 346     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
 347     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 348     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 349     aml_append(scope, dev);
 350 }
 351
 352 /* RSDP */
 353 static GArray *
 354 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
 355 {
 356     AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
 357
 358     bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
 359                              true /* fseg memory */);
 360
 361     memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
 362     memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
 363     rsdp->length = cpu_to_le32(sizeof(*rsdp));
 364     rsdp->revision = 0x02;
 365
 366     /* Point to RSDT */
 367     rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
 368     /* Address to be filled by Guest linker */
 369     bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
 370                                    ACPI_BUILD_TABLE_FILE,
 371                                    rsdp_table, &rsdp->rsdt_physical_address,
 372                                    sizeof rsdp->rsdt_physical_address);
 373     rsdp->checksum = 0;
 374     /* Checksum to be filled by Guest linker */
 375     bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
 376                                     rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
 377
 378     return rsdp_table;
 379 }
 380
 381 static void
 382 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 383 {
 384     AcpiSerialPortConsoleRedirection *spcr;
 385     const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART];
 386     int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE;
 387
 388     spcr = acpi_data_push(table_data, sizeof(*spcr));
 389
 390     spcr->interface_type = 0x3;    /* ARM PL011 UART */
 391
 392     spcr->base_address.space_id = AML_SYSTEM_MEMORY;
 393     spcr->base_address.bit_width = 8;
 394     spcr->base_address.bit_offset = 0;
 395     spcr->base_address.access_width = 1;
 396     spcr->base_address.address = cpu_to_le64(uart_memmap->base);
 397
 398     spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
 399     spcr->gsi = cpu_to_le32(irq);  /* Global System Interrupt */
 400
 401     spcr->baud = 3;                /* Baud Rate: 3 = 9600 */
 402     spcr->parity = 0;              /* No Parity */
 403     spcr->stopbits = 1;            /* 1 Stop bit */
 404     spcr->flowctrl = (1 << 1);     /* Bit[1] = RTS/CTS hardware flow control */
 405     spcr->term_type = 0;           /* Terminal Type: 0 = VT100 */
 406
 407     spcr->pci_device_id = 0xffff;  /* PCI Device ID: not a PCI device */
 408     spcr->pci_vendor_id = 0xffff;  /* PCI Vendor ID: not a PCI device */
 409
 410     build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2,
 411                  NULL);
 412 }
 413
 414 static void
 415 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 416 {
 417     AcpiTableMcfg *mcfg;
 418     const MemMapEntry *memmap = guest_info->memmap;
 419     int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
 420
 421     mcfg = acpi_data_push(table_data, len);
 422     mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
 423
 424     /* Only a single allocation so no need to play with segments */
 425     mcfg->allocation[0].pci_segment = cpu_to_le16(0);
 426     mcfg->allocation[0].start_bus_number = 0;
 427     mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
 428                                           / PCIE_MMCFG_SIZE_MIN) - 1;
 429
 430     build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL);
 431 }
 432
 433 /* GTDT */
 434 static void
 435 build_gtdt(GArray *table_data, GArray *linker)
 436 {
 437     int gtdt_start = table_data->len;
 438     AcpiGenericTimerTable *gtdt;
 439
 440     gtdt = acpi_data_push(table_data, sizeof *gtdt);
 441     /* The interrupt values are the same with the device tree when adding 16 */
 442     gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16;
 443     gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
 444
 445     gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16;
 446     gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE | ACPI_GTDT_ALWAYS_ON;
 447
 448     gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16;
 449     gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
 450
 451     gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16;
 452     gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
 453
 454     build_header(linker, table_data,
 455                  (void *)(table_data->data + gtdt_start), "GTDT",
 456                  table_data->len - gtdt_start, 2, NULL);
 457 }
 458
 459 /* MADT */
 460 static void
 461 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
 462            VirtAcpiCpuInfo *cpuinfo)
 463 {
 464     int madt_start = table_data->len;
 465     const MemMapEntry *memmap = guest_info->memmap;
 466     const int *irqmap = guest_info->irqmap;
 467     AcpiMultipleApicTable *madt;
 468     AcpiMadtGenericDistributor *gicd;
 469     AcpiMadtGenericMsiFrame *gic_msi;
 470     int i;
 471
 472     madt = acpi_data_push(table_data, sizeof *madt);
 473
 474     gicd = acpi_data_push(table_data, sizeof *gicd);
 475     gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
 476     gicd->length = sizeof(*gicd);
 477     gicd->base_address = memmap[VIRT_GIC_DIST].base;
 478
 479     for (i = 0; i < guest_info->smp_cpus; i++) {
 480         AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
 481                                                      sizeof *gicc);
 482         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
 483
 484         gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
 485         gicc->length = sizeof(*gicc);
 486         if (guest_info->gic_version == 2) {
 487             gicc->base_address = memmap[VIRT_GIC_CPU].base;
 488         }
 489         gicc->cpu_interface_number = i;
 490         gicc->arm_mpidr = armcpu->mp_affinity;
 491         gicc->uid = i;
 492         if (test_bit(i, cpuinfo->found_cpus)) {
 493             gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
 494         }
 495     }
 496
 497     if (guest_info->gic_version == 3) {
 498         AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
 499                                                          sizeof *gicr);
 500
 501         gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
 502         gicr->length = sizeof(*gicr);
 503         gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
 504         gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
 505     } else {
 506         gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
 507         gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
 508         gic_msi->length = sizeof(*gic_msi);
 509         gic_msi->gic_msi_frame_id = 0;
 510         gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
 511         gic_msi->flags = cpu_to_le32(1);
 512         gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
 513         gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
 514     }
 515
 516     build_header(linker, table_data,
 517                  (void *)(table_data->data + madt_start), "APIC",
 518                  table_data->len - madt_start, 3, NULL);
 519 }
 520
 521 /* FADT */
 522 static void
 523 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
 524 {
 525     AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
 526
 527     /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
 528     fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
 529     fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
 530                                        (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
 531
 532     /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
 533     fadt->minor_revision = 0x1;
 534
 535     fadt->dsdt = cpu_to_le32(dsdt);
 536     /* DSDT address to be filled by Guest linker */
 537     bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
 538                                    ACPI_BUILD_TABLE_FILE,
 539                                    table_data, &fadt->dsdt,
 540                                    sizeof fadt->dsdt);
 541
 542     build_header(linker, table_data,
 543                  (void *)fadt, "FACP", sizeof(*fadt), 5, NULL);
 544 }
 545
 546 /* DSDT */
 547 static void
 548 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 549 {
 550     Aml *scope, *dsdt;
 551     const MemMapEntry *memmap = guest_info->memmap;
 552     const int *irqmap = guest_info->irqmap;
 553
 554     dsdt = init_aml_allocator();
 555     /* Reserve space for header */
 556     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
 557
 558     /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
 559      * While UEFI can use libfdt to disable the RTC device node in the DTB that
 560      * it passes to the OS, it cannot modify AML. Therefore, we won't generate
 561      * the RTC ACPI device at all when using UEFI.
 562      */
 563     scope = aml_scope("\\_SB");
 564     acpi_dsdt_add_cpus(scope, guest_info->smp_cpus);
 565     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
 566                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
 567     acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 568     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
 569                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 570     acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
 571                       guest_info->use_highmem);
 572     acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
 573                        (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
 574     acpi_dsdt_add_power_button(scope);
 575
 576     aml_append(dsdt, scope);
 577
 578     /* copy AML table into ACPI tables blob and patch header there */
 579     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
 580     build_header(linker, table_data,
 581         (void *)(table_data->data + table_data->len - dsdt->buf->len),
 582         "DSDT", dsdt->buf->len, 2, NULL);
 583     free_aml_allocator();
 584 }
 585
 586 typedef
 587 struct AcpiBuildState {
 588     /* Copy of table in RAM (for patching). */
 589     MemoryRegion *table_mr;
 590     MemoryRegion *rsdp_mr;
 591     MemoryRegion *linker_mr;
 592     /* Is table patched? */
 593     bool patched;
 594     VirtGuestInfo *guest_info;
 595 } AcpiBuildState;
 596
 597 static
 598 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
 599 {
 600     GArray *table_offsets;
 601     unsigned dsdt, rsdt;
 602     VirtAcpiCpuInfo cpuinfo;
 603     GArray *tables_blob = tables->table_data;
 604
 605     virt_acpi_get_cpu_info(&cpuinfo);
 606
 607     table_offsets = g_array_new(false, true /* clear */,
 608                                         sizeof(uint32_t));
 609
 610     bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
 611                              64, false /* high memory */);
 612
 613     /*
 614      * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
 615      * RSDP
 616      * RSDT
 617      * FADT
 618      * GTDT
 619      * MADT
 620      * MCFG
 621      * DSDT
 622      */
 623
 624     /* DSDT is pointed to by FADT */
 625     dsdt = tables_blob->len;
 626     build_dsdt(tables_blob, tables->linker, guest_info);
 627
 628     /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
 629     acpi_add_table(table_offsets, tables_blob);
 630     build_fadt(tables_blob, tables->linker, dsdt);
 631
 632     acpi_add_table(table_offsets, tables_blob);
 633     build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
 634
 635     acpi_add_table(table_offsets, tables_blob);
 636     build_gtdt(tables_blob, tables->linker);
 637
 638     acpi_add_table(table_offsets, tables_blob);
 639     build_mcfg(tables_blob, tables->linker, guest_info);
 640
 641     acpi_add_table(table_offsets, tables_blob);
 642     build_spcr(tables_blob, tables->linker, guest_info);
 643
 644     /* RSDT is pointed to by RSDP */
 645     rsdt = tables_blob->len;
 646     build_rsdt(tables_blob, tables->linker, table_offsets);
 647
 648     /* RSDP is in FSEG memory, so allocate it separately */
 649     build_rsdp(tables->rsdp, tables->linker, rsdt);
 650
 651     /* Cleanup memory that's no longer used. */
 652     g_array_free(table_offsets, true);
 653 }
 654
 655 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
 656 {
 657     uint32_t size = acpi_data_len(data);
 658
 659     /* Make sure RAM size is correct - in case it got changed
 660      * e.g. by migration */
 661     memory_region_ram_resize(mr, size, &error_abort);
 662
 663     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
 664     memory_region_set_dirty(mr, 0, size);
 665 }
 666
 667 static void virt_acpi_build_update(void *build_opaque)
 668 {
 669     AcpiBuildState *build_state = build_opaque;
 670     AcpiBuildTables tables;
 671
 672     /* No state to update or already patched? Nothing to do. */
 673     if (!build_state || build_state->patched) {
 674         return;
 675     }
 676     build_state->patched = true;
 677
 678     acpi_build_tables_init(&tables);
 679
 680     virt_acpi_build(build_state->guest_info, &tables);
 681
 682     acpi_ram_update(build_state->table_mr, tables.table_data);
 683     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
 684     acpi_ram_update(build_state->linker_mr, tables.linker);
 685
 686
 687     acpi_build_tables_cleanup(&tables, true);
 688 }
 689
 690 static void virt_acpi_build_reset(void *build_opaque)
 691 {
 692     AcpiBuildState *build_state = build_opaque;
 693     build_state->patched = false;
 694 }
 695
 696 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
 697                                        GArray *blob, const char *name,
 698                                        uint64_t max_size)
 699 {
 700     return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
 701                         name, virt_acpi_build_update, build_state);
 702 }
 703
 704 static const VMStateDescription vmstate_virt_acpi_build = {
 705     .name = "virt_acpi_build",
 706     .version_id = 1,
 707     .minimum_version_id = 1,
 708     .fields = (VMStateField[]) {
 709         VMSTATE_BOOL(patched, AcpiBuildState),
 710         VMSTATE_END_OF_LIST()
 711     },
 712 };
 713
 714 void virt_acpi_setup(VirtGuestInfo *guest_info)
 715 {
 716     AcpiBuildTables tables;
 717     AcpiBuildState *build_state;
 718
 719     if (!guest_info->fw_cfg) {
 720         trace_virt_acpi_setup();
 721         return;
 722     }
 723
 724     if (!acpi_enabled) {
 725         trace_virt_acpi_setup();
 726         return;
 727     }
 728
 729     build_state = g_malloc0(sizeof *build_state);
 730     build_state->guest_info = guest_info;
 731
 732     acpi_build_tables_init(&tables);
 733     virt_acpi_build(build_state->guest_info, &tables);
 734
 735     /* Now expose it all to Guest */
 736     build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
 737                                                ACPI_BUILD_TABLE_FILE,
 738                                                ACPI_BUILD_TABLE_MAX_SIZE);
 739     assert(build_state->table_mr != NULL);
 740
 741     build_state->linker_mr =
 742         acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
 743
 744     fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
 745                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
 746
 747     build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
 748                                               ACPI_BUILD_RSDP_FILE, 0);
 749
 750     qemu_register_reset(virt_acpi_build_reset, build_state);
 751     virt_acpi_build_reset(build_state);
 752     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
 753
 754     /* Cleanup tables but don't free the memory: we track it
 755      * in build_state.
 756      */
 757     acpi_build_tables_cleanup(&tables, false);
 758 }