hw/block/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "qemu/osdep.h"
  40 #include "hw/block/block.h"
  41 #include "hw/block/flash.h"
  42 #include "hw/qdev-properties.h"
  43 #include "hw/qdev-properties-system.h"
  44 #include "sysemu/block-backend.h"
  45 #include "qapi/error.h"
  46 #include "qemu/error-report.h"
  47 #include "qemu/bitops.h"
  48 #include "qemu/error-report.h"
  49 #include "qemu/host-utils.h"
  50 #include "qemu/log.h"
  51 #include "qemu/module.h"
  52 #include "qemu/option.h"
  53 #include "hw/sysbus.h"
  54 #include "migration/vmstate.h"
  55 #include "sysemu/blockdev.h"
  56 #include "sysemu/runstate.h"
  57 #include "trace.h"
  58
  59 /* #define PFLASH_DEBUG */
  60 #ifdef PFLASH_DEBUG
  61 #define DPRINTF(fmt, ...)                                   \
  62 do {                                                        \
  63     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  64 } while (0)
  65 #else
  66 #define DPRINTF(fmt, ...) do { } while (0)
  67 #endif
  68
  69 #define PFLASH_BE          0
  70 #define PFLASH_SECURE      1
  71
  72 struct PFlashCFI01 {
  73     /*< private >*/
  74     SysBusDevice parent_obj;
  75     /*< public >*/
  76
  77     BlockBackend *blk;
  78     uint32_t nb_blocs;
  79     uint64_t sector_len;
  80     uint8_t bank_width;
  81     uint8_t device_width; /* If 0, device width not specified. */
  82     uint8_t max_device_width;  /* max device width in bytes */
  83     uint32_t features;
  84     uint8_t wcycle; /* if 0, the flash is read normally */
  85     int ro;
  86     uint8_t cmd;
  87     uint8_t status;
  88     uint16_t ident0;
  89     uint16_t ident1;
  90     uint16_t ident2;
  91     uint16_t ident3;
  92     uint8_t cfi_table[0x52];
  93     uint64_t counter;
  94     unsigned int writeblock_size;
  95     MemoryRegion mem;
  96     char *name;
  97     void *storage;
  98     VMChangeStateEntry *vmstate;
  99     bool old_multiple_chip_handling;
 100 };
 101
 102 static int pflash_post_load(void *opaque, int version_id);
 103
 104 static const VMStateDescription vmstate_pflash = {
 105     .name = "pflash_cfi01",
 106     .version_id = 1,
 107     .minimum_version_id = 1,
 108     .post_load = pflash_post_load,
 109     .fields = (VMStateField[]) {
 110         VMSTATE_UINT8(wcycle, PFlashCFI01),
 111         VMSTATE_UINT8(cmd, PFlashCFI01),
 112         VMSTATE_UINT8(status, PFlashCFI01),
 113         VMSTATE_UINT64(counter, PFlashCFI01),
 114         VMSTATE_END_OF_LIST()
 115     }
 116 };
 117
 118 /*
 119  * Perform a CFI query based on the bank width of the flash.
 120  * If this code is called we know we have a device_width set for
 121  * this flash.
 122  */
 123 static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
 124 {
 125     int i;
 126     uint32_t resp = 0;
 127     hwaddr boff;
 128
 129     /*
 130      * Adjust incoming offset to match expected device-width
 131      * addressing. CFI query addresses are always specified in terms of
 132      * the maximum supported width of the device.  This means that x8
 133      * devices and x8/x16 devices in x8 mode behave differently.  For
 134      * devices that are not used at their max width, we will be
 135      * provided with addresses that use higher address bits than
 136      * expected (based on the max width), so we will shift them lower
 137      * so that they will match the addresses used when
 138      * device_width==max_device_width.
 139      */
 140     boff = offset >> (ctz32(pfl->bank_width) +
 141                       ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
 142
 143     if (boff >= sizeof(pfl->cfi_table)) {
 144         return 0;
 145     }
 146     /*
 147      * Now we will construct the CFI response generated by a single
 148      * device, then replicate that for all devices that make up the
 149      * bus.  For wide parts used in x8 mode, CFI query responses
 150      * are different than native byte-wide parts.
 151      */
 152     resp = pfl->cfi_table[boff];
 153     if (pfl->device_width != pfl->max_device_width) {
 154         /* The only case currently supported is x8 mode for a
 155          * wider part.
 156          */
 157         if (pfl->device_width != 1 || pfl->bank_width > 4) {
 158             DPRINTF("%s: Unsupported device configuration: "
 159                     "device_width=%d, max_device_width=%d\n",
 160                     __func__, pfl->device_width,
 161                     pfl->max_device_width);
 162             return 0;
 163         }
 164         /* CFI query data is repeated, rather than zero padded for
 165          * wide devices used in x8 mode.
 166          */
 167         for (i = 1; i < pfl->max_device_width; i++) {
 168             resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]);
 169         }
 170     }
 171     /* Replicate responses for each device in bank. */
 172     if (pfl->device_width < pfl->bank_width) {
 173         for (i = pfl->device_width;
 174              i < pfl->bank_width; i += pfl->device_width) {
 175             resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp);
 176         }
 177     }
 178
 179     return resp;
 180 }
 181
 182
 183
 184 /* Perform a device id query based on the bank width of the flash. */
 185 static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
 186 {
 187     int i;
 188     uint32_t resp;
 189     hwaddr boff;
 190
 191     /*
 192      * Adjust incoming offset to match expected device-width
 193      * addressing. Device ID read addresses are always specified in
 194      * terms of the maximum supported width of the device.  This means
 195      * that x8 devices and x8/x16 devices in x8 mode behave
 196      * differently. For devices that are not used at their max width,
 197      * we will be provided with addresses that use higher address bits
 198      * than expected (based on the max width), so we will shift them
 199      * lower so that they will match the addresses used when
 200      * device_width==max_device_width.
 201      */
 202     boff = offset >> (ctz32(pfl->bank_width) +
 203                       ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
 204
 205     /*
 206      * Mask off upper bits which may be used in to query block
 207      * or sector lock status at other addresses.
 208      * Offsets 2/3 are block lock status, is not emulated.
 209      */
 210     switch (boff & 0xFF) {
 211     case 0:
 212         resp = pfl->ident0;
 213         trace_pflash_manufacturer_id(resp);
 214         break;
 215     case 1:
 216         resp = pfl->ident1;
 217         trace_pflash_device_id(resp);
 218         break;
 219     default:
 220         trace_pflash_device_info(offset);
 221         return 0;
 222     }
 223     /* Replicate responses for each device in bank. */
 224     if (pfl->device_width < pfl->bank_width) {
 225         for (i = pfl->device_width;
 226               i < pfl->bank_width; i += pfl->device_width) {
 227             resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp);
 228         }
 229     }
 230
 231     return resp;
 232 }
 233
 234 static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset,
 235                                  int width, int be)
 236 {
 237     uint8_t *p;
 238     uint32_t ret;
 239
 240     p = pfl->storage;
 241     switch (width) {
 242     case 1:
 243         ret = p[offset];
 244         break;
 245     case 2:
 246         if (be) {
 247             ret = p[offset] << 8;
 248             ret |= p[offset + 1];
 249         } else {
 250             ret = p[offset];
 251             ret |= p[offset + 1] << 8;
 252         }
 253         break;
 254     case 4:
 255         if (be) {
 256             ret = p[offset] << 24;
 257             ret |= p[offset + 1] << 16;
 258             ret |= p[offset + 2] << 8;
 259             ret |= p[offset + 3];
 260         } else {
 261             ret = p[offset];
 262             ret |= p[offset + 1] << 8;
 263             ret |= p[offset + 2] << 16;
 264             ret |= p[offset + 3] << 24;
 265         }
 266         break;
 267     default:
 268         DPRINTF("BUG in %s\n", __func__);
 269         abort();
 270     }
 271     trace_pflash_data_read(offset, width, ret);
 272     return ret;
 273 }
 274
 275 static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
 276                             int width, int be)
 277 {
 278     hwaddr boff;
 279     uint32_t ret;
 280
 281     ret = -1;
 282     switch (pfl->cmd) {
 283     default:
 284         /* This should never happen : reset state & treat it as a read */
 285         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 286         pfl->wcycle = 0;
 287         /*
 288          * The command 0x00 is not assigned by the CFI open standard,
 289          * but QEMU historically uses it for the READ_ARRAY command (0xff).
 290          */
 291         pfl->cmd = 0x00;
 292         /* fall through to read code */
 293     case 0x00: /* This model reset value for READ_ARRAY (not CFI compliant) */
 294         /* Flash area read */
 295         ret = pflash_data_read(pfl, offset, width, be);
 296         break;
 297     case 0x10: /* Single byte program */
 298     case 0x20: /* Block erase */
 299     case 0x28: /* Block erase */
 300     case 0x40: /* single byte program */
 301     case 0x50: /* Clear status register */
 302     case 0x60: /* Block /un)lock */
 303     case 0x70: /* Status Register */
 304     case 0xe8: /* Write block */
 305         /*
 306          * Status register read.  Return status from each device in
 307          * bank.
 308          */
 309         ret = pfl->status;
 310         if (pfl->device_width && width > pfl->device_width) {
 311             int shift = pfl->device_width * 8;
 312             while (shift + pfl->device_width * 8 <= width * 8) {
 313                 ret |= pfl->status << shift;
 314                 shift += pfl->device_width * 8;
 315             }
 316         } else if (!pfl->device_width && width > 2) {
 317             /*
 318              * Handle 32 bit flash cases where device width is not
 319              * set. (Existing behavior before device width added.)
 320              */
 321             ret |= pfl->status << 16;
 322         }
 323         DPRINTF("%s: status %x\n", __func__, ret);
 324         break;
 325     case 0x90:
 326         if (!pfl->device_width) {
 327             /* Preserve old behavior if device width not specified */
 328             boff = offset & 0xFF;
 329             if (pfl->bank_width == 2) {
 330                 boff = boff >> 1;
 331             } else if (pfl->bank_width == 4) {
 332                 boff = boff >> 2;
 333             }
 334
 335             switch (boff) {
 336             case 0:
 337                 ret = pfl->ident0 << 8 | pfl->ident1;
 338                 trace_pflash_manufacturer_id(ret);
 339                 break;
 340             case 1:
 341                 ret = pfl->ident2 << 8 | pfl->ident3;
 342                 trace_pflash_device_id(ret);
 343                 break;
 344             default:
 345                 trace_pflash_device_info(boff);
 346                 ret = 0;
 347                 break;
 348             }
 349         } else {
 350             /*
 351              * If we have a read larger than the bank_width, combine multiple
 352              * manufacturer/device ID queries into a single response.
 353              */
 354             int i;
 355             for (i = 0; i < width; i += pfl->bank_width) {
 356                 ret = deposit32(ret, i * 8, pfl->bank_width * 8,
 357                                 pflash_devid_query(pfl,
 358                                                  offset + i * pfl->bank_width));
 359             }
 360         }
 361         break;
 362     case 0x98: /* Query mode */
 363         if (!pfl->device_width) {
 364             /* Preserve old behavior if device width not specified */
 365             boff = offset & 0xFF;
 366             if (pfl->bank_width == 2) {
 367                 boff = boff >> 1;
 368             } else if (pfl->bank_width == 4) {
 369                 boff = boff >> 2;
 370             }
 371
 372             if (boff < sizeof(pfl->cfi_table)) {
 373                 ret = pfl->cfi_table[boff];
 374             } else {
 375                 ret = 0;
 376             }
 377         } else {
 378             /*
 379              * If we have a read larger than the bank_width, combine multiple
 380              * CFI queries into a single response.
 381              */
 382             int i;
 383             for (i = 0; i < width; i += pfl->bank_width) {
 384                 ret = deposit32(ret, i * 8, pfl->bank_width * 8,
 385                                 pflash_cfi_query(pfl,
 386                                                  offset + i * pfl->bank_width));
 387             }
 388         }
 389
 390         break;
 391     }
 392     trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle);
 393
 394     return ret;
 395 }
 396
 397 /* update flash content on disk */
 398 static void pflash_update(PFlashCFI01 *pfl, int offset,
 399                           int size)
 400 {
 401     int offset_end;
 402     int ret;
 403     if (pfl->blk) {
 404         offset_end = offset + size;
 405         /* widen to sector boundaries */
 406         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 407         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 408         ret = blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 409                    offset_end - offset, 0);
 410         if (ret < 0) {
 411             /* TODO set error bit in status */
 412             error_report("Could not update PFLASH: %s", strerror(-ret));
 413         }
 414     }
 415 }
 416
 417 static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset,
 418                                      uint32_t value, int width, int be)
 419 {
 420     uint8_t *p = pfl->storage;
 421
 422     trace_pflash_data_write(offset, width, value, pfl->counter);
 423     switch (width) {
 424     case 1:
 425         p[offset] = value;
 426         break;
 427     case 2:
 428         if (be) {
 429             p[offset] = value >> 8;
 430             p[offset + 1] = value;
 431         } else {
 432             p[offset] = value;
 433             p[offset + 1] = value >> 8;
 434         }
 435         break;
 436     case 4:
 437         if (be) {
 438             p[offset] = value >> 24;
 439             p[offset + 1] = value >> 16;
 440             p[offset + 2] = value >> 8;
 441             p[offset + 3] = value;
 442         } else {
 443             p[offset] = value;
 444             p[offset + 1] = value >> 8;
 445             p[offset + 2] = value >> 16;
 446             p[offset + 3] = value >> 24;
 447         }
 448         break;
 449     }
 450
 451 }
 452
 453 static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
 454                          uint32_t value, int width, int be)
 455 {
 456     uint8_t *p;
 457     uint8_t cmd;
 458
 459     cmd = value;
 460
 461     trace_pflash_io_write(offset, width, value, pfl->wcycle);
 462     if (!pfl->wcycle) {
 463         /* Set the device in I/O access mode */
 464         memory_region_rom_device_set_romd(&pfl->mem, false);
 465     }
 466
 467     switch (pfl->wcycle) {
 468     case 0:
 469         /* read mode */
 470         switch (cmd) {
 471         case 0x00: /* This model reset value for READ_ARRAY (not CFI) */
 472             goto mode_read_array;
 473         case 0x10: /* Single Byte Program */
 474         case 0x40: /* Single Byte Program */
 475             DPRINTF("%s: Single Byte Program\n", __func__);
 476             break;
 477         case 0x20: /* Block erase */
 478             p = pfl->storage;
 479             offset &= ~(pfl->sector_len - 1);
 480
 481             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
 482                     __func__, offset, (unsigned)pfl->sector_len);
 483
 484             if (!pfl->ro) {
 485                 memset(p + offset, 0xff, pfl->sector_len);
 486                 pflash_update(pfl, offset, pfl->sector_len);
 487             } else {
 488                 pfl->status |= 0x20; /* Block erase error */
 489             }
 490             pfl->status |= 0x80; /* Ready! */
 491             break;
 492         case 0x50: /* Clear status bits */
 493             DPRINTF("%s: Clear status bits\n", __func__);
 494             pfl->status = 0x0;
 495             goto mode_read_array;
 496         case 0x60: /* Block (un)lock */
 497             DPRINTF("%s: Block unlock\n", __func__);
 498             break;
 499         case 0x70: /* Status Register */
 500             DPRINTF("%s: Read status register\n", __func__);
 501             pfl->cmd = cmd;
 502             return;
 503         case 0x90: /* Read Device ID */
 504             DPRINTF("%s: Read Device information\n", __func__);
 505             pfl->cmd = cmd;
 506             return;
 507         case 0x98: /* CFI query */
 508             DPRINTF("%s: CFI query\n", __func__);
 509             break;
 510         case 0xe8: /* Write to buffer */
 511             DPRINTF("%s: Write to buffer\n", __func__);
 512             /* FIXME should save @offset, @width for case 1+ */
 513             qemu_log_mask(LOG_UNIMP,
 514                           "%s: Write to buffer emulation is flawed\n",
 515                           __func__);
 516             pfl->status |= 0x80; /* Ready! */
 517             break;
 518         case 0xf0: /* Probe for AMD flash */
 519             DPRINTF("%s: Probe for AMD flash\n", __func__);
 520             goto mode_read_array;
 521         case 0xff: /* Read Array */
 522             DPRINTF("%s: Read array mode\n", __func__);
 523             goto mode_read_array;
 524         default:
 525             goto error_flash;
 526         }
 527         pfl->wcycle++;
 528         pfl->cmd = cmd;
 529         break;
 530     case 1:
 531         switch (pfl->cmd) {
 532         case 0x10: /* Single Byte Program */
 533         case 0x40: /* Single Byte Program */
 534             DPRINTF("%s: Single Byte Program\n", __func__);
 535             if (!pfl->ro) {
 536                 pflash_data_write(pfl, offset, value, width, be);
 537                 pflash_update(pfl, offset, width);
 538             } else {
 539                 pfl->status |= 0x10; /* Programming error */
 540             }
 541             pfl->status |= 0x80; /* Ready! */
 542             pfl->wcycle = 0;
 543         break;
 544         case 0x20: /* Block erase */
 545         case 0x28:
 546             if (cmd == 0xd0) { /* confirm */
 547                 pfl->wcycle = 0;
 548                 pfl->status |= 0x80;
 549             } else if (cmd == 0xff) { /* Read Array */
 550                 goto mode_read_array;
 551             } else
 552                 goto error_flash;
 553
 554             break;
 555         case 0xe8:
 556             /*
 557              * Mask writeblock size based on device width, or bank width if
 558              * device width not specified.
 559              */
 560             /* FIXME check @offset, @width */
 561             if (pfl->device_width) {
 562                 value = extract32(value, 0, pfl->device_width * 8);
 563             } else {
 564                 value = extract32(value, 0, pfl->bank_width * 8);
 565             }
 566             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 567             pfl->counter = value;
 568             pfl->wcycle++;
 569             break;
 570         case 0x60:
 571             if (cmd == 0xd0) {
 572                 pfl->wcycle = 0;
 573                 pfl->status |= 0x80;
 574             } else if (cmd == 0x01) {
 575                 pfl->wcycle = 0;
 576                 pfl->status |= 0x80;
 577             } else if (cmd == 0xff) { /* Read Array */
 578                 goto mode_read_array;
 579             } else {
 580                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 581                 goto mode_read_array;
 582             }
 583             break;
 584         case 0x98:
 585             if (cmd == 0xff) { /* Read Array */
 586                 goto mode_read_array;
 587             } else {
 588                 DPRINTF("%s: leaving query mode\n", __func__);
 589             }
 590             break;
 591         default:
 592             goto error_flash;
 593         }
 594         break;
 595     case 2:
 596         switch (pfl->cmd) {
 597         case 0xe8: /* Block write */
 598             /* FIXME check @offset, @width */
 599             if (!pfl->ro) {
 600                 /*
 601                  * FIXME writing straight to memory is *wrong*.  We
 602                  * should write to a buffer, and flush it to memory
 603                  * only on confirm command (see below).
 604                  */
 605                 pflash_data_write(pfl, offset, value, width, be);
 606             } else {
 607                 pfl->status |= 0x10; /* Programming error */
 608             }
 609
 610             pfl->status |= 0x80;
 611
 612             if (!pfl->counter) {
 613                 hwaddr mask = pfl->writeblock_size - 1;
 614                 mask = ~mask;
 615
 616                 DPRINTF("%s: block write finished\n", __func__);
 617                 pfl->wcycle++;
 618                 if (!pfl->ro) {
 619                     /* Flush the entire write buffer onto backing storage.  */
 620                     /* FIXME premature! */
 621                     pflash_update(pfl, offset & mask, pfl->writeblock_size);
 622                 } else {
 623                     pfl->status |= 0x10; /* Programming error */
 624                 }
 625             }
 626
 627             pfl->counter--;
 628             break;
 629         default:
 630             goto error_flash;
 631         }
 632         break;
 633     case 3: /* Confirm mode */
 634         switch (pfl->cmd) {
 635         case 0xe8: /* Block write */
 636             if (cmd == 0xd0) {
 637                 /* FIXME this is where we should write out the buffer */
 638                 pfl->wcycle = 0;
 639                 pfl->status |= 0x80;
 640             } else {
 641                 qemu_log_mask(LOG_UNIMP,
 642                     "%s: Aborting write to buffer not implemented,"
 643                     " the data is already written to storage!\n"
 644                     "Flash device reset into READ mode.\n",
 645                     __func__);
 646                 goto mode_read_array;
 647             }
 648             break;
 649         default:
 650             goto error_flash;
 651         }
 652         break;
 653     default:
 654         /* Should never happen */
 655         DPRINTF("%s: invalid write state\n",  __func__);
 656         goto mode_read_array;
 657     }
 658     return;
 659
 660  error_flash:
 661     qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
 662                   "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
 663                   "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
 664
 665  mode_read_array:
 666     trace_pflash_reset();
 667     memory_region_rom_device_set_romd(&pfl->mem, true);
 668     pfl->wcycle = 0;
 669     pfl->cmd = 0x00; /* This model reset value for READ_ARRAY (not CFI) */
 670 }
 671
 672
 673 static MemTxResult pflash_mem_read_with_attrs(void *opaque, hwaddr addr, uint64_t *value,
 674                                               unsigned len, MemTxAttrs attrs)
 675 {
 676     PFlashCFI01 *pfl = opaque;
 677     bool be = !!(pfl->features & (1 << PFLASH_BE));
 678
 679     if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) {
 680         *value = pflash_data_read(opaque, addr, len, be);
 681     } else {
 682         *value = pflash_read(opaque, addr, len, be);
 683     }
 684     return MEMTX_OK;
 685 }
 686
 687 static MemTxResult pflash_mem_write_with_attrs(void *opaque, hwaddr addr, uint64_t value,
 688                                                unsigned len, MemTxAttrs attrs)
 689 {
 690     PFlashCFI01 *pfl = opaque;
 691     bool be = !!(pfl->features & (1 << PFLASH_BE));
 692
 693     if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) {
 694         return MEMTX_ERROR;
 695     } else {
 696         pflash_write(opaque, addr, value, len, be);
 697         return MEMTX_OK;
 698     }
 699 }
 700
 701 static const MemoryRegionOps pflash_cfi01_ops = {
 702     .read_with_attrs = pflash_mem_read_with_attrs,
 703     .write_with_attrs = pflash_mem_write_with_attrs,
 704     .endianness = DEVICE_NATIVE_ENDIAN,
 705 };
 706
 707 static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl)
 708 {
 709     uint64_t blocks_per_device, sector_len_per_device, device_len;
 710     int num_devices;
 711
 712     /*
 713      * These are only used to expose the parameters of each device
 714      * in the cfi_table[].
 715      */
 716     num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1;
 717     if (pfl->old_multiple_chip_handling) {
 718         blocks_per_device = pfl->nb_blocs / num_devices;
 719         sector_len_per_device = pfl->sector_len;
 720     } else {
 721         blocks_per_device = pfl->nb_blocs;
 722         sector_len_per_device = pfl->sector_len / num_devices;
 723     }
 724     device_len = sector_len_per_device * blocks_per_device;
 725
 726     /* Hardcoded CFI table */
 727     /* Standard "QRY" string */
 728     pfl->cfi_table[0x10] = 'Q';
 729     pfl->cfi_table[0x11] = 'R';
 730     pfl->cfi_table[0x12] = 'Y';
 731     /* Command set (Intel) */
 732     pfl->cfi_table[0x13] = 0x01;
 733     pfl->cfi_table[0x14] = 0x00;
 734     /* Primary extended table address (none) */
 735     pfl->cfi_table[0x15] = 0x31;
 736     pfl->cfi_table[0x16] = 0x00;
 737     /* Alternate command set (none) */
 738     pfl->cfi_table[0x17] = 0x00;
 739     pfl->cfi_table[0x18] = 0x00;
 740     /* Alternate extended table (none) */
 741     pfl->cfi_table[0x19] = 0x00;
 742     pfl->cfi_table[0x1A] = 0x00;
 743     /* Vcc min */
 744     pfl->cfi_table[0x1B] = 0x45;
 745     /* Vcc max */
 746     pfl->cfi_table[0x1C] = 0x55;
 747     /* Vpp min (no Vpp pin) */
 748     pfl->cfi_table[0x1D] = 0x00;
 749     /* Vpp max (no Vpp pin) */
 750     pfl->cfi_table[0x1E] = 0x00;
 751     /* Reserved */
 752     pfl->cfi_table[0x1F] = 0x07;
 753     /* Timeout for min size buffer write */
 754     pfl->cfi_table[0x20] = 0x07;
 755     /* Typical timeout for block erase */
 756     pfl->cfi_table[0x21] = 0x0a;
 757     /* Typical timeout for full chip erase (4096 ms) */
 758     pfl->cfi_table[0x22] = 0x00;
 759     /* Reserved */
 760     pfl->cfi_table[0x23] = 0x04;
 761     /* Max timeout for buffer write */
 762     pfl->cfi_table[0x24] = 0x04;
 763     /* Max timeout for block erase */
 764     pfl->cfi_table[0x25] = 0x04;
 765     /* Max timeout for chip erase */
 766     pfl->cfi_table[0x26] = 0x00;
 767     /* Device size */
 768     pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */
 769     /* Flash device interface (8 & 16 bits) */
 770     pfl->cfi_table[0x28] = 0x02;
 771     pfl->cfi_table[0x29] = 0x00;
 772     /* Max number of bytes in multi-bytes write */
 773     if (pfl->bank_width == 1) {
 774         pfl->cfi_table[0x2A] = 0x08;
 775     } else {
 776         pfl->cfi_table[0x2A] = 0x0B;
 777     }
 778     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 779     if (!pfl->old_multiple_chip_handling && num_devices > 1) {
 780         pfl->writeblock_size *= num_devices;
 781     }
 782
 783     pfl->cfi_table[0x2B] = 0x00;
 784     /* Number of erase block regions (uniform) */
 785     pfl->cfi_table[0x2C] = 0x01;
 786     /* Erase block region 1 */
 787     pfl->cfi_table[0x2D] = blocks_per_device - 1;
 788     pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8;
 789     pfl->cfi_table[0x2F] = sector_len_per_device >> 8;
 790     pfl->cfi_table[0x30] = sector_len_per_device >> 16;
 791
 792     /* Extended */
 793     pfl->cfi_table[0x31] = 'P';
 794     pfl->cfi_table[0x32] = 'R';
 795     pfl->cfi_table[0x33] = 'I';
 796
 797     pfl->cfi_table[0x34] = '1';
 798     pfl->cfi_table[0x35] = '0';
 799
 800     pfl->cfi_table[0x36] = 0x00;
 801     pfl->cfi_table[0x37] = 0x00;
 802     pfl->cfi_table[0x38] = 0x00;
 803     pfl->cfi_table[0x39] = 0x00;
 804
 805     pfl->cfi_table[0x3a] = 0x00;
 806
 807     pfl->cfi_table[0x3b] = 0x00;
 808     pfl->cfi_table[0x3c] = 0x00;
 809
 810     pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
 811 }
 812
 813 static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
 814 {
 815     ERRP_GUARD();
 816     PFlashCFI01 *pfl = PFLASH_CFI01(dev);
 817     uint64_t total_len;
 818     int ret;
 819
 820     if (pfl->sector_len == 0) {
 821         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 822         return;
 823     }
 824     if (pfl->nb_blocs == 0) {
 825         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 826         return;
 827     }
 828     if (pfl->name == NULL) {
 829         error_setg(errp, "attribute \"name\" not specified.");
 830         return;
 831     }
 832
 833     total_len = pfl->sector_len * pfl->nb_blocs;
 834
 835     memory_region_init_rom_device(
 836         &pfl->mem, OBJECT(dev),
 837         &pflash_cfi01_ops,
 838         pfl,
 839         pfl->name, total_len, errp);
 840     if (*errp) {
 841         return;
 842     }
 843
 844     pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
 845     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 846
 847     if (pfl->blk) {
 848         uint64_t perm;
 849         pfl->ro = !blk_supports_write_perm(pfl->blk);
 850         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 851         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 852         if (ret < 0) {
 853             return;
 854         }
 855     } else {
 856         pfl->ro = 0;
 857     }
 858
 859     if (pfl->blk) {
 860         if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, total_len,
 861                                          errp)) {
 862             vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
 863             return;
 864         }
 865     }
 866
 867     /*
 868      * Default to devices being used at their maximum device width. This was
 869      * assumed before the device_width support was added.
 870      */
 871     if (!pfl->max_device_width) {
 872         pfl->max_device_width = pfl->device_width;
 873     }
 874
 875     pfl->wcycle = 0;
 876     /*
 877      * The command 0x00 is not assigned by the CFI open standard,
 878      * but QEMU historically uses it for the READ_ARRAY command (0xff).
 879      */
 880     pfl->cmd = 0x00;
 881     pfl->status = 0x80; /* WSM ready */
 882     pflash_cfi01_fill_cfi_table(pfl);
 883 }
 884
 885 static void pflash_cfi01_system_reset(DeviceState *dev)
 886 {
 887     PFlashCFI01 *pfl = PFLASH_CFI01(dev);
 888
 889     /*
 890      * The command 0x00 is not assigned by the CFI open standard,
 891      * but QEMU historically uses it for the READ_ARRAY command (0xff).
 892      */
 893     pfl->cmd = 0x00;
 894     pfl->wcycle = 0;
 895     memory_region_rom_device_set_romd(&pfl->mem, true);
 896     /*
 897      * The WSM ready timer occurs at most 150ns after system reset.
 898      * This model deliberately ignores this delay.
 899      */
 900     pfl->status = 0x80;
 901 }
 902
 903 static Property pflash_cfi01_properties[] = {
 904     DEFINE_PROP_DRIVE("drive", PFlashCFI01, blk),
 905     /* num-blocks is the number of blocks actually visible to the guest,
 906      * ie the total size of the device divided by the sector length.
 907      * If we're emulating flash devices wired in parallel the actual
 908      * number of blocks per indvidual device will differ.
 909      */
 910     DEFINE_PROP_UINT32("num-blocks", PFlashCFI01, nb_blocs, 0),
 911     DEFINE_PROP_UINT64("sector-length", PFlashCFI01, sector_len, 0),
 912     /* width here is the overall width of this QEMU device in bytes.
 913      * The QEMU device may be emulating a number of flash devices
 914      * wired up in parallel; the width of each individual flash
 915      * device should be specified via device-width. If the individual
 916      * devices have a maximum width which is greater than the width
 917      * they are being used for, this maximum width should be set via
 918      * max-device-width (which otherwise defaults to device-width).
 919      * So for instance a 32-bit wide QEMU flash device made from four
 920      * 16-bit flash devices used in 8-bit wide mode would be configured
 921      * with width = 4, device-width = 1, max-device-width = 2.
 922      *
 923      * If device-width is not specified we default to backwards
 924      * compatible behaviour which is a bad emulation of two
 925      * 16 bit devices making up a 32 bit wide QEMU device. This
 926      * is deprecated for new uses of this device.
 927      */
 928     DEFINE_PROP_UINT8("width", PFlashCFI01, bank_width, 0),
 929     DEFINE_PROP_UINT8("device-width", PFlashCFI01, device_width, 0),
 930     DEFINE_PROP_UINT8("max-device-width", PFlashCFI01, max_device_width, 0),
 931     DEFINE_PROP_BIT("big-endian", PFlashCFI01, features, PFLASH_BE, 0),
 932     DEFINE_PROP_BIT("secure", PFlashCFI01, features, PFLASH_SECURE, 0),
 933     DEFINE_PROP_UINT16("id0", PFlashCFI01, ident0, 0),
 934     DEFINE_PROP_UINT16("id1", PFlashCFI01, ident1, 0),
 935     DEFINE_PROP_UINT16("id2", PFlashCFI01, ident2, 0),
 936     DEFINE_PROP_UINT16("id3", PFlashCFI01, ident3, 0),
 937     DEFINE_PROP_STRING("name", PFlashCFI01, name),
 938     DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01,
 939                      old_multiple_chip_handling, false),
 940     DEFINE_PROP_END_OF_LIST(),
 941 };
 942
 943 static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
 944 {
 945     DeviceClass *dc = DEVICE_CLASS(klass);
 946
 947     dc->reset = pflash_cfi01_system_reset;
 948     dc->realize = pflash_cfi01_realize;
 949     device_class_set_props(dc, pflash_cfi01_properties);
 950     dc->vmsd = &vmstate_pflash;
 951     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 952 }
 953
 954
 955 static const TypeInfo pflash_cfi01_info = {
 956     .name           = TYPE_PFLASH_CFI01,
 957     .parent         = TYPE_SYS_BUS_DEVICE,
 958     .instance_size  = sizeof(PFlashCFI01),
 959     .class_init     = pflash_cfi01_class_init,
 960 };
 961
 962 static void pflash_cfi01_register_types(void)
 963 {
 964     type_register_static(&pflash_cfi01_info);
 965 }
 966
 967 type_init(pflash_cfi01_register_types)
 968
 969 PFlashCFI01 *pflash_cfi01_register(hwaddr base,
 970                                    const char *name,
 971                                    hwaddr size,
 972                                    BlockBackend *blk,
 973                                    uint32_t sector_len,
 974                                    int bank_width,
 975                                    uint16_t id0, uint16_t id1,
 976                                    uint16_t id2, uint16_t id3,
 977                                    int be)
 978 {
 979     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 980
 981     if (blk) {
 982         qdev_prop_set_drive(dev, "drive", blk);
 983     }
 984     assert(QEMU_IS_ALIGNED(size, sector_len));
 985     qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
 986     qdev_prop_set_uint64(dev, "sector-length", sector_len);
 987     qdev_prop_set_uint8(dev, "width", bank_width);
 988     qdev_prop_set_bit(dev, "big-endian", !!be);
 989     qdev_prop_set_uint16(dev, "id0", id0);
 990     qdev_prop_set_uint16(dev, "id1", id1);
 991     qdev_prop_set_uint16(dev, "id2", id2);
 992     qdev_prop_set_uint16(dev, "id3", id3);
 993     qdev_prop_set_string(dev, "name", name);
 994     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 995
 996     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 997     return PFLASH_CFI01(dev);
 998 }
 999
1000 BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl)
1001 {
1002     return fl->blk;
1003 }
1004
1005 MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl)
1006 {
1007     return &fl->mem;
1008 }
1009
1010 /*
1011  * Handle -drive if=pflash for machines that use properties.
1012  * If @dinfo is null, do nothing.
1013  * Else if @fl's property "drive" is already set, fatal error.
1014  * Else set it to the BlockBackend with @dinfo.
1015  */
1016 void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo)
1017 {
1018     Location loc;
1019
1020     if (!dinfo) {
1021         return;
1022     }
1023
1024     loc_push_none(&loc);
1025     qemu_opts_loc_restore(dinfo->opts);
1026     if (fl->blk) {
1027         error_report("clashes with -machine");
1028         exit(1);
1029     }
1030     qdev_prop_set_drive_err(DEVICE(fl), "drive", blk_by_legacy_dinfo(dinfo),
1031                             &error_fatal);
1032     loc_pop(&loc);
1033 }
1034
1035 static void postload_update_cb(void *opaque, bool running, RunState state)
1036 {
1037     PFlashCFI01 *pfl = opaque;
1038
1039     /* This is called after bdrv_invalidate_cache_all.  */
1040     qemu_del_vm_change_state_handler(pfl->vmstate);
1041     pfl->vmstate = NULL;
1042
1043     DPRINTF("%s: updating bdrv for %s\n", __func__, pfl->name);
1044     pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs);
1045 }
1046
1047 static int pflash_post_load(void *opaque, int version_id)
1048 {
1049     PFlashCFI01 *pfl = opaque;
1050
1051     if (!pfl->ro) {
1052         pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
1053                                                         pfl);
1054     }
1055     return 0;
1056 }