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xen-disk: use g_new0 to fix build
[qemu/ar7.git] / hw / ppc / ppc405_uc.c
blobe621d0aec502a4d2feebe8d64750d7b92a09c695
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/hw.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/boards.h"
31 #include "hw/i2c/ppc4xx_i2c.h"
32 #include "ppc405.h"
33 #include "hw/char/serial.h"
34 #include "qemu/timer.h"
35 #include "sysemu/sysemu.h"
36 #include "qemu/log.h"
37 #include "exec/address-spaces.h"
38
39 //#define DEBUG_OPBA
40 //#define DEBUG_SDRAM
41 //#define DEBUG_GPIO
42 //#define DEBUG_SERIAL
43 //#define DEBUG_OCM
44 //#define DEBUG_GPT
45 //#define DEBUG_CLOCKS
46 //#define DEBUG_CLOCKS_LL
47
48 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
49 uint32_t flags)
50 {
51 CPUState *cs = CPU(ppc_env_get_cpu(env));
52 ram_addr_t bdloc;
53 int i, n;
54
55 /* We put the bd structure at the top of memory */
56 if (bd->bi_memsize >= 0x01000000UL)
57 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
58 else
59 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
60 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
61 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
62 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
63 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
64 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
65 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
66 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
67 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
68 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
69 for (i = 0; i < 6; i++) {
70 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
71 }
72 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
73 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
74 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
75 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
76 for (i = 0; i < 4; i++) {
77 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
78 }
79 for (i = 0; i < 32; i++) {
80 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
81 }
82 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
83 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
84 for (i = 0; i < 6; i++) {
85 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
86 }
87 n = 0x6A;
88 if (flags & 0x00000001) {
89 for (i = 0; i < 6; i++)
90 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
91 }
92 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
93 n += 4;
94 for (i = 0; i < 2; i++) {
95 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
96 n += 4;
97 }
98
99 return bdloc;
100 }
101
102 /*****************************************************************************/
103 /* Shared peripherals */
104
105 /*****************************************************************************/
106 /* Peripheral local bus arbitrer */
107 enum {
108 PLB0_BESR = 0x084,
109 PLB0_BEAR = 0x086,
110 PLB0_ACR = 0x087,
111 };
112
113 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
114 struct ppc4xx_plb_t {
115 uint32_t acr;
116 uint32_t bear;
117 uint32_t besr;
118 };
119
120 static uint32_t dcr_read_plb (void *opaque, int dcrn)
121 {
122 ppc4xx_plb_t *plb;
123 uint32_t ret;
124
125 plb = opaque;
126 switch (dcrn) {
127 case PLB0_ACR:
128 ret = plb->acr;
129 break;
130 case PLB0_BEAR:
131 ret = plb->bear;
132 break;
133 case PLB0_BESR:
134 ret = plb->besr;
135 break;
136 default:
137 /* Avoid gcc warning */
138 ret = 0;
139 break;
140 }
141
142 return ret;
143 }
144
145 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
146 {
147 ppc4xx_plb_t *plb;
148
149 plb = opaque;
150 switch (dcrn) {
151 case PLB0_ACR:
152 /* We don't care about the actual parameters written as
153 * we don't manage any priorities on the bus
154 */
155 plb->acr = val & 0xF8000000;
156 break;
157 case PLB0_BEAR:
158 /* Read only */
159 break;
160 case PLB0_BESR:
161 /* Write-clear */
162 plb->besr &= ~val;
163 break;
164 }
165 }
166
167 static void ppc4xx_plb_reset (void *opaque)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = opaque;
172 plb->acr = 0x00000000;
173 plb->bear = 0x00000000;
174 plb->besr = 0x00000000;
175 }
176
177 void ppc4xx_plb_init(CPUPPCState *env)
178 {
179 ppc4xx_plb_t *plb;
180
181 plb = g_malloc0(sizeof(ppc4xx_plb_t));
182 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
183 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
184 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
185 qemu_register_reset(ppc4xx_plb_reset, plb);
186 }
187
188 /*****************************************************************************/
189 /* PLB to OPB bridge */
190 enum {
191 POB0_BESR0 = 0x0A0,
192 POB0_BESR1 = 0x0A2,
193 POB0_BEAR = 0x0A4,
194 };
195
196 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
197 struct ppc4xx_pob_t {
198 uint32_t bear;
199 uint32_t besr0;
200 uint32_t besr1;
201 };
202
203 static uint32_t dcr_read_pob (void *opaque, int dcrn)
204 {
205 ppc4xx_pob_t *pob;
206 uint32_t ret;
207
208 pob = opaque;
209 switch (dcrn) {
210 case POB0_BEAR:
211 ret = pob->bear;
212 break;
213 case POB0_BESR0:
214 ret = pob->besr0;
215 break;
216 case POB0_BESR1:
217 ret = pob->besr1;
218 break;
219 default:
220 /* Avoid gcc warning */
221 ret = 0;
222 break;
223 }
224
225 return ret;
226 }
227
228 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
229 {
230 ppc4xx_pob_t *pob;
231
232 pob = opaque;
233 switch (dcrn) {
234 case POB0_BEAR:
235 /* Read only */
236 break;
237 case POB0_BESR0:
238 /* Write-clear */
239 pob->besr0 &= ~val;
240 break;
241 case POB0_BESR1:
242 /* Write-clear */
243 pob->besr1 &= ~val;
244 break;
245 }
246 }
247
248 static void ppc4xx_pob_reset (void *opaque)
249 {
250 ppc4xx_pob_t *pob;
251
252 pob = opaque;
253 /* No error */
254 pob->bear = 0x00000000;
255 pob->besr0 = 0x0000000;
256 pob->besr1 = 0x0000000;
257 }
258
259 static void ppc4xx_pob_init(CPUPPCState *env)
260 {
261 ppc4xx_pob_t *pob;
262
263 pob = g_malloc0(sizeof(ppc4xx_pob_t));
264 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
265 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
266 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
267 qemu_register_reset(ppc4xx_pob_reset, pob);
268 }
269
270 /*****************************************************************************/
271 /* OPB arbitrer */
272 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
273 struct ppc4xx_opba_t {
274 MemoryRegion io;
275 uint8_t cr;
276 uint8_t pr;
277 };
278
279 static uint32_t opba_readb (void *opaque, hwaddr addr)
280 {
281 ppc4xx_opba_t *opba;
282 uint32_t ret;
283
284 #ifdef DEBUG_OPBA
285 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
286 #endif
287 opba = opaque;
288 switch (addr) {
289 case 0x00:
290 ret = opba->cr;
291 break;
292 case 0x01:
293 ret = opba->pr;
294 break;
295 default:
296 ret = 0x00;
297 break;
298 }
299
300 return ret;
301 }
302
303 static void opba_writeb (void *opaque,
304 hwaddr addr, uint32_t value)
305 {
306 ppc4xx_opba_t *opba;
307
308 #ifdef DEBUG_OPBA
309 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
310 value);
311 #endif
312 opba = opaque;
313 switch (addr) {
314 case 0x00:
315 opba->cr = value & 0xF8;
316 break;
317 case 0x01:
318 opba->pr = value & 0xFF;
319 break;
320 default:
321 break;
322 }
323 }
324
325 static uint32_t opba_readw (void *opaque, hwaddr addr)
326 {
327 uint32_t ret;
328
329 #ifdef DEBUG_OPBA
330 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
331 #endif
332 ret = opba_readb(opaque, addr) << 8;
333 ret |= opba_readb(opaque, addr + 1);
334
335 return ret;
336 }
337
338 static void opba_writew (void *opaque,
339 hwaddr addr, uint32_t value)
340 {
341 #ifdef DEBUG_OPBA
342 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
343 value);
344 #endif
345 opba_writeb(opaque, addr, value >> 8);
346 opba_writeb(opaque, addr + 1, value);
347 }
348
349 static uint32_t opba_readl (void *opaque, hwaddr addr)
350 {
351 uint32_t ret;
352
353 #ifdef DEBUG_OPBA
354 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
355 #endif
356 ret = opba_readb(opaque, addr) << 24;
357 ret |= opba_readb(opaque, addr + 1) << 16;
358
359 return ret;
360 }
361
362 static void opba_writel (void *opaque,
363 hwaddr addr, uint32_t value)
364 {
365 #ifdef DEBUG_OPBA
366 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
367 value);
368 #endif
369 opba_writeb(opaque, addr, value >> 24);
370 opba_writeb(opaque, addr + 1, value >> 16);
371 }
372
373 static const MemoryRegionOps opba_ops = {
374 .old_mmio = {
375 .read = { opba_readb, opba_readw, opba_readl, },
376 .write = { opba_writeb, opba_writew, opba_writel, },
377 },
378 .endianness = DEVICE_NATIVE_ENDIAN,
379 };
380
381 static void ppc4xx_opba_reset (void *opaque)
382 {
383 ppc4xx_opba_t *opba;
384
385 opba = opaque;
386 opba->cr = 0x00; /* No dynamic priorities - park disabled */
387 opba->pr = 0x11;
388 }
389
390 static void ppc4xx_opba_init(hwaddr base)
391 {
392 ppc4xx_opba_t *opba;
393
394 opba = g_malloc0(sizeof(ppc4xx_opba_t));
395 #ifdef DEBUG_OPBA
396 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
397 #endif
398 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
399 memory_region_add_subregion(get_system_memory(), base, &opba->io);
400 qemu_register_reset(ppc4xx_opba_reset, opba);
401 }
402
403 /*****************************************************************************/
404 /* Code decompression controller */
405 /* XXX: TODO */
406
407 /*****************************************************************************/
408 /* Peripheral controller */
409 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
410 struct ppc4xx_ebc_t {
411 uint32_t addr;
412 uint32_t bcr[8];
413 uint32_t bap[8];
414 uint32_t bear;
415 uint32_t besr0;
416 uint32_t besr1;
417 uint32_t cfg;
418 };
419
420 enum {
421 EBC0_CFGADDR = 0x012,
422 EBC0_CFGDATA = 0x013,
423 };
424
425 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
426 {
427 ppc4xx_ebc_t *ebc;
428 uint32_t ret;
429
430 ebc = opaque;
431 switch (dcrn) {
432 case EBC0_CFGADDR:
433 ret = ebc->addr;
434 break;
435 case EBC0_CFGDATA:
436 switch (ebc->addr) {
437 case 0x00: /* B0CR */
438 ret = ebc->bcr[0];
439 break;
440 case 0x01: /* B1CR */
441 ret = ebc->bcr[1];
442 break;
443 case 0x02: /* B2CR */
444 ret = ebc->bcr[2];
445 break;
446 case 0x03: /* B3CR */
447 ret = ebc->bcr[3];
448 break;
449 case 0x04: /* B4CR */
450 ret = ebc->bcr[4];
451 break;
452 case 0x05: /* B5CR */
453 ret = ebc->bcr[5];
454 break;
455 case 0x06: /* B6CR */
456 ret = ebc->bcr[6];
457 break;
458 case 0x07: /* B7CR */
459 ret = ebc->bcr[7];
460 break;
461 case 0x10: /* B0AP */
462 ret = ebc->bap[0];
463 break;
464 case 0x11: /* B1AP */
465 ret = ebc->bap[1];
466 break;
467 case 0x12: /* B2AP */
468 ret = ebc->bap[2];
469 break;
470 case 0x13: /* B3AP */
471 ret = ebc->bap[3];
472 break;
473 case 0x14: /* B4AP */
474 ret = ebc->bap[4];
475 break;
476 case 0x15: /* B5AP */
477 ret = ebc->bap[5];
478 break;
479 case 0x16: /* B6AP */
480 ret = ebc->bap[6];
481 break;
482 case 0x17: /* B7AP */
483 ret = ebc->bap[7];
484 break;
485 case 0x20: /* BEAR */
486 ret = ebc->bear;
487 break;
488 case 0x21: /* BESR0 */
489 ret = ebc->besr0;
490 break;
491 case 0x22: /* BESR1 */
492 ret = ebc->besr1;
493 break;
494 case 0x23: /* CFG */
495 ret = ebc->cfg;
496 break;
497 default:
498 ret = 0x00000000;
499 break;
500 }
501 break;
502 default:
503 ret = 0x00000000;
504 break;
505 }
506
507 return ret;
508 }
509
510 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
511 {
512 ppc4xx_ebc_t *ebc;
513
514 ebc = opaque;
515 switch (dcrn) {
516 case EBC0_CFGADDR:
517 ebc->addr = val;
518 break;
519 case EBC0_CFGDATA:
520 switch (ebc->addr) {
521 case 0x00: /* B0CR */
522 break;
523 case 0x01: /* B1CR */
524 break;
525 case 0x02: /* B2CR */
526 break;
527 case 0x03: /* B3CR */
528 break;
529 case 0x04: /* B4CR */
530 break;
531 case 0x05: /* B5CR */
532 break;
533 case 0x06: /* B6CR */
534 break;
535 case 0x07: /* B7CR */
536 break;
537 case 0x10: /* B0AP */
538 break;
539 case 0x11: /* B1AP */
540 break;
541 case 0x12: /* B2AP */
542 break;
543 case 0x13: /* B3AP */
544 break;
545 case 0x14: /* B4AP */
546 break;
547 case 0x15: /* B5AP */
548 break;
549 case 0x16: /* B6AP */
550 break;
551 case 0x17: /* B7AP */
552 break;
553 case 0x20: /* BEAR */
554 break;
555 case 0x21: /* BESR0 */
556 break;
557 case 0x22: /* BESR1 */
558 break;
559 case 0x23: /* CFG */
560 break;
561 default:
562 break;
563 }
564 break;
565 default:
566 break;
567 }
568 }
569
570 static void ebc_reset (void *opaque)
571 {
572 ppc4xx_ebc_t *ebc;
573 int i;
574
575 ebc = opaque;
576 ebc->addr = 0x00000000;
577 ebc->bap[0] = 0x7F8FFE80;
578 ebc->bcr[0] = 0xFFE28000;
579 for (i = 0; i < 8; i++) {
580 ebc->bap[i] = 0x00000000;
581 ebc->bcr[i] = 0x00000000;
582 }
583 ebc->besr0 = 0x00000000;
584 ebc->besr1 = 0x00000000;
585 ebc->cfg = 0x80400000;
586 }
587
588 void ppc405_ebc_init(CPUPPCState *env)
589 {
590 ppc4xx_ebc_t *ebc;
591
592 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
593 qemu_register_reset(&ebc_reset, ebc);
594 ppc_dcr_register(env, EBC0_CFGADDR,
595 ebc, &dcr_read_ebc, &dcr_write_ebc);
596 ppc_dcr_register(env, EBC0_CFGDATA,
597 ebc, &dcr_read_ebc, &dcr_write_ebc);
598 }
599
600 /*****************************************************************************/
601 /* DMA controller */
602 enum {
603 DMA0_CR0 = 0x100,
604 DMA0_CT0 = 0x101,
605 DMA0_DA0 = 0x102,
606 DMA0_SA0 = 0x103,
607 DMA0_SG0 = 0x104,
608 DMA0_CR1 = 0x108,
609 DMA0_CT1 = 0x109,
610 DMA0_DA1 = 0x10A,
611 DMA0_SA1 = 0x10B,
612 DMA0_SG1 = 0x10C,
613 DMA0_CR2 = 0x110,
614 DMA0_CT2 = 0x111,
615 DMA0_DA2 = 0x112,
616 DMA0_SA2 = 0x113,
617 DMA0_SG2 = 0x114,
618 DMA0_CR3 = 0x118,
619 DMA0_CT3 = 0x119,
620 DMA0_DA3 = 0x11A,
621 DMA0_SA3 = 0x11B,
622 DMA0_SG3 = 0x11C,
623 DMA0_SR = 0x120,
624 DMA0_SGC = 0x123,
625 DMA0_SLP = 0x125,
626 DMA0_POL = 0x126,
627 };
628
629 typedef struct ppc405_dma_t ppc405_dma_t;
630 struct ppc405_dma_t {
631 qemu_irq irqs[4];
632 uint32_t cr[4];
633 uint32_t ct[4];
634 uint32_t da[4];
635 uint32_t sa[4];
636 uint32_t sg[4];
637 uint32_t sr;
638 uint32_t sgc;
639 uint32_t slp;
640 uint32_t pol;
641 };
642
643 static uint32_t dcr_read_dma (void *opaque, int dcrn)
644 {
645 return 0;
646 }
647
648 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
649 {
650 }
651
652 static void ppc405_dma_reset (void *opaque)
653 {
654 ppc405_dma_t *dma;
655 int i;
656
657 dma = opaque;
658 for (i = 0; i < 4; i++) {
659 dma->cr[i] = 0x00000000;
660 dma->ct[i] = 0x00000000;
661 dma->da[i] = 0x00000000;
662 dma->sa[i] = 0x00000000;
663 dma->sg[i] = 0x00000000;
664 }
665 dma->sr = 0x00000000;
666 dma->sgc = 0x00000000;
667 dma->slp = 0x7C000000;
668 dma->pol = 0x00000000;
669 }
670
671 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
672 {
673 ppc405_dma_t *dma;
674
675 dma = g_malloc0(sizeof(ppc405_dma_t));
676 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
677 qemu_register_reset(&ppc405_dma_reset, dma);
678 ppc_dcr_register(env, DMA0_CR0,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_CT0,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_DA0,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_SA0,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_SG0,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_CR1,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_CT1,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_DA1,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_SA1,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_SG1,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_CR2,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_CT2,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_DA2,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_SA2,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_SG2,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_CR3,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_CT3,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_DA3,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 ppc_dcr_register(env, DMA0_SA3,
715 dma, &dcr_read_dma, &dcr_write_dma);
716 ppc_dcr_register(env, DMA0_SG3,
717 dma, &dcr_read_dma, &dcr_write_dma);
718 ppc_dcr_register(env, DMA0_SR,
719 dma, &dcr_read_dma, &dcr_write_dma);
720 ppc_dcr_register(env, DMA0_SGC,
721 dma, &dcr_read_dma, &dcr_write_dma);
722 ppc_dcr_register(env, DMA0_SLP,
723 dma, &dcr_read_dma, &dcr_write_dma);
724 ppc_dcr_register(env, DMA0_POL,
725 dma, &dcr_read_dma, &dcr_write_dma);
726 }
727
728 /*****************************************************************************/
729 /* GPIO */
730 typedef struct ppc405_gpio_t ppc405_gpio_t;
731 struct ppc405_gpio_t {
732 MemoryRegion io;
733 uint32_t or;
734 uint32_t tcr;
735 uint32_t osrh;
736 uint32_t osrl;
737 uint32_t tsrh;
738 uint32_t tsrl;
739 uint32_t odr;
740 uint32_t ir;
741 uint32_t rr1;
742 uint32_t isr1h;
743 uint32_t isr1l;
744 };
745
746 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
747 {
748 #ifdef DEBUG_GPIO
749 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
750 #endif
751
752 return 0;
753 }
754
755 static void ppc405_gpio_writeb (void *opaque,
756 hwaddr addr, uint32_t value)
757 {
758 #ifdef DEBUG_GPIO
759 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
760 value);
761 #endif
762 }
763
764 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
765 {
766 #ifdef DEBUG_GPIO
767 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
768 #endif
769
770 return 0;
771 }
772
773 static void ppc405_gpio_writew (void *opaque,
774 hwaddr addr, uint32_t value)
775 {
776 #ifdef DEBUG_GPIO
777 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
778 value);
779 #endif
780 }
781
782 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
783 {
784 #ifdef DEBUG_GPIO
785 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
786 #endif
787
788 return 0;
789 }
790
791 static void ppc405_gpio_writel (void *opaque,
792 hwaddr addr, uint32_t value)
793 {
794 #ifdef DEBUG_GPIO
795 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
796 value);
797 #endif
798 }
799
800 static const MemoryRegionOps ppc405_gpio_ops = {
801 .old_mmio = {
802 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
803 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
804 },
805 .endianness = DEVICE_NATIVE_ENDIAN,
806 };
807
808 static void ppc405_gpio_reset (void *opaque)
809 {
810 }
811
812 static void ppc405_gpio_init(hwaddr base)
813 {
814 ppc405_gpio_t *gpio;
815
816 gpio = g_malloc0(sizeof(ppc405_gpio_t));
817 #ifdef DEBUG_GPIO
818 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
819 #endif
820 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
821 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
822 qemu_register_reset(&ppc405_gpio_reset, gpio);
823 }
824
825 /*****************************************************************************/
826 /* On Chip Memory */
827 enum {
828 OCM0_ISARC = 0x018,
829 OCM0_ISACNTL = 0x019,
830 OCM0_DSARC = 0x01A,
831 OCM0_DSACNTL = 0x01B,
832 };
833
834 typedef struct ppc405_ocm_t ppc405_ocm_t;
835 struct ppc405_ocm_t {
836 MemoryRegion ram;
837 MemoryRegion isarc_ram;
838 MemoryRegion dsarc_ram;
839 uint32_t isarc;
840 uint32_t isacntl;
841 uint32_t dsarc;
842 uint32_t dsacntl;
843 };
844
845 static void ocm_update_mappings (ppc405_ocm_t *ocm,
846 uint32_t isarc, uint32_t isacntl,
847 uint32_t dsarc, uint32_t dsacntl)
848 {
849 #ifdef DEBUG_OCM
850 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
851 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
852 " (%08" PRIx32 " %08" PRIx32 ")\n",
853 isarc, isacntl, dsarc, dsacntl,
854 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
855 #endif
856 if (ocm->isarc != isarc ||
857 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
858 if (ocm->isacntl & 0x80000000) {
859 /* Unmap previously assigned memory region */
860 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
861 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
862 }
863 if (isacntl & 0x80000000) {
864 /* Map new instruction memory region */
865 #ifdef DEBUG_OCM
866 printf("OCM map ISA %08" PRIx32 "\n", isarc);
867 #endif
868 memory_region_add_subregion(get_system_memory(), isarc,
869 &ocm->isarc_ram);
870 }
871 }
872 if (ocm->dsarc != dsarc ||
873 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
874 if (ocm->dsacntl & 0x80000000) {
875 /* Beware not to unmap the region we just mapped */
876 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
877 /* Unmap previously assigned memory region */
878 #ifdef DEBUG_OCM
879 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
880 #endif
881 memory_region_del_subregion(get_system_memory(),
882 &ocm->dsarc_ram);
883 }
884 }
885 if (dsacntl & 0x80000000) {
886 /* Beware not to remap the region we just mapped */
887 if (!(isacntl & 0x80000000) || dsarc != isarc) {
888 /* Map new data memory region */
889 #ifdef DEBUG_OCM
890 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
891 #endif
892 memory_region_add_subregion(get_system_memory(), dsarc,
893 &ocm->dsarc_ram);
894 }
895 }
896 }
897 }
898
899 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
900 {
901 ppc405_ocm_t *ocm;
902 uint32_t ret;
903
904 ocm = opaque;
905 switch (dcrn) {
906 case OCM0_ISARC:
907 ret = ocm->isarc;
908 break;
909 case OCM0_ISACNTL:
910 ret = ocm->isacntl;
911 break;
912 case OCM0_DSARC:
913 ret = ocm->dsarc;
914 break;
915 case OCM0_DSACNTL:
916 ret = ocm->dsacntl;
917 break;
918 default:
919 ret = 0;
920 break;
921 }
922
923 return ret;
924 }
925
926 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
927 {
928 ppc405_ocm_t *ocm;
929 uint32_t isarc, dsarc, isacntl, dsacntl;
930
931 ocm = opaque;
932 isarc = ocm->isarc;
933 dsarc = ocm->dsarc;
934 isacntl = ocm->isacntl;
935 dsacntl = ocm->dsacntl;
936 switch (dcrn) {
937 case OCM0_ISARC:
938 isarc = val & 0xFC000000;
939 break;
940 case OCM0_ISACNTL:
941 isacntl = val & 0xC0000000;
942 break;
943 case OCM0_DSARC:
944 isarc = val & 0xFC000000;
945 break;
946 case OCM0_DSACNTL:
947 isacntl = val & 0xC0000000;
948 break;
949 }
950 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
951 ocm->isarc = isarc;
952 ocm->dsarc = dsarc;
953 ocm->isacntl = isacntl;
954 ocm->dsacntl = dsacntl;
955 }
956
957 static void ocm_reset (void *opaque)
958 {
959 ppc405_ocm_t *ocm;
960 uint32_t isarc, dsarc, isacntl, dsacntl;
961
962 ocm = opaque;
963 isarc = 0x00000000;
964 isacntl = 0x00000000;
965 dsarc = 0x00000000;
966 dsacntl = 0x00000000;
967 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
968 ocm->isarc = isarc;
969 ocm->dsarc = dsarc;
970 ocm->isacntl = isacntl;
971 ocm->dsacntl = dsacntl;
972 }
973
974 static void ppc405_ocm_init(CPUPPCState *env)
975 {
976 ppc405_ocm_t *ocm;
977
978 ocm = g_malloc0(sizeof(ppc405_ocm_t));
979 /* XXX: Size is 4096 or 0x04000000 */
980 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096,
981 &error_fatal);
982 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
983 0, 4096);
984 qemu_register_reset(&ocm_reset, ocm);
985 ppc_dcr_register(env, OCM0_ISARC,
986 ocm, &dcr_read_ocm, &dcr_write_ocm);
987 ppc_dcr_register(env, OCM0_ISACNTL,
988 ocm, &dcr_read_ocm, &dcr_write_ocm);
989 ppc_dcr_register(env, OCM0_DSARC,
990 ocm, &dcr_read_ocm, &dcr_write_ocm);
991 ppc_dcr_register(env, OCM0_DSACNTL,
992 ocm, &dcr_read_ocm, &dcr_write_ocm);
993 }
994
995 /*****************************************************************************/
996 /* General purpose timers */
997 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
998 struct ppc4xx_gpt_t {
999 MemoryRegion iomem;
1000 int64_t tb_offset;
1001 uint32_t tb_freq;
1002 QEMUTimer *timer;
1003 qemu_irq irqs[5];
1004 uint32_t oe;
1005 uint32_t ol;
1006 uint32_t im;
1007 uint32_t is;
1008 uint32_t ie;
1009 uint32_t comp[5];
1010 uint32_t mask[5];
1011 };
1012
1013 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1014 {
1015 #ifdef DEBUG_GPT
1016 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1017 #endif
1018 /* XXX: generate a bus fault */
1019 return -1;
1020 }
1021
1022 static void ppc4xx_gpt_writeb (void *opaque,
1023 hwaddr addr, uint32_t value)
1024 {
1025 #ifdef DEBUG_I2C
1026 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1027 value);
1028 #endif
1029 /* XXX: generate a bus fault */
1030 }
1031
1032 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1033 {
1034 #ifdef DEBUG_GPT
1035 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1036 #endif
1037 /* XXX: generate a bus fault */
1038 return -1;
1039 }
1040
1041 static void ppc4xx_gpt_writew (void *opaque,
1042 hwaddr addr, uint32_t value)
1043 {
1044 #ifdef DEBUG_I2C
1045 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1046 value);
1047 #endif
1048 /* XXX: generate a bus fault */
1049 }
1050
1051 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1052 {
1053 /* XXX: TODO */
1054 return 0;
1055 }
1056
1057 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1058 {
1059 /* XXX: TODO */
1060 }
1061
1062 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1063 {
1064 uint32_t mask;
1065 int i;
1066
1067 mask = 0x80000000;
1068 for (i = 0; i < 5; i++) {
1069 if (gpt->oe & mask) {
1070 /* Output is enabled */
1071 if (ppc4xx_gpt_compare(gpt, i)) {
1072 /* Comparison is OK */
1073 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1074 } else {
1075 /* Comparison is KO */
1076 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1077 }
1078 }
1079 mask = mask >> 1;
1080 }
1081 }
1082
1083 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1084 {
1085 uint32_t mask;
1086 int i;
1087
1088 mask = 0x00008000;
1089 for (i = 0; i < 5; i++) {
1090 if (gpt->is & gpt->im & mask)
1091 qemu_irq_raise(gpt->irqs[i]);
1092 else
1093 qemu_irq_lower(gpt->irqs[i]);
1094 mask = mask >> 1;
1095 }
1096 }
1097
1098 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1099 {
1100 /* XXX: TODO */
1101 }
1102
1103 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1104 {
1105 ppc4xx_gpt_t *gpt;
1106 uint32_t ret;
1107 int idx;
1108
1109 #ifdef DEBUG_GPT
1110 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1111 #endif
1112 gpt = opaque;
1113 switch (addr) {
1114 case 0x00:
1115 /* Time base counter */
1116 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1117 gpt->tb_freq, NANOSECONDS_PER_SECOND);
1118 break;
1119 case 0x10:
1120 /* Output enable */
1121 ret = gpt->oe;
1122 break;
1123 case 0x14:
1124 /* Output level */
1125 ret = gpt->ol;
1126 break;
1127 case 0x18:
1128 /* Interrupt mask */
1129 ret = gpt->im;
1130 break;
1131 case 0x1C:
1132 case 0x20:
1133 /* Interrupt status */
1134 ret = gpt->is;
1135 break;
1136 case 0x24:
1137 /* Interrupt enable */
1138 ret = gpt->ie;
1139 break;
1140 case 0x80 ... 0x90:
1141 /* Compare timer */
1142 idx = (addr - 0x80) >> 2;
1143 ret = gpt->comp[idx];
1144 break;
1145 case 0xC0 ... 0xD0:
1146 /* Compare mask */
1147 idx = (addr - 0xC0) >> 2;
1148 ret = gpt->mask[idx];
1149 break;
1150 default:
1151 ret = -1;
1152 break;
1153 }
1154
1155 return ret;
1156 }
1157
1158 static void ppc4xx_gpt_writel (void *opaque,
1159 hwaddr addr, uint32_t value)
1160 {
1161 ppc4xx_gpt_t *gpt;
1162 int idx;
1163
1164 #ifdef DEBUG_I2C
1165 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1166 value);
1167 #endif
1168 gpt = opaque;
1169 switch (addr) {
1170 case 0x00:
1171 /* Time base counter */
1172 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
1173 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1174 ppc4xx_gpt_compute_timer(gpt);
1175 break;
1176 case 0x10:
1177 /* Output enable */
1178 gpt->oe = value & 0xF8000000;
1179 ppc4xx_gpt_set_outputs(gpt);
1180 break;
1181 case 0x14:
1182 /* Output level */
1183 gpt->ol = value & 0xF8000000;
1184 ppc4xx_gpt_set_outputs(gpt);
1185 break;
1186 case 0x18:
1187 /* Interrupt mask */
1188 gpt->im = value & 0x0000F800;
1189 break;
1190 case 0x1C:
1191 /* Interrupt status set */
1192 gpt->is |= value & 0x0000F800;
1193 ppc4xx_gpt_set_irqs(gpt);
1194 break;
1195 case 0x20:
1196 /* Interrupt status clear */
1197 gpt->is &= ~(value & 0x0000F800);
1198 ppc4xx_gpt_set_irqs(gpt);
1199 break;
1200 case 0x24:
1201 /* Interrupt enable */
1202 gpt->ie = value & 0x0000F800;
1203 ppc4xx_gpt_set_irqs(gpt);
1204 break;
1205 case 0x80 ... 0x90:
1206 /* Compare timer */
1207 idx = (addr - 0x80) >> 2;
1208 gpt->comp[idx] = value & 0xF8000000;
1209 ppc4xx_gpt_compute_timer(gpt);
1210 break;
1211 case 0xC0 ... 0xD0:
1212 /* Compare mask */
1213 idx = (addr - 0xC0) >> 2;
1214 gpt->mask[idx] = value & 0xF8000000;
1215 ppc4xx_gpt_compute_timer(gpt);
1216 break;
1217 }
1218 }
1219
1220 static const MemoryRegionOps gpt_ops = {
1221 .old_mmio = {
1222 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1223 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1224 },
1225 .endianness = DEVICE_NATIVE_ENDIAN,
1226 };
1227
1228 static void ppc4xx_gpt_cb (void *opaque)
1229 {
1230 ppc4xx_gpt_t *gpt;
1231
1232 gpt = opaque;
1233 ppc4xx_gpt_set_irqs(gpt);
1234 ppc4xx_gpt_set_outputs(gpt);
1235 ppc4xx_gpt_compute_timer(gpt);
1236 }
1237
1238 static void ppc4xx_gpt_reset (void *opaque)
1239 {
1240 ppc4xx_gpt_t *gpt;
1241 int i;
1242
1243 gpt = opaque;
1244 timer_del(gpt->timer);
1245 gpt->oe = 0x00000000;
1246 gpt->ol = 0x00000000;
1247 gpt->im = 0x00000000;
1248 gpt->is = 0x00000000;
1249 gpt->ie = 0x00000000;
1250 for (i = 0; i < 5; i++) {
1251 gpt->comp[i] = 0x00000000;
1252 gpt->mask[i] = 0x00000000;
1253 }
1254 }
1255
1256 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1257 {
1258 ppc4xx_gpt_t *gpt;
1259 int i;
1260
1261 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1262 for (i = 0; i < 5; i++) {
1263 gpt->irqs[i] = irqs[i];
1264 }
1265 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1266 #ifdef DEBUG_GPT
1267 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1268 #endif
1269 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1270 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1271 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1272 }
1273
1274 /*****************************************************************************/
1275 /* SPR */
1276 void ppc40x_core_reset(PowerPCCPU *cpu)
1277 {
1278 CPUPPCState *env = &cpu->env;
1279 target_ulong dbsr;
1280
1281 printf("Reset PowerPC core\n");
1282 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1283 dbsr = env->spr[SPR_40x_DBSR];
1284 dbsr &= ~0x00000300;
1285 dbsr |= 0x00000100;
1286 env->spr[SPR_40x_DBSR] = dbsr;
1287 }
1288
1289 void ppc40x_chip_reset(PowerPCCPU *cpu)
1290 {
1291 CPUPPCState *env = &cpu->env;
1292 target_ulong dbsr;
1293
1294 printf("Reset PowerPC chip\n");
1295 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1296 /* XXX: TODO reset all internal peripherals */
1297 dbsr = env->spr[SPR_40x_DBSR];
1298 dbsr &= ~0x00000300;
1299 dbsr |= 0x00000200;
1300 env->spr[SPR_40x_DBSR] = dbsr;
1301 }
1302
1303 void ppc40x_system_reset(PowerPCCPU *cpu)
1304 {
1305 printf("Reset PowerPC system\n");
1306 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1307 }
1308
1309 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1310 {
1311 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1312
1313 switch ((val >> 28) & 0x3) {
1314 case 0x0:
1315 /* No action */
1316 break;
1317 case 0x1:
1318 /* Core reset */
1319 ppc40x_core_reset(cpu);
1320 break;
1321 case 0x2:
1322 /* Chip reset */
1323 ppc40x_chip_reset(cpu);
1324 break;
1325 case 0x3:
1326 /* System reset */
1327 ppc40x_system_reset(cpu);
1328 break;
1329 }
1330 }
1331
1332 /*****************************************************************************/
1333 /* PowerPC 405CR */
1334 enum {
1335 PPC405CR_CPC0_PLLMR = 0x0B0,
1336 PPC405CR_CPC0_CR0 = 0x0B1,
1337 PPC405CR_CPC0_CR1 = 0x0B2,
1338 PPC405CR_CPC0_PSR = 0x0B4,
1339 PPC405CR_CPC0_JTAGID = 0x0B5,
1340 PPC405CR_CPC0_ER = 0x0B9,
1341 PPC405CR_CPC0_FR = 0x0BA,
1342 PPC405CR_CPC0_SR = 0x0BB,
1343 };
1344
1345 enum {
1346 PPC405CR_CPU_CLK = 0,
1347 PPC405CR_TMR_CLK = 1,
1348 PPC405CR_PLB_CLK = 2,
1349 PPC405CR_SDRAM_CLK = 3,
1350 PPC405CR_OPB_CLK = 4,
1351 PPC405CR_EXT_CLK = 5,
1352 PPC405CR_UART_CLK = 6,
1353 PPC405CR_CLK_NB = 7,
1354 };
1355
1356 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1357 struct ppc405cr_cpc_t {
1358 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1359 uint32_t sysclk;
1360 uint32_t psr;
1361 uint32_t cr0;
1362 uint32_t cr1;
1363 uint32_t jtagid;
1364 uint32_t pllmr;
1365 uint32_t er;
1366 uint32_t fr;
1367 };
1368
1369 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1370 {
1371 uint64_t VCO_out, PLL_out;
1372 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1373 int M, D0, D1, D2;
1374
1375 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1376 if (cpc->pllmr & 0x80000000) {
1377 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1378 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1379 M = D0 * D1 * D2;
1380 VCO_out = (uint64_t)cpc->sysclk * M;
1381 if (VCO_out < 400000000 || VCO_out > 800000000) {
1382 /* PLL cannot lock */
1383 cpc->pllmr &= ~0x80000000;
1384 goto bypass_pll;
1385 }
1386 PLL_out = VCO_out / D2;
1387 } else {
1388 /* Bypass PLL */
1389 bypass_pll:
1390 M = D0;
1391 PLL_out = (uint64_t)cpc->sysclk * M;
1392 }
1393 CPU_clk = PLL_out;
1394 if (cpc->cr1 & 0x00800000)
1395 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1396 else
1397 TMR_clk = CPU_clk;
1398 PLB_clk = CPU_clk / D0;
1399 SDRAM_clk = PLB_clk;
1400 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1401 OPB_clk = PLB_clk / D0;
1402 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1403 EXT_clk = PLB_clk / D0;
1404 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1405 UART_clk = CPU_clk / D0;
1406 /* Setup CPU clocks */
1407 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1408 /* Setup time-base clock */
1409 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1410 /* Setup PLB clock */
1411 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1412 /* Setup SDRAM clock */
1413 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1414 /* Setup OPB clock */
1415 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1416 /* Setup external clock */
1417 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1418 /* Setup UART clock */
1419 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1420 }
1421
1422 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1423 {
1424 ppc405cr_cpc_t *cpc;
1425 uint32_t ret;
1426
1427 cpc = opaque;
1428 switch (dcrn) {
1429 case PPC405CR_CPC0_PLLMR:
1430 ret = cpc->pllmr;
1431 break;
1432 case PPC405CR_CPC0_CR0:
1433 ret = cpc->cr0;
1434 break;
1435 case PPC405CR_CPC0_CR1:
1436 ret = cpc->cr1;
1437 break;
1438 case PPC405CR_CPC0_PSR:
1439 ret = cpc->psr;
1440 break;
1441 case PPC405CR_CPC0_JTAGID:
1442 ret = cpc->jtagid;
1443 break;
1444 case PPC405CR_CPC0_ER:
1445 ret = cpc->er;
1446 break;
1447 case PPC405CR_CPC0_FR:
1448 ret = cpc->fr;
1449 break;
1450 case PPC405CR_CPC0_SR:
1451 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1452 break;
1453 default:
1454 /* Avoid gcc warning */
1455 ret = 0;
1456 break;
1457 }
1458
1459 return ret;
1460 }
1461
1462 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1463 {
1464 ppc405cr_cpc_t *cpc;
1465
1466 cpc = opaque;
1467 switch (dcrn) {
1468 case PPC405CR_CPC0_PLLMR:
1469 cpc->pllmr = val & 0xFFF77C3F;
1470 break;
1471 case PPC405CR_CPC0_CR0:
1472 cpc->cr0 = val & 0x0FFFFFFE;
1473 break;
1474 case PPC405CR_CPC0_CR1:
1475 cpc->cr1 = val & 0x00800000;
1476 break;
1477 case PPC405CR_CPC0_PSR:
1478 /* Read-only */
1479 break;
1480 case PPC405CR_CPC0_JTAGID:
1481 /* Read-only */
1482 break;
1483 case PPC405CR_CPC0_ER:
1484 cpc->er = val & 0xBFFC0000;
1485 break;
1486 case PPC405CR_CPC0_FR:
1487 cpc->fr = val & 0xBFFC0000;
1488 break;
1489 case PPC405CR_CPC0_SR:
1490 /* Read-only */
1491 break;
1492 }
1493 }
1494
1495 static void ppc405cr_cpc_reset (void *opaque)
1496 {
1497 ppc405cr_cpc_t *cpc;
1498 int D;
1499
1500 cpc = opaque;
1501 /* Compute PLLMR value from PSR settings */
1502 cpc->pllmr = 0x80000000;
1503 /* PFWD */
1504 switch ((cpc->psr >> 30) & 3) {
1505 case 0:
1506 /* Bypass */
1507 cpc->pllmr &= ~0x80000000;
1508 break;
1509 case 1:
1510 /* Divide by 3 */
1511 cpc->pllmr |= 5 << 16;
1512 break;
1513 case 2:
1514 /* Divide by 4 */
1515 cpc->pllmr |= 4 << 16;
1516 break;
1517 case 3:
1518 /* Divide by 6 */
1519 cpc->pllmr |= 2 << 16;
1520 break;
1521 }
1522 /* PFBD */
1523 D = (cpc->psr >> 28) & 3;
1524 cpc->pllmr |= (D + 1) << 20;
1525 /* PT */
1526 D = (cpc->psr >> 25) & 7;
1527 switch (D) {
1528 case 0x2:
1529 cpc->pllmr |= 0x13;
1530 break;
1531 case 0x4:
1532 cpc->pllmr |= 0x15;
1533 break;
1534 case 0x5:
1535 cpc->pllmr |= 0x16;
1536 break;
1537 default:
1538 break;
1539 }
1540 /* PDC */
1541 D = (cpc->psr >> 23) & 3;
1542 cpc->pllmr |= D << 26;
1543 /* ODP */
1544 D = (cpc->psr >> 21) & 3;
1545 cpc->pllmr |= D << 10;
1546 /* EBPD */
1547 D = (cpc->psr >> 17) & 3;
1548 cpc->pllmr |= D << 24;
1549 cpc->cr0 = 0x0000003C;
1550 cpc->cr1 = 0x2B0D8800;
1551 cpc->er = 0x00000000;
1552 cpc->fr = 0x00000000;
1553 ppc405cr_clk_setup(cpc);
1554 }
1555
1556 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
1557 {
1558 int D;
1559
1560 /* XXX: this should be read from IO pins */
1561 cpc->psr = 0x00000000; /* 8 bits ROM */
1562 /* PFWD */
1563 D = 0x2; /* Divide by 4 */
1564 cpc->psr |= D << 30;
1565 /* PFBD */
1566 D = 0x1; /* Divide by 2 */
1567 cpc->psr |= D << 28;
1568 /* PDC */
1569 D = 0x1; /* Divide by 2 */
1570 cpc->psr |= D << 23;
1571 /* PT */
1572 D = 0x5; /* M = 16 */
1573 cpc->psr |= D << 25;
1574 /* ODP */
1575 D = 0x1; /* Divide by 2 */
1576 cpc->psr |= D << 21;
1577 /* EBDP */
1578 D = 0x2; /* Divide by 4 */
1579 cpc->psr |= D << 17;
1580 }
1581
1582 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
1583 uint32_t sysclk)
1584 {
1585 ppc405cr_cpc_t *cpc;
1586
1587 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
1588 memcpy(cpc->clk_setup, clk_setup,
1589 PPC405CR_CLK_NB * sizeof(clk_setup_t));
1590 cpc->sysclk = sysclk;
1591 cpc->jtagid = 0x42051049;
1592 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
1593 &dcr_read_crcpc, &dcr_write_crcpc);
1594 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
1595 &dcr_read_crcpc, &dcr_write_crcpc);
1596 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
1597 &dcr_read_crcpc, &dcr_write_crcpc);
1598 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
1599 &dcr_read_crcpc, &dcr_write_crcpc);
1600 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
1601 &dcr_read_crcpc, &dcr_write_crcpc);
1602 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
1603 &dcr_read_crcpc, &dcr_write_crcpc);
1604 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
1605 &dcr_read_crcpc, &dcr_write_crcpc);
1606 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
1607 &dcr_read_crcpc, &dcr_write_crcpc);
1608 ppc405cr_clk_init(cpc);
1609 qemu_register_reset(ppc405cr_cpc_reset, cpc);
1610 }
1611
1612 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
1613 MemoryRegion ram_memories[4],
1614 hwaddr ram_bases[4],
1615 hwaddr ram_sizes[4],
1616 uint32_t sysclk, qemu_irq **picp,
1617 int do_init)
1618 {
1619 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1620 qemu_irq dma_irqs[4];
1621 PowerPCCPU *cpu;
1622 CPUPPCState *env;
1623 qemu_irq *pic, *irqs;
1624
1625 memset(clk_setup, 0, sizeof(clk_setup));
1626 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
1627 &clk_setup[PPC405CR_TMR_CLK], sysclk);
1628 env = &cpu->env;
1629 /* Memory mapped devices registers */
1630 /* PLB arbitrer */
1631 ppc4xx_plb_init(env);
1632 /* PLB to OPB bridge */
1633 ppc4xx_pob_init(env);
1634 /* OBP arbitrer */
1635 ppc4xx_opba_init(0xef600600);
1636 /* Universal interrupt controller */
1637 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
1638 irqs[PPCUIC_OUTPUT_INT] =
1639 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
1640 irqs[PPCUIC_OUTPUT_CINT] =
1641 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
1642 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
1643 *picp = pic;
1644 /* SDRAM controller */
1645 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
1646 ram_bases, ram_sizes, do_init);
1647 /* External bus controller */
1648 ppc405_ebc_init(env);
1649 /* DMA controller */
1650 dma_irqs[0] = pic[26];
1651 dma_irqs[1] = pic[25];
1652 dma_irqs[2] = pic[24];
1653 dma_irqs[3] = pic[23];
1654 ppc405_dma_init(env, dma_irqs);
1655 /* Serial ports */
1656 if (serial_hds[0] != NULL) {
1657 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
1658 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
1659 DEVICE_BIG_ENDIAN);
1660 }
1661 if (serial_hds[1] != NULL) {
1662 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
1663 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
1664 DEVICE_BIG_ENDIAN);
1665 }
1666 /* IIC controller */
1667 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
1668 /* GPIO */
1669 ppc405_gpio_init(0xef600700);
1670 /* CPU control */
1671 ppc405cr_cpc_init(env, clk_setup, sysclk);
1672
1673 return env;
1674 }
1675
1676 /*****************************************************************************/
1677 /* PowerPC 405EP */
1678 /* CPU control */
1679 enum {
1680 PPC405EP_CPC0_PLLMR0 = 0x0F0,
1681 PPC405EP_CPC0_BOOT = 0x0F1,
1682 PPC405EP_CPC0_EPCTL = 0x0F3,
1683 PPC405EP_CPC0_PLLMR1 = 0x0F4,
1684 PPC405EP_CPC0_UCR = 0x0F5,
1685 PPC405EP_CPC0_SRR = 0x0F6,
1686 PPC405EP_CPC0_JTAGID = 0x0F7,
1687 PPC405EP_CPC0_PCI = 0x0F9,
1688 #if 0
1689 PPC405EP_CPC0_ER = xxx,
1690 PPC405EP_CPC0_FR = xxx,
1691 PPC405EP_CPC0_SR = xxx,
1692 #endif
1693 };
1694
1695 enum {
1696 PPC405EP_CPU_CLK = 0,
1697 PPC405EP_PLB_CLK = 1,
1698 PPC405EP_OPB_CLK = 2,
1699 PPC405EP_EBC_CLK = 3,
1700 PPC405EP_MAL_CLK = 4,
1701 PPC405EP_PCI_CLK = 5,
1702 PPC405EP_UART0_CLK = 6,
1703 PPC405EP_UART1_CLK = 7,
1704 PPC405EP_CLK_NB = 8,
1705 };
1706
1707 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
1708 struct ppc405ep_cpc_t {
1709 uint32_t sysclk;
1710 clk_setup_t clk_setup[PPC405EP_CLK_NB];
1711 uint32_t boot;
1712 uint32_t epctl;
1713 uint32_t pllmr[2];
1714 uint32_t ucr;
1715 uint32_t srr;
1716 uint32_t jtagid;
1717 uint32_t pci;
1718 /* Clock and power management */
1719 uint32_t er;
1720 uint32_t fr;
1721 uint32_t sr;
1722 };
1723
1724 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
1725 {
1726 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
1727 uint32_t UART0_clk, UART1_clk;
1728 uint64_t VCO_out, PLL_out;
1729 int M, D;
1730
1731 VCO_out = 0;
1732 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
1733 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
1734 #ifdef DEBUG_CLOCKS_LL
1735 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
1736 #endif
1737 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
1738 #ifdef DEBUG_CLOCKS_LL
1739 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
1740 #endif
1741 VCO_out = (uint64_t)cpc->sysclk * M * D;
1742 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
1743 /* Error - unlock the PLL */
1744 printf("VCO out of range %" PRIu64 "\n", VCO_out);
1745 #if 0
1746 cpc->pllmr[1] &= ~0x80000000;
1747 goto pll_bypass;
1748 #endif
1749 }
1750 PLL_out = VCO_out / D;
1751 /* Pretend the PLL is locked */
1752 cpc->boot |= 0x00000001;
1753 } else {
1754 #if 0
1755 pll_bypass:
1756 #endif
1757 PLL_out = cpc->sysclk;
1758 if (cpc->pllmr[1] & 0x40000000) {
1759 /* Pretend the PLL is not locked */
1760 cpc->boot &= ~0x00000001;
1761 }
1762 }
1763 /* Now, compute all other clocks */
1764 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
1765 #ifdef DEBUG_CLOCKS_LL
1766 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
1767 #endif
1768 CPU_clk = PLL_out / D;
1769 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
1770 #ifdef DEBUG_CLOCKS_LL
1771 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
1772 #endif
1773 PLB_clk = CPU_clk / D;
1774 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
1775 #ifdef DEBUG_CLOCKS_LL
1776 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
1777 #endif
1778 OPB_clk = PLB_clk / D;
1779 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
1780 #ifdef DEBUG_CLOCKS_LL
1781 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
1782 #endif
1783 EBC_clk = PLB_clk / D;
1784 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
1785 #ifdef DEBUG_CLOCKS_LL
1786 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
1787 #endif
1788 MAL_clk = PLB_clk / D;
1789 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
1790 #ifdef DEBUG_CLOCKS_LL
1791 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
1792 #endif
1793 PCI_clk = PLB_clk / D;
1794 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
1795 #ifdef DEBUG_CLOCKS_LL
1796 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
1797 #endif
1798 UART0_clk = PLL_out / D;
1799 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
1800 #ifdef DEBUG_CLOCKS_LL
1801 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
1802 #endif
1803 UART1_clk = PLL_out / D;
1804 #ifdef DEBUG_CLOCKS
1805 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
1806 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
1807 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
1808 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
1809 " UART1 %" PRIu32 "\n",
1810 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
1811 UART0_clk, UART1_clk);
1812 #endif
1813 /* Setup CPU clocks */
1814 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
1815 /* Setup PLB clock */
1816 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
1817 /* Setup OPB clock */
1818 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
1819 /* Setup external clock */
1820 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
1821 /* Setup MAL clock */
1822 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
1823 /* Setup PCI clock */
1824 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
1825 /* Setup UART0 clock */
1826 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
1827 /* Setup UART1 clock */
1828 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
1829 }
1830
1831 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
1832 {
1833 ppc405ep_cpc_t *cpc;
1834 uint32_t ret;
1835
1836 cpc = opaque;
1837 switch (dcrn) {
1838 case PPC405EP_CPC0_BOOT:
1839 ret = cpc->boot;
1840 break;
1841 case PPC405EP_CPC0_EPCTL:
1842 ret = cpc->epctl;
1843 break;
1844 case PPC405EP_CPC0_PLLMR0:
1845 ret = cpc->pllmr[0];
1846 break;
1847 case PPC405EP_CPC0_PLLMR1:
1848 ret = cpc->pllmr[1];
1849 break;
1850 case PPC405EP_CPC0_UCR:
1851 ret = cpc->ucr;
1852 break;
1853 case PPC405EP_CPC0_SRR:
1854 ret = cpc->srr;
1855 break;
1856 case PPC405EP_CPC0_JTAGID:
1857 ret = cpc->jtagid;
1858 break;
1859 case PPC405EP_CPC0_PCI:
1860 ret = cpc->pci;
1861 break;
1862 default:
1863 /* Avoid gcc warning */
1864 ret = 0;
1865 break;
1866 }
1867
1868 return ret;
1869 }
1870
1871 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
1872 {
1873 ppc405ep_cpc_t *cpc;
1874
1875 cpc = opaque;
1876 switch (dcrn) {
1877 case PPC405EP_CPC0_BOOT:
1878 /* Read-only register */
1879 break;
1880 case PPC405EP_CPC0_EPCTL:
1881 /* Don't care for now */
1882 cpc->epctl = val & 0xC00000F3;
1883 break;
1884 case PPC405EP_CPC0_PLLMR0:
1885 cpc->pllmr[0] = val & 0x00633333;
1886 ppc405ep_compute_clocks(cpc);
1887 break;
1888 case PPC405EP_CPC0_PLLMR1:
1889 cpc->pllmr[1] = val & 0xC0F73FFF;
1890 ppc405ep_compute_clocks(cpc);
1891 break;
1892 case PPC405EP_CPC0_UCR:
1893 /* UART control - don't care for now */
1894 cpc->ucr = val & 0x003F7F7F;
1895 break;
1896 case PPC405EP_CPC0_SRR:
1897 cpc->srr = val;
1898 break;
1899 case PPC405EP_CPC0_JTAGID:
1900 /* Read-only */
1901 break;
1902 case PPC405EP_CPC0_PCI:
1903 cpc->pci = val;
1904 break;
1905 }
1906 }
1907
1908 static void ppc405ep_cpc_reset (void *opaque)
1909 {
1910 ppc405ep_cpc_t *cpc = opaque;
1911
1912 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
1913 cpc->epctl = 0x00000000;
1914 cpc->pllmr[0] = 0x00011010;
1915 cpc->pllmr[1] = 0x40000000;
1916 cpc->ucr = 0x00000000;
1917 cpc->srr = 0x00040000;
1918 cpc->pci = 0x00000000;
1919 cpc->er = 0x00000000;
1920 cpc->fr = 0x00000000;
1921 cpc->sr = 0x00000000;
1922 ppc405ep_compute_clocks(cpc);
1923 }
1924
1925 /* XXX: sysclk should be between 25 and 100 MHz */
1926 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
1927 uint32_t sysclk)
1928 {
1929 ppc405ep_cpc_t *cpc;
1930
1931 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
1932 memcpy(cpc->clk_setup, clk_setup,
1933 PPC405EP_CLK_NB * sizeof(clk_setup_t));
1934 cpc->jtagid = 0x20267049;
1935 cpc->sysclk = sysclk;
1936 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
1937 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
1938 &dcr_read_epcpc, &dcr_write_epcpc);
1939 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
1940 &dcr_read_epcpc, &dcr_write_epcpc);
1941 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
1942 &dcr_read_epcpc, &dcr_write_epcpc);
1943 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
1944 &dcr_read_epcpc, &dcr_write_epcpc);
1945 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
1946 &dcr_read_epcpc, &dcr_write_epcpc);
1947 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
1948 &dcr_read_epcpc, &dcr_write_epcpc);
1949 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
1950 &dcr_read_epcpc, &dcr_write_epcpc);
1951 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
1952 &dcr_read_epcpc, &dcr_write_epcpc);
1953 #if 0
1954 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
1955 &dcr_read_epcpc, &dcr_write_epcpc);
1956 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
1957 &dcr_read_epcpc, &dcr_write_epcpc);
1958 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
1959 &dcr_read_epcpc, &dcr_write_epcpc);
1960 #endif
1961 }
1962
1963 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
1964 MemoryRegion ram_memories[2],
1965 hwaddr ram_bases[2],
1966 hwaddr ram_sizes[2],
1967 uint32_t sysclk, qemu_irq **picp,
1968 int do_init)
1969 {
1970 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
1971 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
1972 PowerPCCPU *cpu;
1973 CPUPPCState *env;
1974 qemu_irq *pic, *irqs;
1975
1976 memset(clk_setup, 0, sizeof(clk_setup));
1977 /* init CPUs */
1978 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
1979 &tlb_clk_setup, sysclk);
1980 env = &cpu->env;
1981 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
1982 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
1983 /* Internal devices init */
1984 /* Memory mapped devices registers */
1985 /* PLB arbitrer */
1986 ppc4xx_plb_init(env);
1987 /* PLB to OPB bridge */
1988 ppc4xx_pob_init(env);
1989 /* OBP arbitrer */
1990 ppc4xx_opba_init(0xef600600);
1991 /* Initialize timers */
1992 ppc_booke_timers_init(cpu, sysclk, 0);
1993 /* Universal interrupt controller */
1994 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
1995 irqs[PPCUIC_OUTPUT_INT] =
1996 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
1997 irqs[PPCUIC_OUTPUT_CINT] =
1998 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
1999 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2000 *picp = pic;
2001 /* SDRAM controller */
2002 /* XXX 405EP has no ECC interrupt */
2003 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2004 ram_bases, ram_sizes, do_init);
2005 /* External bus controller */
2006 ppc405_ebc_init(env);
2007 /* DMA controller */
2008 dma_irqs[0] = pic[5];
2009 dma_irqs[1] = pic[6];
2010 dma_irqs[2] = pic[7];
2011 dma_irqs[3] = pic[8];
2012 ppc405_dma_init(env, dma_irqs);
2013 /* IIC controller */
2014 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
2015 /* GPIO */
2016 ppc405_gpio_init(0xef600700);
2017 /* Serial ports */
2018 if (serial_hds[0] != NULL) {
2019 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2020 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2021 DEVICE_BIG_ENDIAN);
2022 }
2023 if (serial_hds[1] != NULL) {
2024 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2025 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2026 DEVICE_BIG_ENDIAN);
2027 }
2028 /* OCM */
2029 ppc405_ocm_init(env);
2030 /* GPT */
2031 gpt_irqs[0] = pic[19];
2032 gpt_irqs[1] = pic[20];
2033 gpt_irqs[2] = pic[21];
2034 gpt_irqs[3] = pic[22];
2035 gpt_irqs[4] = pic[23];
2036 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2037 /* PCI */
2038 /* Uses pic[3], pic[16], pic[18] */
2039 /* MAL */
2040 mal_irqs[0] = pic[11];
2041 mal_irqs[1] = pic[12];
2042 mal_irqs[2] = pic[13];
2043 mal_irqs[3] = pic[14];
2044 ppc4xx_mal_init(env, 4, 2, mal_irqs);
2045 /* Ethernet */
2046 /* Uses pic[9], pic[15], pic[17] */
2047 /* CPU control */
2048 ppc405ep_cpc_init(env, clk_setup, sysclk);
2049
2050 return env;
2051 }
AR7 emulation for QEMU