target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  34                                 int error_code)
  35 {
  36     do_raise_exception_err(env, exception, error_code, 0);
  37 }
  38
  39 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  40 {
  41     do_raise_exception(env, exception, GETPC());
  42 }
  43
  44 void helper_raise_exception_debug(CPUMIPSState *env)
  45 {
  46     do_raise_exception(env, EXCP_DEBUG, 0);
  47 }
  48
  49 static void raise_exception(CPUMIPSState *env, uint32_t exception)
  50 {
  51     do_raise_exception(env, exception, 0);
  52 }
  53
  54 #if defined(CONFIG_USER_ONLY)
  55 #define HELPER_LD(name, insn, type)                                     \
  56 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  57                              int mem_idx, uintptr_t retaddr)            \
  58 {                                                                       \
  59     return (type) cpu_##insn##_data_ra(env, addr, retaddr);             \
  60 }
  61 #else
  62 #define HELPER_LD(name, insn, type)                                     \
  63 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  64                              int mem_idx, uintptr_t retaddr)            \
  65 {                                                                       \
  66     switch (mem_idx)                                                    \
  67     {                                                                   \
  68     case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr);   \
  69     case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr);    \
  70     default:                                                            \
  71     case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr);     \
  72     }                                                                   \
  73 }
  74 #endif
  75 HELPER_LD(lw, ldl, int32_t)
  76 #if defined(TARGET_MIPS64)
  77 HELPER_LD(ld, ldq, int64_t)
  78 #endif
  79 #undef HELPER_LD
  80
  81 #if defined(CONFIG_USER_ONLY)
  82 #define HELPER_ST(name, insn, type)                                     \
  83 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  84                              type val, int mem_idx, uintptr_t retaddr)  \
  85 {                                                                       \
  86     cpu_##insn##_data_ra(env, addr, val, retaddr);                      \
  87 }
  88 #else
  89 #define HELPER_ST(name, insn, type)                                     \
  90 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  91                              type val, int mem_idx, uintptr_t retaddr)  \
  92 {                                                                       \
  93     switch (mem_idx)                                                    \
  94     {                                                                   \
  95     case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break;     \
  96     case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break;      \
  97     default:                                                            \
  98     case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break;       \
  99     }                                                                   \
 100 }
 101 #endif
 102 HELPER_ST(sb, stb, uint8_t)
 103 HELPER_ST(sw, stl, uint32_t)
 104 #if defined(TARGET_MIPS64)
 105 HELPER_ST(sd, stq, uint64_t)
 106 #endif
 107 #undef HELPER_ST
 108
 109 target_ulong helper_clo (target_ulong arg1)
 110 {
 111     return clo32(arg1);
 112 }
 113
 114 target_ulong helper_clz (target_ulong arg1)
 115 {
 116     return clz32(arg1);
 117 }
 118
 119 #if defined(TARGET_MIPS64)
 120 target_ulong helper_dclo (target_ulong arg1)
 121 {
 122     return clo64(arg1);
 123 }
 124
 125 target_ulong helper_dclz (target_ulong arg1)
 126 {
 127     return clz64(arg1);
 128 }
 129 #endif /* TARGET_MIPS64 */
 130
 131 /* 64 bits arithmetic for 32 bits hosts */
 132 static inline uint64_t get_HILO(CPUMIPSState *env)
 133 {
 134     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 135 }
 136
 137 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 138 {
 139     target_ulong tmp;
 140     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 141     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 142     return tmp;
 143 }
 144
 145 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 146 {
 147     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 148     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 149     return tmp;
 150 }
 151
 152 /* Multiplication variants of the vr54xx. */
 153 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 154                          target_ulong arg2)
 155 {
 156     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 157                                  (int64_t)(int32_t)arg2));
 158 }
 159
 160 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 161                           target_ulong arg2)
 162 {
 163     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 164                        (uint64_t)(uint32_t)arg2);
 165 }
 166
 167 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 168                          target_ulong arg2)
 169 {
 170     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 171                        (int64_t)(int32_t)arg2);
 172 }
 173
 174 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 175                            target_ulong arg2)
 176 {
 177     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 178                        (int64_t)(int32_t)arg2);
 179 }
 180
 181 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 182                           target_ulong arg2)
 183 {
 184     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 185                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 186 }
 187
 188 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 189                             target_ulong arg2)
 190 {
 191     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 192                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 193 }
 194
 195 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 196                          target_ulong arg2)
 197 {
 198     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 199                        (int64_t)(int32_t)arg2);
 200 }
 201
 202 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 203                            target_ulong arg2)
 204 {
 205     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 206                        (int64_t)(int32_t)arg2);
 207 }
 208
 209 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 210                           target_ulong arg2)
 211 {
 212     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 213                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 214 }
 215
 216 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 217                             target_ulong arg2)
 218 {
 219     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 220                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 221 }
 222
 223 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 224                           target_ulong arg2)
 225 {
 226     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 227 }
 228
 229 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 230                            target_ulong arg2)
 231 {
 232     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 233                        (uint64_t)(uint32_t)arg2);
 234 }
 235
 236 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 237                            target_ulong arg2)
 238 {
 239     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 240                        (int64_t)(int32_t)arg2);
 241 }
 242
 243 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 244                             target_ulong arg2)
 245 {
 246     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 247                        (uint64_t)(uint32_t)arg2);
 248 }
 249
 250 static inline target_ulong bitswap(target_ulong v)
 251 {
 252     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 253               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 254     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 255               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 256     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 257               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 258     return v;
 259 }
 260
 261 #ifdef TARGET_MIPS64
 262 target_ulong helper_dbitswap(target_ulong rt)
 263 {
 264     return bitswap(rt);
 265 }
 266 #endif
 267
 268 target_ulong helper_bitswap(target_ulong rt)
 269 {
 270     return (int32_t)bitswap(rt);
 271 }
 272
 273 #ifndef CONFIG_USER_ONLY
 274
 275 static inline hwaddr do_translate_address(CPUMIPSState *env,
 276                                                       target_ulong address,
 277                                                       int rw, uintptr_t retaddr)
 278 {
 279     hwaddr lladdr;
 280     CPUState *cs = CPU(mips_env_get_cpu(env));
 281
 282     lladdr = cpu_mips_translate_address(env, address, rw);
 283
 284     if (lladdr == -1LL) {
 285         cpu_loop_exit_restore(cs, retaddr);
 286     } else {
 287         return lladdr;
 288     }
 289 }
 290
 291 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 292 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 293 {                                                                             \
 294     if (arg & almask) {                                                       \
 295         env->CP0_BadVAddr = arg;                                              \
 296         do_raise_exception(env, EXCP_AdEL, GETPC());                          \
 297     }                                                                         \
 298     env->lladdr = do_translate_address(env, arg, 0, GETPC());                 \
 299     env->llval = do_##insn(env, arg, mem_idx, GETPC());                       \
 300     return env->llval;                                                        \
 301 }
 302 HELPER_LD_ATOMIC(ll, lw, 0x3)
 303 #ifdef TARGET_MIPS64
 304 HELPER_LD_ATOMIC(lld, ld, 0x7)
 305 #endif
 306 #undef HELPER_LD_ATOMIC
 307
 308 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 310                            target_ulong arg2, int mem_idx)                    \
 311 {                                                                             \
 312     target_long tmp;                                                          \
 313                                                                               \
 314     if (arg2 & almask) {                                                      \
 315         env->CP0_BadVAddr = arg2;                                             \
 316         do_raise_exception(env, EXCP_AdES, GETPC());                          \
 317     }                                                                         \
 318     if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) {         \
 319         tmp = do_##ld_insn(env, arg2, mem_idx, GETPC());                      \
 320         if (tmp == env->llval) {                                              \
 321             do_##st_insn(env, arg2, arg1, mem_idx, GETPC());                  \
 322             return 1;                                                         \
 323         }                                                                     \
 324     }                                                                         \
 325     return 0;                                                                 \
 326 }
 327 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 328 #ifdef TARGET_MIPS64
 329 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 330 #endif
 331 #undef HELPER_ST_ATOMIC
 332 #endif
 333
 334 #ifdef TARGET_WORDS_BIGENDIAN
 335 #define GET_LMASK(v) ((v) & 3)
 336 #define GET_OFFSET(addr, offset) (addr + (offset))
 337 #else
 338 #define GET_LMASK(v) (((v) & 3) ^ 3)
 339 #define GET_OFFSET(addr, offset) (addr - (offset))
 340 #endif
 341
 342 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 343                 int mem_idx)
 344 {
 345     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
 346
 347     if (GET_LMASK(arg2) <= 2) {
 348         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
 349               GETPC());
 350     }
 351
 352     if (GET_LMASK(arg2) <= 1) {
 353         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
 354               GETPC());
 355     }
 356
 357     if (GET_LMASK(arg2) == 0) {
 358         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
 359               GETPC());
 360     }
 361 }
 362
 363 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 364                 int mem_idx)
 365 {
 366     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 367
 368     if (GET_LMASK(arg2) >= 1) {
 369         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 370               GETPC());
 371     }
 372
 373     if (GET_LMASK(arg2) >= 2) {
 374         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 375               GETPC());
 376     }
 377
 378     if (GET_LMASK(arg2) == 3) {
 379         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 380               GETPC());
 381     }
 382 }
 383
 384 #if defined(TARGET_MIPS64)
 385 /* "half" load and stores.  We must do the memory access inline,
 386    or fault handling won't work.  */
 387
 388 #ifdef TARGET_WORDS_BIGENDIAN
 389 #define GET_LMASK64(v) ((v) & 7)
 390 #else
 391 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 392 #endif
 393
 394 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 395                 int mem_idx)
 396 {
 397     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
 398
 399     if (GET_LMASK64(arg2) <= 6) {
 400         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
 401               GETPC());
 402     }
 403
 404     if (GET_LMASK64(arg2) <= 5) {
 405         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
 406               GETPC());
 407     }
 408
 409     if (GET_LMASK64(arg2) <= 4) {
 410         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
 411               GETPC());
 412     }
 413
 414     if (GET_LMASK64(arg2) <= 3) {
 415         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
 416               GETPC());
 417     }
 418
 419     if (GET_LMASK64(arg2) <= 2) {
 420         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
 421               GETPC());
 422     }
 423
 424     if (GET_LMASK64(arg2) <= 1) {
 425         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
 426               GETPC());
 427     }
 428
 429     if (GET_LMASK64(arg2) <= 0) {
 430         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
 431               GETPC());
 432     }
 433 }
 434
 435 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 436                 int mem_idx)
 437 {
 438     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 439
 440     if (GET_LMASK64(arg2) >= 1) {
 441         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 442               GETPC());
 443     }
 444
 445     if (GET_LMASK64(arg2) >= 2) {
 446         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 447               GETPC());
 448     }
 449
 450     if (GET_LMASK64(arg2) >= 3) {
 451         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 452               GETPC());
 453     }
 454
 455     if (GET_LMASK64(arg2) >= 4) {
 456         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
 457               GETPC());
 458     }
 459
 460     if (GET_LMASK64(arg2) >= 5) {
 461         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
 462               GETPC());
 463     }
 464
 465     if (GET_LMASK64(arg2) >= 6) {
 466         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
 467               GETPC());
 468     }
 469
 470     if (GET_LMASK64(arg2) == 7) {
 471         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
 472               GETPC());
 473     }
 474 }
 475 #endif /* TARGET_MIPS64 */
 476
 477 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 478
 479 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 480                 uint32_t mem_idx)
 481 {
 482     target_ulong base_reglist = reglist & 0xf;
 483     target_ulong do_r31 = reglist & 0x10;
 484
 485     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 486         target_ulong i;
 487
 488         for (i = 0; i < base_reglist; i++) {
 489             env->active_tc.gpr[multiple_regs[i]] =
 490                 (target_long)do_lw(env, addr, mem_idx, GETPC());
 491             addr += 4;
 492         }
 493     }
 494
 495     if (do_r31) {
 496         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
 497                                                     GETPC());
 498     }
 499 }
 500
 501 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 502                 uint32_t mem_idx)
 503 {
 504     target_ulong base_reglist = reglist & 0xf;
 505     target_ulong do_r31 = reglist & 0x10;
 506
 507     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 508         target_ulong i;
 509
 510         for (i = 0; i < base_reglist; i++) {
 511             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 512                   GETPC());
 513             addr += 4;
 514         }
 515     }
 516
 517     if (do_r31) {
 518         do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 519     }
 520 }
 521
 522 #if defined(TARGET_MIPS64)
 523 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 524                 uint32_t mem_idx)
 525 {
 526     target_ulong base_reglist = reglist & 0xf;
 527     target_ulong do_r31 = reglist & 0x10;
 528
 529     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 530         target_ulong i;
 531
 532         for (i = 0; i < base_reglist; i++) {
 533             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
 534                                                          GETPC());
 535             addr += 8;
 536         }
 537     }
 538
 539     if (do_r31) {
 540         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
 541     }
 542 }
 543
 544 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 545                 uint32_t mem_idx)
 546 {
 547     target_ulong base_reglist = reglist & 0xf;
 548     target_ulong do_r31 = reglist & 0x10;
 549
 550     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 551         target_ulong i;
 552
 553         for (i = 0; i < base_reglist; i++) {
 554             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 555                   GETPC());
 556             addr += 8;
 557         }
 558     }
 559
 560     if (do_r31) {
 561         do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 562     }
 563 }
 564 #endif
 565
 566 #ifndef CONFIG_USER_ONLY
 567 /* SMP helpers.  */
 568 static bool mips_vpe_is_wfi(MIPSCPU *c)
 569 {
 570     CPUState *cpu = CPU(c);
 571     CPUMIPSState *env = &c->env;
 572
 573     /* If the VPE is halted but otherwise active, it means it's waiting for
 574        an interrupt.  */
 575     return cpu->halted && mips_vpe_active(env);
 576 }
 577
 578 static inline void mips_vpe_wake(MIPSCPU *c)
 579 {
 580     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 581        because there might be other conditions that state that c should
 582        be sleeping.  */
 583     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 584 }
 585
 586 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 587 {
 588     CPUState *cs = CPU(cpu);
 589
 590     /* The VPE was shut off, really go to bed.
 591        Reset any old _WAKE requests.  */
 592     cs->halted = 1;
 593     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 594 }
 595
 596 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 597 {
 598     CPUMIPSState *c = &cpu->env;
 599
 600     /* FIXME: TC reschedule.  */
 601     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 602         mips_vpe_wake(cpu);
 603     }
 604 }
 605
 606 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 607 {
 608     CPUMIPSState *c = &cpu->env;
 609
 610     /* FIXME: TC reschedule.  */
 611     if (!mips_vpe_active(c)) {
 612         mips_vpe_sleep(cpu);
 613     }
 614 }
 615
 616 /**
 617  * mips_cpu_map_tc:
 618  * @env: CPU from which mapping is performed.
 619  * @tc: Should point to an int with the value of the global TC index.
 620  *
 621  * This function will transform @tc into a local index within the
 622  * returned #CPUMIPSState.
 623  */
 624 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 625           which depends on runtime setup. Can probably be fixed by
 626           walking the list of CPUMIPSStates.  */
 627 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 628 {
 629     MIPSCPU *cpu;
 630     CPUState *cs;
 631     CPUState *other_cs;
 632     int vpe_idx;
 633     int tc_idx = *tc;
 634
 635     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 636         /* Not allowed to address other CPUs.  */
 637         *tc = env->current_tc;
 638         return env;
 639     }
 640
 641     cs = CPU(mips_env_get_cpu(env));
 642     vpe_idx = tc_idx / cs->nr_threads;
 643     *tc = tc_idx % cs->nr_threads;
 644     other_cs = qemu_get_cpu(vpe_idx);
 645     if (other_cs == NULL) {
 646         return env;
 647     }
 648     cpu = MIPS_CPU(other_cs);
 649     return &cpu->env;
 650 }
 651
 652 /* The per VPE CP0_Status register shares some fields with the per TC
 653    CP0_TCStatus registers. These fields are wired to the same registers,
 654    so changes to either of them should be reflected on both registers.
 655
 656    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 657
 658    These helper call synchronizes the regs for a given cpu.  */
 659
 660 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 661 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 662                                      int tc);  */
 663
 664 /* Called for updates to CP0_TCStatus.  */
 665 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 666                              target_ulong v)
 667 {
 668     uint32_t status;
 669     uint32_t tcu, tmx, tasid, tksu;
 670     uint32_t mask = ((1U << CP0St_CU3)
 671                        | (1 << CP0St_CU2)
 672                        | (1 << CP0St_CU1)
 673                        | (1 << CP0St_CU0)
 674                        | (1 << CP0St_MX)
 675                        | (3 << CP0St_KSU));
 676
 677     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 678     tmx = (v >> CP0TCSt_TMX) & 0x1;
 679     tasid = v & 0xff;
 680     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 681
 682     status = tcu << CP0St_CU0;
 683     status |= tmx << CP0St_MX;
 684     status |= tksu << CP0St_KSU;
 685
 686     cpu->CP0_Status &= ~mask;
 687     cpu->CP0_Status |= status;
 688
 689     /* Sync the TASID with EntryHi.  */
 690     cpu->CP0_EntryHi &= ~0xff;
 691     cpu->CP0_EntryHi |= tasid;
 692
 693     compute_hflags(cpu);
 694 }
 695
 696 /* Called for updates to CP0_EntryHi.  */
 697 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 698 {
 699     int32_t *tcst;
 700     uint32_t asid, v = cpu->CP0_EntryHi;
 701
 702     asid = v & 0xff;
 703
 704     if (tc == cpu->current_tc) {
 705         tcst = &cpu->active_tc.CP0_TCStatus;
 706     } else {
 707         tcst = &cpu->tcs[tc].CP0_TCStatus;
 708     }
 709
 710     *tcst &= ~0xff;
 711     *tcst |= asid;
 712 }
 713
 714 /* CP0 helpers */
 715 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 716 {
 717     return env->mvp->CP0_MVPControl;
 718 }
 719
 720 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 721 {
 722     return env->mvp->CP0_MVPConf0;
 723 }
 724
 725 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 726 {
 727     return env->mvp->CP0_MVPConf1;
 728 }
 729
 730 target_ulong helper_mfc0_random(CPUMIPSState *env)
 731 {
 732     return (int32_t)cpu_mips_get_random(env);
 733 }
 734
 735 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 736 {
 737     return env->active_tc.CP0_TCStatus;
 738 }
 739
 740 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 741 {
 742     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 743     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 744
 745     if (other_tc == other->current_tc)
 746         return other->active_tc.CP0_TCStatus;
 747     else
 748         return other->tcs[other_tc].CP0_TCStatus;
 749 }
 750
 751 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 752 {
 753     return env->active_tc.CP0_TCBind;
 754 }
 755
 756 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 757 {
 758     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 759     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 760
 761     if (other_tc == other->current_tc)
 762         return other->active_tc.CP0_TCBind;
 763     else
 764         return other->tcs[other_tc].CP0_TCBind;
 765 }
 766
 767 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 768 {
 769     return env->active_tc.PC;
 770 }
 771
 772 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 773 {
 774     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 775     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 776
 777     if (other_tc == other->current_tc)
 778         return other->active_tc.PC;
 779     else
 780         return other->tcs[other_tc].PC;
 781 }
 782
 783 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 784 {
 785     return env->active_tc.CP0_TCHalt;
 786 }
 787
 788 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 789 {
 790     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 791     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 792
 793     if (other_tc == other->current_tc)
 794         return other->active_tc.CP0_TCHalt;
 795     else
 796         return other->tcs[other_tc].CP0_TCHalt;
 797 }
 798
 799 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 800 {
 801     return env->active_tc.CP0_TCContext;
 802 }
 803
 804 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 805 {
 806     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 807     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 808
 809     if (other_tc == other->current_tc)
 810         return other->active_tc.CP0_TCContext;
 811     else
 812         return other->tcs[other_tc].CP0_TCContext;
 813 }
 814
 815 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 816 {
 817     return env->active_tc.CP0_TCSchedule;
 818 }
 819
 820 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 821 {
 822     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 823     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 824
 825     if (other_tc == other->current_tc)
 826         return other->active_tc.CP0_TCSchedule;
 827     else
 828         return other->tcs[other_tc].CP0_TCSchedule;
 829 }
 830
 831 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 832 {
 833     return env->active_tc.CP0_TCScheFBack;
 834 }
 835
 836 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 837 {
 838     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 839     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 840
 841     if (other_tc == other->current_tc)
 842         return other->active_tc.CP0_TCScheFBack;
 843     else
 844         return other->tcs[other_tc].CP0_TCScheFBack;
 845 }
 846
 847 target_ulong helper_mfc0_count(CPUMIPSState *env)
 848 {
 849     return (int32_t)cpu_mips_get_count(env);
 850 }
 851
 852 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 853 {
 854     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 855     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 856
 857     return other->CP0_EntryHi;
 858 }
 859
 860 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 861 {
 862     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 863     int32_t tccause;
 864     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 865
 866     if (other_tc == other->current_tc) {
 867         tccause = other->CP0_Cause;
 868     } else {
 869         tccause = other->CP0_Cause;
 870     }
 871
 872     return tccause;
 873 }
 874
 875 target_ulong helper_mftc0_status(CPUMIPSState *env)
 876 {
 877     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 878     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 879
 880     return other->CP0_Status;
 881 }
 882
 883 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 884 {
 885     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 886 }
 887
 888 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 889 {
 890     return (int32_t)env->CP0_WatchLo[sel];
 891 }
 892
 893 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 894 {
 895     return env->CP0_WatchHi[sel];
 896 }
 897
 898 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 899 {
 900     target_ulong t0 = env->CP0_Debug;
 901     if (env->hflags & MIPS_HFLAG_DM)
 902         t0 |= 1 << CP0DB_DM;
 903
 904     return t0;
 905 }
 906
 907 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 908 {
 909     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 910     int32_t tcstatus;
 911     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 912
 913     if (other_tc == other->current_tc)
 914         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 915     else
 916         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 917
 918     /* XXX: Might be wrong, check with EJTAG spec. */
 919     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 920             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 921 }
 922
 923 #if defined(TARGET_MIPS64)
 924 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 925 {
 926     return env->active_tc.PC;
 927 }
 928
 929 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 930 {
 931     return env->active_tc.CP0_TCHalt;
 932 }
 933
 934 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 935 {
 936     return env->active_tc.CP0_TCContext;
 937 }
 938
 939 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 940 {
 941     return env->active_tc.CP0_TCSchedule;
 942 }
 943
 944 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 945 {
 946     return env->active_tc.CP0_TCScheFBack;
 947 }
 948
 949 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 950 {
 951     return env->lladdr >> env->CP0_LLAddr_shift;
 952 }
 953
 954 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 955 {
 956     return env->CP0_WatchLo[sel];
 957 }
 958 #endif /* TARGET_MIPS64 */
 959
 960 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 961 {
 962     uint32_t index_p = env->CP0_Index & 0x80000000;
 963     uint32_t tlb_index = arg1 & 0x7fffffff;
 964     if (tlb_index < env->tlb->nb_tlb) {
 965         if (env->insn_flags & ISA_MIPS32R6) {
 966             index_p |= arg1 & 0x80000000;
 967         }
 968         env->CP0_Index = index_p | tlb_index;
 969     }
 970 }
 971
 972 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 973 {
 974     uint32_t mask = 0;
 975     uint32_t newval;
 976
 977     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 978         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 979                 (1 << CP0MVPCo_EVP);
 980     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 981         mask |= (1 << CP0MVPCo_STLB);
 982     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 983
 984     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 985
 986     env->mvp->CP0_MVPControl = newval;
 987 }
 988
 989 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 990 {
 991     uint32_t mask;
 992     uint32_t newval;
 993
 994     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 995            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 996     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 997
 998     /* Yield scheduler intercept not implemented. */
 999     /* Gating storage scheduler intercept not implemented. */
1000
1001     // TODO: Enable/disable TCs.
1002
1003     env->CP0_VPEControl = newval;
1004 }
1005
1006 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1007 {
1008     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1009     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1010     uint32_t mask;
1011     uint32_t newval;
1012
1013     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1014            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1015     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1016
1017     /* TODO: Enable/disable TCs.  */
1018
1019     other->CP0_VPEControl = newval;
1020 }
1021
1022 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1023 {
1024     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1025     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1026     /* FIXME: Mask away return zero on read bits.  */
1027     return other->CP0_VPEControl;
1028 }
1029
1030 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1031 {
1032     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1033     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1034
1035     return other->CP0_VPEConf0;
1036 }
1037
1038 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1039 {
1040     uint32_t mask = 0;
1041     uint32_t newval;
1042
1043     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1044         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1045             mask |= (0xff << CP0VPEC0_XTC);
1046         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1047     }
1048     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1049
1050     // TODO: TC exclusive handling due to ERL/EXL.
1051
1052     env->CP0_VPEConf0 = newval;
1053 }
1054
1055 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1056 {
1057     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1059     uint32_t mask = 0;
1060     uint32_t newval;
1061
1062     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1063     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1064
1065     /* TODO: TC exclusive handling due to ERL/EXL.  */
1066     other->CP0_VPEConf0 = newval;
1067 }
1068
1069 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1070 {
1071     uint32_t mask = 0;
1072     uint32_t newval;
1073
1074     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1075         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1076                 (0xff << CP0VPEC1_NCP1);
1077     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1078
1079     /* UDI not implemented. */
1080     /* CP2 not implemented. */
1081
1082     // TODO: Handle FPU (CP1) binding.
1083
1084     env->CP0_VPEConf1 = newval;
1085 }
1086
1087 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1088 {
1089     /* Yield qualifier inputs not implemented. */
1090     env->CP0_YQMask = 0x00000000;
1091 }
1092
1093 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1094 {
1095     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1096 }
1097
1098 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1099
1100 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1101 {
1102     /* 1k pages not implemented */
1103     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1104     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1105                         | (rxi << (CP0EnLo_XI - 30));
1106 }
1107
1108 #if defined(TARGET_MIPS64)
1109 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1110
1111 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1112 {
1113     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1114     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1115 }
1116 #endif
1117
1118 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1119 {
1120     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1121     uint32_t newval;
1122
1123     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1124
1125     env->active_tc.CP0_TCStatus = newval;
1126     sync_c0_tcstatus(env, env->current_tc, newval);
1127 }
1128
1129 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1130 {
1131     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1132     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1133
1134     if (other_tc == other->current_tc)
1135         other->active_tc.CP0_TCStatus = arg1;
1136     else
1137         other->tcs[other_tc].CP0_TCStatus = arg1;
1138     sync_c0_tcstatus(other, other_tc, arg1);
1139 }
1140
1141 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1142 {
1143     uint32_t mask = (1 << CP0TCBd_TBE);
1144     uint32_t newval;
1145
1146     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1147         mask |= (1 << CP0TCBd_CurVPE);
1148     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1149     env->active_tc.CP0_TCBind = newval;
1150 }
1151
1152 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1153 {
1154     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1155     uint32_t mask = (1 << CP0TCBd_TBE);
1156     uint32_t newval;
1157     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1158
1159     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1160         mask |= (1 << CP0TCBd_CurVPE);
1161     if (other_tc == other->current_tc) {
1162         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1163         other->active_tc.CP0_TCBind = newval;
1164     } else {
1165         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1166         other->tcs[other_tc].CP0_TCBind = newval;
1167     }
1168 }
1169
1170 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1171 {
1172     env->active_tc.PC = arg1;
1173     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1174     env->lladdr = 0ULL;
1175     /* MIPS16 not implemented. */
1176 }
1177
1178 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1179 {
1180     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1182
1183     if (other_tc == other->current_tc) {
1184         other->active_tc.PC = arg1;
1185         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1186         other->lladdr = 0ULL;
1187         /* MIPS16 not implemented. */
1188     } else {
1189         other->tcs[other_tc].PC = arg1;
1190         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1191         other->lladdr = 0ULL;
1192         /* MIPS16 not implemented. */
1193     }
1194 }
1195
1196 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1197 {
1198     MIPSCPU *cpu = mips_env_get_cpu(env);
1199
1200     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1201
1202     // TODO: Halt TC / Restart (if allocated+active) TC.
1203     if (env->active_tc.CP0_TCHalt & 1) {
1204         mips_tc_sleep(cpu, env->current_tc);
1205     } else {
1206         mips_tc_wake(cpu, env->current_tc);
1207     }
1208 }
1209
1210 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1211 {
1212     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1213     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1214     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1215
1216     // TODO: Halt TC / Restart (if allocated+active) TC.
1217
1218     if (other_tc == other->current_tc)
1219         other->active_tc.CP0_TCHalt = arg1;
1220     else
1221         other->tcs[other_tc].CP0_TCHalt = arg1;
1222
1223     if (arg1 & 1) {
1224         mips_tc_sleep(other_cpu, other_tc);
1225     } else {
1226         mips_tc_wake(other_cpu, other_tc);
1227     }
1228 }
1229
1230 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1231 {
1232     env->active_tc.CP0_TCContext = arg1;
1233 }
1234
1235 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1236 {
1237     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1238     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1239
1240     if (other_tc == other->current_tc)
1241         other->active_tc.CP0_TCContext = arg1;
1242     else
1243         other->tcs[other_tc].CP0_TCContext = arg1;
1244 }
1245
1246 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1247 {
1248     env->active_tc.CP0_TCSchedule = arg1;
1249 }
1250
1251 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1252 {
1253     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1254     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1255
1256     if (other_tc == other->current_tc)
1257         other->active_tc.CP0_TCSchedule = arg1;
1258     else
1259         other->tcs[other_tc].CP0_TCSchedule = arg1;
1260 }
1261
1262 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1263 {
1264     env->active_tc.CP0_TCScheFBack = arg1;
1265 }
1266
1267 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1270     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1271
1272     if (other_tc == other->current_tc)
1273         other->active_tc.CP0_TCScheFBack = arg1;
1274     else
1275         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1276 }
1277
1278 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1279 {
1280     /* 1k pages not implemented */
1281     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1282     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1283                         | (rxi << (CP0EnLo_XI - 30));
1284 }
1285
1286 #if defined(TARGET_MIPS64)
1287 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1288 {
1289     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1290     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1291 }
1292 #endif
1293
1294 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1295 {
1296     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1297 }
1298
1299 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1300 {
1301     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1302     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1303         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1304          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1305          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1306         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1307     }
1308 }
1309
1310 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1311 {
1312     /* SmartMIPS not implemented */
1313     /* 1k pages not implemented */
1314     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1315                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1316     compute_hflags(env);
1317     restore_pamask(env);
1318 }
1319
1320 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1321 {
1322     if (env->insn_flags & ISA_MIPS32R6) {
1323         if (arg1 < env->tlb->nb_tlb) {
1324             env->CP0_Wired = arg1;
1325         }
1326     } else {
1327         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1328     }
1329 }
1330
1331 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1332 {
1333     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1334 }
1335
1336 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1337 {
1338     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1339 }
1340
1341 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1342 {
1343     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1344 }
1345
1346 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1347 {
1348     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1349 }
1350
1351 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1352 {
1353     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1354 }
1355
1356 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1357 {
1358     uint32_t mask = 0x0000000F;
1359
1360     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1361         mask |= (1 << 29);
1362
1363         if (arg1 & (1 << 29)) {
1364             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1365         } else {
1366             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1367         }
1368     }
1369
1370     env->CP0_HWREna = arg1 & mask;
1371 }
1372
1373 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1374 {
1375     cpu_mips_store_count(env, arg1);
1376 }
1377
1378 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1379 {
1380     target_ulong old, val, mask;
1381     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1382     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1383         mask |= 1 << CP0EnHi_EHINV;
1384     }
1385
1386     /* 1k pages not implemented */
1387 #if defined(TARGET_MIPS64)
1388     if (env->insn_flags & ISA_MIPS32R6) {
1389         int entryhi_r = extract64(arg1, 62, 2);
1390         int config0_at = extract32(env->CP0_Config0, 13, 2);
1391         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1392         if ((entryhi_r == 2) ||
1393             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1394             /* skip EntryHi.R field if new value is reserved */
1395             mask &= ~(0x3ull << 62);
1396         }
1397     }
1398     mask &= env->SEGMask;
1399 #endif
1400     old = env->CP0_EntryHi;
1401     val = (arg1 & mask) | (old & ~mask);
1402     env->CP0_EntryHi = val;
1403     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1404         sync_c0_entryhi(env, env->current_tc);
1405     }
1406     /* If the ASID changes, flush qemu's TLB.  */
1407     if ((old & 0xFF) != (val & 0xFF))
1408         cpu_mips_tlb_flush(env, 1);
1409 }
1410
1411 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1412 {
1413     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1414     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1415
1416     other->CP0_EntryHi = arg1;
1417     sync_c0_entryhi(other, other_tc);
1418 }
1419
1420 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1421 {
1422     cpu_mips_store_compare(env, arg1);
1423 }
1424
1425 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1426 {
1427     MIPSCPU *cpu = mips_env_get_cpu(env);
1428     uint32_t val, old;
1429
1430     old = env->CP0_Status;
1431     cpu_mips_store_status(env, arg1);
1432     val = env->CP0_Status;
1433
1434     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1435         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1436                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1437                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1438                 env->CP0_Cause);
1439         switch (env->hflags & MIPS_HFLAG_KSU) {
1440         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1441         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1442         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1443         default:
1444             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1445             break;
1446         }
1447     }
1448 }
1449
1450 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1451 {
1452     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1453     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1454     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1455
1456     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1457     sync_c0_status(env, other, other_tc);
1458 }
1459
1460 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1461 {
1462     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1463 }
1464
1465 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1466 {
1467     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1468     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1469 }
1470
1471 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1472 {
1473     cpu_mips_store_cause(env, arg1);
1474 }
1475
1476 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1477 {
1478     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1479     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1480
1481     cpu_mips_store_cause(other, arg1);
1482 }
1483
1484 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1485 {
1486     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1487     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1488
1489     return other->CP0_EPC;
1490 }
1491
1492 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1493 {
1494     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1495     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1496
1497     return other->CP0_EBase;
1498 }
1499
1500 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1501 {
1502     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1503 }
1504
1505 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1506 {
1507     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1508     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1509     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1510 }
1511
1512 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1513 {
1514     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1515     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1516
1517     switch (idx) {
1518     case 0: return other->CP0_Config0;
1519     case 1: return other->CP0_Config1;
1520     case 2: return other->CP0_Config2;
1521     case 3: return other->CP0_Config3;
1522     /* 4 and 5 are reserved.  */
1523     case 6: return other->CP0_Config6;
1524     case 7: return other->CP0_Config7;
1525     default:
1526         break;
1527     }
1528     return 0;
1529 }
1530
1531 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1532 {
1533     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1534 }
1535
1536 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1537 {
1538     /* tertiary/secondary caches not implemented */
1539     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1540 }
1541
1542 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1543 {
1544     if (env->insn_flags & ASE_MICROMIPS) {
1545         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1546                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1547     }
1548 }
1549
1550 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1551 {
1552     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1553                        (arg1 & env->CP0_Config4_rw_bitmask);
1554 }
1555
1556 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1557 {
1558     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1559                        (arg1 & env->CP0_Config5_rw_bitmask);
1560     compute_hflags(env);
1561 }
1562
1563 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1564 {
1565     target_long mask = env->CP0_LLAddr_rw_bitmask;
1566     arg1 = arg1 << env->CP0_LLAddr_shift;
1567     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1568 }
1569
1570 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1571 {
1572     /* Watch exceptions for instructions, data loads, data stores
1573        not implemented. */
1574     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1575 }
1576
1577 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1578 {
1579     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1580     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1581 }
1582
1583 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1584 {
1585     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1586     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1587 }
1588
1589 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1590 {
1591     env->CP0_Framemask = arg1; /* XXX */
1592 }
1593
1594 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1595 {
1596     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1597     if (arg1 & (1 << CP0DB_DM))
1598         env->hflags |= MIPS_HFLAG_DM;
1599     else
1600         env->hflags &= ~MIPS_HFLAG_DM;
1601 }
1602
1603 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1604 {
1605     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1606     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1607     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1608
1609     /* XXX: Might be wrong, check with EJTAG spec. */
1610     if (other_tc == other->current_tc)
1611         other->active_tc.CP0_Debug_tcstatus = val;
1612     else
1613         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1614     other->CP0_Debug = (other->CP0_Debug &
1615                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1616                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1617 }
1618
1619 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1620 {
1621     env->CP0_Performance0 = arg1 & 0x000007ff;
1622 }
1623
1624 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1625 {
1626     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1627 }
1628
1629 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1630 {
1631     env->CP0_DataLo = arg1; /* XXX */
1632 }
1633
1634 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1635 {
1636     env->CP0_TagHi = arg1; /* XXX */
1637 }
1638
1639 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1640 {
1641     env->CP0_DataHi = arg1; /* XXX */
1642 }
1643
1644 /* MIPS MT functions */
1645 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1646 {
1647     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1648     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1649
1650     if (other_tc == other->current_tc)
1651         return other->active_tc.gpr[sel];
1652     else
1653         return other->tcs[other_tc].gpr[sel];
1654 }
1655
1656 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1657 {
1658     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1659     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1660
1661     if (other_tc == other->current_tc)
1662         return other->active_tc.LO[sel];
1663     else
1664         return other->tcs[other_tc].LO[sel];
1665 }
1666
1667 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1668 {
1669     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1670     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1671
1672     if (other_tc == other->current_tc)
1673         return other->active_tc.HI[sel];
1674     else
1675         return other->tcs[other_tc].HI[sel];
1676 }
1677
1678 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1679 {
1680     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1681     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1682
1683     if (other_tc == other->current_tc)
1684         return other->active_tc.ACX[sel];
1685     else
1686         return other->tcs[other_tc].ACX[sel];
1687 }
1688
1689 target_ulong helper_mftdsp(CPUMIPSState *env)
1690 {
1691     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1692     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1693
1694     if (other_tc == other->current_tc)
1695         return other->active_tc.DSPControl;
1696     else
1697         return other->tcs[other_tc].DSPControl;
1698 }
1699
1700 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1701 {
1702     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1703     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1704
1705     if (other_tc == other->current_tc)
1706         other->active_tc.gpr[sel] = arg1;
1707     else
1708         other->tcs[other_tc].gpr[sel] = arg1;
1709 }
1710
1711 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1712 {
1713     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1714     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1715
1716     if (other_tc == other->current_tc)
1717         other->active_tc.LO[sel] = arg1;
1718     else
1719         other->tcs[other_tc].LO[sel] = arg1;
1720 }
1721
1722 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1723 {
1724     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1725     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1726
1727     if (other_tc == other->current_tc)
1728         other->active_tc.HI[sel] = arg1;
1729     else
1730         other->tcs[other_tc].HI[sel] = arg1;
1731 }
1732
1733 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1734 {
1735     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1736     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1737
1738     if (other_tc == other->current_tc)
1739         other->active_tc.ACX[sel] = arg1;
1740     else
1741         other->tcs[other_tc].ACX[sel] = arg1;
1742 }
1743
1744 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1745 {
1746     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1747     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1748
1749     if (other_tc == other->current_tc)
1750         other->active_tc.DSPControl = arg1;
1751     else
1752         other->tcs[other_tc].DSPControl = arg1;
1753 }
1754
1755 /* MIPS MT functions */
1756 target_ulong helper_dmt(void)
1757 {
1758     // TODO
1759      return 0;
1760 }
1761
1762 target_ulong helper_emt(void)
1763 {
1764     // TODO
1765     return 0;
1766 }
1767
1768 target_ulong helper_dvpe(CPUMIPSState *env)
1769 {
1770     CPUState *other_cs = first_cpu;
1771     target_ulong prev = env->mvp->CP0_MVPControl;
1772
1773     CPU_FOREACH(other_cs) {
1774         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1775         /* Turn off all VPEs except the one executing the dvpe.  */
1776         if (&other_cpu->env != env) {
1777             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1778             mips_vpe_sleep(other_cpu);
1779         }
1780     }
1781     return prev;
1782 }
1783
1784 target_ulong helper_evpe(CPUMIPSState *env)
1785 {
1786     CPUState *other_cs = first_cpu;
1787     target_ulong prev = env->mvp->CP0_MVPControl;
1788
1789     CPU_FOREACH(other_cs) {
1790         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1791
1792         if (&other_cpu->env != env
1793             /* If the VPE is WFI, don't disturb its sleep.  */
1794             && !mips_vpe_is_wfi(other_cpu)) {
1795             /* Enable the VPE.  */
1796             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1797             mips_vpe_wake(other_cpu); /* And wake it up.  */
1798         }
1799     }
1800     return prev;
1801 }
1802 #endif /* !CONFIG_USER_ONLY */
1803
1804 void helper_fork(target_ulong arg1, target_ulong arg2)
1805 {
1806     // arg1 = rt, arg2 = rs
1807     // TODO: store to TC register
1808 }
1809
1810 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1811 {
1812     target_long arg1 = arg;
1813
1814     if (arg1 < 0) {
1815         /* No scheduling policy implemented. */
1816         if (arg1 != -2) {
1817             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1818                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1819                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1820                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1821                 do_raise_exception(env, EXCP_THREAD, GETPC());
1822             }
1823         }
1824     } else if (arg1 == 0) {
1825         if (0 /* TODO: TC underflow */) {
1826             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1827             do_raise_exception(env, EXCP_THREAD, GETPC());
1828         } else {
1829             // TODO: Deallocate TC
1830         }
1831     } else if (arg1 > 0) {
1832         /* Yield qualifier inputs not implemented. */
1833         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1834         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1835         do_raise_exception(env, EXCP_THREAD, GETPC());
1836     }
1837     return env->CP0_YQMask;
1838 }
1839
1840 #ifndef CONFIG_USER_ONLY
1841 /* TLB management */
1842 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1843 {
1844     MIPSCPU *cpu = mips_env_get_cpu(env);
1845
1846     /* Flush qemu's TLB and discard all shadowed entries.  */
1847     tlb_flush(CPU(cpu), flush_global);
1848     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1849 }
1850
1851 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1852 {
1853     /* Discard entries from env->tlb[first] onwards.  */
1854     while (env->tlb->tlb_in_use > first) {
1855         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1856     }
1857 }
1858
1859 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1860 {
1861 #if defined(TARGET_MIPS64)
1862     return extract64(entrylo, 6, 54);
1863 #else
1864     return extract64(entrylo, 6, 24) | /* PFN */
1865            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1866 #endif
1867 }
1868
1869 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1870 {
1871     r4k_tlb_t *tlb;
1872
1873     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1874     tlb = &env->tlb->mmu.r4k.tlb[idx];
1875     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1876         tlb->EHINV = 1;
1877         return;
1878     }
1879     tlb->EHINV = 0;
1880     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1881 #if defined(TARGET_MIPS64)
1882     tlb->VPN &= env->SEGMask;
1883 #endif
1884     tlb->ASID = env->CP0_EntryHi & 0xFF;
1885     tlb->PageMask = env->CP0_PageMask;
1886     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1887     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1888     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1889     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1890     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1891     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1892     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1893     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1894     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1895     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1896     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1897     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1898     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1899 }
1900
1901 void r4k_helper_tlbinv(CPUMIPSState *env)
1902 {
1903     int idx;
1904     r4k_tlb_t *tlb;
1905     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1906
1907     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1908         tlb = &env->tlb->mmu.r4k.tlb[idx];
1909         if (!tlb->G && tlb->ASID == ASID) {
1910             tlb->EHINV = 1;
1911         }
1912     }
1913     cpu_mips_tlb_flush(env, 1);
1914 }
1915
1916 void r4k_helper_tlbinvf(CPUMIPSState *env)
1917 {
1918     int idx;
1919
1920     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1921         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1922     }
1923     cpu_mips_tlb_flush(env, 1);
1924 }
1925
1926 void r4k_helper_tlbwi(CPUMIPSState *env)
1927 {
1928     r4k_tlb_t *tlb;
1929     int idx;
1930     target_ulong VPN;
1931     uint8_t ASID;
1932     bool G, V0, D0, V1, D1;
1933
1934     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1935     tlb = &env->tlb->mmu.r4k.tlb[idx];
1936     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1937 #if defined(TARGET_MIPS64)
1938     VPN &= env->SEGMask;
1939 #endif
1940     ASID = env->CP0_EntryHi & 0xff;
1941     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1942     V0 = (env->CP0_EntryLo0 & 2) != 0;
1943     D0 = (env->CP0_EntryLo0 & 4) != 0;
1944     V1 = (env->CP0_EntryLo1 & 2) != 0;
1945     D1 = (env->CP0_EntryLo1 & 4) != 0;
1946
1947     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1948        permissions on the current entry. */
1949     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1950         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1951         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1952         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1953     }
1954
1955     r4k_invalidate_tlb(env, idx, 0);
1956     r4k_fill_tlb(env, idx);
1957 }
1958
1959 void r4k_helper_tlbwr(CPUMIPSState *env)
1960 {
1961     int r = cpu_mips_get_random(env);
1962
1963     r4k_invalidate_tlb(env, r, 1);
1964     r4k_fill_tlb(env, r);
1965 }
1966
1967 void r4k_helper_tlbp(CPUMIPSState *env)
1968 {
1969     r4k_tlb_t *tlb;
1970     target_ulong mask;
1971     target_ulong tag;
1972     target_ulong VPN;
1973     uint8_t ASID;
1974     int i;
1975
1976     ASID = env->CP0_EntryHi & 0xFF;
1977     for (i = 0; i < env->tlb->nb_tlb; i++) {
1978         tlb = &env->tlb->mmu.r4k.tlb[i];
1979         /* 1k pages are not supported. */
1980         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1981         tag = env->CP0_EntryHi & ~mask;
1982         VPN = tlb->VPN & ~mask;
1983 #if defined(TARGET_MIPS64)
1984         tag &= env->SEGMask;
1985 #endif
1986         /* Check ASID, virtual page number & size */
1987         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1988             /* TLB match */
1989             env->CP0_Index = i;
1990             break;
1991         }
1992     }
1993     if (i == env->tlb->nb_tlb) {
1994         /* No match.  Discard any shadow entries, if any of them match.  */
1995         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1996             tlb = &env->tlb->mmu.r4k.tlb[i];
1997             /* 1k pages are not supported. */
1998             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1999             tag = env->CP0_EntryHi & ~mask;
2000             VPN = tlb->VPN & ~mask;
2001 #if defined(TARGET_MIPS64)
2002             tag &= env->SEGMask;
2003 #endif
2004             /* Check ASID, virtual page number & size */
2005             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2006                 r4k_mips_tlb_flush_extra (env, i);
2007                 break;
2008             }
2009         }
2010
2011         env->CP0_Index |= 0x80000000;
2012     }
2013 }
2014
2015 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2016 {
2017 #if defined(TARGET_MIPS64)
2018     return tlb_pfn << 6;
2019 #else
2020     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2021            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2022 #endif
2023 }
2024
2025 void r4k_helper_tlbr(CPUMIPSState *env)
2026 {
2027     r4k_tlb_t *tlb;
2028     uint8_t ASID;
2029     int idx;
2030
2031     ASID = env->CP0_EntryHi & 0xFF;
2032     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2033     tlb = &env->tlb->mmu.r4k.tlb[idx];
2034
2035     /* If this will change the current ASID, flush qemu's TLB.  */
2036     if (ASID != tlb->ASID)
2037         cpu_mips_tlb_flush (env, 1);
2038
2039     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2040
2041     if (tlb->EHINV) {
2042         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2043         env->CP0_PageMask = 0;
2044         env->CP0_EntryLo0 = 0;
2045         env->CP0_EntryLo1 = 0;
2046     } else {
2047         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2048         env->CP0_PageMask = tlb->PageMask;
2049         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2050                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2051                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2052                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2053         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2054                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2055                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2056                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2057     }
2058 }
2059
2060 void helper_tlbwi(CPUMIPSState *env)
2061 {
2062     env->tlb->helper_tlbwi(env);
2063 }
2064
2065 void helper_tlbwr(CPUMIPSState *env)
2066 {
2067     env->tlb->helper_tlbwr(env);
2068 }
2069
2070 void helper_tlbp(CPUMIPSState *env)
2071 {
2072     env->tlb->helper_tlbp(env);
2073 }
2074
2075 void helper_tlbr(CPUMIPSState *env)
2076 {
2077     env->tlb->helper_tlbr(env);
2078 }
2079
2080 void helper_tlbinv(CPUMIPSState *env)
2081 {
2082     env->tlb->helper_tlbinv(env);
2083 }
2084
2085 void helper_tlbinvf(CPUMIPSState *env)
2086 {
2087     env->tlb->helper_tlbinvf(env);
2088 }
2089
2090 /* Specials */
2091 target_ulong helper_di(CPUMIPSState *env)
2092 {
2093     target_ulong t0 = env->CP0_Status;
2094
2095     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2096     return t0;
2097 }
2098
2099 target_ulong helper_ei(CPUMIPSState *env)
2100 {
2101     target_ulong t0 = env->CP0_Status;
2102
2103     env->CP0_Status = t0 | (1 << CP0St_IE);
2104     return t0;
2105 }
2106
2107 static void debug_pre_eret(CPUMIPSState *env)
2108 {
2109     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2110         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2111                 env->active_tc.PC, env->CP0_EPC);
2112         if (env->CP0_Status & (1 << CP0St_ERL))
2113             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2114         if (env->hflags & MIPS_HFLAG_DM)
2115             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2116         qemu_log("\n");
2117     }
2118 }
2119
2120 static void debug_post_eret(CPUMIPSState *env)
2121 {
2122     MIPSCPU *cpu = mips_env_get_cpu(env);
2123
2124     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2125         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2126                 env->active_tc.PC, env->CP0_EPC);
2127         if (env->CP0_Status & (1 << CP0St_ERL))
2128             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2129         if (env->hflags & MIPS_HFLAG_DM)
2130             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2131         switch (env->hflags & MIPS_HFLAG_KSU) {
2132         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2133         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2134         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2135         default:
2136             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2137             break;
2138         }
2139     }
2140 }
2141
2142 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2143 {
2144     env->active_tc.PC = error_pc & ~(target_ulong)1;
2145     if (error_pc & 1) {
2146         env->hflags |= MIPS_HFLAG_M16;
2147     } else {
2148         env->hflags &= ~(MIPS_HFLAG_M16);
2149     }
2150 }
2151
2152 static inline void exception_return(CPUMIPSState *env)
2153 {
2154     debug_pre_eret(env);
2155     if (env->CP0_Status & (1 << CP0St_ERL)) {
2156         set_pc(env, env->CP0_ErrorEPC);
2157         env->CP0_Status &= ~(1 << CP0St_ERL);
2158     } else {
2159         set_pc(env, env->CP0_EPC);
2160         env->CP0_Status &= ~(1 << CP0St_EXL);
2161     }
2162     compute_hflags(env);
2163     debug_post_eret(env);
2164 }
2165
2166 void helper_eret(CPUMIPSState *env)
2167 {
2168     exception_return(env);
2169     env->lladdr = 1;
2170 }
2171
2172 void helper_eretnc(CPUMIPSState *env)
2173 {
2174     exception_return(env);
2175 }
2176
2177 void helper_deret(CPUMIPSState *env)
2178 {
2179     debug_pre_eret(env);
2180     set_pc(env, env->CP0_DEPC);
2181
2182     env->hflags &= ~MIPS_HFLAG_DM;
2183     compute_hflags(env);
2184     debug_post_eret(env);
2185 }
2186 #endif /* !CONFIG_USER_ONLY */
2187
2188 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2189 {
2190     if ((env->hflags & MIPS_HFLAG_CP0) ||
2191         (env->CP0_HWREna & (1 << 0)))
2192         return env->CP0_EBase & 0x3ff;
2193     else
2194         do_raise_exception(env, EXCP_RI, GETPC());
2195
2196     return 0;
2197 }
2198
2199 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2200 {
2201     if ((env->hflags & MIPS_HFLAG_CP0) ||
2202         (env->CP0_HWREna & (1 << 1)))
2203         return env->SYNCI_Step;
2204     else
2205         do_raise_exception(env, EXCP_RI, GETPC());
2206
2207     return 0;
2208 }
2209
2210 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2211 {
2212     if ((env->hflags & MIPS_HFLAG_CP0) ||
2213         (env->CP0_HWREna & (1 << 2))) {
2214 #ifdef CONFIG_USER_ONLY
2215         return env->CP0_Count;
2216 #else
2217         return (int32_t)cpu_mips_get_count(env);
2218 #endif
2219     } else {
2220         do_raise_exception(env, EXCP_RI, GETPC());
2221     }
2222
2223     return 0;
2224 }
2225
2226 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2227 {
2228     if ((env->hflags & MIPS_HFLAG_CP0) ||
2229         (env->CP0_HWREna & (1 << 3)))
2230         return env->CCRes;
2231     else
2232         do_raise_exception(env, EXCP_RI, GETPC());
2233
2234     return 0;
2235 }
2236
2237 void helper_pmon(CPUMIPSState *env, int function)
2238 {
2239     function /= 2;
2240     switch (function) {
2241     case 2: /* TODO: char inbyte(int waitflag); */
2242         if (env->active_tc.gpr[4] == 0)
2243             env->active_tc.gpr[2] = -1;
2244         /* Fall through */
2245     case 11: /* TODO: char inbyte (void); */
2246         env->active_tc.gpr[2] = -1;
2247         break;
2248     case 3:
2249     case 12:
2250         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2251         break;
2252     case 17:
2253         break;
2254     case 158:
2255         {
2256             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2257             printf("%s", fmt);
2258         }
2259         break;
2260     }
2261 }
2262
2263 void helper_wait(CPUMIPSState *env)
2264 {
2265     CPUState *cs = CPU(mips_env_get_cpu(env));
2266
2267     cs->halted = 1;
2268     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2269     /* Last instruction in the block, PC was updated before
2270        - no need to recover PC and icount */
2271     raise_exception(env, EXCP_HLT);
2272 }
2273
2274 #if !defined(CONFIG_USER_ONLY)
2275
2276 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2277                                   int access_type, int is_user,
2278                                   uintptr_t retaddr)
2279 {
2280     MIPSCPU *cpu = MIPS_CPU(cs);
2281     CPUMIPSState *env = &cpu->env;
2282     int error_code = 0;
2283     int excp;
2284
2285     env->CP0_BadVAddr = addr;
2286
2287     if (access_type == MMU_DATA_STORE) {
2288         excp = EXCP_AdES;
2289     } else {
2290         excp = EXCP_AdEL;
2291         if (access_type == MMU_INST_FETCH) {
2292             error_code |= EXCP_INST_NOTAVAIL;
2293         }
2294     }
2295
2296     do_raise_exception_err(env, excp, error_code, retaddr);
2297 }
2298
2299 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2300               uintptr_t retaddr)
2301 {
2302     int ret;
2303
2304     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2305     if (ret) {
2306         MIPSCPU *cpu = MIPS_CPU(cs);
2307         CPUMIPSState *env = &cpu->env;
2308
2309         do_raise_exception_err(env, cs->exception_index,
2310                                env->error_code, retaddr);
2311     }
2312 }
2313
2314 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2315                                 bool is_write, bool is_exec, int unused,
2316                                 unsigned size)
2317 {
2318     MIPSCPU *cpu = MIPS_CPU(cs);
2319     CPUMIPSState *env = &cpu->env;
2320
2321     /*
2322      * Raising an exception with KVM enabled will crash because it won't be from
2323      * the main execution loop so the longjmp won't have a matching setjmp.
2324      * Until we can trigger a bus error exception through KVM lets just ignore
2325      * the access.
2326      */
2327     if (kvm_enabled()) {
2328         return;
2329     }
2330
2331     if (is_exec) {
2332         raise_exception(env, EXCP_IBE);
2333     } else {
2334         raise_exception(env, EXCP_DBE);
2335     }
2336 }
2337 #endif /* !CONFIG_USER_ONLY */
2338
2339 /* Complex FPU operations which may need stack space. */
2340
2341 #define FLOAT_TWO32 make_float32(1 << 30)
2342 #define FLOAT_TWO64 make_float64(1ULL << 62)
2343 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2344 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2345
2346 /* convert MIPS rounding mode in FCR31 to IEEE library */
2347 unsigned int ieee_rm[] = {
2348     float_round_nearest_even,
2349     float_round_to_zero,
2350     float_round_up,
2351     float_round_down
2352 };
2353
2354 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2355 {
2356     target_ulong arg1 = 0;
2357
2358     switch (reg) {
2359     case 0:
2360         arg1 = (int32_t)env->active_fpu.fcr0;
2361         break;
2362     case 1:
2363         /* UFR Support - Read Status FR */
2364         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2365             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2366                 arg1 = (int32_t)
2367                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2368             } else {
2369                 do_raise_exception(env, EXCP_RI, GETPC());
2370             }
2371         }
2372         break;
2373     case 5:
2374         /* FRE Support - read Config5.FRE bit */
2375         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2376             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2377                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2378             } else {
2379                 helper_raise_exception(env, EXCP_RI);
2380             }
2381         }
2382         break;
2383     case 25:
2384         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2385         break;
2386     case 26:
2387         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2388         break;
2389     case 28:
2390         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2391         break;
2392     default:
2393         arg1 = (int32_t)env->active_fpu.fcr31;
2394         break;
2395     }
2396
2397     return arg1;
2398 }
2399
2400 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2401 {
2402     switch (fs) {
2403     case 1:
2404         /* UFR Alias - Reset Status FR */
2405         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2406             return;
2407         }
2408         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2409             env->CP0_Status &= ~(1 << CP0St_FR);
2410             compute_hflags(env);
2411         } else {
2412             do_raise_exception(env, EXCP_RI, GETPC());
2413         }
2414         break;
2415     case 4:
2416         /* UNFR Alias - Set Status FR */
2417         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2418             return;
2419         }
2420         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2421             env->CP0_Status |= (1 << CP0St_FR);
2422             compute_hflags(env);
2423         } else {
2424             do_raise_exception(env, EXCP_RI, GETPC());
2425         }
2426         break;
2427     case 5:
2428         /* FRE Support - clear Config5.FRE bit */
2429         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2430             return;
2431         }
2432         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2433             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2434             compute_hflags(env);
2435         } else {
2436             helper_raise_exception(env, EXCP_RI);
2437         }
2438         break;
2439     case 6:
2440         /* FRE Support - set Config5.FRE bit */
2441         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2442             return;
2443         }
2444         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2445             env->CP0_Config5 |= (1 << CP0C5_FRE);
2446             compute_hflags(env);
2447         } else {
2448             helper_raise_exception(env, EXCP_RI);
2449         }
2450         break;
2451     case 25:
2452         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2453             return;
2454         }
2455         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2456                      ((arg1 & 0x1) << 23);
2457         break;
2458     case 26:
2459         if (arg1 & 0x007c0000)
2460             return;
2461         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2462         break;
2463     case 28:
2464         if (arg1 & 0x007c0000)
2465             return;
2466         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2467                      ((arg1 & 0x4) << 22);
2468         break;
2469     case 31:
2470         if (env->insn_flags & ISA_MIPS32R6) {
2471             uint32_t mask = 0xfefc0000;
2472             env->active_fpu.fcr31 = (arg1 & ~mask) |
2473                 (env->active_fpu.fcr31 & mask);
2474         } else if (!(arg1 & 0x007c0000)) {
2475             env->active_fpu.fcr31 = arg1;
2476         }
2477         break;
2478     default:
2479         return;
2480     }
2481     /* set rounding mode */
2482     restore_rounding_mode(env);
2483     /* set flush-to-zero mode */
2484     restore_flush_mode(env);
2485     set_float_exception_flags(0, &env->active_fpu.fp_status);
2486     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2487         do_raise_exception(env, EXCP_FPE, GETPC());
2488 }
2489
2490 int ieee_ex_to_mips(int xcpt)
2491 {
2492     int ret = 0;
2493     if (xcpt) {
2494         if (xcpt & float_flag_invalid) {
2495             ret |= FP_INVALID;
2496         }
2497         if (xcpt & float_flag_overflow) {
2498             ret |= FP_OVERFLOW;
2499         }
2500         if (xcpt & float_flag_underflow) {
2501             ret |= FP_UNDERFLOW;
2502         }
2503         if (xcpt & float_flag_divbyzero) {
2504             ret |= FP_DIV0;
2505         }
2506         if (xcpt & float_flag_inexact) {
2507             ret |= FP_INEXACT;
2508         }
2509     }
2510     return ret;
2511 }
2512
2513 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2514 {
2515     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2516
2517     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2518
2519     if (tmp) {
2520         set_float_exception_flags(0, &env->active_fpu.fp_status);
2521
2522         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2523             do_raise_exception(env, EXCP_FPE, pc);
2524         } else {
2525             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2526         }
2527     }
2528 }
2529
2530 /* Float support.
2531    Single precition routines have a "s" suffix, double precision a
2532    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2533    paired single lower "pl", paired single upper "pu".  */
2534
2535 /* unary operations, modifying fp status  */
2536 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2537 {
2538     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2539     update_fcr31(env, GETPC());
2540     return fdt0;
2541 }
2542
2543 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2544 {
2545     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2546     update_fcr31(env, GETPC());
2547     return fst0;
2548 }
2549
2550 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2551 {
2552     uint64_t fdt2;
2553
2554     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2555     update_fcr31(env, GETPC());
2556     return fdt2;
2557 }
2558
2559 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2560 {
2561     uint64_t fdt2;
2562
2563     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2564     update_fcr31(env, GETPC());
2565     return fdt2;
2566 }
2567
2568 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2569 {
2570     uint64_t fdt2;
2571
2572     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2573     update_fcr31(env, GETPC());
2574     return fdt2;
2575 }
2576
2577 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2578 {
2579     uint64_t dt2;
2580
2581     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2582     if (get_float_exception_flags(&env->active_fpu.fp_status)
2583         & (float_flag_invalid | float_flag_overflow)) {
2584         dt2 = FP_TO_INT64_OVERFLOW;
2585     }
2586     update_fcr31(env, GETPC());
2587     return dt2;
2588 }
2589
2590 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2591 {
2592     uint64_t dt2;
2593
2594     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2595     if (get_float_exception_flags(&env->active_fpu.fp_status)
2596         & (float_flag_invalid | float_flag_overflow)) {
2597         dt2 = FP_TO_INT64_OVERFLOW;
2598     }
2599     update_fcr31(env, GETPC());
2600     return dt2;
2601 }
2602
2603 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2604 {
2605     uint32_t fst2;
2606     uint32_t fsth2;
2607
2608     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2609     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2610     update_fcr31(env, GETPC());
2611     return ((uint64_t)fsth2 << 32) | fst2;
2612 }
2613
2614 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2615 {
2616     uint32_t wt2;
2617     uint32_t wth2;
2618     int excp, excph;
2619
2620     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2621     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2622     if (excp & (float_flag_overflow | float_flag_invalid)) {
2623         wt2 = FP_TO_INT32_OVERFLOW;
2624     }
2625
2626     set_float_exception_flags(0, &env->active_fpu.fp_status);
2627     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2628     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2629     if (excph & (float_flag_overflow | float_flag_invalid)) {
2630         wth2 = FP_TO_INT32_OVERFLOW;
2631     }
2632
2633     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2634     update_fcr31(env, GETPC());
2635
2636     return ((uint64_t)wth2 << 32) | wt2;
2637 }
2638
2639 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2640 {
2641     uint32_t fst2;
2642
2643     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2644     update_fcr31(env, GETPC());
2645     return fst2;
2646 }
2647
2648 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2649 {
2650     uint32_t fst2;
2651
2652     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2653     update_fcr31(env, GETPC());
2654     return fst2;
2655 }
2656
2657 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2658 {
2659     uint32_t fst2;
2660
2661     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2662     update_fcr31(env, GETPC());
2663     return fst2;
2664 }
2665
2666 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2667 {
2668     uint32_t wt2;
2669
2670     wt2 = wt0;
2671     update_fcr31(env, GETPC());
2672     return wt2;
2673 }
2674
2675 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2676 {
2677     uint32_t wt2;
2678
2679     wt2 = wth0;
2680     update_fcr31(env, GETPC());
2681     return wt2;
2682 }
2683
2684 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2685 {
2686     uint32_t wt2;
2687
2688     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2689     if (get_float_exception_flags(&env->active_fpu.fp_status)
2690         & (float_flag_invalid | float_flag_overflow)) {
2691         wt2 = FP_TO_INT32_OVERFLOW;
2692     }
2693     update_fcr31(env, GETPC());
2694     return wt2;
2695 }
2696
2697 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2698 {
2699     uint32_t wt2;
2700
2701     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2702     if (get_float_exception_flags(&env->active_fpu.fp_status)
2703         & (float_flag_invalid | float_flag_overflow)) {
2704         wt2 = FP_TO_INT32_OVERFLOW;
2705     }
2706     update_fcr31(env, GETPC());
2707     return wt2;
2708 }
2709
2710 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2711 {
2712     uint64_t dt2;
2713
2714     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2715     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2716     restore_rounding_mode(env);
2717     if (get_float_exception_flags(&env->active_fpu.fp_status)
2718         & (float_flag_invalid | float_flag_overflow)) {
2719         dt2 = FP_TO_INT64_OVERFLOW;
2720     }
2721     update_fcr31(env, GETPC());
2722     return dt2;
2723 }
2724
2725 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2726 {
2727     uint64_t dt2;
2728
2729     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2730     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2731     restore_rounding_mode(env);
2732     if (get_float_exception_flags(&env->active_fpu.fp_status)
2733         & (float_flag_invalid | float_flag_overflow)) {
2734         dt2 = FP_TO_INT64_OVERFLOW;
2735     }
2736     update_fcr31(env, GETPC());
2737     return dt2;
2738 }
2739
2740 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2741 {
2742     uint32_t wt2;
2743
2744     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2745     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2746     restore_rounding_mode(env);
2747     if (get_float_exception_flags(&env->active_fpu.fp_status)
2748         & (float_flag_invalid | float_flag_overflow)) {
2749         wt2 = FP_TO_INT32_OVERFLOW;
2750     }
2751     update_fcr31(env, GETPC());
2752     return wt2;
2753 }
2754
2755 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2756 {
2757     uint32_t wt2;
2758
2759     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2760     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2761     restore_rounding_mode(env);
2762     if (get_float_exception_flags(&env->active_fpu.fp_status)
2763         & (float_flag_invalid | float_flag_overflow)) {
2764         wt2 = FP_TO_INT32_OVERFLOW;
2765     }
2766     update_fcr31(env, GETPC());
2767     return wt2;
2768 }
2769
2770 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2771 {
2772     uint64_t dt2;
2773
2774     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2775     if (get_float_exception_flags(&env->active_fpu.fp_status)
2776         & (float_flag_invalid | float_flag_overflow)) {
2777         dt2 = FP_TO_INT64_OVERFLOW;
2778     }
2779     update_fcr31(env, GETPC());
2780     return dt2;
2781 }
2782
2783 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2784 {
2785     uint64_t dt2;
2786
2787     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2788     if (get_float_exception_flags(&env->active_fpu.fp_status)
2789         & (float_flag_invalid | float_flag_overflow)) {
2790         dt2 = FP_TO_INT64_OVERFLOW;
2791     }
2792     update_fcr31(env, GETPC());
2793     return dt2;
2794 }
2795
2796 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2797 {
2798     uint32_t wt2;
2799
2800     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2801     if (get_float_exception_flags(&env->active_fpu.fp_status)
2802         & (float_flag_invalid | float_flag_overflow)) {
2803         wt2 = FP_TO_INT32_OVERFLOW;
2804     }
2805     update_fcr31(env, GETPC());
2806     return wt2;
2807 }
2808
2809 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2810 {
2811     uint32_t wt2;
2812
2813     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2814     if (get_float_exception_flags(&env->active_fpu.fp_status)
2815         & (float_flag_invalid | float_flag_overflow)) {
2816         wt2 = FP_TO_INT32_OVERFLOW;
2817     }
2818     update_fcr31(env, GETPC());
2819     return wt2;
2820 }
2821
2822 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2823 {
2824     uint64_t dt2;
2825
2826     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2827     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2828     restore_rounding_mode(env);
2829     if (get_float_exception_flags(&env->active_fpu.fp_status)
2830         & (float_flag_invalid | float_flag_overflow)) {
2831         dt2 = FP_TO_INT64_OVERFLOW;
2832     }
2833     update_fcr31(env, GETPC());
2834     return dt2;
2835 }
2836
2837 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2838 {
2839     uint64_t dt2;
2840
2841     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2842     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2843     restore_rounding_mode(env);
2844     if (get_float_exception_flags(&env->active_fpu.fp_status)
2845         & (float_flag_invalid | float_flag_overflow)) {
2846         dt2 = FP_TO_INT64_OVERFLOW;
2847     }
2848     update_fcr31(env, GETPC());
2849     return dt2;
2850 }
2851
2852 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2853 {
2854     uint32_t wt2;
2855
2856     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2857     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2858     restore_rounding_mode(env);
2859     if (get_float_exception_flags(&env->active_fpu.fp_status)
2860         & (float_flag_invalid | float_flag_overflow)) {
2861         wt2 = FP_TO_INT32_OVERFLOW;
2862     }
2863     update_fcr31(env, GETPC());
2864     return wt2;
2865 }
2866
2867 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2868 {
2869     uint32_t wt2;
2870
2871     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2872     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2873     restore_rounding_mode(env);
2874     if (get_float_exception_flags(&env->active_fpu.fp_status)
2875         & (float_flag_invalid | float_flag_overflow)) {
2876         wt2 = FP_TO_INT32_OVERFLOW;
2877     }
2878     update_fcr31(env, GETPC());
2879     return wt2;
2880 }
2881
2882 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2883 {
2884     uint64_t dt2;
2885
2886     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2887     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2888     restore_rounding_mode(env);
2889     if (get_float_exception_flags(&env->active_fpu.fp_status)
2890         & (float_flag_invalid | float_flag_overflow)) {
2891         dt2 = FP_TO_INT64_OVERFLOW;
2892     }
2893     update_fcr31(env, GETPC());
2894     return dt2;
2895 }
2896
2897 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2898 {
2899     uint64_t dt2;
2900
2901     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2902     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2903     restore_rounding_mode(env);
2904     if (get_float_exception_flags(&env->active_fpu.fp_status)
2905         & (float_flag_invalid | float_flag_overflow)) {
2906         dt2 = FP_TO_INT64_OVERFLOW;
2907     }
2908     update_fcr31(env, GETPC());
2909     return dt2;
2910 }
2911
2912 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2913 {
2914     uint32_t wt2;
2915
2916     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2917     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2918     restore_rounding_mode(env);
2919     if (get_float_exception_flags(&env->active_fpu.fp_status)
2920         & (float_flag_invalid | float_flag_overflow)) {
2921         wt2 = FP_TO_INT32_OVERFLOW;
2922     }
2923     update_fcr31(env, GETPC());
2924     return wt2;
2925 }
2926
2927 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2928 {
2929     uint32_t wt2;
2930
2931     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2932     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2933     restore_rounding_mode(env);
2934     if (get_float_exception_flags(&env->active_fpu.fp_status)
2935         & (float_flag_invalid | float_flag_overflow)) {
2936         wt2 = FP_TO_INT32_OVERFLOW;
2937     }
2938     update_fcr31(env, GETPC());
2939     return wt2;
2940 }
2941
2942 /* unary operations, not modifying fp status  */
2943 #define FLOAT_UNOP(name)                                       \
2944 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2945 {                                                              \
2946     return float64_ ## name(fdt0);                             \
2947 }                                                              \
2948 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2949 {                                                              \
2950     return float32_ ## name(fst0);                             \
2951 }                                                              \
2952 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2953 {                                                              \
2954     uint32_t wt0;                                              \
2955     uint32_t wth0;                                             \
2956                                                                \
2957     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2958     wth0 = float32_ ## name(fdt0 >> 32);                       \
2959     return ((uint64_t)wth0 << 32) | wt0;                       \
2960 }
2961 FLOAT_UNOP(abs)
2962 FLOAT_UNOP(chs)
2963 #undef FLOAT_UNOP
2964
2965 /* MIPS specific unary operations */
2966 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2967 {
2968     uint64_t fdt2;
2969
2970     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2971     update_fcr31(env, GETPC());
2972     return fdt2;
2973 }
2974
2975 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2976 {
2977     uint32_t fst2;
2978
2979     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2980     update_fcr31(env, GETPC());
2981     return fst2;
2982 }
2983
2984 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2985 {
2986     uint64_t fdt2;
2987
2988     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2989     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2990     update_fcr31(env, GETPC());
2991     return fdt2;
2992 }
2993
2994 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2995 {
2996     uint32_t fst2;
2997
2998     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2999     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3000     update_fcr31(env, GETPC());
3001     return fst2;
3002 }
3003
3004 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3005 {
3006     uint64_t fdt2;
3007
3008     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3009     update_fcr31(env, GETPC());
3010     return fdt2;
3011 }
3012
3013 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3014 {
3015     uint32_t fst2;
3016
3017     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3018     update_fcr31(env, GETPC());
3019     return fst2;
3020 }
3021
3022 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3023 {
3024     uint32_t fst2;
3025     uint32_t fsth2;
3026
3027     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3028     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3029     update_fcr31(env, GETPC());
3030     return ((uint64_t)fsth2 << 32) | fst2;
3031 }
3032
3033 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3034 {
3035     uint64_t fdt2;
3036
3037     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3038     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3039     update_fcr31(env, GETPC());
3040     return fdt2;
3041 }
3042
3043 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3044 {
3045     uint32_t fst2;
3046
3047     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3048     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3049     update_fcr31(env, GETPC());
3050     return fst2;
3051 }
3052
3053 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3054 {
3055     uint32_t fst2;
3056     uint32_t fsth2;
3057
3058     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3059     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3060     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3061     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3062     update_fcr31(env, GETPC());
3063     return ((uint64_t)fsth2 << 32) | fst2;
3064 }
3065
3066 #define FLOAT_RINT(name, bits)                                              \
3067 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3068                                           uint ## bits ## _t fs)            \
3069 {                                                                           \
3070     uint ## bits ## _t fdret;                                               \
3071                                                                             \
3072     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3073     update_fcr31(env, GETPC());                                             \
3074     return fdret;                                                           \
3075 }
3076
3077 FLOAT_RINT(rint_s, 32)
3078 FLOAT_RINT(rint_d, 64)
3079 #undef FLOAT_RINT
3080
3081 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3082 #define FLOAT_CLASS_QUIET_NAN          0x002
3083 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3084 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3085 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3086 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3087 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3088 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3089 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3090 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3091
3092 #define FLOAT_CLASS(name, bits)                                      \
3093 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3094 {                                                                    \
3095     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3096         return FLOAT_CLASS_SIGNALING_NAN;                            \
3097     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3098         return FLOAT_CLASS_QUIET_NAN;                                \
3099     } else if (float ## bits ## _is_neg(arg)) {                      \
3100         if (float ## bits ## _is_infinity(arg)) {                    \
3101             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3102         } else if (float ## bits ## _is_zero(arg)) {                 \
3103             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3104         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3105             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3106         } else {                                                     \
3107             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3108         }                                                            \
3109     } else {                                                         \
3110         if (float ## bits ## _is_infinity(arg)) {                    \
3111             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3112         } else if (float ## bits ## _is_zero(arg)) {                 \
3113             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3114         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3115             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3116         } else {                                                     \
3117             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3118         }                                                            \
3119     }                                                                \
3120 }
3121
3122 FLOAT_CLASS(class_s, 32)
3123 FLOAT_CLASS(class_d, 64)
3124 #undef FLOAT_CLASS
3125
3126 /* binary operations */
3127 #define FLOAT_BINOP(name)                                          \
3128 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3129                                      uint64_t fdt0, uint64_t fdt1) \
3130 {                                                                  \
3131     uint64_t dt2;                                                  \
3132                                                                    \
3133     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3134     update_fcr31(env, GETPC());                                    \
3135     return dt2;                                                    \
3136 }                                                                  \
3137                                                                    \
3138 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3139                                      uint32_t fst0, uint32_t fst1) \
3140 {                                                                  \
3141     uint32_t wt2;                                                  \
3142                                                                    \
3143     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3144     update_fcr31(env, GETPC());                                    \
3145     return wt2;                                                    \
3146 }                                                                  \
3147                                                                    \
3148 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3149                                       uint64_t fdt0,               \
3150                                       uint64_t fdt1)               \
3151 {                                                                  \
3152     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3153     uint32_t fsth0 = fdt0 >> 32;                                   \
3154     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3155     uint32_t fsth1 = fdt1 >> 32;                                   \
3156     uint32_t wt2;                                                  \
3157     uint32_t wth2;                                                 \
3158                                                                    \
3159     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3160     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3161     update_fcr31(env, GETPC());                                    \
3162     return ((uint64_t)wth2 << 32) | wt2;                           \
3163 }
3164
3165 FLOAT_BINOP(add)
3166 FLOAT_BINOP(sub)
3167 FLOAT_BINOP(mul)
3168 FLOAT_BINOP(div)
3169 #undef FLOAT_BINOP
3170
3171 /* MIPS specific binary operations */
3172 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3173 {
3174     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3175     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3176     update_fcr31(env, GETPC());
3177     return fdt2;
3178 }
3179
3180 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3181 {
3182     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3183     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3184     update_fcr31(env, GETPC());
3185     return fst2;
3186 }
3187
3188 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3189 {
3190     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3191     uint32_t fsth0 = fdt0 >> 32;
3192     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3193     uint32_t fsth2 = fdt2 >> 32;
3194
3195     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3196     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3197     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3198     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3199     update_fcr31(env, GETPC());
3200     return ((uint64_t)fsth2 << 32) | fst2;
3201 }
3202
3203 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3204 {
3205     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3206     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3207     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3208     update_fcr31(env, GETPC());
3209     return fdt2;
3210 }
3211
3212 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3213 {
3214     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3215     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3216     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3217     update_fcr31(env, GETPC());
3218     return fst2;
3219 }
3220
3221 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3222 {
3223     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3224     uint32_t fsth0 = fdt0 >> 32;
3225     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3226     uint32_t fsth2 = fdt2 >> 32;
3227
3228     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3229     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3230     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3231     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3232     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3233     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3234     update_fcr31(env, GETPC());
3235     return ((uint64_t)fsth2 << 32) | fst2;
3236 }
3237
3238 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3239 {
3240     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3241     uint32_t fsth0 = fdt0 >> 32;
3242     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3243     uint32_t fsth1 = fdt1 >> 32;
3244     uint32_t fst2;
3245     uint32_t fsth2;
3246
3247     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3248     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3249     update_fcr31(env, GETPC());
3250     return ((uint64_t)fsth2 << 32) | fst2;
3251 }
3252
3253 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3254 {
3255     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3256     uint32_t fsth0 = fdt0 >> 32;
3257     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3258     uint32_t fsth1 = fdt1 >> 32;
3259     uint32_t fst2;
3260     uint32_t fsth2;
3261
3262     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3263     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3264     update_fcr31(env, GETPC());
3265     return ((uint64_t)fsth2 << 32) | fst2;
3266 }
3267
3268 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3269 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3270                                           uint ## bits ## _t fs,        \
3271                                           uint ## bits ## _t ft)        \
3272 {                                                                       \
3273     uint ## bits ## _t fdret;                                           \
3274                                                                         \
3275     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3276                                            &env->active_fpu.fp_status); \
3277     update_fcr31(env, GETPC());                                         \
3278     return fdret;                                                       \
3279 }
3280
3281 FLOAT_MINMAX(max_s, 32, maxnum)
3282 FLOAT_MINMAX(max_d, 64, maxnum)
3283 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3284 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3285
3286 FLOAT_MINMAX(min_s, 32, minnum)
3287 FLOAT_MINMAX(min_d, 64, minnum)
3288 FLOAT_MINMAX(mina_s, 32, minnummag)
3289 FLOAT_MINMAX(mina_d, 64, minnummag)
3290 #undef FLOAT_MINMAX
3291
3292 /* ternary operations */
3293 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3294 {                                                                    \
3295     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3296     if ((flags) & float_muladd_negate_c) {                           \
3297         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3298     } else {                                                         \
3299         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3300     }                                                                \
3301     if ((flags) & float_muladd_negate_result) {                      \
3302         a = prefix##_chs(a);                                         \
3303     }                                                                \
3304 }
3305
3306 /* FMA based operations */
3307 #define FLOAT_FMA(name, type)                                        \
3308 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3309                                      uint64_t fdt0, uint64_t fdt1,   \
3310                                      uint64_t fdt2)                  \
3311 {                                                                    \
3312     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3313     update_fcr31(env, GETPC());                                      \
3314     return fdt0;                                                     \
3315 }                                                                    \
3316                                                                      \
3317 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3318                                      uint32_t fst0, uint32_t fst1,   \
3319                                      uint32_t fst2)                  \
3320 {                                                                    \
3321     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3322     update_fcr31(env, GETPC());                                      \
3323     return fst0;                                                     \
3324 }                                                                    \
3325                                                                      \
3326 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3327                                       uint64_t fdt0, uint64_t fdt1,  \
3328                                       uint64_t fdt2)                 \
3329 {                                                                    \
3330     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3331     uint32_t fsth0 = fdt0 >> 32;                                     \
3332     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3333     uint32_t fsth1 = fdt1 >> 32;                                     \
3334     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3335     uint32_t fsth2 = fdt2 >> 32;                                     \
3336                                                                      \
3337     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3338     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3339     update_fcr31(env, GETPC());                                      \
3340     return ((uint64_t)fsth0 << 32) | fst0;                           \
3341 }
3342 FLOAT_FMA(madd, 0)
3343 FLOAT_FMA(msub, float_muladd_negate_c)
3344 FLOAT_FMA(nmadd, float_muladd_negate_result)
3345 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3346 #undef FLOAT_FMA
3347
3348 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3349 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3350                                           uint ## bits ## _t fs,        \
3351                                           uint ## bits ## _t ft,        \
3352                                           uint ## bits ## _t fd)        \
3353 {                                                                       \
3354     uint ## bits ## _t fdret;                                           \
3355                                                                         \
3356     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3357                                      &env->active_fpu.fp_status);       \
3358     update_fcr31(env, GETPC());                                         \
3359     return fdret;                                                       \
3360 }
3361
3362 FLOAT_FMADDSUB(maddf_s, 32, 0)
3363 FLOAT_FMADDSUB(maddf_d, 64, 0)
3364 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3365 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3366 #undef FLOAT_FMADDSUB
3367
3368 /* compare operations */
3369 #define FOP_COND_D(op, cond)                                   \
3370 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3371                          uint64_t fdt1, int cc)                \
3372 {                                                              \
3373     int c;                                                     \
3374     c = cond;                                                  \
3375     update_fcr31(env, GETPC());                                \
3376     if (c)                                                     \
3377         SET_FP_COND(cc, env->active_fpu);                      \
3378     else                                                       \
3379         CLEAR_FP_COND(cc, env->active_fpu);                    \
3380 }                                                              \
3381 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3382                             uint64_t fdt1, int cc)             \
3383 {                                                              \
3384     int c;                                                     \
3385     fdt0 = float64_abs(fdt0);                                  \
3386     fdt1 = float64_abs(fdt1);                                  \
3387     c = cond;                                                  \
3388     update_fcr31(env, GETPC());                                \
3389     if (c)                                                     \
3390         SET_FP_COND(cc, env->active_fpu);                      \
3391     else                                                       \
3392         CLEAR_FP_COND(cc, env->active_fpu);                    \
3393 }
3394
3395 /* NOTE: the comma operator will make "cond" to eval to false,
3396  * but float64_unordered_quiet() is still called. */
3397 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3398 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3399 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3400 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3401 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3402 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3403 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3404 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3405 /* NOTE: the comma operator will make "cond" to eval to false,
3406  * but float64_unordered() is still called. */
3407 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3408 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3409 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3410 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3411 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3412 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3413 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3414 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3415
3416 #define FOP_COND_S(op, cond)                                   \
3417 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3418                          uint32_t fst1, int cc)                \
3419 {                                                              \
3420     int c;                                                     \
3421     c = cond;                                                  \
3422     update_fcr31(env, GETPC());                                \
3423     if (c)                                                     \
3424         SET_FP_COND(cc, env->active_fpu);                      \
3425     else                                                       \
3426         CLEAR_FP_COND(cc, env->active_fpu);                    \
3427 }                                                              \
3428 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3429                             uint32_t fst1, int cc)             \
3430 {                                                              \
3431     int c;                                                     \
3432     fst0 = float32_abs(fst0);                                  \
3433     fst1 = float32_abs(fst1);                                  \
3434     c = cond;                                                  \
3435     update_fcr31(env, GETPC());                                \
3436     if (c)                                                     \
3437         SET_FP_COND(cc, env->active_fpu);                      \
3438     else                                                       \
3439         CLEAR_FP_COND(cc, env->active_fpu);                    \
3440 }
3441
3442 /* NOTE: the comma operator will make "cond" to eval to false,
3443  * but float32_unordered_quiet() is still called. */
3444 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3445 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3446 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3447 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3448 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3449 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3450 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3451 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3452 /* NOTE: the comma operator will make "cond" to eval to false,
3453  * but float32_unordered() is still called. */
3454 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3455 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3456 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3457 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3458 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3459 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3460 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3461 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3462
3463 #define FOP_COND_PS(op, condl, condh)                           \
3464 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3465                           uint64_t fdt1, int cc)                \
3466 {                                                               \
3467     uint32_t fst0, fsth0, fst1, fsth1;                          \
3468     int ch, cl;                                                 \
3469     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3470     fsth0 = fdt0 >> 32;                                         \
3471     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3472     fsth1 = fdt1 >> 32;                                         \
3473     cl = condl;                                                 \
3474     ch = condh;                                                 \
3475     update_fcr31(env, GETPC());                                 \
3476     if (cl)                                                     \
3477         SET_FP_COND(cc, env->active_fpu);                       \
3478     else                                                        \
3479         CLEAR_FP_COND(cc, env->active_fpu);                     \
3480     if (ch)                                                     \
3481         SET_FP_COND(cc + 1, env->active_fpu);                   \
3482     else                                                        \
3483         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3484 }                                                               \
3485 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3486                              uint64_t fdt1, int cc)             \
3487 {                                                               \
3488     uint32_t fst0, fsth0, fst1, fsth1;                          \
3489     int ch, cl;                                                 \
3490     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3491     fsth0 = float32_abs(fdt0 >> 32);                            \
3492     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3493     fsth1 = float32_abs(fdt1 >> 32);                            \
3494     cl = condl;                                                 \
3495     ch = condh;                                                 \
3496     update_fcr31(env, GETPC());                                 \
3497     if (cl)                                                     \
3498         SET_FP_COND(cc, env->active_fpu);                       \
3499     else                                                        \
3500         CLEAR_FP_COND(cc, env->active_fpu);                     \
3501     if (ch)                                                     \
3502         SET_FP_COND(cc + 1, env->active_fpu);                   \
3503     else                                                        \
3504         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3505 }
3506
3507 /* NOTE: the comma operator will make "cond" to eval to false,
3508  * but float32_unordered_quiet() is still called. */
3509 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3510                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3511 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3512                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3513 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3514                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3515 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3516                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3517 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3518                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3519 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3520                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3521 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3522                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3523 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3524                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3525 /* NOTE: the comma operator will make "cond" to eval to false,
3526  * but float32_unordered() is still called. */
3527 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3528                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3529 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3530                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3531 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3532                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3533 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3534                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3535 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3536                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3537 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3538                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3539 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3540                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3541 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3542                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3543
3544 /* R6 compare operations */
3545 #define FOP_CONDN_D(op, cond)                                       \
3546 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3547                          uint64_t fdt1)                             \
3548 {                                                                   \
3549     uint64_t c;                                                     \
3550     c = cond;                                                       \
3551     update_fcr31(env, GETPC());                                     \
3552     if (c) {                                                        \
3553         return -1;                                                  \
3554     } else {                                                        \
3555         return 0;                                                   \
3556     }                                                               \
3557 }
3558
3559 /* NOTE: the comma operator will make "cond" to eval to false,
3560  * but float64_unordered_quiet() is still called. */
3561 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3562 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3563 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3564 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3565                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3566 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3567 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3568                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3569 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3570 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3571                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3572 /* NOTE: the comma operator will make "cond" to eval to false,
3573  * but float64_unordered() is still called. */
3574 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3575 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3576 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3577 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3578                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3579 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3580 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3581                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3582 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3583 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3584                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3585 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3586                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3587 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3588                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3589                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3590 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3591                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3592 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3593                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3594 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3595                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3596                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3597 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3598                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3599
3600 #define FOP_CONDN_S(op, cond)                                       \
3601 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3602                          uint32_t fst1)                             \
3603 {                                                                   \
3604     uint64_t c;                                                     \
3605     c = cond;                                                       \
3606     update_fcr31(env, GETPC());                                     \
3607     if (c) {                                                        \
3608         return -1;                                                  \
3609     } else {                                                        \
3610         return 0;                                                   \
3611     }                                                               \
3612 }
3613
3614 /* NOTE: the comma operator will make "cond" to eval to false,
3615  * but float32_unordered_quiet() is still called. */
3616 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3617 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3618 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3619 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3620                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3621 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3622 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3623                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3624 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3625 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3626                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3627 /* NOTE: the comma operator will make "cond" to eval to false,
3628  * but float32_unordered() is still called. */
3629 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3630 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3631 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3632 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3633                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3634 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3635 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3636                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3637 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3638 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3639                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3640 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3641                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3642 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3643                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3644                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3645 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3646                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3647 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3648                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3649 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3650                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3651                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3652 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3653                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3654
3655 /* MSA */
3656 /* Data format min and max values */
3657 #define DF_BITS(df) (1 << ((df) + 3))
3658
3659 /* Element-by-element access macros */
3660 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3661
3662 #if !defined(CONFIG_USER_ONLY)
3663 #define MEMOP_IDX(DF)                                           \
3664         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3665                                         cpu_mmu_index(env, false));
3666 #else
3667 #define MEMOP_IDX(DF)
3668 #endif
3669
3670 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3671 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3672                             target_ulong addr)                          \
3673 {                                                                       \
3674     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3675     wr_t wx;                                                            \
3676     int i;                                                              \
3677     MEMOP_IDX(DF)                                                       \
3678     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3679         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3680     }                                                                   \
3681     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3682 }
3683
3684 #if !defined(CONFIG_USER_ONLY)
3685 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3686 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3687 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3688 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3689 #else
3690 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3691 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3692 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3693 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3694 #endif
3695
3696 #define MSA_PAGESPAN(x) \
3697         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3698
3699 static inline void ensure_writable_pages(CPUMIPSState *env,
3700                                          target_ulong addr,
3701                                          int mmu_idx,
3702                                          uintptr_t retaddr)
3703 {
3704 #if !defined(CONFIG_USER_ONLY)
3705     target_ulong page_addr;
3706     if (unlikely(MSA_PAGESPAN(addr))) {
3707         /* first page */
3708         probe_write(env, addr, mmu_idx, retaddr);
3709         /* second page */
3710         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3711         probe_write(env, page_addr, mmu_idx, retaddr);
3712     }
3713 #endif
3714 }
3715
3716 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3717 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3718                             target_ulong addr)                          \
3719 {                                                                       \
3720     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3721     int mmu_idx = cpu_mmu_index(env, false);                            \
3722     int i;                                                              \
3723     MEMOP_IDX(DF)                                                       \
3724     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3725     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3726         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3727     }                                                                   \
3728 }
3729
3730 #if !defined(CONFIG_USER_ONLY)
3731 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3732 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3733 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3734 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3735 #else
3736 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3737 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3738 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3739 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3740 #endif