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Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging
[qemu/ar7.git] / hw / ppc / ppc405_uc.c
blob4bd9fbcc1ef6845442a0a5293b4e24b4fadaef98
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/hw.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/boards.h"
32 #include "hw/i2c/ppc4xx_i2c.h"
33 #include "ppc405.h"
34 #include "hw/char/serial.h"
35 #include "qemu/timer.h"
36 #include "sysemu/sysemu.h"
37 #include "qemu/log.h"
38 #include "exec/address-spaces.h"
39
40 //#define DEBUG_OPBA
41 //#define DEBUG_SDRAM
42 //#define DEBUG_GPIO
43 //#define DEBUG_SERIAL
44 //#define DEBUG_OCM
45 //#define DEBUG_GPT
46 //#define DEBUG_CLOCKS
47 //#define DEBUG_CLOCKS_LL
48
49 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
50 uint32_t flags)
51 {
52 CPUState *cs = CPU(ppc_env_get_cpu(env));
53 ram_addr_t bdloc;
54 int i, n;
55
56 /* We put the bd structure at the top of memory */
57 if (bd->bi_memsize >= 0x01000000UL)
58 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
59 else
60 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
61 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
62 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
63 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
64 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
65 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
66 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
67 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
68 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
69 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
70 for (i = 0; i < 6; i++) {
71 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
72 }
73 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
74 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
75 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
76 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
77 for (i = 0; i < 4; i++) {
78 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
79 }
80 for (i = 0; i < 32; i++) {
81 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
82 }
83 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
84 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
85 for (i = 0; i < 6; i++) {
86 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
87 }
88 n = 0x6A;
89 if (flags & 0x00000001) {
90 for (i = 0; i < 6; i++)
91 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
92 }
93 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
94 n += 4;
95 for (i = 0; i < 2; i++) {
96 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
97 n += 4;
98 }
99
100 return bdloc;
101 }
102
103 /*****************************************************************************/
104 /* Shared peripherals */
105
106 /*****************************************************************************/
107 /* Peripheral local bus arbitrer */
108 enum {
109 PLB3A0_ACR = 0x077,
110 PLB4A0_ACR = 0x081,
111 PLB0_BESR = 0x084,
112 PLB0_BEAR = 0x086,
113 PLB0_ACR = 0x087,
114 PLB4A1_ACR = 0x089,
115 };
116
117 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
118 struct ppc4xx_plb_t {
119 uint32_t acr;
120 uint32_t bear;
121 uint32_t besr;
122 };
123
124 static uint32_t dcr_read_plb (void *opaque, int dcrn)
125 {
126 ppc4xx_plb_t *plb;
127 uint32_t ret;
128
129 plb = opaque;
130 switch (dcrn) {
131 case PLB0_ACR:
132 ret = plb->acr;
133 break;
134 case PLB0_BEAR:
135 ret = plb->bear;
136 break;
137 case PLB0_BESR:
138 ret = plb->besr;
139 break;
140 default:
141 /* Avoid gcc warning */
142 ret = 0;
143 break;
144 }
145
146 return ret;
147 }
148
149 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
150 {
151 ppc4xx_plb_t *plb;
152
153 plb = opaque;
154 switch (dcrn) {
155 case PLB0_ACR:
156 /* We don't care about the actual parameters written as
157 * we don't manage any priorities on the bus
158 */
159 plb->acr = val & 0xF8000000;
160 break;
161 case PLB0_BEAR:
162 /* Read only */
163 break;
164 case PLB0_BESR:
165 /* Write-clear */
166 plb->besr &= ~val;
167 break;
168 }
169 }
170
171 static void ppc4xx_plb_reset (void *opaque)
172 {
173 ppc4xx_plb_t *plb;
174
175 plb = opaque;
176 plb->acr = 0x00000000;
177 plb->bear = 0x00000000;
178 plb->besr = 0x00000000;
179 }
180
181 void ppc4xx_plb_init(CPUPPCState *env)
182 {
183 ppc4xx_plb_t *plb;
184
185 plb = g_malloc0(sizeof(ppc4xx_plb_t));
186 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
187 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
188 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
189 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
190 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
191 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
192 qemu_register_reset(ppc4xx_plb_reset, plb);
193 }
194
195 /*****************************************************************************/
196 /* PLB to OPB bridge */
197 enum {
198 POB0_BESR0 = 0x0A0,
199 POB0_BESR1 = 0x0A2,
200 POB0_BEAR = 0x0A4,
201 };
202
203 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
204 struct ppc4xx_pob_t {
205 uint32_t bear;
206 uint32_t besr0;
207 uint32_t besr1;
208 };
209
210 static uint32_t dcr_read_pob (void *opaque, int dcrn)
211 {
212 ppc4xx_pob_t *pob;
213 uint32_t ret;
214
215 pob = opaque;
216 switch (dcrn) {
217 case POB0_BEAR:
218 ret = pob->bear;
219 break;
220 case POB0_BESR0:
221 ret = pob->besr0;
222 break;
223 case POB0_BESR1:
224 ret = pob->besr1;
225 break;
226 default:
227 /* Avoid gcc warning */
228 ret = 0;
229 break;
230 }
231
232 return ret;
233 }
234
235 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
236 {
237 ppc4xx_pob_t *pob;
238
239 pob = opaque;
240 switch (dcrn) {
241 case POB0_BEAR:
242 /* Read only */
243 break;
244 case POB0_BESR0:
245 /* Write-clear */
246 pob->besr0 &= ~val;
247 break;
248 case POB0_BESR1:
249 /* Write-clear */
250 pob->besr1 &= ~val;
251 break;
252 }
253 }
254
255 static void ppc4xx_pob_reset (void *opaque)
256 {
257 ppc4xx_pob_t *pob;
258
259 pob = opaque;
260 /* No error */
261 pob->bear = 0x00000000;
262 pob->besr0 = 0x0000000;
263 pob->besr1 = 0x0000000;
264 }
265
266 static void ppc4xx_pob_init(CPUPPCState *env)
267 {
268 ppc4xx_pob_t *pob;
269
270 pob = g_malloc0(sizeof(ppc4xx_pob_t));
271 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
272 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
273 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
274 qemu_register_reset(ppc4xx_pob_reset, pob);
275 }
276
277 /*****************************************************************************/
278 /* OPB arbitrer */
279 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
280 struct ppc4xx_opba_t {
281 MemoryRegion io;
282 uint8_t cr;
283 uint8_t pr;
284 };
285
286 static uint32_t opba_readb (void *opaque, hwaddr addr)
287 {
288 ppc4xx_opba_t *opba;
289 uint32_t ret;
290
291 #ifdef DEBUG_OPBA
292 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
293 #endif
294 opba = opaque;
295 switch (addr) {
296 case 0x00:
297 ret = opba->cr;
298 break;
299 case 0x01:
300 ret = opba->pr;
301 break;
302 default:
303 ret = 0x00;
304 break;
305 }
306
307 return ret;
308 }
309
310 static void opba_writeb (void *opaque,
311 hwaddr addr, uint32_t value)
312 {
313 ppc4xx_opba_t *opba;
314
315 #ifdef DEBUG_OPBA
316 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
317 value);
318 #endif
319 opba = opaque;
320 switch (addr) {
321 case 0x00:
322 opba->cr = value & 0xF8;
323 break;
324 case 0x01:
325 opba->pr = value & 0xFF;
326 break;
327 default:
328 break;
329 }
330 }
331
332 static uint32_t opba_readw (void *opaque, hwaddr addr)
333 {
334 uint32_t ret;
335
336 #ifdef DEBUG_OPBA
337 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
338 #endif
339 ret = opba_readb(opaque, addr) << 8;
340 ret |= opba_readb(opaque, addr + 1);
341
342 return ret;
343 }
344
345 static void opba_writew (void *opaque,
346 hwaddr addr, uint32_t value)
347 {
348 #ifdef DEBUG_OPBA
349 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
350 value);
351 #endif
352 opba_writeb(opaque, addr, value >> 8);
353 opba_writeb(opaque, addr + 1, value);
354 }
355
356 static uint32_t opba_readl (void *opaque, hwaddr addr)
357 {
358 uint32_t ret;
359
360 #ifdef DEBUG_OPBA
361 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
362 #endif
363 ret = opba_readb(opaque, addr) << 24;
364 ret |= opba_readb(opaque, addr + 1) << 16;
365
366 return ret;
367 }
368
369 static void opba_writel (void *opaque,
370 hwaddr addr, uint32_t value)
371 {
372 #ifdef DEBUG_OPBA
373 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
374 value);
375 #endif
376 opba_writeb(opaque, addr, value >> 24);
377 opba_writeb(opaque, addr + 1, value >> 16);
378 }
379
380 static const MemoryRegionOps opba_ops = {
381 .old_mmio = {
382 .read = { opba_readb, opba_readw, opba_readl, },
383 .write = { opba_writeb, opba_writew, opba_writel, },
384 },
385 .endianness = DEVICE_NATIVE_ENDIAN,
386 };
387
388 static void ppc4xx_opba_reset (void *opaque)
389 {
390 ppc4xx_opba_t *opba;
391
392 opba = opaque;
393 opba->cr = 0x00; /* No dynamic priorities - park disabled */
394 opba->pr = 0x11;
395 }
396
397 static void ppc4xx_opba_init(hwaddr base)
398 {
399 ppc4xx_opba_t *opba;
400
401 opba = g_malloc0(sizeof(ppc4xx_opba_t));
402 #ifdef DEBUG_OPBA
403 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
404 #endif
405 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
406 memory_region_add_subregion(get_system_memory(), base, &opba->io);
407 qemu_register_reset(ppc4xx_opba_reset, opba);
408 }
409
410 /*****************************************************************************/
411 /* Code decompression controller */
412 /* XXX: TODO */
413
414 /*****************************************************************************/
415 /* Peripheral controller */
416 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
417 struct ppc4xx_ebc_t {
418 uint32_t addr;
419 uint32_t bcr[8];
420 uint32_t bap[8];
421 uint32_t bear;
422 uint32_t besr0;
423 uint32_t besr1;
424 uint32_t cfg;
425 };
426
427 enum {
428 EBC0_CFGADDR = 0x012,
429 EBC0_CFGDATA = 0x013,
430 };
431
432 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
433 {
434 ppc4xx_ebc_t *ebc;
435 uint32_t ret;
436
437 ebc = opaque;
438 switch (dcrn) {
439 case EBC0_CFGADDR:
440 ret = ebc->addr;
441 break;
442 case EBC0_CFGDATA:
443 switch (ebc->addr) {
444 case 0x00: /* B0CR */
445 ret = ebc->bcr[0];
446 break;
447 case 0x01: /* B1CR */
448 ret = ebc->bcr[1];
449 break;
450 case 0x02: /* B2CR */
451 ret = ebc->bcr[2];
452 break;
453 case 0x03: /* B3CR */
454 ret = ebc->bcr[3];
455 break;
456 case 0x04: /* B4CR */
457 ret = ebc->bcr[4];
458 break;
459 case 0x05: /* B5CR */
460 ret = ebc->bcr[5];
461 break;
462 case 0x06: /* B6CR */
463 ret = ebc->bcr[6];
464 break;
465 case 0x07: /* B7CR */
466 ret = ebc->bcr[7];
467 break;
468 case 0x10: /* B0AP */
469 ret = ebc->bap[0];
470 break;
471 case 0x11: /* B1AP */
472 ret = ebc->bap[1];
473 break;
474 case 0x12: /* B2AP */
475 ret = ebc->bap[2];
476 break;
477 case 0x13: /* B3AP */
478 ret = ebc->bap[3];
479 break;
480 case 0x14: /* B4AP */
481 ret = ebc->bap[4];
482 break;
483 case 0x15: /* B5AP */
484 ret = ebc->bap[5];
485 break;
486 case 0x16: /* B6AP */
487 ret = ebc->bap[6];
488 break;
489 case 0x17: /* B7AP */
490 ret = ebc->bap[7];
491 break;
492 case 0x20: /* BEAR */
493 ret = ebc->bear;
494 break;
495 case 0x21: /* BESR0 */
496 ret = ebc->besr0;
497 break;
498 case 0x22: /* BESR1 */
499 ret = ebc->besr1;
500 break;
501 case 0x23: /* CFG */
502 ret = ebc->cfg;
503 break;
504 default:
505 ret = 0x00000000;
506 break;
507 }
508 break;
509 default:
510 ret = 0x00000000;
511 break;
512 }
513
514 return ret;
515 }
516
517 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
518 {
519 ppc4xx_ebc_t *ebc;
520
521 ebc = opaque;
522 switch (dcrn) {
523 case EBC0_CFGADDR:
524 ebc->addr = val;
525 break;
526 case EBC0_CFGDATA:
527 switch (ebc->addr) {
528 case 0x00: /* B0CR */
529 break;
530 case 0x01: /* B1CR */
531 break;
532 case 0x02: /* B2CR */
533 break;
534 case 0x03: /* B3CR */
535 break;
536 case 0x04: /* B4CR */
537 break;
538 case 0x05: /* B5CR */
539 break;
540 case 0x06: /* B6CR */
541 break;
542 case 0x07: /* B7CR */
543 break;
544 case 0x10: /* B0AP */
545 break;
546 case 0x11: /* B1AP */
547 break;
548 case 0x12: /* B2AP */
549 break;
550 case 0x13: /* B3AP */
551 break;
552 case 0x14: /* B4AP */
553 break;
554 case 0x15: /* B5AP */
555 break;
556 case 0x16: /* B6AP */
557 break;
558 case 0x17: /* B7AP */
559 break;
560 case 0x20: /* BEAR */
561 break;
562 case 0x21: /* BESR0 */
563 break;
564 case 0x22: /* BESR1 */
565 break;
566 case 0x23: /* CFG */
567 break;
568 default:
569 break;
570 }
571 break;
572 default:
573 break;
574 }
575 }
576
577 static void ebc_reset (void *opaque)
578 {
579 ppc4xx_ebc_t *ebc;
580 int i;
581
582 ebc = opaque;
583 ebc->addr = 0x00000000;
584 ebc->bap[0] = 0x7F8FFE80;
585 ebc->bcr[0] = 0xFFE28000;
586 for (i = 0; i < 8; i++) {
587 ebc->bap[i] = 0x00000000;
588 ebc->bcr[i] = 0x00000000;
589 }
590 ebc->besr0 = 0x00000000;
591 ebc->besr1 = 0x00000000;
592 ebc->cfg = 0x80400000;
593 }
594
595 void ppc405_ebc_init(CPUPPCState *env)
596 {
597 ppc4xx_ebc_t *ebc;
598
599 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
600 qemu_register_reset(&ebc_reset, ebc);
601 ppc_dcr_register(env, EBC0_CFGADDR,
602 ebc, &dcr_read_ebc, &dcr_write_ebc);
603 ppc_dcr_register(env, EBC0_CFGDATA,
604 ebc, &dcr_read_ebc, &dcr_write_ebc);
605 }
606
607 /*****************************************************************************/
608 /* DMA controller */
609 enum {
610 DMA0_CR0 = 0x100,
611 DMA0_CT0 = 0x101,
612 DMA0_DA0 = 0x102,
613 DMA0_SA0 = 0x103,
614 DMA0_SG0 = 0x104,
615 DMA0_CR1 = 0x108,
616 DMA0_CT1 = 0x109,
617 DMA0_DA1 = 0x10A,
618 DMA0_SA1 = 0x10B,
619 DMA0_SG1 = 0x10C,
620 DMA0_CR2 = 0x110,
621 DMA0_CT2 = 0x111,
622 DMA0_DA2 = 0x112,
623 DMA0_SA2 = 0x113,
624 DMA0_SG2 = 0x114,
625 DMA0_CR3 = 0x118,
626 DMA0_CT3 = 0x119,
627 DMA0_DA3 = 0x11A,
628 DMA0_SA3 = 0x11B,
629 DMA0_SG3 = 0x11C,
630 DMA0_SR = 0x120,
631 DMA0_SGC = 0x123,
632 DMA0_SLP = 0x125,
633 DMA0_POL = 0x126,
634 };
635
636 typedef struct ppc405_dma_t ppc405_dma_t;
637 struct ppc405_dma_t {
638 qemu_irq irqs[4];
639 uint32_t cr[4];
640 uint32_t ct[4];
641 uint32_t da[4];
642 uint32_t sa[4];
643 uint32_t sg[4];
644 uint32_t sr;
645 uint32_t sgc;
646 uint32_t slp;
647 uint32_t pol;
648 };
649
650 static uint32_t dcr_read_dma (void *opaque, int dcrn)
651 {
652 return 0;
653 }
654
655 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
656 {
657 }
658
659 static void ppc405_dma_reset (void *opaque)
660 {
661 ppc405_dma_t *dma;
662 int i;
663
664 dma = opaque;
665 for (i = 0; i < 4; i++) {
666 dma->cr[i] = 0x00000000;
667 dma->ct[i] = 0x00000000;
668 dma->da[i] = 0x00000000;
669 dma->sa[i] = 0x00000000;
670 dma->sg[i] = 0x00000000;
671 }
672 dma->sr = 0x00000000;
673 dma->sgc = 0x00000000;
674 dma->slp = 0x7C000000;
675 dma->pol = 0x00000000;
676 }
677
678 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
679 {
680 ppc405_dma_t *dma;
681
682 dma = g_malloc0(sizeof(ppc405_dma_t));
683 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
684 qemu_register_reset(&ppc405_dma_reset, dma);
685 ppc_dcr_register(env, DMA0_CR0,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CT0,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_DA0,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_SA0,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SG0,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_CR1,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CT1,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_DA1,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_SA1,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SG1,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_CR2,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_CT2,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_DA2,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SA2,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SG2,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_CR3,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_CT3,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_DA3,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 ppc_dcr_register(env, DMA0_SA3,
722 dma, &dcr_read_dma, &dcr_write_dma);
723 ppc_dcr_register(env, DMA0_SG3,
724 dma, &dcr_read_dma, &dcr_write_dma);
725 ppc_dcr_register(env, DMA0_SR,
726 dma, &dcr_read_dma, &dcr_write_dma);
727 ppc_dcr_register(env, DMA0_SGC,
728 dma, &dcr_read_dma, &dcr_write_dma);
729 ppc_dcr_register(env, DMA0_SLP,
730 dma, &dcr_read_dma, &dcr_write_dma);
731 ppc_dcr_register(env, DMA0_POL,
732 dma, &dcr_read_dma, &dcr_write_dma);
733 }
734
735 /*****************************************************************************/
736 /* GPIO */
737 typedef struct ppc405_gpio_t ppc405_gpio_t;
738 struct ppc405_gpio_t {
739 MemoryRegion io;
740 uint32_t or;
741 uint32_t tcr;
742 uint32_t osrh;
743 uint32_t osrl;
744 uint32_t tsrh;
745 uint32_t tsrl;
746 uint32_t odr;
747 uint32_t ir;
748 uint32_t rr1;
749 uint32_t isr1h;
750 uint32_t isr1l;
751 };
752
753 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
754 {
755 #ifdef DEBUG_GPIO
756 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
757 #endif
758
759 return 0;
760 }
761
762 static void ppc405_gpio_writeb (void *opaque,
763 hwaddr addr, uint32_t value)
764 {
765 #ifdef DEBUG_GPIO
766 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
767 value);
768 #endif
769 }
770
771 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
772 {
773 #ifdef DEBUG_GPIO
774 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
775 #endif
776
777 return 0;
778 }
779
780 static void ppc405_gpio_writew (void *opaque,
781 hwaddr addr, uint32_t value)
782 {
783 #ifdef DEBUG_GPIO
784 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
785 value);
786 #endif
787 }
788
789 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
790 {
791 #ifdef DEBUG_GPIO
792 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
793 #endif
794
795 return 0;
796 }
797
798 static void ppc405_gpio_writel (void *opaque,
799 hwaddr addr, uint32_t value)
800 {
801 #ifdef DEBUG_GPIO
802 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
803 value);
804 #endif
805 }
806
807 static const MemoryRegionOps ppc405_gpio_ops = {
808 .old_mmio = {
809 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
810 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
811 },
812 .endianness = DEVICE_NATIVE_ENDIAN,
813 };
814
815 static void ppc405_gpio_reset (void *opaque)
816 {
817 }
818
819 static void ppc405_gpio_init(hwaddr base)
820 {
821 ppc405_gpio_t *gpio;
822
823 gpio = g_malloc0(sizeof(ppc405_gpio_t));
824 #ifdef DEBUG_GPIO
825 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
826 #endif
827 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
828 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
829 qemu_register_reset(&ppc405_gpio_reset, gpio);
830 }
831
832 /*****************************************************************************/
833 /* On Chip Memory */
834 enum {
835 OCM0_ISARC = 0x018,
836 OCM0_ISACNTL = 0x019,
837 OCM0_DSARC = 0x01A,
838 OCM0_DSACNTL = 0x01B,
839 };
840
841 typedef struct ppc405_ocm_t ppc405_ocm_t;
842 struct ppc405_ocm_t {
843 MemoryRegion ram;
844 MemoryRegion isarc_ram;
845 MemoryRegion dsarc_ram;
846 uint32_t isarc;
847 uint32_t isacntl;
848 uint32_t dsarc;
849 uint32_t dsacntl;
850 };
851
852 static void ocm_update_mappings (ppc405_ocm_t *ocm,
853 uint32_t isarc, uint32_t isacntl,
854 uint32_t dsarc, uint32_t dsacntl)
855 {
856 #ifdef DEBUG_OCM
857 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
858 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
859 " (%08" PRIx32 " %08" PRIx32 ")\n",
860 isarc, isacntl, dsarc, dsacntl,
861 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
862 #endif
863 if (ocm->isarc != isarc ||
864 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
865 if (ocm->isacntl & 0x80000000) {
866 /* Unmap previously assigned memory region */
867 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
868 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
869 }
870 if (isacntl & 0x80000000) {
871 /* Map new instruction memory region */
872 #ifdef DEBUG_OCM
873 printf("OCM map ISA %08" PRIx32 "\n", isarc);
874 #endif
875 memory_region_add_subregion(get_system_memory(), isarc,
876 &ocm->isarc_ram);
877 }
878 }
879 if (ocm->dsarc != dsarc ||
880 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
881 if (ocm->dsacntl & 0x80000000) {
882 /* Beware not to unmap the region we just mapped */
883 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
884 /* Unmap previously assigned memory region */
885 #ifdef DEBUG_OCM
886 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
887 #endif
888 memory_region_del_subregion(get_system_memory(),
889 &ocm->dsarc_ram);
890 }
891 }
892 if (dsacntl & 0x80000000) {
893 /* Beware not to remap the region we just mapped */
894 if (!(isacntl & 0x80000000) || dsarc != isarc) {
895 /* Map new data memory region */
896 #ifdef DEBUG_OCM
897 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
898 #endif
899 memory_region_add_subregion(get_system_memory(), dsarc,
900 &ocm->dsarc_ram);
901 }
902 }
903 }
904 }
905
906 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
907 {
908 ppc405_ocm_t *ocm;
909 uint32_t ret;
910
911 ocm = opaque;
912 switch (dcrn) {
913 case OCM0_ISARC:
914 ret = ocm->isarc;
915 break;
916 case OCM0_ISACNTL:
917 ret = ocm->isacntl;
918 break;
919 case OCM0_DSARC:
920 ret = ocm->dsarc;
921 break;
922 case OCM0_DSACNTL:
923 ret = ocm->dsacntl;
924 break;
925 default:
926 ret = 0;
927 break;
928 }
929
930 return ret;
931 }
932
933 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
934 {
935 ppc405_ocm_t *ocm;
936 uint32_t isarc, dsarc, isacntl, dsacntl;
937
938 ocm = opaque;
939 isarc = ocm->isarc;
940 dsarc = ocm->dsarc;
941 isacntl = ocm->isacntl;
942 dsacntl = ocm->dsacntl;
943 switch (dcrn) {
944 case OCM0_ISARC:
945 isarc = val & 0xFC000000;
946 break;
947 case OCM0_ISACNTL:
948 isacntl = val & 0xC0000000;
949 break;
950 case OCM0_DSARC:
951 isarc = val & 0xFC000000;
952 break;
953 case OCM0_DSACNTL:
954 isacntl = val & 0xC0000000;
955 break;
956 }
957 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
958 ocm->isarc = isarc;
959 ocm->dsarc = dsarc;
960 ocm->isacntl = isacntl;
961 ocm->dsacntl = dsacntl;
962 }
963
964 static void ocm_reset (void *opaque)
965 {
966 ppc405_ocm_t *ocm;
967 uint32_t isarc, dsarc, isacntl, dsacntl;
968
969 ocm = opaque;
970 isarc = 0x00000000;
971 isacntl = 0x00000000;
972 dsarc = 0x00000000;
973 dsacntl = 0x00000000;
974 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
975 ocm->isarc = isarc;
976 ocm->dsarc = dsarc;
977 ocm->isacntl = isacntl;
978 ocm->dsacntl = dsacntl;
979 }
980
981 static void ppc405_ocm_init(CPUPPCState *env)
982 {
983 ppc405_ocm_t *ocm;
984
985 ocm = g_malloc0(sizeof(ppc405_ocm_t));
986 /* XXX: Size is 4096 or 0x04000000 */
987 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
988 &error_fatal);
989 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
990 &ocm->isarc_ram, 0, 4 * KiB);
991 qemu_register_reset(&ocm_reset, ocm);
992 ppc_dcr_register(env, OCM0_ISARC,
993 ocm, &dcr_read_ocm, &dcr_write_ocm);
994 ppc_dcr_register(env, OCM0_ISACNTL,
995 ocm, &dcr_read_ocm, &dcr_write_ocm);
996 ppc_dcr_register(env, OCM0_DSARC,
997 ocm, &dcr_read_ocm, &dcr_write_ocm);
998 ppc_dcr_register(env, OCM0_DSACNTL,
999 ocm, &dcr_read_ocm, &dcr_write_ocm);
1000 }
1001
1002 /*****************************************************************************/
1003 /* General purpose timers */
1004 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1005 struct ppc4xx_gpt_t {
1006 MemoryRegion iomem;
1007 int64_t tb_offset;
1008 uint32_t tb_freq;
1009 QEMUTimer *timer;
1010 qemu_irq irqs[5];
1011 uint32_t oe;
1012 uint32_t ol;
1013 uint32_t im;
1014 uint32_t is;
1015 uint32_t ie;
1016 uint32_t comp[5];
1017 uint32_t mask[5];
1018 };
1019
1020 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1021 {
1022 #ifdef DEBUG_GPT
1023 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1024 #endif
1025 /* XXX: generate a bus fault */
1026 return -1;
1027 }
1028
1029 static void ppc4xx_gpt_writeb (void *opaque,
1030 hwaddr addr, uint32_t value)
1031 {
1032 #ifdef DEBUG_I2C
1033 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1034 value);
1035 #endif
1036 /* XXX: generate a bus fault */
1037 }
1038
1039 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1040 {
1041 #ifdef DEBUG_GPT
1042 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1043 #endif
1044 /* XXX: generate a bus fault */
1045 return -1;
1046 }
1047
1048 static void ppc4xx_gpt_writew (void *opaque,
1049 hwaddr addr, uint32_t value)
1050 {
1051 #ifdef DEBUG_I2C
1052 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1053 value);
1054 #endif
1055 /* XXX: generate a bus fault */
1056 }
1057
1058 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1059 {
1060 /* XXX: TODO */
1061 return 0;
1062 }
1063
1064 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1065 {
1066 /* XXX: TODO */
1067 }
1068
1069 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1070 {
1071 uint32_t mask;
1072 int i;
1073
1074 mask = 0x80000000;
1075 for (i = 0; i < 5; i++) {
1076 if (gpt->oe & mask) {
1077 /* Output is enabled */
1078 if (ppc4xx_gpt_compare(gpt, i)) {
1079 /* Comparison is OK */
1080 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1081 } else {
1082 /* Comparison is KO */
1083 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1084 }
1085 }
1086 mask = mask >> 1;
1087 }
1088 }
1089
1090 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1091 {
1092 uint32_t mask;
1093 int i;
1094
1095 mask = 0x00008000;
1096 for (i = 0; i < 5; i++) {
1097 if (gpt->is & gpt->im & mask)
1098 qemu_irq_raise(gpt->irqs[i]);
1099 else
1100 qemu_irq_lower(gpt->irqs[i]);
1101 mask = mask >> 1;
1102 }
1103 }
1104
1105 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1106 {
1107 /* XXX: TODO */
1108 }
1109
1110 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1111 {
1112 ppc4xx_gpt_t *gpt;
1113 uint32_t ret;
1114 int idx;
1115
1116 #ifdef DEBUG_GPT
1117 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1118 #endif
1119 gpt = opaque;
1120 switch (addr) {
1121 case 0x00:
1122 /* Time base counter */
1123 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1124 gpt->tb_freq, NANOSECONDS_PER_SECOND);
1125 break;
1126 case 0x10:
1127 /* Output enable */
1128 ret = gpt->oe;
1129 break;
1130 case 0x14:
1131 /* Output level */
1132 ret = gpt->ol;
1133 break;
1134 case 0x18:
1135 /* Interrupt mask */
1136 ret = gpt->im;
1137 break;
1138 case 0x1C:
1139 case 0x20:
1140 /* Interrupt status */
1141 ret = gpt->is;
1142 break;
1143 case 0x24:
1144 /* Interrupt enable */
1145 ret = gpt->ie;
1146 break;
1147 case 0x80 ... 0x90:
1148 /* Compare timer */
1149 idx = (addr - 0x80) >> 2;
1150 ret = gpt->comp[idx];
1151 break;
1152 case 0xC0 ... 0xD0:
1153 /* Compare mask */
1154 idx = (addr - 0xC0) >> 2;
1155 ret = gpt->mask[idx];
1156 break;
1157 default:
1158 ret = -1;
1159 break;
1160 }
1161
1162 return ret;
1163 }
1164
1165 static void ppc4xx_gpt_writel (void *opaque,
1166 hwaddr addr, uint32_t value)
1167 {
1168 ppc4xx_gpt_t *gpt;
1169 int idx;
1170
1171 #ifdef DEBUG_I2C
1172 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1173 value);
1174 #endif
1175 gpt = opaque;
1176 switch (addr) {
1177 case 0x00:
1178 /* Time base counter */
1179 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
1180 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1181 ppc4xx_gpt_compute_timer(gpt);
1182 break;
1183 case 0x10:
1184 /* Output enable */
1185 gpt->oe = value & 0xF8000000;
1186 ppc4xx_gpt_set_outputs(gpt);
1187 break;
1188 case 0x14:
1189 /* Output level */
1190 gpt->ol = value & 0xF8000000;
1191 ppc4xx_gpt_set_outputs(gpt);
1192 break;
1193 case 0x18:
1194 /* Interrupt mask */
1195 gpt->im = value & 0x0000F800;
1196 break;
1197 case 0x1C:
1198 /* Interrupt status set */
1199 gpt->is |= value & 0x0000F800;
1200 ppc4xx_gpt_set_irqs(gpt);
1201 break;
1202 case 0x20:
1203 /* Interrupt status clear */
1204 gpt->is &= ~(value & 0x0000F800);
1205 ppc4xx_gpt_set_irqs(gpt);
1206 break;
1207 case 0x24:
1208 /* Interrupt enable */
1209 gpt->ie = value & 0x0000F800;
1210 ppc4xx_gpt_set_irqs(gpt);
1211 break;
1212 case 0x80 ... 0x90:
1213 /* Compare timer */
1214 idx = (addr - 0x80) >> 2;
1215 gpt->comp[idx] = value & 0xF8000000;
1216 ppc4xx_gpt_compute_timer(gpt);
1217 break;
1218 case 0xC0 ... 0xD0:
1219 /* Compare mask */
1220 idx = (addr - 0xC0) >> 2;
1221 gpt->mask[idx] = value & 0xF8000000;
1222 ppc4xx_gpt_compute_timer(gpt);
1223 break;
1224 }
1225 }
1226
1227 static const MemoryRegionOps gpt_ops = {
1228 .old_mmio = {
1229 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1230 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1231 },
1232 .endianness = DEVICE_NATIVE_ENDIAN,
1233 };
1234
1235 static void ppc4xx_gpt_cb (void *opaque)
1236 {
1237 ppc4xx_gpt_t *gpt;
1238
1239 gpt = opaque;
1240 ppc4xx_gpt_set_irqs(gpt);
1241 ppc4xx_gpt_set_outputs(gpt);
1242 ppc4xx_gpt_compute_timer(gpt);
1243 }
1244
1245 static void ppc4xx_gpt_reset (void *opaque)
1246 {
1247 ppc4xx_gpt_t *gpt;
1248 int i;
1249
1250 gpt = opaque;
1251 timer_del(gpt->timer);
1252 gpt->oe = 0x00000000;
1253 gpt->ol = 0x00000000;
1254 gpt->im = 0x00000000;
1255 gpt->is = 0x00000000;
1256 gpt->ie = 0x00000000;
1257 for (i = 0; i < 5; i++) {
1258 gpt->comp[i] = 0x00000000;
1259 gpt->mask[i] = 0x00000000;
1260 }
1261 }
1262
1263 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1264 {
1265 ppc4xx_gpt_t *gpt;
1266 int i;
1267
1268 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1269 for (i = 0; i < 5; i++) {
1270 gpt->irqs[i] = irqs[i];
1271 }
1272 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1273 #ifdef DEBUG_GPT
1274 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1275 #endif
1276 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1277 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1278 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1279 }
1280
1281 /*****************************************************************************/
1282 /* SPR */
1283 void ppc40x_core_reset(PowerPCCPU *cpu)
1284 {
1285 CPUPPCState *env = &cpu->env;
1286 target_ulong dbsr;
1287
1288 printf("Reset PowerPC core\n");
1289 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1290 dbsr = env->spr[SPR_40x_DBSR];
1291 dbsr &= ~0x00000300;
1292 dbsr |= 0x00000100;
1293 env->spr[SPR_40x_DBSR] = dbsr;
1294 }
1295
1296 void ppc40x_chip_reset(PowerPCCPU *cpu)
1297 {
1298 CPUPPCState *env = &cpu->env;
1299 target_ulong dbsr;
1300
1301 printf("Reset PowerPC chip\n");
1302 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1303 /* XXX: TODO reset all internal peripherals */
1304 dbsr = env->spr[SPR_40x_DBSR];
1305 dbsr &= ~0x00000300;
1306 dbsr |= 0x00000200;
1307 env->spr[SPR_40x_DBSR] = dbsr;
1308 }
1309
1310 void ppc40x_system_reset(PowerPCCPU *cpu)
1311 {
1312 printf("Reset PowerPC system\n");
1313 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1314 }
1315
1316 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1317 {
1318 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1319
1320 switch ((val >> 28) & 0x3) {
1321 case 0x0:
1322 /* No action */
1323 break;
1324 case 0x1:
1325 /* Core reset */
1326 ppc40x_core_reset(cpu);
1327 break;
1328 case 0x2:
1329 /* Chip reset */
1330 ppc40x_chip_reset(cpu);
1331 break;
1332 case 0x3:
1333 /* System reset */
1334 ppc40x_system_reset(cpu);
1335 break;
1336 }
1337 }
1338
1339 /*****************************************************************************/
1340 /* PowerPC 405CR */
1341 enum {
1342 PPC405CR_CPC0_PLLMR = 0x0B0,
1343 PPC405CR_CPC0_CR0 = 0x0B1,
1344 PPC405CR_CPC0_CR1 = 0x0B2,
1345 PPC405CR_CPC0_PSR = 0x0B4,
1346 PPC405CR_CPC0_JTAGID = 0x0B5,
1347 PPC405CR_CPC0_ER = 0x0B9,
1348 PPC405CR_CPC0_FR = 0x0BA,
1349 PPC405CR_CPC0_SR = 0x0BB,
1350 };
1351
1352 enum {
1353 PPC405CR_CPU_CLK = 0,
1354 PPC405CR_TMR_CLK = 1,
1355 PPC405CR_PLB_CLK = 2,
1356 PPC405CR_SDRAM_CLK = 3,
1357 PPC405CR_OPB_CLK = 4,
1358 PPC405CR_EXT_CLK = 5,
1359 PPC405CR_UART_CLK = 6,
1360 PPC405CR_CLK_NB = 7,
1361 };
1362
1363 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1364 struct ppc405cr_cpc_t {
1365 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1366 uint32_t sysclk;
1367 uint32_t psr;
1368 uint32_t cr0;
1369 uint32_t cr1;
1370 uint32_t jtagid;
1371 uint32_t pllmr;
1372 uint32_t er;
1373 uint32_t fr;
1374 };
1375
1376 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1377 {
1378 uint64_t VCO_out, PLL_out;
1379 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1380 int M, D0, D1, D2;
1381
1382 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1383 if (cpc->pllmr & 0x80000000) {
1384 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1385 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1386 M = D0 * D1 * D2;
1387 VCO_out = (uint64_t)cpc->sysclk * M;
1388 if (VCO_out < 400000000 || VCO_out > 800000000) {
1389 /* PLL cannot lock */
1390 cpc->pllmr &= ~0x80000000;
1391 goto bypass_pll;
1392 }
1393 PLL_out = VCO_out / D2;
1394 } else {
1395 /* Bypass PLL */
1396 bypass_pll:
1397 M = D0;
1398 PLL_out = (uint64_t)cpc->sysclk * M;
1399 }
1400 CPU_clk = PLL_out;
1401 if (cpc->cr1 & 0x00800000)
1402 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1403 else
1404 TMR_clk = CPU_clk;
1405 PLB_clk = CPU_clk / D0;
1406 SDRAM_clk = PLB_clk;
1407 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1408 OPB_clk = PLB_clk / D0;
1409 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1410 EXT_clk = PLB_clk / D0;
1411 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1412 UART_clk = CPU_clk / D0;
1413 /* Setup CPU clocks */
1414 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1415 /* Setup time-base clock */
1416 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1417 /* Setup PLB clock */
1418 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1419 /* Setup SDRAM clock */
1420 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1421 /* Setup OPB clock */
1422 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1423 /* Setup external clock */
1424 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1425 /* Setup UART clock */
1426 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1427 }
1428
1429 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1430 {
1431 ppc405cr_cpc_t *cpc;
1432 uint32_t ret;
1433
1434 cpc = opaque;
1435 switch (dcrn) {
1436 case PPC405CR_CPC0_PLLMR:
1437 ret = cpc->pllmr;
1438 break;
1439 case PPC405CR_CPC0_CR0:
1440 ret = cpc->cr0;
1441 break;
1442 case PPC405CR_CPC0_CR1:
1443 ret = cpc->cr1;
1444 break;
1445 case PPC405CR_CPC0_PSR:
1446 ret = cpc->psr;
1447 break;
1448 case PPC405CR_CPC0_JTAGID:
1449 ret = cpc->jtagid;
1450 break;
1451 case PPC405CR_CPC0_ER:
1452 ret = cpc->er;
1453 break;
1454 case PPC405CR_CPC0_FR:
1455 ret = cpc->fr;
1456 break;
1457 case PPC405CR_CPC0_SR:
1458 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1459 break;
1460 default:
1461 /* Avoid gcc warning */
1462 ret = 0;
1463 break;
1464 }
1465
1466 return ret;
1467 }
1468
1469 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1470 {
1471 ppc405cr_cpc_t *cpc;
1472
1473 cpc = opaque;
1474 switch (dcrn) {
1475 case PPC405CR_CPC0_PLLMR:
1476 cpc->pllmr = val & 0xFFF77C3F;
1477 break;
1478 case PPC405CR_CPC0_CR0:
1479 cpc->cr0 = val & 0x0FFFFFFE;
1480 break;
1481 case PPC405CR_CPC0_CR1:
1482 cpc->cr1 = val & 0x00800000;
1483 break;
1484 case PPC405CR_CPC0_PSR:
1485 /* Read-only */
1486 break;
1487 case PPC405CR_CPC0_JTAGID:
1488 /* Read-only */
1489 break;
1490 case PPC405CR_CPC0_ER:
1491 cpc->er = val & 0xBFFC0000;
1492 break;
1493 case PPC405CR_CPC0_FR:
1494 cpc->fr = val & 0xBFFC0000;
1495 break;
1496 case PPC405CR_CPC0_SR:
1497 /* Read-only */
1498 break;
1499 }
1500 }
1501
1502 static void ppc405cr_cpc_reset (void *opaque)
1503 {
1504 ppc405cr_cpc_t *cpc;
1505 int D;
1506
1507 cpc = opaque;
1508 /* Compute PLLMR value from PSR settings */
1509 cpc->pllmr = 0x80000000;
1510 /* PFWD */
1511 switch ((cpc->psr >> 30) & 3) {
1512 case 0:
1513 /* Bypass */
1514 cpc->pllmr &= ~0x80000000;
1515 break;
1516 case 1:
1517 /* Divide by 3 */
1518 cpc->pllmr |= 5 << 16;
1519 break;
1520 case 2:
1521 /* Divide by 4 */
1522 cpc->pllmr |= 4 << 16;
1523 break;
1524 case 3:
1525 /* Divide by 6 */
1526 cpc->pllmr |= 2 << 16;
1527 break;
1528 }
1529 /* PFBD */
1530 D = (cpc->psr >> 28) & 3;
1531 cpc->pllmr |= (D + 1) << 20;
1532 /* PT */
1533 D = (cpc->psr >> 25) & 7;
1534 switch (D) {
1535 case 0x2:
1536 cpc->pllmr |= 0x13;
1537 break;
1538 case 0x4:
1539 cpc->pllmr |= 0x15;
1540 break;
1541 case 0x5:
1542 cpc->pllmr |= 0x16;
1543 break;
1544 default:
1545 break;
1546 }
1547 /* PDC */
1548 D = (cpc->psr >> 23) & 3;
1549 cpc->pllmr |= D << 26;
1550 /* ODP */
1551 D = (cpc->psr >> 21) & 3;
1552 cpc->pllmr |= D << 10;
1553 /* EBPD */
1554 D = (cpc->psr >> 17) & 3;
1555 cpc->pllmr |= D << 24;
1556 cpc->cr0 = 0x0000003C;
1557 cpc->cr1 = 0x2B0D8800;
1558 cpc->er = 0x00000000;
1559 cpc->fr = 0x00000000;
1560 ppc405cr_clk_setup(cpc);
1561 }
1562
1563 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
1564 {
1565 int D;
1566
1567 /* XXX: this should be read from IO pins */
1568 cpc->psr = 0x00000000; /* 8 bits ROM */
1569 /* PFWD */
1570 D = 0x2; /* Divide by 4 */
1571 cpc->psr |= D << 30;
1572 /* PFBD */
1573 D = 0x1; /* Divide by 2 */
1574 cpc->psr |= D << 28;
1575 /* PDC */
1576 D = 0x1; /* Divide by 2 */
1577 cpc->psr |= D << 23;
1578 /* PT */
1579 D = 0x5; /* M = 16 */
1580 cpc->psr |= D << 25;
1581 /* ODP */
1582 D = 0x1; /* Divide by 2 */
1583 cpc->psr |= D << 21;
1584 /* EBDP */
1585 D = 0x2; /* Divide by 4 */
1586 cpc->psr |= D << 17;
1587 }
1588
1589 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
1590 uint32_t sysclk)
1591 {
1592 ppc405cr_cpc_t *cpc;
1593
1594 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
1595 memcpy(cpc->clk_setup, clk_setup,
1596 PPC405CR_CLK_NB * sizeof(clk_setup_t));
1597 cpc->sysclk = sysclk;
1598 cpc->jtagid = 0x42051049;
1599 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
1600 &dcr_read_crcpc, &dcr_write_crcpc);
1601 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
1602 &dcr_read_crcpc, &dcr_write_crcpc);
1603 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
1604 &dcr_read_crcpc, &dcr_write_crcpc);
1605 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
1606 &dcr_read_crcpc, &dcr_write_crcpc);
1607 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
1608 &dcr_read_crcpc, &dcr_write_crcpc);
1609 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
1610 &dcr_read_crcpc, &dcr_write_crcpc);
1611 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
1612 &dcr_read_crcpc, &dcr_write_crcpc);
1613 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
1614 &dcr_read_crcpc, &dcr_write_crcpc);
1615 ppc405cr_clk_init(cpc);
1616 qemu_register_reset(ppc405cr_cpc_reset, cpc);
1617 }
1618
1619 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
1620 MemoryRegion ram_memories[4],
1621 hwaddr ram_bases[4],
1622 hwaddr ram_sizes[4],
1623 uint32_t sysclk, qemu_irq **picp,
1624 int do_init)
1625 {
1626 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1627 qemu_irq dma_irqs[4];
1628 PowerPCCPU *cpu;
1629 CPUPPCState *env;
1630 qemu_irq *pic, *irqs;
1631
1632 memset(clk_setup, 0, sizeof(clk_setup));
1633 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"),
1634 &clk_setup[PPC405CR_CPU_CLK],
1635 &clk_setup[PPC405CR_TMR_CLK], sysclk);
1636 env = &cpu->env;
1637 /* Memory mapped devices registers */
1638 /* PLB arbitrer */
1639 ppc4xx_plb_init(env);
1640 /* PLB to OPB bridge */
1641 ppc4xx_pob_init(env);
1642 /* OBP arbitrer */
1643 ppc4xx_opba_init(0xef600600);
1644 /* Universal interrupt controller */
1645 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
1646 irqs[PPCUIC_OUTPUT_INT] =
1647 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
1648 irqs[PPCUIC_OUTPUT_CINT] =
1649 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
1650 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
1651 *picp = pic;
1652 /* SDRAM controller */
1653 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
1654 ram_bases, ram_sizes, do_init);
1655 /* External bus controller */
1656 ppc405_ebc_init(env);
1657 /* DMA controller */
1658 dma_irqs[0] = pic[26];
1659 dma_irqs[1] = pic[25];
1660 dma_irqs[2] = pic[24];
1661 dma_irqs[3] = pic[23];
1662 ppc405_dma_init(env, dma_irqs);
1663 /* Serial ports */
1664 if (serial_hd(0) != NULL) {
1665 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
1666 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
1667 DEVICE_BIG_ENDIAN);
1668 }
1669 if (serial_hd(1) != NULL) {
1670 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
1671 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
1672 DEVICE_BIG_ENDIAN);
1673 }
1674 /* IIC controller */
1675 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
1676 /* GPIO */
1677 ppc405_gpio_init(0xef600700);
1678 /* CPU control */
1679 ppc405cr_cpc_init(env, clk_setup, sysclk);
1680
1681 return env;
1682 }
1683
1684 /*****************************************************************************/
1685 /* PowerPC 405EP */
1686 /* CPU control */
1687 enum {
1688 PPC405EP_CPC0_PLLMR0 = 0x0F0,
1689 PPC405EP_CPC0_BOOT = 0x0F1,
1690 PPC405EP_CPC0_EPCTL = 0x0F3,
1691 PPC405EP_CPC0_PLLMR1 = 0x0F4,
1692 PPC405EP_CPC0_UCR = 0x0F5,
1693 PPC405EP_CPC0_SRR = 0x0F6,
1694 PPC405EP_CPC0_JTAGID = 0x0F7,
1695 PPC405EP_CPC0_PCI = 0x0F9,
1696 #if 0
1697 PPC405EP_CPC0_ER = xxx,
1698 PPC405EP_CPC0_FR = xxx,
1699 PPC405EP_CPC0_SR = xxx,
1700 #endif
1701 };
1702
1703 enum {
1704 PPC405EP_CPU_CLK = 0,
1705 PPC405EP_PLB_CLK = 1,
1706 PPC405EP_OPB_CLK = 2,
1707 PPC405EP_EBC_CLK = 3,
1708 PPC405EP_MAL_CLK = 4,
1709 PPC405EP_PCI_CLK = 5,
1710 PPC405EP_UART0_CLK = 6,
1711 PPC405EP_UART1_CLK = 7,
1712 PPC405EP_CLK_NB = 8,
1713 };
1714
1715 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
1716 struct ppc405ep_cpc_t {
1717 uint32_t sysclk;
1718 clk_setup_t clk_setup[PPC405EP_CLK_NB];
1719 uint32_t boot;
1720 uint32_t epctl;
1721 uint32_t pllmr[2];
1722 uint32_t ucr;
1723 uint32_t srr;
1724 uint32_t jtagid;
1725 uint32_t pci;
1726 /* Clock and power management */
1727 uint32_t er;
1728 uint32_t fr;
1729 uint32_t sr;
1730 };
1731
1732 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
1733 {
1734 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
1735 uint32_t UART0_clk, UART1_clk;
1736 uint64_t VCO_out, PLL_out;
1737 int M, D;
1738
1739 VCO_out = 0;
1740 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
1741 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
1742 #ifdef DEBUG_CLOCKS_LL
1743 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
1744 #endif
1745 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
1746 #ifdef DEBUG_CLOCKS_LL
1747 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
1748 #endif
1749 VCO_out = (uint64_t)cpc->sysclk * M * D;
1750 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
1751 /* Error - unlock the PLL */
1752 printf("VCO out of range %" PRIu64 "\n", VCO_out);
1753 #if 0
1754 cpc->pllmr[1] &= ~0x80000000;
1755 goto pll_bypass;
1756 #endif
1757 }
1758 PLL_out = VCO_out / D;
1759 /* Pretend the PLL is locked */
1760 cpc->boot |= 0x00000001;
1761 } else {
1762 #if 0
1763 pll_bypass:
1764 #endif
1765 PLL_out = cpc->sysclk;
1766 if (cpc->pllmr[1] & 0x40000000) {
1767 /* Pretend the PLL is not locked */
1768 cpc->boot &= ~0x00000001;
1769 }
1770 }
1771 /* Now, compute all other clocks */
1772 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
1773 #ifdef DEBUG_CLOCKS_LL
1774 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
1775 #endif
1776 CPU_clk = PLL_out / D;
1777 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
1778 #ifdef DEBUG_CLOCKS_LL
1779 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
1780 #endif
1781 PLB_clk = CPU_clk / D;
1782 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
1783 #ifdef DEBUG_CLOCKS_LL
1784 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
1785 #endif
1786 OPB_clk = PLB_clk / D;
1787 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
1788 #ifdef DEBUG_CLOCKS_LL
1789 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
1790 #endif
1791 EBC_clk = PLB_clk / D;
1792 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
1793 #ifdef DEBUG_CLOCKS_LL
1794 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
1795 #endif
1796 MAL_clk = PLB_clk / D;
1797 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
1798 #ifdef DEBUG_CLOCKS_LL
1799 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
1800 #endif
1801 PCI_clk = PLB_clk / D;
1802 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
1803 #ifdef DEBUG_CLOCKS_LL
1804 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
1805 #endif
1806 UART0_clk = PLL_out / D;
1807 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
1808 #ifdef DEBUG_CLOCKS_LL
1809 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
1810 #endif
1811 UART1_clk = PLL_out / D;
1812 #ifdef DEBUG_CLOCKS
1813 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
1814 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
1815 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
1816 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
1817 " UART1 %" PRIu32 "\n",
1818 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
1819 UART0_clk, UART1_clk);
1820 #endif
1821 /* Setup CPU clocks */
1822 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
1823 /* Setup PLB clock */
1824 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
1825 /* Setup OPB clock */
1826 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
1827 /* Setup external clock */
1828 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
1829 /* Setup MAL clock */
1830 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
1831 /* Setup PCI clock */
1832 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
1833 /* Setup UART0 clock */
1834 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
1835 /* Setup UART1 clock */
1836 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
1837 }
1838
1839 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
1840 {
1841 ppc405ep_cpc_t *cpc;
1842 uint32_t ret;
1843
1844 cpc = opaque;
1845 switch (dcrn) {
1846 case PPC405EP_CPC0_BOOT:
1847 ret = cpc->boot;
1848 break;
1849 case PPC405EP_CPC0_EPCTL:
1850 ret = cpc->epctl;
1851 break;
1852 case PPC405EP_CPC0_PLLMR0:
1853 ret = cpc->pllmr[0];
1854 break;
1855 case PPC405EP_CPC0_PLLMR1:
1856 ret = cpc->pllmr[1];
1857 break;
1858 case PPC405EP_CPC0_UCR:
1859 ret = cpc->ucr;
1860 break;
1861 case PPC405EP_CPC0_SRR:
1862 ret = cpc->srr;
1863 break;
1864 case PPC405EP_CPC0_JTAGID:
1865 ret = cpc->jtagid;
1866 break;
1867 case PPC405EP_CPC0_PCI:
1868 ret = cpc->pci;
1869 break;
1870 default:
1871 /* Avoid gcc warning */
1872 ret = 0;
1873 break;
1874 }
1875
1876 return ret;
1877 }
1878
1879 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
1880 {
1881 ppc405ep_cpc_t *cpc;
1882
1883 cpc = opaque;
1884 switch (dcrn) {
1885 case PPC405EP_CPC0_BOOT:
1886 /* Read-only register */
1887 break;
1888 case PPC405EP_CPC0_EPCTL:
1889 /* Don't care for now */
1890 cpc->epctl = val & 0xC00000F3;
1891 break;
1892 case PPC405EP_CPC0_PLLMR0:
1893 cpc->pllmr[0] = val & 0x00633333;
1894 ppc405ep_compute_clocks(cpc);
1895 break;
1896 case PPC405EP_CPC0_PLLMR1:
1897 cpc->pllmr[1] = val & 0xC0F73FFF;
1898 ppc405ep_compute_clocks(cpc);
1899 break;
1900 case PPC405EP_CPC0_UCR:
1901 /* UART control - don't care for now */
1902 cpc->ucr = val & 0x003F7F7F;
1903 break;
1904 case PPC405EP_CPC0_SRR:
1905 cpc->srr = val;
1906 break;
1907 case PPC405EP_CPC0_JTAGID:
1908 /* Read-only */
1909 break;
1910 case PPC405EP_CPC0_PCI:
1911 cpc->pci = val;
1912 break;
1913 }
1914 }
1915
1916 static void ppc405ep_cpc_reset (void *opaque)
1917 {
1918 ppc405ep_cpc_t *cpc = opaque;
1919
1920 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
1921 cpc->epctl = 0x00000000;
1922 cpc->pllmr[0] = 0x00011010;
1923 cpc->pllmr[1] = 0x40000000;
1924 cpc->ucr = 0x00000000;
1925 cpc->srr = 0x00040000;
1926 cpc->pci = 0x00000000;
1927 cpc->er = 0x00000000;
1928 cpc->fr = 0x00000000;
1929 cpc->sr = 0x00000000;
1930 ppc405ep_compute_clocks(cpc);
1931 }
1932
1933 /* XXX: sysclk should be between 25 and 100 MHz */
1934 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
1935 uint32_t sysclk)
1936 {
1937 ppc405ep_cpc_t *cpc;
1938
1939 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
1940 memcpy(cpc->clk_setup, clk_setup,
1941 PPC405EP_CLK_NB * sizeof(clk_setup_t));
1942 cpc->jtagid = 0x20267049;
1943 cpc->sysclk = sysclk;
1944 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
1945 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
1946 &dcr_read_epcpc, &dcr_write_epcpc);
1947 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
1948 &dcr_read_epcpc, &dcr_write_epcpc);
1949 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
1950 &dcr_read_epcpc, &dcr_write_epcpc);
1951 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
1952 &dcr_read_epcpc, &dcr_write_epcpc);
1953 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
1954 &dcr_read_epcpc, &dcr_write_epcpc);
1955 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
1956 &dcr_read_epcpc, &dcr_write_epcpc);
1957 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
1958 &dcr_read_epcpc, &dcr_write_epcpc);
1959 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
1960 &dcr_read_epcpc, &dcr_write_epcpc);
1961 #if 0
1962 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
1963 &dcr_read_epcpc, &dcr_write_epcpc);
1964 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
1965 &dcr_read_epcpc, &dcr_write_epcpc);
1966 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
1967 &dcr_read_epcpc, &dcr_write_epcpc);
1968 #endif
1969 }
1970
1971 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
1972 MemoryRegion ram_memories[2],
1973 hwaddr ram_bases[2],
1974 hwaddr ram_sizes[2],
1975 uint32_t sysclk, qemu_irq **picp,
1976 int do_init)
1977 {
1978 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
1979 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
1980 PowerPCCPU *cpu;
1981 CPUPPCState *env;
1982 qemu_irq *pic, *irqs;
1983
1984 memset(clk_setup, 0, sizeof(clk_setup));
1985 /* init CPUs */
1986 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
1987 &clk_setup[PPC405EP_CPU_CLK],
1988 &tlb_clk_setup, sysclk);
1989 env = &cpu->env;
1990 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
1991 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
1992 /* Internal devices init */
1993 /* Memory mapped devices registers */
1994 /* PLB arbitrer */
1995 ppc4xx_plb_init(env);
1996 /* PLB to OPB bridge */
1997 ppc4xx_pob_init(env);
1998 /* OBP arbitrer */
1999 ppc4xx_opba_init(0xef600600);
2000 /* Initialize timers */
2001 ppc_booke_timers_init(cpu, sysclk, 0);
2002 /* Universal interrupt controller */
2003 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2004 irqs[PPCUIC_OUTPUT_INT] =
2005 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2006 irqs[PPCUIC_OUTPUT_CINT] =
2007 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2008 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2009 *picp = pic;
2010 /* SDRAM controller */
2011 /* XXX 405EP has no ECC interrupt */
2012 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2013 ram_bases, ram_sizes, do_init);
2014 /* External bus controller */
2015 ppc405_ebc_init(env);
2016 /* DMA controller */
2017 dma_irqs[0] = pic[5];
2018 dma_irqs[1] = pic[6];
2019 dma_irqs[2] = pic[7];
2020 dma_irqs[3] = pic[8];
2021 ppc405_dma_init(env, dma_irqs);
2022 /* IIC controller */
2023 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
2024 /* GPIO */
2025 ppc405_gpio_init(0xef600700);
2026 /* Serial ports */
2027 if (serial_hd(0) != NULL) {
2028 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2029 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
2030 DEVICE_BIG_ENDIAN);
2031 }
2032 if (serial_hd(1) != NULL) {
2033 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2034 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
2035 DEVICE_BIG_ENDIAN);
2036 }
2037 /* OCM */
2038 ppc405_ocm_init(env);
2039 /* GPT */
2040 gpt_irqs[0] = pic[19];
2041 gpt_irqs[1] = pic[20];
2042 gpt_irqs[2] = pic[21];
2043 gpt_irqs[3] = pic[22];
2044 gpt_irqs[4] = pic[23];
2045 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2046 /* PCI */
2047 /* Uses pic[3], pic[16], pic[18] */
2048 /* MAL */
2049 mal_irqs[0] = pic[11];
2050 mal_irqs[1] = pic[12];
2051 mal_irqs[2] = pic[13];
2052 mal_irqs[3] = pic[14];
2053 ppc4xx_mal_init(env, 4, 2, mal_irqs);
2054 /* Ethernet */
2055 /* Uses pic[9], pic[15], pic[17] */
2056 /* CPU control */
2057 ppc405ep_cpc_init(env, clk_setup, sysclk);
2058
2059 return env;
2060 }
AR7 emulation for QEMU