?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
i386: Add support for SPEC_CTRL MSR
[qemu/ar7.git] / target / i386 / kvm.c
blobad4b159b28af56419330be932fa56ab283b2ad82
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "exec/ioport.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_xss;
94 static bool has_msr_spec_ctrl;
95
96 static uint32_t has_architectural_pmu_version;
97 static uint32_t num_architectural_pmu_gp_counters;
98 static uint32_t num_architectural_pmu_fixed_counters;
99
100 static int has_xsave;
101 static int has_xcrs;
102 static int has_pit_state2;
103
104 static bool has_msr_mcg_ext_ctl;
105
106 static struct kvm_cpuid2 *cpuid_cache;
107
108 int kvm_has_pit_state2(void)
109 {
110 return has_pit_state2;
111 }
112
113 bool kvm_has_smm(void)
114 {
115 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
116 }
117
118 bool kvm_has_adjust_clock_stable(void)
119 {
120 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
121
122 return (ret == KVM_CLOCK_TSC_STABLE);
123 }
124
125 bool kvm_allows_irq0_override(void)
126 {
127 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
128 }
129
130 static bool kvm_x2apic_api_set_flags(uint64_t flags)
131 {
132 KVMState *s = KVM_STATE(current_machine->accelerator);
133
134 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
135 }
136
137 #define MEMORIZE(fn, _result) \
138 ({ \
139 static bool _memorized; \
140 \
141 if (_memorized) { \
142 return _result; \
143 } \
144 _memorized = true; \
145 _result = fn; \
146 })
147
148 static bool has_x2apic_api;
149
150 bool kvm_has_x2apic_api(void)
151 {
152 return has_x2apic_api;
153 }
154
155 bool kvm_enable_x2apic(void)
156 {
157 return MEMORIZE(
158 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
159 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
160 has_x2apic_api);
161 }
162
163 static int kvm_get_tsc(CPUState *cs)
164 {
165 X86CPU *cpu = X86_CPU(cs);
166 CPUX86State *env = &cpu->env;
167 struct {
168 struct kvm_msrs info;
169 struct kvm_msr_entry entries[1];
170 } msr_data;
171 int ret;
172
173 if (env->tsc_valid) {
174 return 0;
175 }
176
177 msr_data.info.nmsrs = 1;
178 msr_data.entries[0].index = MSR_IA32_TSC;
179 env->tsc_valid = !runstate_is_running();
180
181 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
182 if (ret < 0) {
183 return ret;
184 }
185
186 assert(ret == 1);
187 env->tsc = msr_data.entries[0].data;
188 return 0;
189 }
190
191 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
192 {
193 kvm_get_tsc(cpu);
194 }
195
196 void kvm_synchronize_all_tsc(void)
197 {
198 CPUState *cpu;
199
200 if (kvm_enabled()) {
201 CPU_FOREACH(cpu) {
202 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
203 }
204 }
205 }
206
207 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
208 {
209 struct kvm_cpuid2 *cpuid;
210 int r, size;
211
212 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
213 cpuid = g_malloc0(size);
214 cpuid->nent = max;
215 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
216 if (r == 0 && cpuid->nent >= max) {
217 r = -E2BIG;
218 }
219 if (r < 0) {
220 if (r == -E2BIG) {
221 g_free(cpuid);
222 return NULL;
223 } else {
224 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
225 strerror(-r));
226 exit(1);
227 }
228 }
229 return cpuid;
230 }
231
232 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
233 * for all entries.
234 */
235 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
236 {
237 struct kvm_cpuid2 *cpuid;
238 int max = 1;
239
240 if (cpuid_cache != NULL) {
241 return cpuid_cache;
242 }
243 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
244 max *= 2;
245 }
246 cpuid_cache = cpuid;
247 return cpuid;
248 }
249
250 static const struct kvm_para_features {
251 int cap;
252 int feature;
253 } para_features[] = {
254 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
255 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
256 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
257 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
258 };
259
260 static int get_para_features(KVMState *s)
261 {
262 int i, features = 0;
263
264 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
265 if (kvm_check_extension(s, para_features[i].cap)) {
266 features |= (1 << para_features[i].feature);
267 }
268 }
269
270 return features;
271 }
272
273 static bool host_tsx_blacklisted(void)
274 {
275 int family, model, stepping;\
276 char vendor[CPUID_VENDOR_SZ + 1];
277
278 host_vendor_fms(vendor, &family, &model, &stepping);
279
280 /* Check if we are running on a Haswell host known to have broken TSX */
281 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
282 (family == 6) &&
283 ((model == 63 && stepping < 4) ||
284 model == 60 || model == 69 || model == 70);
285 }
286
287 /* Returns the value for a specific register on the cpuid entry
288 */
289 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
290 {
291 uint32_t ret = 0;
292 switch (reg) {
293 case R_EAX:
294 ret = entry->eax;
295 break;
296 case R_EBX:
297 ret = entry->ebx;
298 break;
299 case R_ECX:
300 ret = entry->ecx;
301 break;
302 case R_EDX:
303 ret = entry->edx;
304 break;
305 }
306 return ret;
307 }
308
309 /* Find matching entry for function/index on kvm_cpuid2 struct
310 */
311 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
312 uint32_t function,
313 uint32_t index)
314 {
315 int i;
316 for (i = 0; i < cpuid->nent; ++i) {
317 if (cpuid->entries[i].function == function &&
318 cpuid->entries[i].index == index) {
319 return &cpuid->entries[i];
320 }
321 }
322 /* not found: */
323 return NULL;
324 }
325
326 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
327 uint32_t index, int reg)
328 {
329 struct kvm_cpuid2 *cpuid;
330 uint32_t ret = 0;
331 uint32_t cpuid_1_edx;
332 bool found = false;
333
334 cpuid = get_supported_cpuid(s);
335
336 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
337 if (entry) {
338 found = true;
339 ret = cpuid_entry_get_reg(entry, reg);
340 }
341
342 /* Fixups for the data returned by KVM, below */
343
344 if (function == 1 && reg == R_EDX) {
345 /* KVM before 2.6.30 misreports the following features */
346 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
347 } else if (function == 1 && reg == R_ECX) {
348 /* We can set the hypervisor flag, even if KVM does not return it on
349 * GET_SUPPORTED_CPUID
350 */
351 ret |= CPUID_EXT_HYPERVISOR;
352 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
353 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
354 * and the irqchip is in the kernel.
355 */
356 if (kvm_irqchip_in_kernel() &&
357 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
358 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
359 }
360
361 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
362 * without the in-kernel irqchip
363 */
364 if (!kvm_irqchip_in_kernel()) {
365 ret &= ~CPUID_EXT_X2APIC;
366 }
367 } else if (function == 6 && reg == R_EAX) {
368 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
369 } else if (function == 7 && index == 0 && reg == R_EBX) {
370 if (host_tsx_blacklisted()) {
371 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
372 }
373 } else if (function == 0x80000001 && reg == R_EDX) {
374 /* On Intel, kvm returns cpuid according to the Intel spec,
375 * so add missing bits according to the AMD spec:
376 */
377 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
378 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
379 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
380 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
381 * be enabled without the in-kernel irqchip
382 */
383 if (!kvm_irqchip_in_kernel()) {
384 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
385 }
386 }
387
388 /* fallback for older kernels */
389 if ((function == KVM_CPUID_FEATURES) && !found) {
390 ret = get_para_features(s);
391 }
392
393 return ret;
394 }
395
396 typedef struct HWPoisonPage {
397 ram_addr_t ram_addr;
398 QLIST_ENTRY(HWPoisonPage) list;
399 } HWPoisonPage;
400
401 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
402 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
403
404 static void kvm_unpoison_all(void *param)
405 {
406 HWPoisonPage *page, *next_page;
407
408 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
409 QLIST_REMOVE(page, list);
410 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
411 g_free(page);
412 }
413 }
414
415 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
416 {
417 HWPoisonPage *page;
418
419 QLIST_FOREACH(page, &hwpoison_page_list, list) {
420 if (page->ram_addr == ram_addr) {
421 return;
422 }
423 }
424 page = g_new(HWPoisonPage, 1);
425 page->ram_addr = ram_addr;
426 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
427 }
428
429 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
430 int *max_banks)
431 {
432 int r;
433
434 r = kvm_check_extension(s, KVM_CAP_MCE);
435 if (r > 0) {
436 *max_banks = r;
437 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
438 }
439 return -ENOSYS;
440 }
441
442 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
443 {
444 CPUState *cs = CPU(cpu);
445 CPUX86State *env = &cpu->env;
446 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
447 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
448 uint64_t mcg_status = MCG_STATUS_MCIP;
449 int flags = 0;
450
451 if (code == BUS_MCEERR_AR) {
452 status |= MCI_STATUS_AR | 0x134;
453 mcg_status |= MCG_STATUS_EIPV;
454 } else {
455 status |= 0xc0;
456 mcg_status |= MCG_STATUS_RIPV;
457 }
458
459 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
460 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
461 * guest kernel back into env->mcg_ext_ctl.
462 */
463 cpu_synchronize_state(cs);
464 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
465 mcg_status |= MCG_STATUS_LMCE;
466 flags = 0;
467 }
468
469 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
470 (MCM_ADDR_PHYS << 6) | 0xc, flags);
471 }
472
473 static void hardware_memory_error(void)
474 {
475 fprintf(stderr, "Hardware memory error!\n");
476 exit(1);
477 }
478
479 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
480 {
481 X86CPU *cpu = X86_CPU(c);
482 CPUX86State *env = &cpu->env;
483 ram_addr_t ram_addr;
484 hwaddr paddr;
485
486 /* If we get an action required MCE, it has been injected by KVM
487 * while the VM was running. An action optional MCE instead should
488 * be coming from the main thread, which qemu_init_sigbus identifies
489 * as the "early kill" thread.
490 */
491 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
492
493 if ((env->mcg_cap & MCG_SER_P) && addr) {
494 ram_addr = qemu_ram_addr_from_host(addr);
495 if (ram_addr != RAM_ADDR_INVALID &&
496 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
497 kvm_hwpoison_page_add(ram_addr);
498 kvm_mce_inject(cpu, paddr, code);
499 return;
500 }
501
502 fprintf(stderr, "Hardware memory error for memory used by "
503 "QEMU itself instead of guest system!\n");
504 }
505
506 if (code == BUS_MCEERR_AR) {
507 hardware_memory_error();
508 }
509
510 /* Hope we are lucky for AO MCE */
511 }
512
513 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
514 {
515 CPUX86State *env = &cpu->env;
516
517 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
518 unsigned int bank, bank_num = env->mcg_cap & 0xff;
519 struct kvm_x86_mce mce;
520
521 env->exception_injected = -1;
522
523 /*
524 * There must be at least one bank in use if an MCE is pending.
525 * Find it and use its values for the event injection.
526 */
527 for (bank = 0; bank < bank_num; bank++) {
528 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
529 break;
530 }
531 }
532 assert(bank < bank_num);
533
534 mce.bank = bank;
535 mce.status = env->mce_banks[bank * 4 + 1];
536 mce.mcg_status = env->mcg_status;
537 mce.addr = env->mce_banks[bank * 4 + 2];
538 mce.misc = env->mce_banks[bank * 4 + 3];
539
540 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
541 }
542 return 0;
543 }
544
545 static void cpu_update_state(void *opaque, int running, RunState state)
546 {
547 CPUX86State *env = opaque;
548
549 if (running) {
550 env->tsc_valid = false;
551 }
552 }
553
554 unsigned long kvm_arch_vcpu_id(CPUState *cs)
555 {
556 X86CPU *cpu = X86_CPU(cs);
557 return cpu->apic_id;
558 }
559
560 #ifndef KVM_CPUID_SIGNATURE_NEXT
561 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
562 #endif
563
564 static bool hyperv_hypercall_available(X86CPU *cpu)
565 {
566 return cpu->hyperv_vapic ||
567 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
568 }
569
570 static bool hyperv_enabled(X86CPU *cpu)
571 {
572 CPUState *cs = CPU(cpu);
573 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
574 (hyperv_hypercall_available(cpu) ||
575 cpu->hyperv_time ||
576 cpu->hyperv_relaxed_timing ||
577 cpu->hyperv_crash ||
578 cpu->hyperv_reset ||
579 cpu->hyperv_vpindex ||
580 cpu->hyperv_runtime ||
581 cpu->hyperv_synic ||
582 cpu->hyperv_stimer);
583 }
584
585 static int kvm_arch_set_tsc_khz(CPUState *cs)
586 {
587 X86CPU *cpu = X86_CPU(cs);
588 CPUX86State *env = &cpu->env;
589 int r;
590
591 if (!env->tsc_khz) {
592 return 0;
593 }
594
595 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
596 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
597 -ENOTSUP;
598 if (r < 0) {
599 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
600 * TSC frequency doesn't match the one we want.
601 */
602 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
603 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
604 -ENOTSUP;
605 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
606 warn_report("TSC frequency mismatch between "
607 "VM (%" PRId64 " kHz) and host (%d kHz), "
608 "and TSC scaling unavailable",
609 env->tsc_khz, cur_freq);
610 return r;
611 }
612 }
613
614 return 0;
615 }
616
617 static bool tsc_is_stable_and_known(CPUX86State *env)
618 {
619 if (!env->tsc_khz) {
620 return false;
621 }
622 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
623 || env->user_tsc_khz;
624 }
625
626 static int hyperv_handle_properties(CPUState *cs)
627 {
628 X86CPU *cpu = X86_CPU(cs);
629 CPUX86State *env = &cpu->env;
630
631 if (cpu->hyperv_time &&
632 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
633 cpu->hyperv_time = false;
634 }
635
636 if (cpu->hyperv_relaxed_timing) {
637 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
638 }
639 if (cpu->hyperv_vapic) {
640 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
641 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
642 }
643 if (cpu->hyperv_time) {
644 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
645 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
646 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
647
648 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
649 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
650 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
651 }
652 }
653 if (cpu->hyperv_crash && has_msr_hv_crash) {
654 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
655 }
656 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
657 if (cpu->hyperv_reset && has_msr_hv_reset) {
658 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
659 }
660 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
661 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
662 }
663 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
664 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
665 }
666 if (cpu->hyperv_synic) {
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
673 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
674 }
675 if (cpu->hyperv_stimer) {
676 if (!has_msr_hv_stimer) {
677 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
678 return -ENOSYS;
679 }
680 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
681 }
682 return 0;
683 }
684
685 static Error *invtsc_mig_blocker;
686
687 #define KVM_MAX_CPUID_ENTRIES 100
688
689 int kvm_arch_init_vcpu(CPUState *cs)
690 {
691 struct {
692 struct kvm_cpuid2 cpuid;
693 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
694 } QEMU_PACKED cpuid_data;
695 X86CPU *cpu = X86_CPU(cs);
696 CPUX86State *env = &cpu->env;
697 uint32_t limit, i, j, cpuid_i;
698 uint32_t unused;
699 struct kvm_cpuid_entry2 *c;
700 uint32_t signature[3];
701 int kvm_base = KVM_CPUID_SIGNATURE;
702 int r;
703 Error *local_err = NULL;
704
705 memset(&cpuid_data, 0, sizeof(cpuid_data));
706
707 cpuid_i = 0;
708
709 r = kvm_arch_set_tsc_khz(cs);
710 if (r < 0) {
711 goto fail;
712 }
713
714 /* vcpu's TSC frequency is either specified by user, or following
715 * the value used by KVM if the former is not present. In the
716 * latter case, we query it from KVM and record in env->tsc_khz,
717 * so that vcpu's TSC frequency can be migrated later via this field.
718 */
719 if (!env->tsc_khz) {
720 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
721 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
722 -ENOTSUP;
723 if (r > 0) {
724 env->tsc_khz = r;
725 }
726 }
727
728 /* Paravirtualization CPUIDs */
729 if (hyperv_enabled(cpu)) {
730 c = &cpuid_data.entries[cpuid_i++];
731 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
732 if (!cpu->hyperv_vendor_id) {
733 memcpy(signature, "Microsoft Hv", 12);
734 } else {
735 size_t len = strlen(cpu->hyperv_vendor_id);
736
737 if (len > 12) {
738 error_report("hv-vendor-id truncated to 12 characters");
739 len = 12;
740 }
741 memset(signature, 0, 12);
742 memcpy(signature, cpu->hyperv_vendor_id, len);
743 }
744 c->eax = HV_CPUID_MIN;
745 c->ebx = signature[0];
746 c->ecx = signature[1];
747 c->edx = signature[2];
748
749 c = &cpuid_data.entries[cpuid_i++];
750 c->function = HV_CPUID_INTERFACE;
751 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
752 c->eax = signature[0];
753 c->ebx = 0;
754 c->ecx = 0;
755 c->edx = 0;
756
757 c = &cpuid_data.entries[cpuid_i++];
758 c->function = HV_CPUID_VERSION;
759 c->eax = 0x00001bbc;
760 c->ebx = 0x00060001;
761
762 c = &cpuid_data.entries[cpuid_i++];
763 c->function = HV_CPUID_FEATURES;
764 r = hyperv_handle_properties(cs);
765 if (r) {
766 return r;
767 }
768 c->eax = env->features[FEAT_HYPERV_EAX];
769 c->ebx = env->features[FEAT_HYPERV_EBX];
770 c->edx = env->features[FEAT_HYPERV_EDX];
771
772 c = &cpuid_data.entries[cpuid_i++];
773 c->function = HV_CPUID_ENLIGHTMENT_INFO;
774 if (cpu->hyperv_relaxed_timing) {
775 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
776 }
777 if (cpu->hyperv_vapic) {
778 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
779 }
780 c->ebx = cpu->hyperv_spinlock_attempts;
781
782 c = &cpuid_data.entries[cpuid_i++];
783 c->function = HV_CPUID_IMPLEMENT_LIMITS;
784
785 c->eax = cpu->hv_max_vps;
786 c->ebx = 0x40;
787
788 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
789 has_msr_hv_hypercall = true;
790 }
791
792 if (cpu->expose_kvm) {
793 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
794 c = &cpuid_data.entries[cpuid_i++];
795 c->function = KVM_CPUID_SIGNATURE | kvm_base;
796 c->eax = KVM_CPUID_FEATURES | kvm_base;
797 c->ebx = signature[0];
798 c->ecx = signature[1];
799 c->edx = signature[2];
800
801 c = &cpuid_data.entries[cpuid_i++];
802 c->function = KVM_CPUID_FEATURES | kvm_base;
803 c->eax = env->features[FEAT_KVM];
804 }
805
806 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
807
808 for (i = 0; i <= limit; i++) {
809 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
810 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
811 abort();
812 }
813 c = &cpuid_data.entries[cpuid_i++];
814
815 switch (i) {
816 case 2: {
817 /* Keep reading function 2 till all the input is received */
818 int times;
819
820 c->function = i;
821 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
822 KVM_CPUID_FLAG_STATE_READ_NEXT;
823 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
824 times = c->eax & 0xff;
825
826 for (j = 1; j < times; ++j) {
827 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
828 fprintf(stderr, "cpuid_data is full, no space for "
829 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
830 abort();
831 }
832 c = &cpuid_data.entries[cpuid_i++];
833 c->function = i;
834 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
835 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
836 }
837 break;
838 }
839 case 4:
840 case 0xb:
841 case 0xd:
842 for (j = 0; ; j++) {
843 if (i == 0xd && j == 64) {
844 break;
845 }
846 c->function = i;
847 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
848 c->index = j;
849 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
850
851 if (i == 4 && c->eax == 0) {
852 break;
853 }
854 if (i == 0xb && !(c->ecx & 0xff00)) {
855 break;
856 }
857 if (i == 0xd && c->eax == 0) {
858 continue;
859 }
860 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
861 fprintf(stderr, "cpuid_data is full, no space for "
862 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
863 abort();
864 }
865 c = &cpuid_data.entries[cpuid_i++];
866 }
867 break;
868 default:
869 c->function = i;
870 c->flags = 0;
871 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
872 break;
873 }
874 }
875
876 if (limit >= 0x0a) {
877 uint32_t eax, edx;
878
879 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
880
881 has_architectural_pmu_version = eax & 0xff;
882 if (has_architectural_pmu_version > 0) {
883 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
884
885 /* Shouldn't be more than 32, since that's the number of bits
886 * available in EBX to tell us _which_ counters are available.
887 * Play it safe.
888 */
889 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
890 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
891 }
892
893 if (has_architectural_pmu_version > 1) {
894 num_architectural_pmu_fixed_counters = edx & 0x1f;
895
896 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
897 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
898 }
899 }
900 }
901 }
902
903 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
904
905 for (i = 0x80000000; i <= limit; i++) {
906 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
907 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
908 abort();
909 }
910 c = &cpuid_data.entries[cpuid_i++];
911
912 c->function = i;
913 c->flags = 0;
914 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
915 }
916
917 /* Call Centaur's CPUID instructions they are supported. */
918 if (env->cpuid_xlevel2 > 0) {
919 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
920
921 for (i = 0xC0000000; i <= limit; i++) {
922 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
923 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
924 abort();
925 }
926 c = &cpuid_data.entries[cpuid_i++];
927
928 c->function = i;
929 c->flags = 0;
930 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
931 }
932 }
933
934 cpuid_data.cpuid.nent = cpuid_i;
935
936 if (((env->cpuid_version >> 8)&0xF) >= 6
937 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
938 (CPUID_MCE | CPUID_MCA)
939 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
940 uint64_t mcg_cap, unsupported_caps;
941 int banks;
942 int ret;
943
944 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
945 if (ret < 0) {
946 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
947 return ret;
948 }
949
950 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
951 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
952 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
953 return -ENOTSUP;
954 }
955
956 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
957 if (unsupported_caps) {
958 if (unsupported_caps & MCG_LMCE_P) {
959 error_report("kvm: LMCE not supported");
960 return -ENOTSUP;
961 }
962 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
963 unsupported_caps);
964 }
965
966 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
967 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
968 if (ret < 0) {
969 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
970 return ret;
971 }
972 }
973
974 qemu_add_vm_change_state_handler(cpu_update_state, env);
975
976 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
977 if (c) {
978 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
979 !!(c->ecx & CPUID_EXT_SMX);
980 }
981
982 if (env->mcg_cap & MCG_LMCE_P) {
983 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
984 }
985
986 if (!env->user_tsc_khz) {
987 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
988 invtsc_mig_blocker == NULL) {
989 /* for migration */
990 error_setg(&invtsc_mig_blocker,
991 "State blocked by non-migratable CPU device"
992 " (invtsc flag)");
993 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
994 if (local_err) {
995 error_report_err(local_err);
996 error_free(invtsc_mig_blocker);
997 goto fail;
998 }
999 /* for savevm */
1000 vmstate_x86_cpu.unmigratable = 1;
1001 }
1002 }
1003
1004 if (cpu->vmware_cpuid_freq
1005 /* Guests depend on 0x40000000 to detect this feature, so only expose
1006 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1007 && cpu->expose_kvm
1008 && kvm_base == KVM_CPUID_SIGNATURE
1009 /* TSC clock must be stable and known for this feature. */
1010 && tsc_is_stable_and_known(env)) {
1011
1012 c = &cpuid_data.entries[cpuid_i++];
1013 c->function = KVM_CPUID_SIGNATURE | 0x10;
1014 c->eax = env->tsc_khz;
1015 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1016 * APIC_BUS_CYCLE_NS */
1017 c->ebx = 1000000;
1018 c->ecx = c->edx = 0;
1019
1020 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1021 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1022 }
1023
1024 cpuid_data.cpuid.nent = cpuid_i;
1025
1026 cpuid_data.cpuid.padding = 0;
1027 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1028 if (r) {
1029 goto fail;
1030 }
1031
1032 if (has_xsave) {
1033 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1034 }
1035 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1036
1037 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1038 has_msr_tsc_aux = false;
1039 }
1040
1041 return 0;
1042
1043 fail:
1044 migrate_del_blocker(invtsc_mig_blocker);
1045 return r;
1046 }
1047
1048 void kvm_arch_reset_vcpu(X86CPU *cpu)
1049 {
1050 CPUX86State *env = &cpu->env;
1051
1052 env->xcr0 = 1;
1053 if (kvm_irqchip_in_kernel()) {
1054 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1055 KVM_MP_STATE_UNINITIALIZED;
1056 } else {
1057 env->mp_state = KVM_MP_STATE_RUNNABLE;
1058 }
1059
1060 if (cpu->hyperv_synic) {
1061 int i;
1062 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1063 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1064 }
1065 }
1066 }
1067
1068 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1069 {
1070 CPUX86State *env = &cpu->env;
1071
1072 /* APs get directly into wait-for-SIPI state. */
1073 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1074 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1075 }
1076 }
1077
1078 static int kvm_get_supported_msrs(KVMState *s)
1079 {
1080 static int kvm_supported_msrs;
1081 int ret = 0;
1082
1083 /* first time */
1084 if (kvm_supported_msrs == 0) {
1085 struct kvm_msr_list msr_list, *kvm_msr_list;
1086
1087 kvm_supported_msrs = -1;
1088
1089 /* Obtain MSR list from KVM. These are the MSRs that we must
1090 * save/restore */
1091 msr_list.nmsrs = 0;
1092 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1093 if (ret < 0 && ret != -E2BIG) {
1094 return ret;
1095 }
1096 /* Old kernel modules had a bug and could write beyond the provided
1097 memory. Allocate at least a safe amount of 1K. */
1098 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1099 msr_list.nmsrs *
1100 sizeof(msr_list.indices[0])));
1101
1102 kvm_msr_list->nmsrs = msr_list.nmsrs;
1103 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1104 if (ret >= 0) {
1105 int i;
1106
1107 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1108 switch (kvm_msr_list->indices[i]) {
1109 case MSR_STAR:
1110 has_msr_star = true;
1111 break;
1112 case MSR_VM_HSAVE_PA:
1113 has_msr_hsave_pa = true;
1114 break;
1115 case MSR_TSC_AUX:
1116 has_msr_tsc_aux = true;
1117 break;
1118 case MSR_TSC_ADJUST:
1119 has_msr_tsc_adjust = true;
1120 break;
1121 case MSR_IA32_TSCDEADLINE:
1122 has_msr_tsc_deadline = true;
1123 break;
1124 case MSR_IA32_SMBASE:
1125 has_msr_smbase = true;
1126 break;
1127 case MSR_IA32_MISC_ENABLE:
1128 has_msr_misc_enable = true;
1129 break;
1130 case MSR_IA32_BNDCFGS:
1131 has_msr_bndcfgs = true;
1132 break;
1133 case MSR_IA32_XSS:
1134 has_msr_xss = true;
1135 break;
1136 case HV_X64_MSR_CRASH_CTL:
1137 has_msr_hv_crash = true;
1138 break;
1139 case HV_X64_MSR_RESET:
1140 has_msr_hv_reset = true;
1141 break;
1142 case HV_X64_MSR_VP_INDEX:
1143 has_msr_hv_vpindex = true;
1144 break;
1145 case HV_X64_MSR_VP_RUNTIME:
1146 has_msr_hv_runtime = true;
1147 break;
1148 case HV_X64_MSR_SCONTROL:
1149 has_msr_hv_synic = true;
1150 break;
1151 case HV_X64_MSR_STIMER0_CONFIG:
1152 has_msr_hv_stimer = true;
1153 break;
1154 case HV_X64_MSR_TSC_FREQUENCY:
1155 has_msr_hv_frequencies = true;
1156 break;
1157 case MSR_IA32_SPEC_CTRL:
1158 has_msr_spec_ctrl = true;
1159 break;
1160 }
1161 }
1162 }
1163
1164 g_free(kvm_msr_list);
1165 }
1166
1167 return ret;
1168 }
1169
1170 static Notifier smram_machine_done;
1171 static KVMMemoryListener smram_listener;
1172 static AddressSpace smram_address_space;
1173 static MemoryRegion smram_as_root;
1174 static MemoryRegion smram_as_mem;
1175
1176 static void register_smram_listener(Notifier *n, void *unused)
1177 {
1178 MemoryRegion *smram =
1179 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1180
1181 /* Outer container... */
1182 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1183 memory_region_set_enabled(&smram_as_root, true);
1184
1185 /* ... with two regions inside: normal system memory with low
1186 * priority, and...
1187 */
1188 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1189 get_system_memory(), 0, ~0ull);
1190 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1191 memory_region_set_enabled(&smram_as_mem, true);
1192
1193 if (smram) {
1194 /* ... SMRAM with higher priority */
1195 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1196 memory_region_set_enabled(smram, true);
1197 }
1198
1199 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1200 kvm_memory_listener_register(kvm_state, &smram_listener,
1201 &smram_address_space, 1);
1202 }
1203
1204 int kvm_arch_init(MachineState *ms, KVMState *s)
1205 {
1206 uint64_t identity_base = 0xfffbc000;
1207 uint64_t shadow_mem;
1208 int ret;
1209 struct utsname utsname;
1210
1211 #ifdef KVM_CAP_XSAVE
1212 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1213 #endif
1214
1215 #ifdef KVM_CAP_XCRS
1216 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1217 #endif
1218
1219 #ifdef KVM_CAP_PIT_STATE2
1220 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1221 #endif
1222
1223 ret = kvm_get_supported_msrs(s);
1224 if (ret < 0) {
1225 return ret;
1226 }
1227
1228 uname(&utsname);
1229 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1230
1231 /*
1232 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1233 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1234 * Since these must be part of guest physical memory, we need to allocate
1235 * them, both by setting their start addresses in the kernel and by
1236 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1237 *
1238 * Older KVM versions may not support setting the identity map base. In
1239 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1240 * size.
1241 */
1242 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1243 /* Allows up to 16M BIOSes. */
1244 identity_base = 0xfeffc000;
1245
1246 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1247 if (ret < 0) {
1248 return ret;
1249 }
1250 }
1251
1252 /* Set TSS base one page after EPT identity map. */
1253 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1254 if (ret < 0) {
1255 return ret;
1256 }
1257
1258 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1259 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1260 if (ret < 0) {
1261 fprintf(stderr, "e820_add_entry() table is full\n");
1262 return ret;
1263 }
1264 qemu_register_reset(kvm_unpoison_all, NULL);
1265
1266 shadow_mem = machine_kvm_shadow_mem(ms);
1267 if (shadow_mem != -1) {
1268 shadow_mem /= 4096;
1269 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1270 if (ret < 0) {
1271 return ret;
1272 }
1273 }
1274
1275 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1276 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1277 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1278 smram_machine_done.notify = register_smram_listener;
1279 qemu_add_machine_init_done_notifier(&smram_machine_done);
1280 }
1281 return 0;
1282 }
1283
1284 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1285 {
1286 lhs->selector = rhs->selector;
1287 lhs->base = rhs->base;
1288 lhs->limit = rhs->limit;
1289 lhs->type = 3;
1290 lhs->present = 1;
1291 lhs->dpl = 3;
1292 lhs->db = 0;
1293 lhs->s = 1;
1294 lhs->l = 0;
1295 lhs->g = 0;
1296 lhs->avl = 0;
1297 lhs->unusable = 0;
1298 }
1299
1300 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1301 {
1302 unsigned flags = rhs->flags;
1303 lhs->selector = rhs->selector;
1304 lhs->base = rhs->base;
1305 lhs->limit = rhs->limit;
1306 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1307 lhs->present = (flags & DESC_P_MASK) != 0;
1308 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1309 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1310 lhs->s = (flags & DESC_S_MASK) != 0;
1311 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1312 lhs->g = (flags & DESC_G_MASK) != 0;
1313 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1314 lhs->unusable = !lhs->present;
1315 lhs->padding = 0;
1316 }
1317
1318 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1319 {
1320 lhs->selector = rhs->selector;
1321 lhs->base = rhs->base;
1322 lhs->limit = rhs->limit;
1323 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1324 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1325 (rhs->dpl << DESC_DPL_SHIFT) |
1326 (rhs->db << DESC_B_SHIFT) |
1327 (rhs->s * DESC_S_MASK) |
1328 (rhs->l << DESC_L_SHIFT) |
1329 (rhs->g * DESC_G_MASK) |
1330 (rhs->avl * DESC_AVL_MASK);
1331 }
1332
1333 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1334 {
1335 if (set) {
1336 *kvm_reg = *qemu_reg;
1337 } else {
1338 *qemu_reg = *kvm_reg;
1339 }
1340 }
1341
1342 static int kvm_getput_regs(X86CPU *cpu, int set)
1343 {
1344 CPUX86State *env = &cpu->env;
1345 struct kvm_regs regs;
1346 int ret = 0;
1347
1348 if (!set) {
1349 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1350 if (ret < 0) {
1351 return ret;
1352 }
1353 }
1354
1355 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1356 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1357 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1358 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1359 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1360 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1361 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1362 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1363 #ifdef TARGET_X86_64
1364 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1365 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1366 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1367 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1368 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1369 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1370 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1371 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1372 #endif
1373
1374 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1375 kvm_getput_reg(&regs.rip, &env->eip, set);
1376
1377 if (set) {
1378 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1379 }
1380
1381 return ret;
1382 }
1383
1384 static int kvm_put_fpu(X86CPU *cpu)
1385 {
1386 CPUX86State *env = &cpu->env;
1387 struct kvm_fpu fpu;
1388 int i;
1389
1390 memset(&fpu, 0, sizeof fpu);
1391 fpu.fsw = env->fpus & ~(7 << 11);
1392 fpu.fsw |= (env->fpstt & 7) << 11;
1393 fpu.fcw = env->fpuc;
1394 fpu.last_opcode = env->fpop;
1395 fpu.last_ip = env->fpip;
1396 fpu.last_dp = env->fpdp;
1397 for (i = 0; i < 8; ++i) {
1398 fpu.ftwx |= (!env->fptags[i]) << i;
1399 }
1400 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1401 for (i = 0; i < CPU_NB_REGS; i++) {
1402 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1403 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1404 }
1405 fpu.mxcsr = env->mxcsr;
1406
1407 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1408 }
1409
1410 #define XSAVE_FCW_FSW 0
1411 #define XSAVE_FTW_FOP 1
1412 #define XSAVE_CWD_RIP 2
1413 #define XSAVE_CWD_RDP 4
1414 #define XSAVE_MXCSR 6
1415 #define XSAVE_ST_SPACE 8
1416 #define XSAVE_XMM_SPACE 40
1417 #define XSAVE_XSTATE_BV 128
1418 #define XSAVE_YMMH_SPACE 144
1419 #define XSAVE_BNDREGS 240
1420 #define XSAVE_BNDCSR 256
1421 #define XSAVE_OPMASK 272
1422 #define XSAVE_ZMM_Hi256 288
1423 #define XSAVE_Hi16_ZMM 416
1424 #define XSAVE_PKRU 672
1425
1426 #define XSAVE_BYTE_OFFSET(word_offset) \
1427 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1428
1429 #define ASSERT_OFFSET(word_offset, field) \
1430 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1431 offsetof(X86XSaveArea, field))
1432
1433 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1434 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1435 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1436 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1437 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1438 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1439 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1440 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1441 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1442 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1443 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1444 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1445 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1446 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1447 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1448
1449 static int kvm_put_xsave(X86CPU *cpu)
1450 {
1451 CPUX86State *env = &cpu->env;
1452 X86XSaveArea *xsave = env->kvm_xsave_buf;
1453
1454 if (!has_xsave) {
1455 return kvm_put_fpu(cpu);
1456 }
1457 x86_cpu_xsave_all_areas(cpu, xsave);
1458
1459 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1460 }
1461
1462 static int kvm_put_xcrs(X86CPU *cpu)
1463 {
1464 CPUX86State *env = &cpu->env;
1465 struct kvm_xcrs xcrs = {};
1466
1467 if (!has_xcrs) {
1468 return 0;
1469 }
1470
1471 xcrs.nr_xcrs = 1;
1472 xcrs.flags = 0;
1473 xcrs.xcrs[0].xcr = 0;
1474 xcrs.xcrs[0].value = env->xcr0;
1475 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1476 }
1477
1478 static int kvm_put_sregs(X86CPU *cpu)
1479 {
1480 CPUX86State *env = &cpu->env;
1481 struct kvm_sregs sregs;
1482
1483 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1484 if (env->interrupt_injected >= 0) {
1485 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1486 (uint64_t)1 << (env->interrupt_injected % 64);
1487 }
1488
1489 if ((env->eflags & VM_MASK)) {
1490 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1491 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1492 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1493 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1494 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1495 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1496 } else {
1497 set_seg(&sregs.cs, &env->segs[R_CS]);
1498 set_seg(&sregs.ds, &env->segs[R_DS]);
1499 set_seg(&sregs.es, &env->segs[R_ES]);
1500 set_seg(&sregs.fs, &env->segs[R_FS]);
1501 set_seg(&sregs.gs, &env->segs[R_GS]);
1502 set_seg(&sregs.ss, &env->segs[R_SS]);
1503 }
1504
1505 set_seg(&sregs.tr, &env->tr);
1506 set_seg(&sregs.ldt, &env->ldt);
1507
1508 sregs.idt.limit = env->idt.limit;
1509 sregs.idt.base = env->idt.base;
1510 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1511 sregs.gdt.limit = env->gdt.limit;
1512 sregs.gdt.base = env->gdt.base;
1513 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1514
1515 sregs.cr0 = env->cr[0];
1516 sregs.cr2 = env->cr[2];
1517 sregs.cr3 = env->cr[3];
1518 sregs.cr4 = env->cr[4];
1519
1520 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1521 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1522
1523 sregs.efer = env->efer;
1524
1525 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1526 }
1527
1528 static void kvm_msr_buf_reset(X86CPU *cpu)
1529 {
1530 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1531 }
1532
1533 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1534 {
1535 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1536 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1537 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1538
1539 assert((void *)(entry + 1) <= limit);
1540
1541 entry->index = index;
1542 entry->reserved = 0;
1543 entry->data = value;
1544 msrs->nmsrs++;
1545 }
1546
1547 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1548 {
1549 kvm_msr_buf_reset(cpu);
1550 kvm_msr_entry_add(cpu, index, value);
1551
1552 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1553 }
1554
1555 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1556 {
1557 int ret;
1558
1559 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1560 assert(ret == 1);
1561 }
1562
1563 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1564 {
1565 CPUX86State *env = &cpu->env;
1566 int ret;
1567
1568 if (!has_msr_tsc_deadline) {
1569 return 0;
1570 }
1571
1572 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1573 if (ret < 0) {
1574 return ret;
1575 }
1576
1577 assert(ret == 1);
1578 return 0;
1579 }
1580
1581 /*
1582 * Provide a separate write service for the feature control MSR in order to
1583 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1584 * before writing any other state because forcibly leaving nested mode
1585 * invalidates the VCPU state.
1586 */
1587 static int kvm_put_msr_feature_control(X86CPU *cpu)
1588 {
1589 int ret;
1590
1591 if (!has_msr_feature_control) {
1592 return 0;
1593 }
1594
1595 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1596 cpu->env.msr_ia32_feature_control);
1597 if (ret < 0) {
1598 return ret;
1599 }
1600
1601 assert(ret == 1);
1602 return 0;
1603 }
1604
1605 static int kvm_put_msrs(X86CPU *cpu, int level)
1606 {
1607 CPUX86State *env = &cpu->env;
1608 int i;
1609 int ret;
1610
1611 kvm_msr_buf_reset(cpu);
1612
1613 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1614 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1615 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1616 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1617 if (has_msr_star) {
1618 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1619 }
1620 if (has_msr_hsave_pa) {
1621 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1622 }
1623 if (has_msr_tsc_aux) {
1624 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1625 }
1626 if (has_msr_tsc_adjust) {
1627 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1628 }
1629 if (has_msr_misc_enable) {
1630 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1631 env->msr_ia32_misc_enable);
1632 }
1633 if (has_msr_smbase) {
1634 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1635 }
1636 if (has_msr_bndcfgs) {
1637 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1638 }
1639 if (has_msr_xss) {
1640 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1641 }
1642 if (has_msr_spec_ctrl) {
1643 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1644 }
1645 #ifdef TARGET_X86_64
1646 if (lm_capable_kernel) {
1647 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1648 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1649 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1650 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1651 }
1652 #endif
1653
1654 /*
1655 * The following MSRs have side effects on the guest or are too heavy
1656 * for normal writeback. Limit them to reset or full state updates.
1657 */
1658 if (level >= KVM_PUT_RESET_STATE) {
1659 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1660 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1661 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1662 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1663 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1664 }
1665 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1666 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1667 }
1668 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1669 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1670 }
1671 if (has_architectural_pmu_version > 0) {
1672 if (has_architectural_pmu_version > 1) {
1673 /* Stop the counter. */
1674 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1675 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1676 }
1677
1678 /* Set the counter values. */
1679 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1680 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1681 env->msr_fixed_counters[i]);
1682 }
1683 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1684 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1685 env->msr_gp_counters[i]);
1686 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1687 env->msr_gp_evtsel[i]);
1688 }
1689 if (has_architectural_pmu_version > 1) {
1690 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1691 env->msr_global_status);
1692 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1693 env->msr_global_ovf_ctrl);
1694
1695 /* Now start the PMU. */
1696 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1697 env->msr_fixed_ctr_ctrl);
1698 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1699 env->msr_global_ctrl);
1700 }
1701 }
1702 /*
1703 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1704 * only sync them to KVM on the first cpu
1705 */
1706 if (current_cpu == first_cpu) {
1707 if (has_msr_hv_hypercall) {
1708 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1709 env->msr_hv_guest_os_id);
1710 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1711 env->msr_hv_hypercall);
1712 }
1713 if (cpu->hyperv_time) {
1714 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1715 env->msr_hv_tsc);
1716 }
1717 }
1718 if (cpu->hyperv_vapic) {
1719 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1720 env->msr_hv_vapic);
1721 }
1722 if (has_msr_hv_crash) {
1723 int j;
1724
1725 for (j = 0; j < HV_CRASH_PARAMS; j++)
1726 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1727 env->msr_hv_crash_params[j]);
1728
1729 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1730 }
1731 if (has_msr_hv_runtime) {
1732 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1733 }
1734 if (cpu->hyperv_synic) {
1735 int j;
1736
1737 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1738
1739 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1740 env->msr_hv_synic_control);
1741 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1742 env->msr_hv_synic_evt_page);
1743 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1744 env->msr_hv_synic_msg_page);
1745
1746 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1747 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1748 env->msr_hv_synic_sint[j]);
1749 }
1750 }
1751 if (has_msr_hv_stimer) {
1752 int j;
1753
1754 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1755 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1756 env->msr_hv_stimer_config[j]);
1757 }
1758
1759 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1760 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1761 env->msr_hv_stimer_count[j]);
1762 }
1763 }
1764 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1765 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1766
1767 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1768 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1769 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1770 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1771 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1772 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1773 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1774 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1775 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1776 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1777 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1778 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1779 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1780 /* The CPU GPs if we write to a bit above the physical limit of
1781 * the host CPU (and KVM emulates that)
1782 */
1783 uint64_t mask = env->mtrr_var[i].mask;
1784 mask &= phys_mask;
1785
1786 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1787 env->mtrr_var[i].base);
1788 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1789 }
1790 }
1791
1792 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1793 * kvm_put_msr_feature_control. */
1794 }
1795 if (env->mcg_cap) {
1796 int i;
1797
1798 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1799 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1800 if (has_msr_mcg_ext_ctl) {
1801 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1802 }
1803 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1804 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1805 }
1806 }
1807
1808 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1809 if (ret < 0) {
1810 return ret;
1811 }
1812
1813 if (ret < cpu->kvm_msr_buf->nmsrs) {
1814 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1815 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1816 (uint32_t)e->index, (uint64_t)e->data);
1817 }
1818
1819 assert(ret == cpu->kvm_msr_buf->nmsrs);
1820 return 0;
1821 }
1822
1823
1824 static int kvm_get_fpu(X86CPU *cpu)
1825 {
1826 CPUX86State *env = &cpu->env;
1827 struct kvm_fpu fpu;
1828 int i, ret;
1829
1830 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1831 if (ret < 0) {
1832 return ret;
1833 }
1834
1835 env->fpstt = (fpu.fsw >> 11) & 7;
1836 env->fpus = fpu.fsw;
1837 env->fpuc = fpu.fcw;
1838 env->fpop = fpu.last_opcode;
1839 env->fpip = fpu.last_ip;
1840 env->fpdp = fpu.last_dp;
1841 for (i = 0; i < 8; ++i) {
1842 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1843 }
1844 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1845 for (i = 0; i < CPU_NB_REGS; i++) {
1846 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1847 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1848 }
1849 env->mxcsr = fpu.mxcsr;
1850
1851 return 0;
1852 }
1853
1854 static int kvm_get_xsave(X86CPU *cpu)
1855 {
1856 CPUX86State *env = &cpu->env;
1857 X86XSaveArea *xsave = env->kvm_xsave_buf;
1858 int ret;
1859
1860 if (!has_xsave) {
1861 return kvm_get_fpu(cpu);
1862 }
1863
1864 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1865 if (ret < 0) {
1866 return ret;
1867 }
1868 x86_cpu_xrstor_all_areas(cpu, xsave);
1869
1870 return 0;
1871 }
1872
1873 static int kvm_get_xcrs(X86CPU *cpu)
1874 {
1875 CPUX86State *env = &cpu->env;
1876 int i, ret;
1877 struct kvm_xcrs xcrs;
1878
1879 if (!has_xcrs) {
1880 return 0;
1881 }
1882
1883 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1884 if (ret < 0) {
1885 return ret;
1886 }
1887
1888 for (i = 0; i < xcrs.nr_xcrs; i++) {
1889 /* Only support xcr0 now */
1890 if (xcrs.xcrs[i].xcr == 0) {
1891 env->xcr0 = xcrs.xcrs[i].value;
1892 break;
1893 }
1894 }
1895 return 0;
1896 }
1897
1898 static int kvm_get_sregs(X86CPU *cpu)
1899 {
1900 CPUX86State *env = &cpu->env;
1901 struct kvm_sregs sregs;
1902 int bit, i, ret;
1903
1904 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1905 if (ret < 0) {
1906 return ret;
1907 }
1908
1909 /* There can only be one pending IRQ set in the bitmap at a time, so try
1910 to find it and save its number instead (-1 for none). */
1911 env->interrupt_injected = -1;
1912 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1913 if (sregs.interrupt_bitmap[i]) {
1914 bit = ctz64(sregs.interrupt_bitmap[i]);
1915 env->interrupt_injected = i * 64 + bit;
1916 break;
1917 }
1918 }
1919
1920 get_seg(&env->segs[R_CS], &sregs.cs);
1921 get_seg(&env->segs[R_DS], &sregs.ds);
1922 get_seg(&env->segs[R_ES], &sregs.es);
1923 get_seg(&env->segs[R_FS], &sregs.fs);
1924 get_seg(&env->segs[R_GS], &sregs.gs);
1925 get_seg(&env->segs[R_SS], &sregs.ss);
1926
1927 get_seg(&env->tr, &sregs.tr);
1928 get_seg(&env->ldt, &sregs.ldt);
1929
1930 env->idt.limit = sregs.idt.limit;
1931 env->idt.base = sregs.idt.base;
1932 env->gdt.limit = sregs.gdt.limit;
1933 env->gdt.base = sregs.gdt.base;
1934
1935 env->cr[0] = sregs.cr0;
1936 env->cr[2] = sregs.cr2;
1937 env->cr[3] = sregs.cr3;
1938 env->cr[4] = sregs.cr4;
1939
1940 env->efer = sregs.efer;
1941
1942 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1943 x86_update_hflags(env);
1944
1945 return 0;
1946 }
1947
1948 static int kvm_get_msrs(X86CPU *cpu)
1949 {
1950 CPUX86State *env = &cpu->env;
1951 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1952 int ret, i;
1953 uint64_t mtrr_top_bits;
1954
1955 kvm_msr_buf_reset(cpu);
1956
1957 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1958 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1959 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1960 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1961 if (has_msr_star) {
1962 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1963 }
1964 if (has_msr_hsave_pa) {
1965 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1966 }
1967 if (has_msr_tsc_aux) {
1968 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1969 }
1970 if (has_msr_tsc_adjust) {
1971 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1972 }
1973 if (has_msr_tsc_deadline) {
1974 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1975 }
1976 if (has_msr_misc_enable) {
1977 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1978 }
1979 if (has_msr_smbase) {
1980 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
1981 }
1982 if (has_msr_feature_control) {
1983 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
1984 }
1985 if (has_msr_bndcfgs) {
1986 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
1987 }
1988 if (has_msr_xss) {
1989 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
1990 }
1991 if (has_msr_spec_ctrl) {
1992 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
1993 }
1994
1995
1996 if (!env->tsc_valid) {
1997 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1998 env->tsc_valid = !runstate_is_running();
1999 }
2000
2001 #ifdef TARGET_X86_64
2002 if (lm_capable_kernel) {
2003 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2004 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2005 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2006 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2007 }
2008 #endif
2009 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2010 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2011 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2012 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2013 }
2014 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2015 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2016 }
2017 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2018 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2019 }
2020 if (has_architectural_pmu_version > 0) {
2021 if (has_architectural_pmu_version > 1) {
2022 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2023 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2024 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2025 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2026 }
2027 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2028 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2029 }
2030 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2031 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2032 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2033 }
2034 }
2035
2036 if (env->mcg_cap) {
2037 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2038 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2039 if (has_msr_mcg_ext_ctl) {
2040 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2041 }
2042 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2043 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2044 }
2045 }
2046
2047 if (has_msr_hv_hypercall) {
2048 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2049 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2050 }
2051 if (cpu->hyperv_vapic) {
2052 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2053 }
2054 if (cpu->hyperv_time) {
2055 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2056 }
2057 if (has_msr_hv_crash) {
2058 int j;
2059
2060 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2061 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2062 }
2063 }
2064 if (has_msr_hv_runtime) {
2065 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2066 }
2067 if (cpu->hyperv_synic) {
2068 uint32_t msr;
2069
2070 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2071 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2072 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2073 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2074 kvm_msr_entry_add(cpu, msr, 0);
2075 }
2076 }
2077 if (has_msr_hv_stimer) {
2078 uint32_t msr;
2079
2080 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2081 msr++) {
2082 kvm_msr_entry_add(cpu, msr, 0);
2083 }
2084 }
2085 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2086 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2087 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2088 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2089 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2090 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2091 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2092 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2093 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2094 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2095 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2096 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2097 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2098 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2099 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2100 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2101 }
2102 }
2103
2104 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2105 if (ret < 0) {
2106 return ret;
2107 }
2108
2109 if (ret < cpu->kvm_msr_buf->nmsrs) {
2110 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2111 error_report("error: failed to get MSR 0x%" PRIx32,
2112 (uint32_t)e->index);
2113 }
2114
2115 assert(ret == cpu->kvm_msr_buf->nmsrs);
2116 /*
2117 * MTRR masks: Each mask consists of 5 parts
2118 * a 10..0: must be zero
2119 * b 11 : valid bit
2120 * c n-1.12: actual mask bits
2121 * d 51..n: reserved must be zero
2122 * e 63.52: reserved must be zero
2123 *
2124 * 'n' is the number of physical bits supported by the CPU and is
2125 * apparently always <= 52. We know our 'n' but don't know what
2126 * the destinations 'n' is; it might be smaller, in which case
2127 * it masks (c) on loading. It might be larger, in which case
2128 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2129 * we're migrating to.
2130 */
2131
2132 if (cpu->fill_mtrr_mask) {
2133 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2134 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2135 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2136 } else {
2137 mtrr_top_bits = 0;
2138 }
2139
2140 for (i = 0; i < ret; i++) {
2141 uint32_t index = msrs[i].index;
2142 switch (index) {
2143 case MSR_IA32_SYSENTER_CS:
2144 env->sysenter_cs = msrs[i].data;
2145 break;
2146 case MSR_IA32_SYSENTER_ESP:
2147 env->sysenter_esp = msrs[i].data;
2148 break;
2149 case MSR_IA32_SYSENTER_EIP:
2150 env->sysenter_eip = msrs[i].data;
2151 break;
2152 case MSR_PAT:
2153 env->pat = msrs[i].data;
2154 break;
2155 case MSR_STAR:
2156 env->star = msrs[i].data;
2157 break;
2158 #ifdef TARGET_X86_64
2159 case MSR_CSTAR:
2160 env->cstar = msrs[i].data;
2161 break;
2162 case MSR_KERNELGSBASE:
2163 env->kernelgsbase = msrs[i].data;
2164 break;
2165 case MSR_FMASK:
2166 env->fmask = msrs[i].data;
2167 break;
2168 case MSR_LSTAR:
2169 env->lstar = msrs[i].data;
2170 break;
2171 #endif
2172 case MSR_IA32_TSC:
2173 env->tsc = msrs[i].data;
2174 break;
2175 case MSR_TSC_AUX:
2176 env->tsc_aux = msrs[i].data;
2177 break;
2178 case MSR_TSC_ADJUST:
2179 env->tsc_adjust = msrs[i].data;
2180 break;
2181 case MSR_IA32_TSCDEADLINE:
2182 env->tsc_deadline = msrs[i].data;
2183 break;
2184 case MSR_VM_HSAVE_PA:
2185 env->vm_hsave = msrs[i].data;
2186 break;
2187 case MSR_KVM_SYSTEM_TIME:
2188 env->system_time_msr = msrs[i].data;
2189 break;
2190 case MSR_KVM_WALL_CLOCK:
2191 env->wall_clock_msr = msrs[i].data;
2192 break;
2193 case MSR_MCG_STATUS:
2194 env->mcg_status = msrs[i].data;
2195 break;
2196 case MSR_MCG_CTL:
2197 env->mcg_ctl = msrs[i].data;
2198 break;
2199 case MSR_MCG_EXT_CTL:
2200 env->mcg_ext_ctl = msrs[i].data;
2201 break;
2202 case MSR_IA32_MISC_ENABLE:
2203 env->msr_ia32_misc_enable = msrs[i].data;
2204 break;
2205 case MSR_IA32_SMBASE:
2206 env->smbase = msrs[i].data;
2207 break;
2208 case MSR_IA32_FEATURE_CONTROL:
2209 env->msr_ia32_feature_control = msrs[i].data;
2210 break;
2211 case MSR_IA32_BNDCFGS:
2212 env->msr_bndcfgs = msrs[i].data;
2213 break;
2214 case MSR_IA32_XSS:
2215 env->xss = msrs[i].data;
2216 break;
2217 default:
2218 if (msrs[i].index >= MSR_MC0_CTL &&
2219 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2220 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2221 }
2222 break;
2223 case MSR_KVM_ASYNC_PF_EN:
2224 env->async_pf_en_msr = msrs[i].data;
2225 break;
2226 case MSR_KVM_PV_EOI_EN:
2227 env->pv_eoi_en_msr = msrs[i].data;
2228 break;
2229 case MSR_KVM_STEAL_TIME:
2230 env->steal_time_msr = msrs[i].data;
2231 break;
2232 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2233 env->msr_fixed_ctr_ctrl = msrs[i].data;
2234 break;
2235 case MSR_CORE_PERF_GLOBAL_CTRL:
2236 env->msr_global_ctrl = msrs[i].data;
2237 break;
2238 case MSR_CORE_PERF_GLOBAL_STATUS:
2239 env->msr_global_status = msrs[i].data;
2240 break;
2241 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2242 env->msr_global_ovf_ctrl = msrs[i].data;
2243 break;
2244 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2245 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2246 break;
2247 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2248 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2249 break;
2250 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2251 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2252 break;
2253 case HV_X64_MSR_HYPERCALL:
2254 env->msr_hv_hypercall = msrs[i].data;
2255 break;
2256 case HV_X64_MSR_GUEST_OS_ID:
2257 env->msr_hv_guest_os_id = msrs[i].data;
2258 break;
2259 case HV_X64_MSR_APIC_ASSIST_PAGE:
2260 env->msr_hv_vapic = msrs[i].data;
2261 break;
2262 case HV_X64_MSR_REFERENCE_TSC:
2263 env->msr_hv_tsc = msrs[i].data;
2264 break;
2265 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2266 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2267 break;
2268 case HV_X64_MSR_VP_RUNTIME:
2269 env->msr_hv_runtime = msrs[i].data;
2270 break;
2271 case HV_X64_MSR_SCONTROL:
2272 env->msr_hv_synic_control = msrs[i].data;
2273 break;
2274 case HV_X64_MSR_SIEFP:
2275 env->msr_hv_synic_evt_page = msrs[i].data;
2276 break;
2277 case HV_X64_MSR_SIMP:
2278 env->msr_hv_synic_msg_page = msrs[i].data;
2279 break;
2280 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2281 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2282 break;
2283 case HV_X64_MSR_STIMER0_CONFIG:
2284 case HV_X64_MSR_STIMER1_CONFIG:
2285 case HV_X64_MSR_STIMER2_CONFIG:
2286 case HV_X64_MSR_STIMER3_CONFIG:
2287 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2288 msrs[i].data;
2289 break;
2290 case HV_X64_MSR_STIMER0_COUNT:
2291 case HV_X64_MSR_STIMER1_COUNT:
2292 case HV_X64_MSR_STIMER2_COUNT:
2293 case HV_X64_MSR_STIMER3_COUNT:
2294 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2295 msrs[i].data;
2296 break;
2297 case MSR_MTRRdefType:
2298 env->mtrr_deftype = msrs[i].data;
2299 break;
2300 case MSR_MTRRfix64K_00000:
2301 env->mtrr_fixed[0] = msrs[i].data;
2302 break;
2303 case MSR_MTRRfix16K_80000:
2304 env->mtrr_fixed[1] = msrs[i].data;
2305 break;
2306 case MSR_MTRRfix16K_A0000:
2307 env->mtrr_fixed[2] = msrs[i].data;
2308 break;
2309 case MSR_MTRRfix4K_C0000:
2310 env->mtrr_fixed[3] = msrs[i].data;
2311 break;
2312 case MSR_MTRRfix4K_C8000:
2313 env->mtrr_fixed[4] = msrs[i].data;
2314 break;
2315 case MSR_MTRRfix4K_D0000:
2316 env->mtrr_fixed[5] = msrs[i].data;
2317 break;
2318 case MSR_MTRRfix4K_D8000:
2319 env->mtrr_fixed[6] = msrs[i].data;
2320 break;
2321 case MSR_MTRRfix4K_E0000:
2322 env->mtrr_fixed[7] = msrs[i].data;
2323 break;
2324 case MSR_MTRRfix4K_E8000:
2325 env->mtrr_fixed[8] = msrs[i].data;
2326 break;
2327 case MSR_MTRRfix4K_F0000:
2328 env->mtrr_fixed[9] = msrs[i].data;
2329 break;
2330 case MSR_MTRRfix4K_F8000:
2331 env->mtrr_fixed[10] = msrs[i].data;
2332 break;
2333 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2334 if (index & 1) {
2335 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2336 mtrr_top_bits;
2337 } else {
2338 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2339 }
2340 break;
2341 case MSR_IA32_SPEC_CTRL:
2342 env->spec_ctrl = msrs[i].data;
2343 break;
2344 }
2345 }
2346
2347 return 0;
2348 }
2349
2350 static int kvm_put_mp_state(X86CPU *cpu)
2351 {
2352 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2353
2354 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2355 }
2356
2357 static int kvm_get_mp_state(X86CPU *cpu)
2358 {
2359 CPUState *cs = CPU(cpu);
2360 CPUX86State *env = &cpu->env;
2361 struct kvm_mp_state mp_state;
2362 int ret;
2363
2364 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2365 if (ret < 0) {
2366 return ret;
2367 }
2368 env->mp_state = mp_state.mp_state;
2369 if (kvm_irqchip_in_kernel()) {
2370 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2371 }
2372 return 0;
2373 }
2374
2375 static int kvm_get_apic(X86CPU *cpu)
2376 {
2377 DeviceState *apic = cpu->apic_state;
2378 struct kvm_lapic_state kapic;
2379 int ret;
2380
2381 if (apic && kvm_irqchip_in_kernel()) {
2382 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2383 if (ret < 0) {
2384 return ret;
2385 }
2386
2387 kvm_get_apic_state(apic, &kapic);
2388 }
2389 return 0;
2390 }
2391
2392 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2393 {
2394 CPUState *cs = CPU(cpu);
2395 CPUX86State *env = &cpu->env;
2396 struct kvm_vcpu_events events = {};
2397
2398 if (!kvm_has_vcpu_events()) {
2399 return 0;
2400 }
2401
2402 events.exception.injected = (env->exception_injected >= 0);
2403 events.exception.nr = env->exception_injected;
2404 events.exception.has_error_code = env->has_error_code;
2405 events.exception.error_code = env->error_code;
2406 events.exception.pad = 0;
2407
2408 events.interrupt.injected = (env->interrupt_injected >= 0);
2409 events.interrupt.nr = env->interrupt_injected;
2410 events.interrupt.soft = env->soft_interrupt;
2411
2412 events.nmi.injected = env->nmi_injected;
2413 events.nmi.pending = env->nmi_pending;
2414 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2415 events.nmi.pad = 0;
2416
2417 events.sipi_vector = env->sipi_vector;
2418 events.flags = 0;
2419
2420 if (has_msr_smbase) {
2421 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2422 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2423 if (kvm_irqchip_in_kernel()) {
2424 /* As soon as these are moved to the kernel, remove them
2425 * from cs->interrupt_request.
2426 */
2427 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2428 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2429 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2430 } else {
2431 /* Keep these in cs->interrupt_request. */
2432 events.smi.pending = 0;
2433 events.smi.latched_init = 0;
2434 }
2435 /* Stop SMI delivery on old machine types to avoid a reboot
2436 * on an inward migration of an old VM.
2437 */
2438 if (!cpu->kvm_no_smi_migration) {
2439 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2440 }
2441 }
2442
2443 if (level >= KVM_PUT_RESET_STATE) {
2444 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2445 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2446 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2447 }
2448 }
2449
2450 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2451 }
2452
2453 static int kvm_get_vcpu_events(X86CPU *cpu)
2454 {
2455 CPUX86State *env = &cpu->env;
2456 struct kvm_vcpu_events events;
2457 int ret;
2458
2459 if (!kvm_has_vcpu_events()) {
2460 return 0;
2461 }
2462
2463 memset(&events, 0, sizeof(events));
2464 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2465 if (ret < 0) {
2466 return ret;
2467 }
2468 env->exception_injected =
2469 events.exception.injected ? events.exception.nr : -1;
2470 env->has_error_code = events.exception.has_error_code;
2471 env->error_code = events.exception.error_code;
2472
2473 env->interrupt_injected =
2474 events.interrupt.injected ? events.interrupt.nr : -1;
2475 env->soft_interrupt = events.interrupt.soft;
2476
2477 env->nmi_injected = events.nmi.injected;
2478 env->nmi_pending = events.nmi.pending;
2479 if (events.nmi.masked) {
2480 env->hflags2 |= HF2_NMI_MASK;
2481 } else {
2482 env->hflags2 &= ~HF2_NMI_MASK;
2483 }
2484
2485 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2486 if (events.smi.smm) {
2487 env->hflags |= HF_SMM_MASK;
2488 } else {
2489 env->hflags &= ~HF_SMM_MASK;
2490 }
2491 if (events.smi.pending) {
2492 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2493 } else {
2494 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2495 }
2496 if (events.smi.smm_inside_nmi) {
2497 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2498 } else {
2499 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2500 }
2501 if (events.smi.latched_init) {
2502 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2503 } else {
2504 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2505 }
2506 }
2507
2508 env->sipi_vector = events.sipi_vector;
2509
2510 return 0;
2511 }
2512
2513 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2514 {
2515 CPUState *cs = CPU(cpu);
2516 CPUX86State *env = &cpu->env;
2517 int ret = 0;
2518 unsigned long reinject_trap = 0;
2519
2520 if (!kvm_has_vcpu_events()) {
2521 if (env->exception_injected == 1) {
2522 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2523 } else if (env->exception_injected == 3) {
2524 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2525 }
2526 env->exception_injected = -1;
2527 }
2528
2529 /*
2530 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2531 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2532 * by updating the debug state once again if single-stepping is on.
2533 * Another reason to call kvm_update_guest_debug here is a pending debug
2534 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2535 * reinject them via SET_GUEST_DEBUG.
2536 */
2537 if (reinject_trap ||
2538 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2539 ret = kvm_update_guest_debug(cs, reinject_trap);
2540 }
2541 return ret;
2542 }
2543
2544 static int kvm_put_debugregs(X86CPU *cpu)
2545 {
2546 CPUX86State *env = &cpu->env;
2547 struct kvm_debugregs dbgregs;
2548 int i;
2549
2550 if (!kvm_has_debugregs()) {
2551 return 0;
2552 }
2553
2554 for (i = 0; i < 4; i++) {
2555 dbgregs.db[i] = env->dr[i];
2556 }
2557 dbgregs.dr6 = env->dr[6];
2558 dbgregs.dr7 = env->dr[7];
2559 dbgregs.flags = 0;
2560
2561 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2562 }
2563
2564 static int kvm_get_debugregs(X86CPU *cpu)
2565 {
2566 CPUX86State *env = &cpu->env;
2567 struct kvm_debugregs dbgregs;
2568 int i, ret;
2569
2570 if (!kvm_has_debugregs()) {
2571 return 0;
2572 }
2573
2574 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2575 if (ret < 0) {
2576 return ret;
2577 }
2578 for (i = 0; i < 4; i++) {
2579 env->dr[i] = dbgregs.db[i];
2580 }
2581 env->dr[4] = env->dr[6] = dbgregs.dr6;
2582 env->dr[5] = env->dr[7] = dbgregs.dr7;
2583
2584 return 0;
2585 }
2586
2587 int kvm_arch_put_registers(CPUState *cpu, int level)
2588 {
2589 X86CPU *x86_cpu = X86_CPU(cpu);
2590 int ret;
2591
2592 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2593
2594 if (level >= KVM_PUT_RESET_STATE) {
2595 ret = kvm_put_msr_feature_control(x86_cpu);
2596 if (ret < 0) {
2597 return ret;
2598 }
2599 }
2600
2601 if (level == KVM_PUT_FULL_STATE) {
2602 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2603 * because TSC frequency mismatch shouldn't abort migration,
2604 * unless the user explicitly asked for a more strict TSC
2605 * setting (e.g. using an explicit "tsc-freq" option).
2606 */
2607 kvm_arch_set_tsc_khz(cpu);
2608 }
2609
2610 ret = kvm_getput_regs(x86_cpu, 1);
2611 if (ret < 0) {
2612 return ret;
2613 }
2614 ret = kvm_put_xsave(x86_cpu);
2615 if (ret < 0) {
2616 return ret;
2617 }
2618 ret = kvm_put_xcrs(x86_cpu);
2619 if (ret < 0) {
2620 return ret;
2621 }
2622 ret = kvm_put_sregs(x86_cpu);
2623 if (ret < 0) {
2624 return ret;
2625 }
2626 /* must be before kvm_put_msrs */
2627 ret = kvm_inject_mce_oldstyle(x86_cpu);
2628 if (ret < 0) {
2629 return ret;
2630 }
2631 ret = kvm_put_msrs(x86_cpu, level);
2632 if (ret < 0) {
2633 return ret;
2634 }
2635 ret = kvm_put_vcpu_events(x86_cpu, level);
2636 if (ret < 0) {
2637 return ret;
2638 }
2639 if (level >= KVM_PUT_RESET_STATE) {
2640 ret = kvm_put_mp_state(x86_cpu);
2641 if (ret < 0) {
2642 return ret;
2643 }
2644 }
2645
2646 ret = kvm_put_tscdeadline_msr(x86_cpu);
2647 if (ret < 0) {
2648 return ret;
2649 }
2650 ret = kvm_put_debugregs(x86_cpu);
2651 if (ret < 0) {
2652 return ret;
2653 }
2654 /* must be last */
2655 ret = kvm_guest_debug_workarounds(x86_cpu);
2656 if (ret < 0) {
2657 return ret;
2658 }
2659 return 0;
2660 }
2661
2662 int kvm_arch_get_registers(CPUState *cs)
2663 {
2664 X86CPU *cpu = X86_CPU(cs);
2665 int ret;
2666
2667 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2668
2669 ret = kvm_get_vcpu_events(cpu);
2670 if (ret < 0) {
2671 goto out;
2672 }
2673 /*
2674 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2675 * KVM_GET_REGS and KVM_GET_SREGS.
2676 */
2677 ret = kvm_get_mp_state(cpu);
2678 if (ret < 0) {
2679 goto out;
2680 }
2681 ret = kvm_getput_regs(cpu, 0);
2682 if (ret < 0) {
2683 goto out;
2684 }
2685 ret = kvm_get_xsave(cpu);
2686 if (ret < 0) {
2687 goto out;
2688 }
2689 ret = kvm_get_xcrs(cpu);
2690 if (ret < 0) {
2691 goto out;
2692 }
2693 ret = kvm_get_sregs(cpu);
2694 if (ret < 0) {
2695 goto out;
2696 }
2697 ret = kvm_get_msrs(cpu);
2698 if (ret < 0) {
2699 goto out;
2700 }
2701 ret = kvm_get_apic(cpu);
2702 if (ret < 0) {
2703 goto out;
2704 }
2705 ret = kvm_get_debugregs(cpu);
2706 if (ret < 0) {
2707 goto out;
2708 }
2709 ret = 0;
2710 out:
2711 cpu_sync_bndcs_hflags(&cpu->env);
2712 return ret;
2713 }
2714
2715 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2716 {
2717 X86CPU *x86_cpu = X86_CPU(cpu);
2718 CPUX86State *env = &x86_cpu->env;
2719 int ret;
2720
2721 /* Inject NMI */
2722 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2723 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2724 qemu_mutex_lock_iothread();
2725 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2726 qemu_mutex_unlock_iothread();
2727 DPRINTF("injected NMI\n");
2728 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2729 if (ret < 0) {
2730 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2731 strerror(-ret));
2732 }
2733 }
2734 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2735 qemu_mutex_lock_iothread();
2736 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2737 qemu_mutex_unlock_iothread();
2738 DPRINTF("injected SMI\n");
2739 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2740 if (ret < 0) {
2741 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2742 strerror(-ret));
2743 }
2744 }
2745 }
2746
2747 if (!kvm_pic_in_kernel()) {
2748 qemu_mutex_lock_iothread();
2749 }
2750
2751 /* Force the VCPU out of its inner loop to process any INIT requests
2752 * or (for userspace APIC, but it is cheap to combine the checks here)
2753 * pending TPR access reports.
2754 */
2755 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2756 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2757 !(env->hflags & HF_SMM_MASK)) {
2758 cpu->exit_request = 1;
2759 }
2760 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2761 cpu->exit_request = 1;
2762 }
2763 }
2764
2765 if (!kvm_pic_in_kernel()) {
2766 /* Try to inject an interrupt if the guest can accept it */
2767 if (run->ready_for_interrupt_injection &&
2768 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2769 (env->eflags & IF_MASK)) {
2770 int irq;
2771
2772 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2773 irq = cpu_get_pic_interrupt(env);
2774 if (irq >= 0) {
2775 struct kvm_interrupt intr;
2776
2777 intr.irq = irq;
2778 DPRINTF("injected interrupt %d\n", irq);
2779 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2780 if (ret < 0) {
2781 fprintf(stderr,
2782 "KVM: injection failed, interrupt lost (%s)\n",
2783 strerror(-ret));
2784 }
2785 }
2786 }
2787
2788 /* If we have an interrupt but the guest is not ready to receive an
2789 * interrupt, request an interrupt window exit. This will
2790 * cause a return to userspace as soon as the guest is ready to
2791 * receive interrupts. */
2792 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2793 run->request_interrupt_window = 1;
2794 } else {
2795 run->request_interrupt_window = 0;
2796 }
2797
2798 DPRINTF("setting tpr\n");
2799 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2800
2801 qemu_mutex_unlock_iothread();
2802 }
2803 }
2804
2805 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2806 {
2807 X86CPU *x86_cpu = X86_CPU(cpu);
2808 CPUX86State *env = &x86_cpu->env;
2809
2810 if (run->flags & KVM_RUN_X86_SMM) {
2811 env->hflags |= HF_SMM_MASK;
2812 } else {
2813 env->hflags &= ~HF_SMM_MASK;
2814 }
2815 if (run->if_flag) {
2816 env->eflags |= IF_MASK;
2817 } else {
2818 env->eflags &= ~IF_MASK;
2819 }
2820
2821 /* We need to protect the apic state against concurrent accesses from
2822 * different threads in case the userspace irqchip is used. */
2823 if (!kvm_irqchip_in_kernel()) {
2824 qemu_mutex_lock_iothread();
2825 }
2826 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2827 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2828 if (!kvm_irqchip_in_kernel()) {
2829 qemu_mutex_unlock_iothread();
2830 }
2831 return cpu_get_mem_attrs(env);
2832 }
2833
2834 int kvm_arch_process_async_events(CPUState *cs)
2835 {
2836 X86CPU *cpu = X86_CPU(cs);
2837 CPUX86State *env = &cpu->env;
2838
2839 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2840 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2841 assert(env->mcg_cap);
2842
2843 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2844
2845 kvm_cpu_synchronize_state(cs);
2846
2847 if (env->exception_injected == EXCP08_DBLE) {
2848 /* this means triple fault */
2849 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2850 cs->exit_request = 1;
2851 return 0;
2852 }
2853 env->exception_injected = EXCP12_MCHK;
2854 env->has_error_code = 0;
2855
2856 cs->halted = 0;
2857 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2858 env->mp_state = KVM_MP_STATE_RUNNABLE;
2859 }
2860 }
2861
2862 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2863 !(env->hflags & HF_SMM_MASK)) {
2864 kvm_cpu_synchronize_state(cs);
2865 do_cpu_init(cpu);
2866 }
2867
2868 if (kvm_irqchip_in_kernel()) {
2869 return 0;
2870 }
2871
2872 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2873 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2874 apic_poll_irq(cpu->apic_state);
2875 }
2876 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2877 (env->eflags & IF_MASK)) ||
2878 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2879 cs->halted = 0;
2880 }
2881 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2882 kvm_cpu_synchronize_state(cs);
2883 do_cpu_sipi(cpu);
2884 }
2885 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2886 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2887 kvm_cpu_synchronize_state(cs);
2888 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2889 env->tpr_access_type);
2890 }
2891
2892 return cs->halted;
2893 }
2894
2895 static int kvm_handle_halt(X86CPU *cpu)
2896 {
2897 CPUState *cs = CPU(cpu);
2898 CPUX86State *env = &cpu->env;
2899
2900 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2901 (env->eflags & IF_MASK)) &&
2902 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2903 cs->halted = 1;
2904 return EXCP_HLT;
2905 }
2906
2907 return 0;
2908 }
2909
2910 static int kvm_handle_tpr_access(X86CPU *cpu)
2911 {
2912 CPUState *cs = CPU(cpu);
2913 struct kvm_run *run = cs->kvm_run;
2914
2915 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2916 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2917 : TPR_ACCESS_READ);
2918 return 1;
2919 }
2920
2921 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2922 {
2923 static const uint8_t int3 = 0xcc;
2924
2925 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2926 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2927 return -EINVAL;
2928 }
2929 return 0;
2930 }
2931
2932 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2933 {
2934 uint8_t int3;
2935
2936 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2937 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2938 return -EINVAL;
2939 }
2940 return 0;
2941 }
2942
2943 static struct {
2944 target_ulong addr;
2945 int len;
2946 int type;
2947 } hw_breakpoint[4];
2948
2949 static int nb_hw_breakpoint;
2950
2951 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2952 {
2953 int n;
2954
2955 for (n = 0; n < nb_hw_breakpoint; n++) {
2956 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2957 (hw_breakpoint[n].len == len || len == -1)) {
2958 return n;
2959 }
2960 }
2961 return -1;
2962 }
2963
2964 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2965 target_ulong len, int type)
2966 {
2967 switch (type) {
2968 case GDB_BREAKPOINT_HW:
2969 len = 1;
2970 break;
2971 case GDB_WATCHPOINT_WRITE:
2972 case GDB_WATCHPOINT_ACCESS:
2973 switch (len) {
2974 case 1:
2975 break;
2976 case 2:
2977 case 4:
2978 case 8:
2979 if (addr & (len - 1)) {
2980 return -EINVAL;
2981 }
2982 break;
2983 default:
2984 return -EINVAL;
2985 }
2986 break;
2987 default:
2988 return -ENOSYS;
2989 }
2990
2991 if (nb_hw_breakpoint == 4) {
2992 return -ENOBUFS;
2993 }
2994 if (find_hw_breakpoint(addr, len, type) >= 0) {
2995 return -EEXIST;
2996 }
2997 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2998 hw_breakpoint[nb_hw_breakpoint].len = len;
2999 hw_breakpoint[nb_hw_breakpoint].type = type;
3000 nb_hw_breakpoint++;
3001
3002 return 0;
3003 }
3004
3005 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3006 target_ulong len, int type)
3007 {
3008 int n;
3009
3010 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3011 if (n < 0) {
3012 return -ENOENT;
3013 }
3014 nb_hw_breakpoint--;
3015 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3016
3017 return 0;
3018 }
3019
3020 void kvm_arch_remove_all_hw_breakpoints(void)
3021 {
3022 nb_hw_breakpoint = 0;
3023 }
3024
3025 static CPUWatchpoint hw_watchpoint;
3026
3027 static int kvm_handle_debug(X86CPU *cpu,
3028 struct kvm_debug_exit_arch *arch_info)
3029 {
3030 CPUState *cs = CPU(cpu);
3031 CPUX86State *env = &cpu->env;
3032 int ret = 0;
3033 int n;
3034
3035 if (arch_info->exception == 1) {
3036 if (arch_info->dr6 & (1 << 14)) {
3037 if (cs->singlestep_enabled) {
3038 ret = EXCP_DEBUG;
3039 }
3040 } else {
3041 for (n = 0; n < 4; n++) {
3042 if (arch_info->dr6 & (1 << n)) {
3043 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3044 case 0x0:
3045 ret = EXCP_DEBUG;
3046 break;
3047 case 0x1:
3048 ret = EXCP_DEBUG;
3049 cs->watchpoint_hit = &hw_watchpoint;
3050 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3051 hw_watchpoint.flags = BP_MEM_WRITE;
3052 break;
3053 case 0x3:
3054 ret = EXCP_DEBUG;
3055 cs->watchpoint_hit = &hw_watchpoint;
3056 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3057 hw_watchpoint.flags = BP_MEM_ACCESS;
3058 break;
3059 }
3060 }
3061 }
3062 }
3063 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3064 ret = EXCP_DEBUG;
3065 }
3066 if (ret == 0) {
3067 cpu_synchronize_state(cs);
3068 assert(env->exception_injected == -1);
3069
3070 /* pass to guest */
3071 env->exception_injected = arch_info->exception;
3072 env->has_error_code = 0;
3073 }
3074
3075 return ret;
3076 }
3077
3078 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3079 {
3080 const uint8_t type_code[] = {
3081 [GDB_BREAKPOINT_HW] = 0x0,
3082 [GDB_WATCHPOINT_WRITE] = 0x1,
3083 [GDB_WATCHPOINT_ACCESS] = 0x3
3084 };
3085 const uint8_t len_code[] = {
3086 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3087 };
3088 int n;
3089
3090 if (kvm_sw_breakpoints_active(cpu)) {
3091 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3092 }
3093 if (nb_hw_breakpoint > 0) {
3094 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3095 dbg->arch.debugreg[7] = 0x0600;
3096 for (n = 0; n < nb_hw_breakpoint; n++) {
3097 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3098 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3099 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3100 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3101 }
3102 }
3103 }
3104
3105 static bool host_supports_vmx(void)
3106 {
3107 uint32_t ecx, unused;
3108
3109 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3110 return ecx & CPUID_EXT_VMX;
3111 }
3112
3113 #define VMX_INVALID_GUEST_STATE 0x80000021
3114
3115 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3116 {
3117 X86CPU *cpu = X86_CPU(cs);
3118 uint64_t code;
3119 int ret;
3120
3121 switch (run->exit_reason) {
3122 case KVM_EXIT_HLT:
3123 DPRINTF("handle_hlt\n");
3124 qemu_mutex_lock_iothread();
3125 ret = kvm_handle_halt(cpu);
3126 qemu_mutex_unlock_iothread();
3127 break;
3128 case KVM_EXIT_SET_TPR:
3129 ret = 0;
3130 break;
3131 case KVM_EXIT_TPR_ACCESS:
3132 qemu_mutex_lock_iothread();
3133 ret = kvm_handle_tpr_access(cpu);
3134 qemu_mutex_unlock_iothread();
3135 break;
3136 case KVM_EXIT_FAIL_ENTRY:
3137 code = run->fail_entry.hardware_entry_failure_reason;
3138 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3139 code);
3140 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3141 fprintf(stderr,
3142 "\nIf you're running a guest on an Intel machine without "
3143 "unrestricted mode\n"
3144 "support, the failure can be most likely due to the guest "
3145 "entering an invalid\n"
3146 "state for Intel VT. For example, the guest maybe running "
3147 "in big real mode\n"
3148 "which is not supported on less recent Intel processors."
3149 "\n\n");
3150 }
3151 ret = -1;
3152 break;
3153 case KVM_EXIT_EXCEPTION:
3154 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3155 run->ex.exception, run->ex.error_code);
3156 ret = -1;
3157 break;
3158 case KVM_EXIT_DEBUG:
3159 DPRINTF("kvm_exit_debug\n");
3160 qemu_mutex_lock_iothread();
3161 ret = kvm_handle_debug(cpu, &run->debug.arch);
3162 qemu_mutex_unlock_iothread();
3163 break;
3164 case KVM_EXIT_HYPERV:
3165 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3166 break;
3167 case KVM_EXIT_IOAPIC_EOI:
3168 ioapic_eoi_broadcast(run->eoi.vector);
3169 ret = 0;
3170 break;
3171 default:
3172 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3173 ret = -1;
3174 break;
3175 }
3176
3177 return ret;
3178 }
3179
3180 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3181 {
3182 X86CPU *cpu = X86_CPU(cs);
3183 CPUX86State *env = &cpu->env;
3184
3185 kvm_cpu_synchronize_state(cs);
3186 return !(env->cr[0] & CR0_PE_MASK) ||
3187 ((env->segs[R_CS].selector & 3) != 3);
3188 }
3189
3190 void kvm_arch_init_irq_routing(KVMState *s)
3191 {
3192 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3193 /* If kernel can't do irq routing, interrupt source
3194 * override 0->2 cannot be set up as required by HPET.
3195 * So we have to disable it.
3196 */
3197 no_hpet = 1;
3198 }
3199 /* We know at this point that we're using the in-kernel
3200 * irqchip, so we can use irqfds, and on x86 we know
3201 * we can use msi via irqfd and GSI routing.
3202 */
3203 kvm_msi_via_irqfd_allowed = true;
3204 kvm_gsi_routing_allowed = true;
3205
3206 if (kvm_irqchip_is_split()) {
3207 int i;
3208
3209 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3210 MSI routes for signaling interrupts to the local apics. */
3211 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3212 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3213 error_report("Could not enable split IRQ mode.");
3214 exit(1);
3215 }
3216 }
3217 }
3218 }
3219
3220 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3221 {
3222 int ret;
3223 if (machine_kernel_irqchip_split(ms)) {
3224 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3225 if (ret) {
3226 error_report("Could not enable split irqchip mode: %s",
3227 strerror(-ret));
3228 exit(1);
3229 } else {
3230 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3231 kvm_split_irqchip = true;
3232 return 1;
3233 }
3234 } else {
3235 return 0;
3236 }
3237 }
3238
3239 /* Classic KVM device assignment interface. Will remain x86 only. */
3240 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3241 uint32_t flags, uint32_t *dev_id)
3242 {
3243 struct kvm_assigned_pci_dev dev_data = {
3244 .segnr = dev_addr->domain,
3245 .busnr = dev_addr->bus,
3246 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3247 .flags = flags,
3248 };
3249 int ret;
3250
3251 dev_data.assigned_dev_id =
3252 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3253
3254 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3255 if (ret < 0) {
3256 return ret;
3257 }
3258
3259 *dev_id = dev_data.assigned_dev_id;
3260
3261 return 0;
3262 }
3263
3264 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3265 {
3266 struct kvm_assigned_pci_dev dev_data = {
3267 .assigned_dev_id = dev_id,
3268 };
3269
3270 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3271 }
3272
3273 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3274 uint32_t irq_type, uint32_t guest_irq)
3275 {
3276 struct kvm_assigned_irq assigned_irq = {
3277 .assigned_dev_id = dev_id,
3278 .guest_irq = guest_irq,
3279 .flags = irq_type,
3280 };
3281
3282 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3283 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3284 } else {
3285 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3286 }
3287 }
3288
3289 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3290 uint32_t guest_irq)
3291 {
3292 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3293 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3294
3295 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3296 }
3297
3298 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3299 {
3300 struct kvm_assigned_pci_dev dev_data = {
3301 .assigned_dev_id = dev_id,
3302 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3303 };
3304
3305 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3306 }
3307
3308 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3309 uint32_t type)
3310 {
3311 struct kvm_assigned_irq assigned_irq = {
3312 .assigned_dev_id = dev_id,
3313 .flags = type,
3314 };
3315
3316 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3317 }
3318
3319 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3320 {
3321 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3322 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3323 }
3324
3325 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3326 {
3327 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3328 KVM_DEV_IRQ_GUEST_MSI, virq);
3329 }
3330
3331 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3332 {
3333 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3334 KVM_DEV_IRQ_HOST_MSI);
3335 }
3336
3337 bool kvm_device_msix_supported(KVMState *s)
3338 {
3339 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3340 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3341 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3342 }
3343
3344 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3345 uint32_t nr_vectors)
3346 {
3347 struct kvm_assigned_msix_nr msix_nr = {
3348 .assigned_dev_id = dev_id,
3349 .entry_nr = nr_vectors,
3350 };
3351
3352 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3353 }
3354
3355 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3356 int virq)
3357 {
3358 struct kvm_assigned_msix_entry msix_entry = {
3359 .assigned_dev_id = dev_id,
3360 .gsi = virq,
3361 .entry = vector,
3362 };
3363
3364 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3365 }
3366
3367 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3368 {
3369 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3370 KVM_DEV_IRQ_GUEST_MSIX, 0);
3371 }
3372
3373 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3374 {
3375 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3376 KVM_DEV_IRQ_HOST_MSIX);
3377 }
3378
3379 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3380 uint64_t address, uint32_t data, PCIDevice *dev)
3381 {
3382 X86IOMMUState *iommu = x86_iommu_get_default();
3383
3384 if (iommu) {
3385 int ret;
3386 MSIMessage src, dst;
3387 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3388
3389 src.address = route->u.msi.address_hi;
3390 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3391 src.address |= route->u.msi.address_lo;
3392 src.data = route->u.msi.data;
3393
3394 ret = class->int_remap(iommu, &src, &dst, dev ? \
3395 pci_requester_id(dev) : \
3396 X86_IOMMU_SID_INVALID);
3397 if (ret) {
3398 trace_kvm_x86_fixup_msi_error(route->gsi);
3399 return 1;
3400 }
3401
3402 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3403 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3404 route->u.msi.data = dst.data;
3405 }
3406
3407 return 0;
3408 }
3409
3410 typedef struct MSIRouteEntry MSIRouteEntry;
3411
3412 struct MSIRouteEntry {
3413 PCIDevice *dev; /* Device pointer */
3414 int vector; /* MSI/MSIX vector index */
3415 int virq; /* Virtual IRQ index */
3416 QLIST_ENTRY(MSIRouteEntry) list;
3417 };
3418
3419 /* List of used GSI routes */
3420 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3421 QLIST_HEAD_INITIALIZER(msi_route_list);
3422
3423 static void kvm_update_msi_routes_all(void *private, bool global,
3424 uint32_t index, uint32_t mask)
3425 {
3426 int cnt = 0;
3427 MSIRouteEntry *entry;
3428 MSIMessage msg;
3429 PCIDevice *dev;
3430
3431 /* TODO: explicit route update */
3432 QLIST_FOREACH(entry, &msi_route_list, list) {
3433 cnt++;
3434 dev = entry->dev;
3435 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3436 continue;
3437 }
3438 msg = pci_get_msi_message(dev, entry->vector);
3439 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3440 }
3441 kvm_irqchip_commit_routes(kvm_state);
3442 trace_kvm_x86_update_msi_routes(cnt);
3443 }
3444
3445 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3446 int vector, PCIDevice *dev)
3447 {
3448 static bool notify_list_inited = false;
3449 MSIRouteEntry *entry;
3450
3451 if (!dev) {
3452 /* These are (possibly) IOAPIC routes only used for split
3453 * kernel irqchip mode, while what we are housekeeping are
3454 * PCI devices only. */
3455 return 0;
3456 }
3457
3458 entry = g_new0(MSIRouteEntry, 1);
3459 entry->dev = dev;
3460 entry->vector = vector;
3461 entry->virq = route->gsi;
3462 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3463
3464 trace_kvm_x86_add_msi_route(route->gsi);
3465
3466 if (!notify_list_inited) {
3467 /* For the first time we do add route, add ourselves into
3468 * IOMMU's IEC notify list if needed. */
3469 X86IOMMUState *iommu = x86_iommu_get_default();
3470 if (iommu) {
3471 x86_iommu_iec_register_notifier(iommu,
3472 kvm_update_msi_routes_all,
3473 NULL);
3474 }
3475 notify_list_inited = true;
3476 }
3477 return 0;
3478 }
3479
3480 int kvm_arch_release_virq_post(int virq)
3481 {
3482 MSIRouteEntry *entry, *next;
3483 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3484 if (entry->virq == virq) {
3485 trace_kvm_x86_remove_msi_route(virq);
3486 QLIST_REMOVE(entry, list);
3487 g_free(entry);
3488 break;
3489 }
3490 }
3491 return 0;
3492 }
3493
3494 int kvm_arch_msi_data_to_gsi(uint32_t data)
3495 {
3496 abort();
3497 }
AR7 emulation for QEMU