target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "hw/sh4/sh_intc.h"
  30 #endif
  31
  32 #if defined(CONFIG_USER_ONLY)
  33
  34 void superh_cpu_do_interrupt(CPUState *cs)
  35 {
  36     cs->exception_index = -1;
  37 }
  38
  39 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  40                                 int mmu_idx)
  41 {
  42     SuperHCPU *cpu = SUPERH_CPU(cs);
  43     CPUSH4State *env = &cpu->env;
  44
  45     env->tea = address;
  46     cs->exception_index = -1;
  47     switch (rw) {
  48     case 0:
  49         cs->exception_index = 0x0a0;
  50         break;
  51     case 1:
  52         cs->exception_index = 0x0c0;
  53         break;
  54     case 2:
  55         cs->exception_index = 0x0a0;
  56         break;
  57     }
  58     return 1;
  59 }
  60
  61 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  62 {
  63     /* For user mode, only U0 area is cachable. */
  64     return !(addr & 0x80000000);
  65 }
  66
  67 #else /* !CONFIG_USER_ONLY */
  68
  69 #define MMU_OK                   0
  70 #define MMU_ITLB_MISS            (-1)
  71 #define MMU_ITLB_MULTIPLE        (-2)
  72 #define MMU_ITLB_VIOLATION       (-3)
  73 #define MMU_DTLB_MISS_READ       (-4)
  74 #define MMU_DTLB_MISS_WRITE      (-5)
  75 #define MMU_DTLB_INITIAL_WRITE   (-6)
  76 #define MMU_DTLB_VIOLATION_READ  (-7)
  77 #define MMU_DTLB_VIOLATION_WRITE (-8)
  78 #define MMU_DTLB_MULTIPLE        (-9)
  79 #define MMU_DTLB_MISS            (-10)
  80 #define MMU_IADDR_ERROR          (-11)
  81 #define MMU_DADDR_ERROR_READ     (-12)
  82 #define MMU_DADDR_ERROR_WRITE    (-13)
  83
  84 void superh_cpu_do_interrupt(CPUState *cs)
  85 {
  86     SuperHCPU *cpu = SUPERH_CPU(cs);
  87     CPUSH4State *env = &cpu->env;
  88     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
  89     int do_exp, irq_vector = cs->exception_index;
  90
  91     /* prioritize exceptions over interrupts */
  92
  93     do_exp = cs->exception_index != -1;
  94     do_irq = do_irq && (cs->exception_index == -1);
  95
  96     if (env->sr & (1u << SR_BL)) {
  97         if (do_exp && cs->exception_index != 0x1e0) {
  98             cs->exception_index = 0x000; /* masked exception -> reset */
  99         }
 100         if (do_irq && !env->in_sleep) {
 101             return; /* masked */
 102         }
 103     }
 104     env->in_sleep = 0;
 105
 106     if (do_irq) {
 107         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 108                                                 (env->sr >> 4) & 0xf);
 109         if (irq_vector == -1) {
 110             return; /* masked */
 111         }
 112     }
 113
 114     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 115         const char *expname;
 116         switch (cs->exception_index) {
 117         case 0x0e0:
 118             expname = "addr_error";
 119             break;
 120         case 0x040:
 121             expname = "tlb_miss";
 122             break;
 123         case 0x0a0:
 124             expname = "tlb_violation";
 125             break;
 126         case 0x180:
 127             expname = "illegal_instruction";
 128             break;
 129         case 0x1a0:
 130             expname = "slot_illegal_instruction";
 131             break;
 132         case 0x800:
 133             expname = "fpu_disable";
 134             break;
 135         case 0x820:
 136             expname = "slot_fpu";
 137             break;
 138         case 0x100:
 139             expname = "data_write";
 140             break;
 141         case 0x060:
 142             expname = "dtlb_miss_write";
 143             break;
 144         case 0x0c0:
 145             expname = "dtlb_violation_write";
 146             break;
 147         case 0x120:
 148             expname = "fpu_exception";
 149             break;
 150         case 0x080:
 151             expname = "initial_page_write";
 152             break;
 153         case 0x160:
 154             expname = "trapa";
 155             break;
 156         default:
 157             expname = do_irq ? "interrupt" : "???";
 158             break;
 159         }
 160         qemu_log("exception 0x%03x [%s] raised\n",
 161                   irq_vector, expname);
 162         log_cpu_state(cs, 0);
 163     }
 164
 165     env->ssr = cpu_read_sr(env);
 166     env->spc = env->pc;
 167     env->sgr = env->gregs[15];
 168     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
 169
 170     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 171         /* Branch instruction should be executed again before delay slot. */
 172         env->spc -= 2;
 173         /* Clear flags for exception/interrupt routine. */
 174         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 175     }
 176     if (env->flags & DELAY_SLOT_CLEARME)
 177         env->flags = 0;
 178
 179     if (do_exp) {
 180         env->expevt = cs->exception_index;
 181         switch (cs->exception_index) {
 182         case 0x000:
 183         case 0x020:
 184         case 0x140:
 185             env->sr &= ~(1u << SR_FD);
 186             env->sr |= 0xf << 4; /* IMASK */
 187             env->pc = 0xa0000000;
 188             break;
 189         case 0x040:
 190         case 0x060:
 191             env->pc = env->vbr + 0x400;
 192             break;
 193         case 0x160:
 194             env->spc += 2; /* special case for TRAPA */
 195             /* fall through */
 196         default:
 197             env->pc = env->vbr + 0x100;
 198             break;
 199         }
 200         return;
 201     }
 202
 203     if (do_irq) {
 204         env->intevt = irq_vector;
 205         env->pc = env->vbr + 0x600;
 206         return;
 207     }
 208 }
 209
 210 static void update_itlb_use(CPUSH4State * env, int itlbnb)
 211 {
 212     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 213
 214     switch (itlbnb) {
 215     case 0:
 216         and_mask = 0x1f;
 217         break;
 218     case 1:
 219         and_mask = 0xe7;
 220         or_mask = 0x80;
 221         break;
 222     case 2:
 223         and_mask = 0xfb;
 224         or_mask = 0x50;
 225         break;
 226     case 3:
 227         or_mask = 0x2c;
 228         break;
 229     }
 230
 231     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 232     env->mmucr |= (or_mask << 24);
 233 }
 234
 235 static int itlb_replacement(CPUSH4State * env)
 236 {
 237     SuperHCPU *cpu = sh_env_get_cpu(env);
 238
 239     if ((env->mmucr & 0xe0000000) == 0xe0000000) {
 240         return 0;
 241     }
 242     if ((env->mmucr & 0x98000000) == 0x18000000) {
 243         return 1;
 244     }
 245     if ((env->mmucr & 0x54000000) == 0x04000000) {
 246         return 2;
 247     }
 248     if ((env->mmucr & 0x2c000000) == 0x00000000) {
 249         return 3;
 250     }
 251     cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
 252 }
 253
 254 /* Find the corresponding entry in the right TLB
 255    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 256 */
 257 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
 258                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 259 {
 260     int match = MMU_DTLB_MISS;
 261     uint32_t start, end;
 262     uint8_t asid;
 263     int i;
 264
 265     asid = env->pteh & 0xff;
 266
 267     for (i = 0; i < nbtlb; i++) {
 268         if (!entries[i].v)
 269             continue;           /* Invalid entry */
 270         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 271             continue;           /* Bad ASID */
 272         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 273         end = start + entries[i].size - 1;
 274         if (address >= start && address <= end) {       /* Match */
 275             if (match != MMU_DTLB_MISS)
 276                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 277             match = i;
 278         }
 279     }
 280     return match;
 281 }
 282
 283 static void increment_urc(CPUSH4State * env)
 284 {
 285     uint8_t urb, urc;
 286
 287     /* Increment URC */
 288     urb = ((env->mmucr) >> 18) & 0x3f;
 289     urc = ((env->mmucr) >> 10) & 0x3f;
 290     urc++;
 291     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 292         urc = 0;
 293     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 294 }
 295
 296 /* Copy and utlb entry into itlb
 297    Return entry
 298 */
 299 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 300 {
 301     int itlb;
 302
 303     tlb_t * ientry;
 304     itlb = itlb_replacement(env);
 305     ientry = &env->itlb[itlb];
 306     if (ientry->v) {
 307         tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
 308     }
 309     *ientry = env->utlb[utlb];
 310     update_itlb_use(env, itlb);
 311     return itlb;
 312 }
 313
 314 /* Find itlb entry
 315    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 316 */
 317 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 318                            int use_asid)
 319 {
 320     int e;
 321
 322     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 323     if (e == MMU_DTLB_MULTIPLE) {
 324         e = MMU_ITLB_MULTIPLE;
 325     } else if (e == MMU_DTLB_MISS) {
 326         e = MMU_ITLB_MISS;
 327     } else if (e >= 0) {
 328         update_itlb_use(env, e);
 329     }
 330     return e;
 331 }
 332
 333 /* Find utlb entry
 334    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 335 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
 336 {
 337     /* per utlb access */
 338     increment_urc(env);
 339
 340     /* Return entry */
 341     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 342 }
 343
 344 /* Match address against MMU
 345    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 346    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 347    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 348    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 349    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 350 */
 351 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
 352                            int *prot, target_ulong address,
 353                            int rw, int access_type)
 354 {
 355     int use_asid, n;
 356     tlb_t *matching = NULL;
 357
 358     use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
 359
 360     if (rw == 2) {
 361         n = find_itlb_entry(env, address, use_asid);
 362         if (n >= 0) {
 363             matching = &env->itlb[n];
 364             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 365                 n = MMU_ITLB_VIOLATION;
 366             } else {
 367                 *prot = PAGE_EXEC;
 368             }
 369         } else {
 370             n = find_utlb_entry(env, address, use_asid);
 371             if (n >= 0) {
 372                 n = copy_utlb_entry_itlb(env, n);
 373                 matching = &env->itlb[n];
 374                 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 375                     n = MMU_ITLB_VIOLATION;
 376                 } else {
 377                     *prot = PAGE_READ | PAGE_EXEC;
 378                     if ((matching->pr & 1) && matching->d) {
 379                         *prot |= PAGE_WRITE;
 380                     }
 381                 }
 382             } else if (n == MMU_DTLB_MULTIPLE) {
 383                 n = MMU_ITLB_MULTIPLE;
 384             } else if (n == MMU_DTLB_MISS) {
 385                 n = MMU_ITLB_MISS;
 386             }
 387         }
 388     } else {
 389         n = find_utlb_entry(env, address, use_asid);
 390         if (n >= 0) {
 391             matching = &env->utlb[n];
 392             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 393                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 394                     MMU_DTLB_VIOLATION_READ;
 395             } else if ((rw == 1) && !(matching->pr & 1)) {
 396                 n = MMU_DTLB_VIOLATION_WRITE;
 397             } else if ((rw == 1) && !matching->d) {
 398                 n = MMU_DTLB_INITIAL_WRITE;
 399             } else {
 400                 *prot = PAGE_READ;
 401                 if ((matching->pr & 1) && matching->d) {
 402                     *prot |= PAGE_WRITE;
 403                 }
 404             }
 405         } else if (n == MMU_DTLB_MISS) {
 406             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 407                 MMU_DTLB_MISS_READ;
 408         }
 409     }
 410     if (n >= 0) {
 411         n = MMU_OK;
 412         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 413             (address & (matching->size - 1));
 414     }
 415     return n;
 416 }
 417
 418 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 419                                 int *prot, target_ulong address,
 420                                 int rw, int access_type)
 421 {
 422     /* P1, P2 and P4 areas do not use translation */
 423     if ((address >= 0x80000000 && address < 0xc0000000) ||
 424         address >= 0xe0000000) {
 425         if (!(env->sr & (1u << SR_MD))
 426             && (address < 0xe0000000 || address >= 0xe4000000)) {
 427             /* Unauthorized access in user mode (only store queues are available) */
 428             fprintf(stderr, "Unauthorized access\n");
 429             if (rw == 0)
 430                 return MMU_DADDR_ERROR_READ;
 431             else if (rw == 1)
 432                 return MMU_DADDR_ERROR_WRITE;
 433             else
 434                 return MMU_IADDR_ERROR;
 435         }
 436         if (address >= 0x80000000 && address < 0xc0000000) {
 437             /* Mask upper 3 bits for P1 and P2 areas */
 438             *physical = address & 0x1fffffff;
 439         } else {
 440             *physical = address;
 441         }
 442         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 443         return MMU_OK;
 444     }
 445
 446     /* If MMU is disabled, return the corresponding physical page */
 447     if (!(env->mmucr & MMUCR_AT)) {
 448         *physical = address & 0x1FFFFFFF;
 449         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 450         return MMU_OK;
 451     }
 452
 453     /* We need to resort to the MMU */
 454     return get_mmu_address(env, physical, prot, address, rw, access_type);
 455 }
 456
 457 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 458                                 int mmu_idx)
 459 {
 460     SuperHCPU *cpu = SUPERH_CPU(cs);
 461     CPUSH4State *env = &cpu->env;
 462     target_ulong physical;
 463     int prot, ret, access_type;
 464
 465     access_type = ACCESS_INT;
 466     ret =
 467         get_physical_address(env, &physical, &prot, address, rw,
 468                              access_type);
 469
 470     if (ret != MMU_OK) {
 471         env->tea = address;
 472         if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
 473             env->pteh = (env->pteh & PTEH_ASID_MASK) |
 474                     (address & PTEH_VPN_MASK);
 475         }
 476         switch (ret) {
 477         case MMU_ITLB_MISS:
 478         case MMU_DTLB_MISS_READ:
 479             cs->exception_index = 0x040;
 480             break;
 481         case MMU_DTLB_MULTIPLE:
 482         case MMU_ITLB_MULTIPLE:
 483             cs->exception_index = 0x140;
 484             break;
 485         case MMU_ITLB_VIOLATION:
 486             cs->exception_index = 0x0a0;
 487             break;
 488         case MMU_DTLB_MISS_WRITE:
 489             cs->exception_index = 0x060;
 490             break;
 491         case MMU_DTLB_INITIAL_WRITE:
 492             cs->exception_index = 0x080;
 493             break;
 494         case MMU_DTLB_VIOLATION_READ:
 495             cs->exception_index = 0x0a0;
 496             break;
 497         case MMU_DTLB_VIOLATION_WRITE:
 498             cs->exception_index = 0x0c0;
 499             break;
 500         case MMU_IADDR_ERROR:
 501         case MMU_DADDR_ERROR_READ:
 502             cs->exception_index = 0x0e0;
 503             break;
 504         case MMU_DADDR_ERROR_WRITE:
 505             cs->exception_index = 0x100;
 506             break;
 507         default:
 508             cpu_abort(cs, "Unhandled MMU fault");
 509         }
 510         return 1;
 511     }
 512
 513     address &= TARGET_PAGE_MASK;
 514     physical &= TARGET_PAGE_MASK;
 515
 516     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 517     return 0;
 518 }
 519
 520 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 521 {
 522     SuperHCPU *cpu = SUPERH_CPU(cs);
 523     target_ulong physical;
 524     int prot;
 525
 526     get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
 527     return physical;
 528 }
 529
 530 void cpu_load_tlb(CPUSH4State * env)
 531 {
 532     SuperHCPU *cpu = sh_env_get_cpu(env);
 533     int n = cpu_mmucr_urc(env->mmucr);
 534     tlb_t * entry = &env->utlb[n];
 535
 536     if (entry->v) {
 537         /* Overwriting valid entry in utlb. */
 538         target_ulong address = entry->vpn << 10;
 539         tlb_flush_page(CPU(cpu), address);
 540     }
 541
 542     /* Take values into cpu status from registers. */
 543     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 544     entry->vpn  = cpu_pteh_vpn(env->pteh);
 545     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 546     entry->ppn  = cpu_ptel_ppn(env->ptel);
 547     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 548     switch (entry->sz) {
 549     case 0: /* 00 */
 550         entry->size = 1024; /* 1K */
 551         break;
 552     case 1: /* 01 */
 553         entry->size = 1024 * 4; /* 4K */
 554         break;
 555     case 2: /* 10 */
 556         entry->size = 1024 * 64; /* 64K */
 557         break;
 558     case 3: /* 11 */
 559         entry->size = 1024 * 1024; /* 1M */
 560         break;
 561     default:
 562         cpu_abort(CPU(cpu), "Unhandled load_tlb");
 563         break;
 564     }
 565     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 566     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 567     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 568     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 569     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 570     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 571     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 572 }
 573
 574  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 575 {
 576     int i;
 577
 578     /* UTLB */
 579     for (i = 0; i < UTLB_SIZE; i++) {
 580         tlb_t * entry = &s->utlb[i];
 581         entry->v = 0;
 582     }
 583     /* ITLB */
 584     for (i = 0; i < ITLB_SIZE; i++) {
 585         tlb_t * entry = &s->itlb[i];
 586         entry->v = 0;
 587     }
 588
 589     tlb_flush(CPU(sh_env_get_cpu(s)), 1);
 590 }
 591
 592 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 593                                        hwaddr addr)
 594 {
 595     int index = (addr & 0x00000300) >> 8;
 596     tlb_t * entry = &s->itlb[index];
 597
 598     return (entry->vpn  << 10) |
 599            (entry->v    <<  8) |
 600            (entry->asid);
 601 }
 602
 603 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 604                                     uint32_t mem_value)
 605 {
 606     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 607     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 608     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 609
 610     int index = (addr & 0x00000300) >> 8;
 611     tlb_t * entry = &s->itlb[index];
 612     if (entry->v) {
 613         /* Overwriting valid entry in itlb. */
 614         target_ulong address = entry->vpn << 10;
 615         tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 616     }
 617     entry->asid = asid;
 618     entry->vpn = vpn;
 619     entry->v = v;
 620 }
 621
 622 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 623                                        hwaddr addr)
 624 {
 625     int array = (addr & 0x00800000) >> 23;
 626     int index = (addr & 0x00000300) >> 8;
 627     tlb_t * entry = &s->itlb[index];
 628
 629     if (array == 0) {
 630         /* ITLB Data Array 1 */
 631         return (entry->ppn << 10) |
 632                (entry->v   <<  8) |
 633                (entry->pr  <<  5) |
 634                ((entry->sz & 1) <<  6) |
 635                ((entry->sz & 2) <<  4) |
 636                (entry->c   <<  3) |
 637                (entry->sh  <<  1);
 638     } else {
 639         /* ITLB Data Array 2 */
 640         return (entry->tc << 1) |
 641                (entry->sa);
 642     }
 643 }
 644
 645 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 646                                     uint32_t mem_value)
 647 {
 648     int array = (addr & 0x00800000) >> 23;
 649     int index = (addr & 0x00000300) >> 8;
 650     tlb_t * entry = &s->itlb[index];
 651
 652     if (array == 0) {
 653         /* ITLB Data Array 1 */
 654         if (entry->v) {
 655             /* Overwriting valid entry in utlb. */
 656             target_ulong address = entry->vpn << 10;
 657             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 658         }
 659         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 660         entry->v   = (mem_value & 0x00000100) >> 8;
 661         entry->sz  = (mem_value & 0x00000080) >> 6 |
 662                      (mem_value & 0x00000010) >> 4;
 663         entry->pr  = (mem_value & 0x00000040) >> 5;
 664         entry->c   = (mem_value & 0x00000008) >> 3;
 665         entry->sh  = (mem_value & 0x00000002) >> 1;
 666     } else {
 667         /* ITLB Data Array 2 */
 668         entry->tc  = (mem_value & 0x00000008) >> 3;
 669         entry->sa  = (mem_value & 0x00000007);
 670     }
 671 }
 672
 673 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 674                                        hwaddr addr)
 675 {
 676     int index = (addr & 0x00003f00) >> 8;
 677     tlb_t * entry = &s->utlb[index];
 678
 679     increment_urc(s); /* per utlb access */
 680
 681     return (entry->vpn  << 10) |
 682            (entry->v    <<  8) |
 683            (entry->asid);
 684 }
 685
 686 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 687                                     uint32_t mem_value)
 688 {
 689     int associate = addr & 0x0000080;
 690     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 691     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 692     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 693     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 694     int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
 695
 696     if (associate) {
 697         int i;
 698         tlb_t * utlb_match_entry = NULL;
 699         int needs_tlb_flush = 0;
 700
 701         /* search UTLB */
 702         for (i = 0; i < UTLB_SIZE; i++) {
 703             tlb_t * entry = &s->utlb[i];
 704             if (!entry->v)
 705                 continue;
 706
 707             if (entry->vpn == vpn
 708                 && (!use_asid || entry->asid == asid || entry->sh)) {
 709                 if (utlb_match_entry) {
 710                     CPUState *cs = CPU(sh_env_get_cpu(s));
 711
 712                     /* Multiple TLB Exception */
 713                     cs->exception_index = 0x140;
 714                     s->tea = addr;
 715                     break;
 716                 }
 717                 if (entry->v && !v)
 718                     needs_tlb_flush = 1;
 719                 entry->v = v;
 720                 entry->d = d;
 721                 utlb_match_entry = entry;
 722             }
 723             increment_urc(s); /* per utlb access */
 724         }
 725
 726         /* search ITLB */
 727         for (i = 0; i < ITLB_SIZE; i++) {
 728             tlb_t * entry = &s->itlb[i];
 729             if (entry->vpn == vpn
 730                 && (!use_asid || entry->asid == asid || entry->sh)) {
 731                 if (entry->v && !v)
 732                     needs_tlb_flush = 1;
 733                 if (utlb_match_entry)
 734                     *entry = *utlb_match_entry;
 735                 else
 736                     entry->v = v;
 737                 break;
 738             }
 739         }
 740
 741         if (needs_tlb_flush) {
 742             tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
 743         }
 744
 745     } else {
 746         int index = (addr & 0x00003f00) >> 8;
 747         tlb_t * entry = &s->utlb[index];
 748         if (entry->v) {
 749             CPUState *cs = CPU(sh_env_get_cpu(s));
 750
 751             /* Overwriting valid entry in utlb. */
 752             target_ulong address = entry->vpn << 10;
 753             tlb_flush_page(cs, address);
 754         }
 755         entry->asid = asid;
 756         entry->vpn = vpn;
 757         entry->d = d;
 758         entry->v = v;
 759         increment_urc(s);
 760     }
 761 }
 762
 763 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 764                                        hwaddr addr)
 765 {
 766     int array = (addr & 0x00800000) >> 23;
 767     int index = (addr & 0x00003f00) >> 8;
 768     tlb_t * entry = &s->utlb[index];
 769
 770     increment_urc(s); /* per utlb access */
 771
 772     if (array == 0) {
 773         /* ITLB Data Array 1 */
 774         return (entry->ppn << 10) |
 775                (entry->v   <<  8) |
 776                (entry->pr  <<  5) |
 777                ((entry->sz & 1) <<  6) |
 778                ((entry->sz & 2) <<  4) |
 779                (entry->c   <<  3) |
 780                (entry->d   <<  2) |
 781                (entry->sh  <<  1) |
 782                (entry->wt);
 783     } else {
 784         /* ITLB Data Array 2 */
 785         return (entry->tc << 1) |
 786                (entry->sa);
 787     }
 788 }
 789
 790 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 791                                     uint32_t mem_value)
 792 {
 793     int array = (addr & 0x00800000) >> 23;
 794     int index = (addr & 0x00003f00) >> 8;
 795     tlb_t * entry = &s->utlb[index];
 796
 797     increment_urc(s); /* per utlb access */
 798
 799     if (array == 0) {
 800         /* UTLB Data Array 1 */
 801         if (entry->v) {
 802             /* Overwriting valid entry in utlb. */
 803             target_ulong address = entry->vpn << 10;
 804             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 805         }
 806         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 807         entry->v   = (mem_value & 0x00000100) >> 8;
 808         entry->sz  = (mem_value & 0x00000080) >> 6 |
 809                      (mem_value & 0x00000010) >> 4;
 810         entry->pr  = (mem_value & 0x00000060) >> 5;
 811         entry->c   = (mem_value & 0x00000008) >> 3;
 812         entry->d   = (mem_value & 0x00000004) >> 2;
 813         entry->sh  = (mem_value & 0x00000002) >> 1;
 814         entry->wt  = (mem_value & 0x00000001);
 815     } else {
 816         /* UTLB Data Array 2 */
 817         entry->tc = (mem_value & 0x00000008) >> 3;
 818         entry->sa = (mem_value & 0x00000007);
 819     }
 820 }
 821
 822 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 823 {
 824     int n;
 825     int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
 826
 827     /* check area */
 828     if (env->sr & (1u << SR_MD)) {
 829         /* For previledged mode, P2 and P4 area is not cachable. */
 830         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 831             return 0;
 832     } else {
 833         /* For user mode, only U0 area is cachable. */
 834         if (0x80000000 <= addr)
 835             return 0;
 836     }
 837
 838     /*
 839      * TODO : Evaluate CCR and check if the cache is on or off.
 840      *        Now CCR is not in CPUSH4State, but in SH7750State.
 841      *        When you move the ccr into CPUSH4State, the code will be
 842      *        as follows.
 843      */
 844 #if 0
 845     /* check if operand cache is enabled or not. */
 846     if (!(env->ccr & 1))
 847         return 0;
 848 #endif
 849
 850     /* if MMU is off, no check for TLB. */
 851     if (env->mmucr & MMUCR_AT)
 852         return 1;
 853
 854     /* check TLB */
 855     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 856     if (n >= 0)
 857         return env->itlb[n].c;
 858
 859     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 860     if (n >= 0)
 861         return env->utlb[n].c;
 862
 863     return 0;
 864 }
 865
 866 #endif
 867
 868 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 869 {
 870     if (interrupt_request & CPU_INTERRUPT_HARD) {
 871         superh_cpu_do_interrupt(cs);
 872         return true;
 873     }
 874     return false;
 875 }