?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pckbd: QOM'ify
[qemu/ar7.git] / hw / usb / hcd-xhci.c
blob2c90e56c9917ba96989069c34cb1b836e290ccc0
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu/timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
27 #include "trace.h"
28
29 //#define DEBUG_XHCI
30 //#define DEBUG_DATA
31
32 #ifdef DEBUG_XHCI
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #else
35 #define DPRINTF(...) do {} while (0)
36 #endif
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
39
40 #define MAXPORTS_2 15
41 #define MAXPORTS_3 15
42
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
44 #define MAXSLOTS 64
45 #define MAXINTRS 16
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
67
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
70 #endif
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
73 #endif
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
76 #endif
77
78 /* bit definitions */
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
88
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
98
99
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
129
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
134
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
137
138 #define ERDP_EHB (1<<3)
139
140 #define TRB_SIZE 16
141 typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
145 dma_addr_t addr;
146 bool ccs;
147 } XHCITRB;
148
149 enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163 };
164
165 typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202 } TRBType;
203
204 #define CR_LINK TR_LINK
205
206 typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242 } TRBCCode;
243
244 #define TRB_C (1<<0)
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
248
249 #define TRB_EV_ED (1<<2)
250
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
265
266 #define TRB_TR_DIR (1<<16)
267
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
272
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
275
276 #define TRB_LK_TC (1<<1)
277
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
281
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
284
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
291
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
299
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
302
303 typedef struct XHCIState XHCIState;
304 typedef struct XHCIStreamContext XHCIStreamContext;
305 typedef struct XHCIEPContext XHCIEPContext;
306
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
317 typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326 } EPType;
327
328 typedef struct XHCIRing {
329 dma_addr_t dequeue;
330 bool ccs;
331 } XHCIRing;
332
333 typedef struct XHCIPort {
334 XHCIState *xhci;
335 uint32_t portsc;
336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
339 char name[16];
340 MemoryRegion mem;
341 } XHCIPort;
342
343 typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
346 QEMUSGList sgl;
347 bool running_async;
348 bool running_retry;
349 bool cancelled;
350 bool complete;
351 bool int_req;
352 unsigned int iso_pkts;
353 unsigned int slotid;
354 unsigned int epid;
355 unsigned int streamid;
356 bool in_xfer;
357 bool iso_xfer;
358
359 unsigned int trb_count;
360 unsigned int trb_alloced;
361 XHCITRB *trbs;
362
363 TRBCCode status;
364
365 unsigned int pkts;
366 unsigned int pktsize;
367 unsigned int cur_pkt;
368
369 uint64_t mfindex_kick;
370 } XHCITransfer;
371
372 struct XHCIStreamContext {
373 dma_addr_t pctx;
374 unsigned int sct;
375 XHCIRing ring;
376 XHCIStreamContext *sstreams;
377 };
378
379 struct XHCIEPContext {
380 XHCIState *xhci;
381 unsigned int slotid;
382 unsigned int epid;
383
384 XHCIRing ring;
385 unsigned int next_xfer;
386 unsigned int comp_xfer;
387 XHCITransfer transfers[TD_QUEUE];
388 XHCITransfer *retry;
389 EPType type;
390 dma_addr_t pctx;
391 unsigned int max_psize;
392 uint32_t state;
393
394 /* streams */
395 unsigned int max_pstreams;
396 bool lsa;
397 unsigned int nr_pstreams;
398 XHCIStreamContext *pstreams;
399
400 /* iso xfer scheduling */
401 unsigned int interval;
402 int64_t mfindex_last;
403 QEMUTimer *kick_timer;
404 };
405
406 typedef struct XHCISlot {
407 bool enabled;
408 dma_addr_t ctx;
409 USBPort *uport;
410 XHCIEPContext * eps[31];
411 } XHCISlot;
412
413 typedef struct XHCIEvent {
414 TRBType type;
415 TRBCCode ccode;
416 uint64_t ptr;
417 uint32_t length;
418 uint32_t flags;
419 uint8_t slotid;
420 uint8_t epid;
421 } XHCIEvent;
422
423 typedef struct XHCIInterrupter {
424 uint32_t iman;
425 uint32_t imod;
426 uint32_t erstsz;
427 uint32_t erstba_low;
428 uint32_t erstba_high;
429 uint32_t erdp_low;
430 uint32_t erdp_high;
431
432 bool msix_used, er_pcs, er_full;
433
434 dma_addr_t er_start;
435 uint32_t er_size;
436 unsigned int er_ep_idx;
437
438 XHCIEvent ev_buffer[EV_QUEUE];
439 unsigned int ev_buffer_put;
440 unsigned int ev_buffer_get;
441
442 } XHCIInterrupter;
443
444 struct XHCIState {
445 PCIDevice pci_dev;
446 USBBus bus;
447 qemu_irq irq;
448 MemoryRegion mem;
449 MemoryRegion mem_cap;
450 MemoryRegion mem_oper;
451 MemoryRegion mem_runtime;
452 MemoryRegion mem_doorbell;
453
454 /* properties */
455 uint32_t numports_2;
456 uint32_t numports_3;
457 uint32_t numintrs;
458 uint32_t numslots;
459 uint32_t flags;
460
461 /* Operational Registers */
462 uint32_t usbcmd;
463 uint32_t usbsts;
464 uint32_t dnctrl;
465 uint32_t crcr_low;
466 uint32_t crcr_high;
467 uint32_t dcbaap_low;
468 uint32_t dcbaap_high;
469 uint32_t config;
470
471 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
472 XHCIPort ports[MAXPORTS];
473 XHCISlot slots[MAXSLOTS];
474 uint32_t numports;
475
476 /* Runtime Registers */
477 int64_t mfindex_start;
478 QEMUTimer *mfwrap_timer;
479 XHCIInterrupter intr[MAXINTRS];
480
481 XHCIRing cmd_ring;
482 };
483
484 typedef struct XHCIEvRingSeg {
485 uint32_t addr_low;
486 uint32_t addr_high;
487 uint32_t size;
488 uint32_t rsvd;
489 } XHCIEvRingSeg;
490
491 enum xhci_flags {
492 XHCI_FLAG_USE_MSI = 1,
493 XHCI_FLAG_USE_MSI_X,
494 };
495
496 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
497 unsigned int epid, unsigned int streamid);
498 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
499 unsigned int epid);
500 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
501 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
502
503 static const char *TRBType_names[] = {
504 [TRB_RESERVED] = "TRB_RESERVED",
505 [TR_NORMAL] = "TR_NORMAL",
506 [TR_SETUP] = "TR_SETUP",
507 [TR_DATA] = "TR_DATA",
508 [TR_STATUS] = "TR_STATUS",
509 [TR_ISOCH] = "TR_ISOCH",
510 [TR_LINK] = "TR_LINK",
511 [TR_EVDATA] = "TR_EVDATA",
512 [TR_NOOP] = "TR_NOOP",
513 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
514 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
515 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
516 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
517 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
518 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
519 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
520 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
521 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
522 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
523 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
524 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
525 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
526 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
527 [CR_NOOP] = "CR_NOOP",
528 [ER_TRANSFER] = "ER_TRANSFER",
529 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
530 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
531 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
532 [ER_DOORBELL] = "ER_DOORBELL",
533 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
534 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
535 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
536 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
537 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
538 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
539 };
540
541 static const char *TRBCCode_names[] = {
542 [CC_INVALID] = "CC_INVALID",
543 [CC_SUCCESS] = "CC_SUCCESS",
544 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
545 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
546 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
547 [CC_TRB_ERROR] = "CC_TRB_ERROR",
548 [CC_STALL_ERROR] = "CC_STALL_ERROR",
549 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
550 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
551 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
552 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
553 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
554 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
555 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
556 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
557 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
558 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
559 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
560 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
561 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
562 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
563 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
564 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
565 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
566 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
567 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
568 [CC_STOPPED] = "CC_STOPPED",
569 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
570 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
571 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
572 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
573 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
574 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
575 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
576 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
577 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
578 };
579
580 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
581 {
582 if (index >= llen || list[index] == NULL) {
583 return "???";
584 }
585 return list[index];
586 }
587
588 static const char *trb_name(XHCITRB *trb)
589 {
590 return lookup_name(TRB_TYPE(*trb), TRBType_names,
591 ARRAY_SIZE(TRBType_names));
592 }
593
594 static const char *event_name(XHCIEvent *event)
595 {
596 return lookup_name(event->ccode, TRBCCode_names,
597 ARRAY_SIZE(TRBCCode_names));
598 }
599
600 static uint64_t xhci_mfindex_get(XHCIState *xhci)
601 {
602 int64_t now = qemu_get_clock_ns(vm_clock);
603 return (now - xhci->mfindex_start) / 125000;
604 }
605
606 static void xhci_mfwrap_update(XHCIState *xhci)
607 {
608 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
609 uint32_t mfindex, left;
610 int64_t now;
611
612 if ((xhci->usbcmd & bits) == bits) {
613 now = qemu_get_clock_ns(vm_clock);
614 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
615 left = 0x4000 - mfindex;
616 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
617 } else {
618 qemu_del_timer(xhci->mfwrap_timer);
619 }
620 }
621
622 static void xhci_mfwrap_timer(void *opaque)
623 {
624 XHCIState *xhci = opaque;
625 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
626
627 xhci_event(xhci, &wrap, 0);
628 xhci_mfwrap_update(xhci);
629 }
630
631 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
632 {
633 if (sizeof(dma_addr_t) == 4) {
634 return low;
635 } else {
636 return low | (((dma_addr_t)high << 16) << 16);
637 }
638 }
639
640 static inline dma_addr_t xhci_mask64(uint64_t addr)
641 {
642 if (sizeof(dma_addr_t) == 4) {
643 return addr & 0xffffffff;
644 } else {
645 return addr;
646 }
647 }
648
649 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
650 uint32_t *buf, size_t len)
651 {
652 int i;
653
654 assert((len % sizeof(uint32_t)) == 0);
655
656 pci_dma_read(&xhci->pci_dev, addr, buf, len);
657
658 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
659 buf[i] = le32_to_cpu(buf[i]);
660 }
661 }
662
663 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
664 uint32_t *buf, size_t len)
665 {
666 int i;
667 uint32_t tmp[len / sizeof(uint32_t)];
668
669 assert((len % sizeof(uint32_t)) == 0);
670
671 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
672 tmp[i] = cpu_to_le32(buf[i]);
673 }
674 pci_dma_write(&xhci->pci_dev, addr, tmp, len);
675 }
676
677 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
678 {
679 int index;
680
681 if (!uport->dev) {
682 return NULL;
683 }
684 switch (uport->dev->speed) {
685 case USB_SPEED_LOW:
686 case USB_SPEED_FULL:
687 case USB_SPEED_HIGH:
688 index = uport->index;
689 break;
690 case USB_SPEED_SUPER:
691 index = uport->index + xhci->numports_2;
692 break;
693 default:
694 return NULL;
695 }
696 return &xhci->ports[index];
697 }
698
699 static void xhci_intx_update(XHCIState *xhci)
700 {
701 int level = 0;
702
703 if (msix_enabled(&xhci->pci_dev) ||
704 msi_enabled(&xhci->pci_dev)) {
705 return;
706 }
707
708 if (xhci->intr[0].iman & IMAN_IP &&
709 xhci->intr[0].iman & IMAN_IE &&
710 xhci->usbcmd & USBCMD_INTE) {
711 level = 1;
712 }
713
714 trace_usb_xhci_irq_intx(level);
715 qemu_set_irq(xhci->irq, level);
716 }
717
718 static void xhci_msix_update(XHCIState *xhci, int v)
719 {
720 bool enabled;
721
722 if (!msix_enabled(&xhci->pci_dev)) {
723 return;
724 }
725
726 enabled = xhci->intr[v].iman & IMAN_IE;
727 if (enabled == xhci->intr[v].msix_used) {
728 return;
729 }
730
731 if (enabled) {
732 trace_usb_xhci_irq_msix_use(v);
733 msix_vector_use(&xhci->pci_dev, v);
734 xhci->intr[v].msix_used = true;
735 } else {
736 trace_usb_xhci_irq_msix_unuse(v);
737 msix_vector_unuse(&xhci->pci_dev, v);
738 xhci->intr[v].msix_used = false;
739 }
740 }
741
742 static void xhci_intr_raise(XHCIState *xhci, int v)
743 {
744 xhci->intr[v].erdp_low |= ERDP_EHB;
745 xhci->intr[v].iman |= IMAN_IP;
746 xhci->usbsts |= USBSTS_EINT;
747
748 if (!(xhci->intr[v].iman & IMAN_IE)) {
749 return;
750 }
751
752 if (!(xhci->usbcmd & USBCMD_INTE)) {
753 return;
754 }
755
756 if (msix_enabled(&xhci->pci_dev)) {
757 trace_usb_xhci_irq_msix(v);
758 msix_notify(&xhci->pci_dev, v);
759 return;
760 }
761
762 if (msi_enabled(&xhci->pci_dev)) {
763 trace_usb_xhci_irq_msi(v);
764 msi_notify(&xhci->pci_dev, v);
765 return;
766 }
767
768 if (v == 0) {
769 trace_usb_xhci_irq_intx(1);
770 qemu_set_irq(xhci->irq, 1);
771 }
772 }
773
774 static inline int xhci_running(XHCIState *xhci)
775 {
776 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
777 }
778
779 static void xhci_die(XHCIState *xhci)
780 {
781 xhci->usbsts |= USBSTS_HCE;
782 fprintf(stderr, "xhci: asserted controller error\n");
783 }
784
785 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
786 {
787 XHCIInterrupter *intr = &xhci->intr[v];
788 XHCITRB ev_trb;
789 dma_addr_t addr;
790
791 ev_trb.parameter = cpu_to_le64(event->ptr);
792 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
793 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
794 event->flags | (event->type << TRB_TYPE_SHIFT);
795 if (intr->er_pcs) {
796 ev_trb.control |= TRB_C;
797 }
798 ev_trb.control = cpu_to_le32(ev_trb.control);
799
800 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
801 event_name(event), ev_trb.parameter,
802 ev_trb.status, ev_trb.control);
803
804 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
805 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
806
807 intr->er_ep_idx++;
808 if (intr->er_ep_idx >= intr->er_size) {
809 intr->er_ep_idx = 0;
810 intr->er_pcs = !intr->er_pcs;
811 }
812 }
813
814 static void xhci_events_update(XHCIState *xhci, int v)
815 {
816 XHCIInterrupter *intr = &xhci->intr[v];
817 dma_addr_t erdp;
818 unsigned int dp_idx;
819 bool do_irq = 0;
820
821 if (xhci->usbsts & USBSTS_HCH) {
822 return;
823 }
824
825 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
826 if (erdp < intr->er_start ||
827 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
828 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
829 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
830 v, intr->er_start, intr->er_size);
831 xhci_die(xhci);
832 return;
833 }
834 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
835 assert(dp_idx < intr->er_size);
836
837 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
838 * deadlocks when the ER is full. Hack it by holding off events until
839 * the driver decides to free at least half of the ring */
840 if (intr->er_full) {
841 int er_free = dp_idx - intr->er_ep_idx;
842 if (er_free <= 0) {
843 er_free += intr->er_size;
844 }
845 if (er_free < (intr->er_size/2)) {
846 DPRINTF("xhci_events_update(): event ring still "
847 "more than half full (hack)\n");
848 return;
849 }
850 }
851
852 while (intr->ev_buffer_put != intr->ev_buffer_get) {
853 assert(intr->er_full);
854 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
855 DPRINTF("xhci_events_update(): event ring full again\n");
856 #ifndef ER_FULL_HACK
857 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
858 xhci_write_event(xhci, &full, v);
859 #endif
860 do_irq = 1;
861 break;
862 }
863 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
864 xhci_write_event(xhci, event, v);
865 intr->ev_buffer_get++;
866 do_irq = 1;
867 if (intr->ev_buffer_get == EV_QUEUE) {
868 intr->ev_buffer_get = 0;
869 }
870 }
871
872 if (do_irq) {
873 xhci_intr_raise(xhci, v);
874 }
875
876 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
877 DPRINTF("xhci_events_update(): event ring no longer full\n");
878 intr->er_full = 0;
879 }
880 }
881
882 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
883 {
884 XHCIInterrupter *intr;
885 dma_addr_t erdp;
886 unsigned int dp_idx;
887
888 if (v >= xhci->numintrs) {
889 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
890 return;
891 }
892 intr = &xhci->intr[v];
893
894 if (intr->er_full) {
895 DPRINTF("xhci_event(): ER full, queueing\n");
896 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
897 fprintf(stderr, "xhci: event queue full, dropping event!\n");
898 return;
899 }
900 intr->ev_buffer[intr->ev_buffer_put++] = *event;
901 if (intr->ev_buffer_put == EV_QUEUE) {
902 intr->ev_buffer_put = 0;
903 }
904 return;
905 }
906
907 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
908 if (erdp < intr->er_start ||
909 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
910 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
911 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
912 v, intr->er_start, intr->er_size);
913 xhci_die(xhci);
914 return;
915 }
916
917 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
918 assert(dp_idx < intr->er_size);
919
920 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
921 DPRINTF("xhci_event(): ER full, queueing\n");
922 #ifndef ER_FULL_HACK
923 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
924 xhci_write_event(xhci, &full);
925 #endif
926 intr->er_full = 1;
927 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
928 fprintf(stderr, "xhci: event queue full, dropping event!\n");
929 return;
930 }
931 intr->ev_buffer[intr->ev_buffer_put++] = *event;
932 if (intr->ev_buffer_put == EV_QUEUE) {
933 intr->ev_buffer_put = 0;
934 }
935 } else {
936 xhci_write_event(xhci, event, v);
937 }
938
939 xhci_intr_raise(xhci, v);
940 }
941
942 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
943 dma_addr_t base)
944 {
945 ring->dequeue = base;
946 ring->ccs = 1;
947 }
948
949 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
950 dma_addr_t *addr)
951 {
952 while (1) {
953 TRBType type;
954 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
955 trb->addr = ring->dequeue;
956 trb->ccs = ring->ccs;
957 le64_to_cpus(&trb->parameter);
958 le32_to_cpus(&trb->status);
959 le32_to_cpus(&trb->control);
960
961 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
962 trb->parameter, trb->status, trb->control);
963
964 if ((trb->control & TRB_C) != ring->ccs) {
965 return 0;
966 }
967
968 type = TRB_TYPE(*trb);
969
970 if (type != TR_LINK) {
971 if (addr) {
972 *addr = ring->dequeue;
973 }
974 ring->dequeue += TRB_SIZE;
975 return type;
976 } else {
977 ring->dequeue = xhci_mask64(trb->parameter);
978 if (trb->control & TRB_LK_TC) {
979 ring->ccs = !ring->ccs;
980 }
981 }
982 }
983 }
984
985 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
986 {
987 XHCITRB trb;
988 int length = 0;
989 dma_addr_t dequeue = ring->dequeue;
990 bool ccs = ring->ccs;
991 /* hack to bundle together the two/three TDs that make a setup transfer */
992 bool control_td_set = 0;
993
994 while (1) {
995 TRBType type;
996 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
997 le64_to_cpus(&trb.parameter);
998 le32_to_cpus(&trb.status);
999 le32_to_cpus(&trb.control);
1000
1001 if ((trb.control & TRB_C) != ccs) {
1002 return -length;
1003 }
1004
1005 type = TRB_TYPE(trb);
1006
1007 if (type == TR_LINK) {
1008 dequeue = xhci_mask64(trb.parameter);
1009 if (trb.control & TRB_LK_TC) {
1010 ccs = !ccs;
1011 }
1012 continue;
1013 }
1014
1015 length += 1;
1016 dequeue += TRB_SIZE;
1017
1018 if (type == TR_SETUP) {
1019 control_td_set = 1;
1020 } else if (type == TR_STATUS) {
1021 control_td_set = 0;
1022 }
1023
1024 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1025 return length;
1026 }
1027 }
1028 }
1029
1030 static void xhci_er_reset(XHCIState *xhci, int v)
1031 {
1032 XHCIInterrupter *intr = &xhci->intr[v];
1033 XHCIEvRingSeg seg;
1034
1035 if (intr->erstsz == 0) {
1036 /* disabled */
1037 intr->er_start = 0;
1038 intr->er_size = 0;
1039 return;
1040 }
1041 /* cache the (sole) event ring segment location */
1042 if (intr->erstsz != 1) {
1043 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1044 xhci_die(xhci);
1045 return;
1046 }
1047 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1048 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
1049 le32_to_cpus(&seg.addr_low);
1050 le32_to_cpus(&seg.addr_high);
1051 le32_to_cpus(&seg.size);
1052 if (seg.size < 16 || seg.size > 4096) {
1053 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
1054 xhci_die(xhci);
1055 return;
1056 }
1057 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1058 intr->er_size = seg.size;
1059
1060 intr->er_ep_idx = 0;
1061 intr->er_pcs = 1;
1062 intr->er_full = 0;
1063
1064 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1065 v, intr->er_start, intr->er_size);
1066 }
1067
1068 static void xhci_run(XHCIState *xhci)
1069 {
1070 trace_usb_xhci_run();
1071 xhci->usbsts &= ~USBSTS_HCH;
1072 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
1073 }
1074
1075 static void xhci_stop(XHCIState *xhci)
1076 {
1077 trace_usb_xhci_stop();
1078 xhci->usbsts |= USBSTS_HCH;
1079 xhci->crcr_low &= ~CRCR_CRR;
1080 }
1081
1082 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1083 dma_addr_t base)
1084 {
1085 XHCIStreamContext *stctx;
1086 unsigned int i;
1087
1088 stctx = g_new0(XHCIStreamContext, count);
1089 for (i = 0; i < count; i++) {
1090 stctx[i].pctx = base + i * 16;
1091 stctx[i].sct = -1;
1092 }
1093 return stctx;
1094 }
1095
1096 static void xhci_reset_streams(XHCIEPContext *epctx)
1097 {
1098 unsigned int i;
1099
1100 for (i = 0; i < epctx->nr_pstreams; i++) {
1101 epctx->pstreams[i].sct = -1;
1102 g_free(epctx->pstreams[i].sstreams);
1103 }
1104 }
1105
1106 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1107 {
1108 assert(epctx->pstreams == NULL);
1109 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1110 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1111 }
1112
1113 static void xhci_free_streams(XHCIEPContext *epctx)
1114 {
1115 int i;
1116
1117 assert(epctx->pstreams != NULL);
1118
1119 if (!epctx->lsa) {
1120 for (i = 0; i < epctx->nr_pstreams; i++) {
1121 g_free(epctx->pstreams[i].sstreams);
1122 }
1123 }
1124 g_free(epctx->pstreams);
1125 epctx->pstreams = NULL;
1126 epctx->nr_pstreams = 0;
1127 }
1128
1129 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1130 unsigned int streamid,
1131 uint32_t *cc_error)
1132 {
1133 XHCIStreamContext *sctx;
1134 dma_addr_t base;
1135 uint32_t ctx[2], sct;
1136
1137 assert(streamid != 0);
1138 if (epctx->lsa) {
1139 if (streamid >= epctx->nr_pstreams) {
1140 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1141 return NULL;
1142 }
1143 sctx = epctx->pstreams + streamid;
1144 } else {
1145 FIXME("secondary streams not implemented yet");
1146 }
1147
1148 if (sctx->sct == -1) {
1149 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1150 fprintf(stderr, "%s: init sctx #%d @ " DMA_ADDR_FMT ": %08x %08x\n",
1151 __func__, streamid, sctx->pctx, ctx[0], ctx[1]);
1152 sct = (ctx[0] >> 1) & 0x07;
1153 if (epctx->lsa && sct != 1) {
1154 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1155 return NULL;
1156 }
1157 sctx->sct = sct;
1158 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1159 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1160 }
1161 return sctx;
1162 }
1163
1164 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1165 XHCIStreamContext *sctx, uint32_t state)
1166 {
1167 uint32_t ctx[5];
1168 uint32_t ctx2[2];
1169
1170 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1171 ctx[0] &= ~EP_STATE_MASK;
1172 ctx[0] |= state;
1173
1174 /* update ring dequeue ptr */
1175 if (epctx->nr_pstreams) {
1176 if (sctx != NULL) {
1177 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1178 ctx2[0] &= 0xe;
1179 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1180 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1181 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1182 }
1183 } else {
1184 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
1185 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
1186 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1187 epctx->pctx, state, ctx[3], ctx[2]);
1188 }
1189
1190 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1191 epctx->state = state;
1192 }
1193
1194 static void xhci_ep_kick_timer(void *opaque)
1195 {
1196 XHCIEPContext *epctx = opaque;
1197 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1198 }
1199
1200 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1201 unsigned int epid, dma_addr_t pctx,
1202 uint32_t *ctx)
1203 {
1204 XHCISlot *slot;
1205 XHCIEPContext *epctx;
1206 dma_addr_t dequeue;
1207 int i;
1208
1209 trace_usb_xhci_ep_enable(slotid, epid);
1210 assert(slotid >= 1 && slotid <= xhci->numslots);
1211 assert(epid >= 1 && epid <= 31);
1212
1213 slot = &xhci->slots[slotid-1];
1214 if (slot->eps[epid-1]) {
1215 xhci_disable_ep(xhci, slotid, epid);
1216 }
1217
1218 epctx = g_malloc(sizeof(XHCIEPContext));
1219 memset(epctx, 0, sizeof(XHCIEPContext));
1220 epctx->xhci = xhci;
1221 epctx->slotid = slotid;
1222 epctx->epid = epid;
1223
1224 slot->eps[epid-1] = epctx;
1225
1226 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1227
1228 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1229 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
1230 epctx->pctx = pctx;
1231 epctx->max_psize = ctx[1]>>16;
1232 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1233 epctx->max_pstreams = (ctx[0] >> 10) & 0xf;
1234 epctx->lsa = (ctx[0] >> 15) & 1;
1235 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1236 epid/2, epid%2, epctx->max_psize);
1237 if (epctx->max_pstreams) {
1238 xhci_alloc_streams(epctx, dequeue);
1239 } else {
1240 xhci_ring_init(xhci, &epctx->ring, dequeue);
1241 epctx->ring.ccs = ctx[2] & 1;
1242 }
1243 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1244 usb_packet_init(&epctx->transfers[i].packet);
1245 }
1246
1247 epctx->interval = 1 << (ctx[0] >> 16) & 0xff;
1248 epctx->mfindex_last = 0;
1249 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx);
1250
1251 epctx->state = EP_RUNNING;
1252 ctx[0] &= ~EP_STATE_MASK;
1253 ctx[0] |= EP_RUNNING;
1254
1255 return CC_SUCCESS;
1256 }
1257
1258 static int xhci_ep_nuke_one_xfer(XHCITransfer *t)
1259 {
1260 int killed = 0;
1261
1262 if (t->running_async) {
1263 usb_cancel_packet(&t->packet);
1264 t->running_async = 0;
1265 t->cancelled = 1;
1266 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n");
1267 killed = 1;
1268 }
1269 if (t->running_retry) {
1270 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1271 if (epctx) {
1272 epctx->retry = NULL;
1273 qemu_del_timer(epctx->kick_timer);
1274 }
1275 t->running_retry = 0;
1276 }
1277 if (t->trbs) {
1278 g_free(t->trbs);
1279 }
1280
1281 t->trbs = NULL;
1282 t->trb_count = t->trb_alloced = 0;
1283
1284 return killed;
1285 }
1286
1287 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1288 unsigned int epid)
1289 {
1290 XHCISlot *slot;
1291 XHCIEPContext *epctx;
1292 int i, xferi, killed = 0;
1293 USBEndpoint *ep = NULL;
1294 assert(slotid >= 1 && slotid <= xhci->numslots);
1295 assert(epid >= 1 && epid <= 31);
1296
1297 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1298
1299 slot = &xhci->slots[slotid-1];
1300
1301 if (!slot->eps[epid-1]) {
1302 return 0;
1303 }
1304
1305 epctx = slot->eps[epid-1];
1306
1307 xferi = epctx->next_xfer;
1308 for (i = 0; i < TD_QUEUE; i++) {
1309 if (epctx->transfers[xferi].packet.ep) {
1310 ep = epctx->transfers[xferi].packet.ep;
1311 }
1312 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]);
1313 epctx->transfers[xferi].packet.ep = NULL;
1314 xferi = (xferi + 1) % TD_QUEUE;
1315 }
1316 if (ep) {
1317 usb_device_ep_stopped(ep->dev, ep);
1318 }
1319 return killed;
1320 }
1321
1322 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1323 unsigned int epid)
1324 {
1325 XHCISlot *slot;
1326 XHCIEPContext *epctx;
1327
1328 trace_usb_xhci_ep_disable(slotid, epid);
1329 assert(slotid >= 1 && slotid <= xhci->numslots);
1330 assert(epid >= 1 && epid <= 31);
1331
1332 slot = &xhci->slots[slotid-1];
1333
1334 if (!slot->eps[epid-1]) {
1335 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1336 return CC_SUCCESS;
1337 }
1338
1339 xhci_ep_nuke_xfers(xhci, slotid, epid);
1340
1341 epctx = slot->eps[epid-1];
1342
1343 if (epctx->nr_pstreams) {
1344 xhci_free_streams(epctx);
1345 }
1346
1347 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1348
1349 qemu_free_timer(epctx->kick_timer);
1350 g_free(epctx);
1351 slot->eps[epid-1] = NULL;
1352
1353 return CC_SUCCESS;
1354 }
1355
1356 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1357 unsigned int epid)
1358 {
1359 XHCISlot *slot;
1360 XHCIEPContext *epctx;
1361
1362 trace_usb_xhci_ep_stop(slotid, epid);
1363 assert(slotid >= 1 && slotid <= xhci->numslots);
1364
1365 if (epid < 1 || epid > 31) {
1366 fprintf(stderr, "xhci: bad ep %d\n", epid);
1367 return CC_TRB_ERROR;
1368 }
1369
1370 slot = &xhci->slots[slotid-1];
1371
1372 if (!slot->eps[epid-1]) {
1373 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1374 return CC_EP_NOT_ENABLED_ERROR;
1375 }
1376
1377 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1378 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1379 "data might be lost\n");
1380 }
1381
1382 epctx = slot->eps[epid-1];
1383
1384 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1385
1386 if (epctx->nr_pstreams) {
1387 xhci_reset_streams(epctx);
1388 }
1389
1390 return CC_SUCCESS;
1391 }
1392
1393 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1394 unsigned int epid)
1395 {
1396 XHCISlot *slot;
1397 XHCIEPContext *epctx;
1398 USBDevice *dev;
1399
1400 trace_usb_xhci_ep_reset(slotid, epid);
1401 assert(slotid >= 1 && slotid <= xhci->numslots);
1402
1403 if (epid < 1 || epid > 31) {
1404 fprintf(stderr, "xhci: bad ep %d\n", epid);
1405 return CC_TRB_ERROR;
1406 }
1407
1408 slot = &xhci->slots[slotid-1];
1409
1410 if (!slot->eps[epid-1]) {
1411 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1412 return CC_EP_NOT_ENABLED_ERROR;
1413 }
1414
1415 epctx = slot->eps[epid-1];
1416
1417 if (epctx->state != EP_HALTED) {
1418 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1419 epid, epctx->state);
1420 return CC_CONTEXT_STATE_ERROR;
1421 }
1422
1423 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1424 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1425 "data might be lost\n");
1426 }
1427
1428 uint8_t ep = epid>>1;
1429
1430 if (epid & 1) {
1431 ep |= 0x80;
1432 }
1433
1434 dev = xhci->slots[slotid-1].uport->dev;
1435 if (!dev) {
1436 return CC_USB_TRANSACTION_ERROR;
1437 }
1438
1439 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1440
1441 if (epctx->nr_pstreams) {
1442 xhci_reset_streams(epctx);
1443 }
1444
1445 return CC_SUCCESS;
1446 }
1447
1448 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1449 unsigned int epid, unsigned int streamid,
1450 uint64_t pdequeue)
1451 {
1452 XHCISlot *slot;
1453 XHCIEPContext *epctx;
1454 XHCIStreamContext *sctx;
1455 dma_addr_t dequeue;
1456
1457 assert(slotid >= 1 && slotid <= xhci->numslots);
1458
1459 if (epid < 1 || epid > 31) {
1460 fprintf(stderr, "xhci: bad ep %d\n", epid);
1461 return CC_TRB_ERROR;
1462 }
1463
1464 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1465 dequeue = xhci_mask64(pdequeue);
1466
1467 slot = &xhci->slots[slotid-1];
1468
1469 if (!slot->eps[epid-1]) {
1470 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1471 return CC_EP_NOT_ENABLED_ERROR;
1472 }
1473
1474 epctx = slot->eps[epid-1];
1475
1476 if (epctx->state != EP_STOPPED) {
1477 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1478 return CC_CONTEXT_STATE_ERROR;
1479 }
1480
1481 if (epctx->nr_pstreams) {
1482 uint32_t err;
1483 sctx = xhci_find_stream(epctx, streamid, &err);
1484 if (sctx == NULL) {
1485 return err;
1486 }
1487 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1488 sctx->ring.ccs = dequeue & 1;
1489 } else {
1490 sctx = NULL;
1491 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1492 epctx->ring.ccs = dequeue & 1;
1493 }
1494
1495 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1496
1497 return CC_SUCCESS;
1498 }
1499
1500 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1501 {
1502 XHCIState *xhci = xfer->xhci;
1503 int i;
1504
1505 xfer->int_req = false;
1506 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
1507 for (i = 0; i < xfer->trb_count; i++) {
1508 XHCITRB *trb = &xfer->trbs[i];
1509 dma_addr_t addr;
1510 unsigned int chunk = 0;
1511
1512 if (trb->control & TRB_TR_IOC) {
1513 xfer->int_req = true;
1514 }
1515
1516 switch (TRB_TYPE(*trb)) {
1517 case TR_DATA:
1518 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1519 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1520 goto err;
1521 }
1522 /* fallthrough */
1523 case TR_NORMAL:
1524 case TR_ISOCH:
1525 addr = xhci_mask64(trb->parameter);
1526 chunk = trb->status & 0x1ffff;
1527 if (trb->control & TRB_TR_IDT) {
1528 if (chunk > 8 || in_xfer) {
1529 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1530 goto err;
1531 }
1532 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1533 } else {
1534 qemu_sglist_add(&xfer->sgl, addr, chunk);
1535 }
1536 break;
1537 }
1538 }
1539
1540 return 0;
1541
1542 err:
1543 qemu_sglist_destroy(&xfer->sgl);
1544 xhci_die(xhci);
1545 return -1;
1546 }
1547
1548 static void xhci_xfer_unmap(XHCITransfer *xfer)
1549 {
1550 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1551 qemu_sglist_destroy(&xfer->sgl);
1552 }
1553
1554 static void xhci_xfer_report(XHCITransfer *xfer)
1555 {
1556 uint32_t edtla = 0;
1557 unsigned int left;
1558 bool reported = 0;
1559 bool shortpkt = 0;
1560 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1561 XHCIState *xhci = xfer->xhci;
1562 int i;
1563
1564 left = xfer->packet.actual_length;
1565
1566 for (i = 0; i < xfer->trb_count; i++) {
1567 XHCITRB *trb = &xfer->trbs[i];
1568 unsigned int chunk = 0;
1569
1570 switch (TRB_TYPE(*trb)) {
1571 case TR_DATA:
1572 case TR_NORMAL:
1573 case TR_ISOCH:
1574 chunk = trb->status & 0x1ffff;
1575 if (chunk > left) {
1576 chunk = left;
1577 if (xfer->status == CC_SUCCESS) {
1578 shortpkt = 1;
1579 }
1580 }
1581 left -= chunk;
1582 edtla += chunk;
1583 break;
1584 case TR_STATUS:
1585 reported = 0;
1586 shortpkt = 0;
1587 break;
1588 }
1589
1590 if (!reported && ((trb->control & TRB_TR_IOC) ||
1591 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1592 (xfer->status != CC_SUCCESS && left == 0))) {
1593 event.slotid = xfer->slotid;
1594 event.epid = xfer->epid;
1595 event.length = (trb->status & 0x1ffff) - chunk;
1596 event.flags = 0;
1597 event.ptr = trb->addr;
1598 if (xfer->status == CC_SUCCESS) {
1599 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1600 } else {
1601 event.ccode = xfer->status;
1602 }
1603 if (TRB_TYPE(*trb) == TR_EVDATA) {
1604 event.ptr = trb->parameter;
1605 event.flags |= TRB_EV_ED;
1606 event.length = edtla & 0xffffff;
1607 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1608 edtla = 0;
1609 }
1610 xhci_event(xhci, &event, TRB_INTR(*trb));
1611 reported = 1;
1612 if (xfer->status != CC_SUCCESS) {
1613 return;
1614 }
1615 }
1616 }
1617 }
1618
1619 static void xhci_stall_ep(XHCITransfer *xfer)
1620 {
1621 XHCIState *xhci = xfer->xhci;
1622 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1623 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1624 uint32_t err;
1625 XHCIStreamContext *sctx;
1626
1627 if (epctx->nr_pstreams) {
1628 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1629 if (sctx == NULL) {
1630 return;
1631 }
1632 sctx->ring.dequeue = xfer->trbs[0].addr;
1633 sctx->ring.ccs = xfer->trbs[0].ccs;
1634 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1635 } else {
1636 epctx->ring.dequeue = xfer->trbs[0].addr;
1637 epctx->ring.ccs = xfer->trbs[0].ccs;
1638 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1639 }
1640 }
1641
1642 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1643 XHCIEPContext *epctx);
1644
1645 static int xhci_setup_packet(XHCITransfer *xfer)
1646 {
1647 XHCIState *xhci = xfer->xhci;
1648 USBDevice *dev;
1649 USBEndpoint *ep;
1650 int dir;
1651
1652 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1653
1654 if (xfer->packet.ep) {
1655 ep = xfer->packet.ep;
1656 dev = ep->dev;
1657 } else {
1658 if (!xhci->slots[xfer->slotid-1].uport) {
1659 fprintf(stderr, "xhci: slot %d has no device\n",
1660 xfer->slotid);
1661 return -1;
1662 }
1663 dev = xhci->slots[xfer->slotid-1].uport->dev;
1664 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1665 }
1666
1667 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1668 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1669 xfer->trbs[0].addr, false, xfer->int_req);
1670 usb_packet_map(&xfer->packet, &xfer->sgl);
1671 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1672 xfer->packet.pid, dev->addr, ep->nr);
1673 return 0;
1674 }
1675
1676 static int xhci_complete_packet(XHCITransfer *xfer)
1677 {
1678 if (xfer->packet.status == USB_RET_ASYNC) {
1679 trace_usb_xhci_xfer_async(xfer);
1680 xfer->running_async = 1;
1681 xfer->running_retry = 0;
1682 xfer->complete = 0;
1683 xfer->cancelled = 0;
1684 return 0;
1685 } else if (xfer->packet.status == USB_RET_NAK) {
1686 trace_usb_xhci_xfer_nak(xfer);
1687 xfer->running_async = 0;
1688 xfer->running_retry = 1;
1689 xfer->complete = 0;
1690 xfer->cancelled = 0;
1691 return 0;
1692 } else {
1693 xfer->running_async = 0;
1694 xfer->running_retry = 0;
1695 xfer->complete = 1;
1696 xhci_xfer_unmap(xfer);
1697 }
1698
1699 if (xfer->packet.status == USB_RET_SUCCESS) {
1700 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1701 xfer->status = CC_SUCCESS;
1702 xhci_xfer_report(xfer);
1703 return 0;
1704 }
1705
1706 /* error */
1707 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1708 switch (xfer->packet.status) {
1709 case USB_RET_NODEV:
1710 xfer->status = CC_USB_TRANSACTION_ERROR;
1711 xhci_xfer_report(xfer);
1712 xhci_stall_ep(xfer);
1713 break;
1714 case USB_RET_STALL:
1715 xfer->status = CC_STALL_ERROR;
1716 xhci_xfer_report(xfer);
1717 xhci_stall_ep(xfer);
1718 break;
1719 default:
1720 fprintf(stderr, "%s: FIXME: status = %d\n", __func__,
1721 xfer->packet.status);
1722 FIXME("unhandled USB_RET_*");
1723 }
1724 return 0;
1725 }
1726
1727 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1728 {
1729 XHCITRB *trb_setup, *trb_status;
1730 uint8_t bmRequestType;
1731
1732 trb_setup = &xfer->trbs[0];
1733 trb_status = &xfer->trbs[xfer->trb_count-1];
1734
1735 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1736
1737 /* at most one Event Data TRB allowed after STATUS */
1738 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1739 trb_status--;
1740 }
1741
1742 /* do some sanity checks */
1743 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1744 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1745 TRB_TYPE(*trb_setup));
1746 return -1;
1747 }
1748 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1749 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1750 TRB_TYPE(*trb_status));
1751 return -1;
1752 }
1753 if (!(trb_setup->control & TRB_TR_IDT)) {
1754 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1755 return -1;
1756 }
1757 if ((trb_setup->status & 0x1ffff) != 8) {
1758 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1759 (trb_setup->status & 0x1ffff));
1760 return -1;
1761 }
1762
1763 bmRequestType = trb_setup->parameter;
1764
1765 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1766 xfer->iso_xfer = false;
1767
1768 if (xhci_setup_packet(xfer) < 0) {
1769 return -1;
1770 }
1771 xfer->packet.parameter = trb_setup->parameter;
1772
1773 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1774
1775 xhci_complete_packet(xfer);
1776 if (!xfer->running_async && !xfer->running_retry) {
1777 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1778 }
1779 return 0;
1780 }
1781
1782 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1783 XHCIEPContext *epctx, uint64_t mfindex)
1784 {
1785 if (xfer->trbs[0].control & TRB_TR_SIA) {
1786 uint64_t asap = ((mfindex + epctx->interval - 1) &
1787 ~(epctx->interval-1));
1788 if (asap >= epctx->mfindex_last &&
1789 asap <= epctx->mfindex_last + epctx->interval * 4) {
1790 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1791 } else {
1792 xfer->mfindex_kick = asap;
1793 }
1794 } else {
1795 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1796 & TRB_TR_FRAMEID_MASK;
1797 xfer->mfindex_kick |= mfindex & ~0x3fff;
1798 if (xfer->mfindex_kick < mfindex) {
1799 xfer->mfindex_kick += 0x4000;
1800 }
1801 }
1802 }
1803
1804 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1805 XHCIEPContext *epctx, uint64_t mfindex)
1806 {
1807 if (xfer->mfindex_kick > mfindex) {
1808 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) +
1809 (xfer->mfindex_kick - mfindex) * 125000);
1810 xfer->running_retry = 1;
1811 } else {
1812 epctx->mfindex_last = xfer->mfindex_kick;
1813 qemu_del_timer(epctx->kick_timer);
1814 xfer->running_retry = 0;
1815 }
1816 }
1817
1818
1819 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1820 {
1821 uint64_t mfindex;
1822
1823 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1824
1825 xfer->in_xfer = epctx->type>>2;
1826
1827 switch(epctx->type) {
1828 case ET_INTR_OUT:
1829 case ET_INTR_IN:
1830 case ET_BULK_OUT:
1831 case ET_BULK_IN:
1832 xfer->pkts = 0;
1833 xfer->iso_xfer = false;
1834 break;
1835 case ET_ISO_OUT:
1836 case ET_ISO_IN:
1837 xfer->pkts = 1;
1838 xfer->iso_xfer = true;
1839 mfindex = xhci_mfindex_get(xhci);
1840 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1841 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1842 if (xfer->running_retry) {
1843 return -1;
1844 }
1845 break;
1846 default:
1847 fprintf(stderr, "xhci: unknown or unhandled EP "
1848 "(type %d, in %d, ep %02x)\n",
1849 epctx->type, xfer->in_xfer, xfer->epid);
1850 return -1;
1851 }
1852
1853 if (xhci_setup_packet(xfer) < 0) {
1854 return -1;
1855 }
1856 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1857
1858 xhci_complete_packet(xfer);
1859 if (!xfer->running_async && !xfer->running_retry) {
1860 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
1861 }
1862 return 0;
1863 }
1864
1865 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1866 {
1867 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1868 return xhci_submit(xhci, xfer, epctx);
1869 }
1870
1871 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1872 unsigned int epid, unsigned int streamid)
1873 {
1874 XHCIStreamContext *stctx;
1875 XHCIEPContext *epctx;
1876 XHCIRing *ring;
1877 USBEndpoint *ep = NULL;
1878 uint64_t mfindex;
1879 int length;
1880 int i;
1881
1882 trace_usb_xhci_ep_kick(slotid, epid, streamid);
1883 assert(slotid >= 1 && slotid <= xhci->numslots);
1884 assert(epid >= 1 && epid <= 31);
1885
1886 if (!xhci->slots[slotid-1].enabled) {
1887 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1888 return;
1889 }
1890 epctx = xhci->slots[slotid-1].eps[epid-1];
1891 if (!epctx) {
1892 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1893 epid, slotid);
1894 return;
1895 }
1896
1897 if (epctx->retry) {
1898 XHCITransfer *xfer = epctx->retry;
1899
1900 trace_usb_xhci_xfer_retry(xfer);
1901 assert(xfer->running_retry);
1902 if (xfer->iso_xfer) {
1903 /* retry delayed iso transfer */
1904 mfindex = xhci_mfindex_get(xhci);
1905 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1906 if (xfer->running_retry) {
1907 return;
1908 }
1909 if (xhci_setup_packet(xfer) < 0) {
1910 return;
1911 }
1912 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1913 assert(xfer->packet.status != USB_RET_NAK);
1914 xhci_complete_packet(xfer);
1915 } else {
1916 /* retry nak'ed transfer */
1917 if (xhci_setup_packet(xfer) < 0) {
1918 return;
1919 }
1920 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1921 if (xfer->packet.status == USB_RET_NAK) {
1922 return;
1923 }
1924 xhci_complete_packet(xfer);
1925 }
1926 assert(!xfer->running_retry);
1927 epctx->retry = NULL;
1928 }
1929
1930 if (epctx->state == EP_HALTED) {
1931 DPRINTF("xhci: ep halted, not running schedule\n");
1932 return;
1933 }
1934
1935
1936 if (epctx->nr_pstreams) {
1937 uint32_t err;
1938 stctx = xhci_find_stream(epctx, streamid, &err);
1939 if (stctx == NULL) {
1940 return;
1941 }
1942 ring = &stctx->ring;
1943 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1944 } else {
1945 ring = &epctx->ring;
1946 streamid = 0;
1947 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1948 }
1949 assert(ring->dequeue != 0);
1950
1951 while (1) {
1952 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1953 if (xfer->running_async || xfer->running_retry) {
1954 break;
1955 }
1956 length = xhci_ring_chain_length(xhci, ring);
1957 if (length < 0) {
1958 break;
1959 } else if (length == 0) {
1960 break;
1961 }
1962 if (xfer->trbs && xfer->trb_alloced < length) {
1963 xfer->trb_count = 0;
1964 xfer->trb_alloced = 0;
1965 g_free(xfer->trbs);
1966 xfer->trbs = NULL;
1967 }
1968 if (!xfer->trbs) {
1969 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1970 xfer->trb_alloced = length;
1971 }
1972 xfer->trb_count = length;
1973
1974 for (i = 0; i < length; i++) {
1975 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL));
1976 }
1977 xfer->xhci = xhci;
1978 xfer->epid = epid;
1979 xfer->slotid = slotid;
1980 xfer->streamid = streamid;
1981
1982 if (epid == 1) {
1983 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1984 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1985 ep = xfer->packet.ep;
1986 } else {
1987 fprintf(stderr, "xhci: error firing CTL transfer\n");
1988 }
1989 } else {
1990 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1991 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1992 ep = xfer->packet.ep;
1993 } else {
1994 if (!xfer->iso_xfer) {
1995 fprintf(stderr, "xhci: error firing data transfer\n");
1996 }
1997 }
1998 }
1999
2000 if (epctx->state == EP_HALTED) {
2001 break;
2002 }
2003 if (xfer->running_retry) {
2004 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2005 epctx->retry = xfer;
2006 break;
2007 }
2008 }
2009 if (ep) {
2010 usb_device_flush_ep_queue(ep->dev, ep);
2011 }
2012 }
2013
2014 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2015 {
2016 trace_usb_xhci_slot_enable(slotid);
2017 assert(slotid >= 1 && slotid <= xhci->numslots);
2018 xhci->slots[slotid-1].enabled = 1;
2019 xhci->slots[slotid-1].uport = NULL;
2020 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2021
2022 return CC_SUCCESS;
2023 }
2024
2025 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2026 {
2027 int i;
2028
2029 trace_usb_xhci_slot_disable(slotid);
2030 assert(slotid >= 1 && slotid <= xhci->numslots);
2031
2032 for (i = 1; i <= 31; i++) {
2033 if (xhci->slots[slotid-1].eps[i-1]) {
2034 xhci_disable_ep(xhci, slotid, i);
2035 }
2036 }
2037
2038 xhci->slots[slotid-1].enabled = 0;
2039 return CC_SUCCESS;
2040 }
2041
2042 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2043 {
2044 USBPort *uport;
2045 char path[32];
2046 int i, pos, port;
2047
2048 port = (slot_ctx[1]>>16) & 0xFF;
2049 port = xhci->ports[port-1].uport->index+1;
2050 pos = snprintf(path, sizeof(path), "%d", port);
2051 for (i = 0; i < 5; i++) {
2052 port = (slot_ctx[0] >> 4*i) & 0x0f;
2053 if (!port) {
2054 break;
2055 }
2056 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2057 }
2058
2059 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2060 if (strcmp(uport->path, path) == 0) {
2061 return uport;
2062 }
2063 }
2064 return NULL;
2065 }
2066
2067 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2068 uint64_t pictx, bool bsr)
2069 {
2070 XHCISlot *slot;
2071 USBPort *uport;
2072 USBDevice *dev;
2073 dma_addr_t ictx, octx, dcbaap;
2074 uint64_t poctx;
2075 uint32_t ictl_ctx[2];
2076 uint32_t slot_ctx[4];
2077 uint32_t ep0_ctx[5];
2078 int i;
2079 TRBCCode res;
2080
2081 trace_usb_xhci_slot_address(slotid);
2082 assert(slotid >= 1 && slotid <= xhci->numslots);
2083
2084 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2085 poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid);
2086 ictx = xhci_mask64(pictx);
2087 octx = xhci_mask64(poctx);
2088
2089 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2090 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2091
2092 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2093
2094 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2095 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2096 ictl_ctx[0], ictl_ctx[1]);
2097 return CC_TRB_ERROR;
2098 }
2099
2100 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2101 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2102
2103 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2104 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2105
2106 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2107 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2108
2109 uport = xhci_lookup_uport(xhci, slot_ctx);
2110 if (uport == NULL) {
2111 fprintf(stderr, "xhci: port not found\n");
2112 return CC_TRB_ERROR;
2113 }
2114
2115 dev = uport->dev;
2116 if (!dev) {
2117 fprintf(stderr, "xhci: port %s not connected\n", uport->path);
2118 return CC_USB_TRANSACTION_ERROR;
2119 }
2120
2121 for (i = 0; i < xhci->numslots; i++) {
2122 if (i == slotid-1) {
2123 continue;
2124 }
2125 if (xhci->slots[i].uport == uport) {
2126 fprintf(stderr, "xhci: port %s already assigned to slot %d\n",
2127 uport->path, i+1);
2128 return CC_TRB_ERROR;
2129 }
2130 }
2131
2132 slot = &xhci->slots[slotid-1];
2133 slot->uport = uport;
2134 slot->ctx = octx;
2135
2136 if (bsr) {
2137 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2138 } else {
2139 USBPacket p;
2140 uint8_t buf[1];
2141
2142 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2143 usb_device_reset(dev);
2144 memset(&p, 0, sizeof(p));
2145 usb_packet_addbuf(&p, buf, sizeof(buf));
2146 usb_packet_setup(&p, USB_TOKEN_OUT,
2147 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2148 0, false, false);
2149 usb_device_handle_control(dev, &p,
2150 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2151 slotid, 0, 0, NULL);
2152 assert(p.status != USB_RET_ASYNC);
2153 }
2154
2155 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2156
2157 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2158 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2159 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2160 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2161
2162 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2163 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2164
2165 return res;
2166 }
2167
2168
2169 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2170 uint64_t pictx, bool dc)
2171 {
2172 dma_addr_t ictx, octx;
2173 uint32_t ictl_ctx[2];
2174 uint32_t slot_ctx[4];
2175 uint32_t islot_ctx[4];
2176 uint32_t ep_ctx[5];
2177 int i;
2178 TRBCCode res;
2179
2180 trace_usb_xhci_slot_configure(slotid);
2181 assert(slotid >= 1 && slotid <= xhci->numslots);
2182
2183 ictx = xhci_mask64(pictx);
2184 octx = xhci->slots[slotid-1].ctx;
2185
2186 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2187 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2188
2189 if (dc) {
2190 for (i = 2; i <= 31; i++) {
2191 if (xhci->slots[slotid-1].eps[i-1]) {
2192 xhci_disable_ep(xhci, slotid, i);
2193 }
2194 }
2195
2196 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2197 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2198 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2199 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2200 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2201 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2202
2203 return CC_SUCCESS;
2204 }
2205
2206 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2207
2208 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2209 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2210 ictl_ctx[0], ictl_ctx[1]);
2211 return CC_TRB_ERROR;
2212 }
2213
2214 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2215 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2216
2217 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2218 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
2219 return CC_CONTEXT_STATE_ERROR;
2220 }
2221
2222 for (i = 2; i <= 31; i++) {
2223 if (ictl_ctx[0] & (1<<i)) {
2224 xhci_disable_ep(xhci, slotid, i);
2225 }
2226 if (ictl_ctx[1] & (1<<i)) {
2227 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2228 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2229 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2230 ep_ctx[3], ep_ctx[4]);
2231 xhci_disable_ep(xhci, slotid, i);
2232 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2233 if (res != CC_SUCCESS) {
2234 return res;
2235 }
2236 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2237 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2238 ep_ctx[3], ep_ctx[4]);
2239 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2240 }
2241 }
2242
2243 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2244 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2245 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2246 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2247 SLOT_CONTEXT_ENTRIES_SHIFT);
2248 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2249 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2250
2251 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2252
2253 return CC_SUCCESS;
2254 }
2255
2256
2257 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2258 uint64_t pictx)
2259 {
2260 dma_addr_t ictx, octx;
2261 uint32_t ictl_ctx[2];
2262 uint32_t iep0_ctx[5];
2263 uint32_t ep0_ctx[5];
2264 uint32_t islot_ctx[4];
2265 uint32_t slot_ctx[4];
2266
2267 trace_usb_xhci_slot_evaluate(slotid);
2268 assert(slotid >= 1 && slotid <= xhci->numslots);
2269
2270 ictx = xhci_mask64(pictx);
2271 octx = xhci->slots[slotid-1].ctx;
2272
2273 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2274 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2275
2276 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2277
2278 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2279 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2280 ictl_ctx[0], ictl_ctx[1]);
2281 return CC_TRB_ERROR;
2282 }
2283
2284 if (ictl_ctx[1] & 0x1) {
2285 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2286
2287 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2288 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2289
2290 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2291
2292 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2293 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2294 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2295 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2296
2297 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2298 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2299
2300 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2301 }
2302
2303 if (ictl_ctx[1] & 0x2) {
2304 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2305
2306 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2307 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2308 iep0_ctx[3], iep0_ctx[4]);
2309
2310 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2311
2312 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2313 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2314
2315 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2316 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2317
2318 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2319 }
2320
2321 return CC_SUCCESS;
2322 }
2323
2324 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2325 {
2326 uint32_t slot_ctx[4];
2327 dma_addr_t octx;
2328 int i;
2329
2330 trace_usb_xhci_slot_reset(slotid);
2331 assert(slotid >= 1 && slotid <= xhci->numslots);
2332
2333 octx = xhci->slots[slotid-1].ctx;
2334
2335 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2336
2337 for (i = 2; i <= 31; i++) {
2338 if (xhci->slots[slotid-1].eps[i-1]) {
2339 xhci_disable_ep(xhci, slotid, i);
2340 }
2341 }
2342
2343 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2344 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2345 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2346 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2347 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2348 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2349
2350 return CC_SUCCESS;
2351 }
2352
2353 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2354 {
2355 unsigned int slotid;
2356 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2357 if (slotid < 1 || slotid > xhci->numslots) {
2358 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2359 event->ccode = CC_TRB_ERROR;
2360 return 0;
2361 } else if (!xhci->slots[slotid-1].enabled) {
2362 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2363 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2364 return 0;
2365 }
2366 return slotid;
2367 }
2368
2369 /* cleanup slot state on usb device detach */
2370 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2371 {
2372 int slot, ep;
2373
2374 for (slot = 0; slot < xhci->numslots; slot++) {
2375 if (xhci->slots[slot].uport == uport) {
2376 break;
2377 }
2378 }
2379 if (slot == xhci->numslots) {
2380 return;
2381 }
2382
2383 for (ep = 0; ep < 31; ep++) {
2384 if (xhci->slots[slot].eps[ep]) {
2385 xhci_ep_nuke_xfers(xhci, slot+1, ep+1);
2386 }
2387 }
2388 xhci->slots[slot].uport = NULL;
2389 }
2390
2391 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2392 {
2393 dma_addr_t ctx;
2394 uint8_t bw_ctx[xhci->numports+1];
2395
2396 DPRINTF("xhci_get_port_bandwidth()\n");
2397
2398 ctx = xhci_mask64(pctx);
2399
2400 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2401
2402 /* TODO: actually implement real values here */
2403 bw_ctx[0] = 0;
2404 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2405 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
2406
2407 return CC_SUCCESS;
2408 }
2409
2410 static uint32_t rotl(uint32_t v, unsigned count)
2411 {
2412 count &= 31;
2413 return (v << count) | (v >> (32 - count));
2414 }
2415
2416
2417 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2418 {
2419 uint32_t val;
2420 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2421 val += rotl(lo + 0x49434878, hi & 0x1F);
2422 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2423 return ~val;
2424 }
2425
2426 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2427 {
2428 uint32_t buf[8];
2429 uint32_t obuf[8];
2430 dma_addr_t paddr = xhci_mask64(addr);
2431
2432 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
2433
2434 memcpy(obuf, buf, sizeof(obuf));
2435
2436 if ((buf[0] & 0xff) == 2) {
2437 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2438 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2439 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2440 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2441 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2442 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2443 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2444 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2445 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2446 }
2447
2448 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
2449 }
2450
2451 static void xhci_process_commands(XHCIState *xhci)
2452 {
2453 XHCITRB trb;
2454 TRBType type;
2455 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2456 dma_addr_t addr;
2457 unsigned int i, slotid = 0;
2458
2459 DPRINTF("xhci_process_commands()\n");
2460 if (!xhci_running(xhci)) {
2461 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2462 return;
2463 }
2464
2465 xhci->crcr_low |= CRCR_CRR;
2466
2467 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2468 event.ptr = addr;
2469 switch (type) {
2470 case CR_ENABLE_SLOT:
2471 for (i = 0; i < xhci->numslots; i++) {
2472 if (!xhci->slots[i].enabled) {
2473 break;
2474 }
2475 }
2476 if (i >= xhci->numslots) {
2477 fprintf(stderr, "xhci: no device slots available\n");
2478 event.ccode = CC_NO_SLOTS_ERROR;
2479 } else {
2480 slotid = i+1;
2481 event.ccode = xhci_enable_slot(xhci, slotid);
2482 }
2483 break;
2484 case CR_DISABLE_SLOT:
2485 slotid = xhci_get_slot(xhci, &event, &trb);
2486 if (slotid) {
2487 event.ccode = xhci_disable_slot(xhci, slotid);
2488 }
2489 break;
2490 case CR_ADDRESS_DEVICE:
2491 slotid = xhci_get_slot(xhci, &event, &trb);
2492 if (slotid) {
2493 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2494 trb.control & TRB_CR_BSR);
2495 }
2496 break;
2497 case CR_CONFIGURE_ENDPOINT:
2498 slotid = xhci_get_slot(xhci, &event, &trb);
2499 if (slotid) {
2500 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2501 trb.control & TRB_CR_DC);
2502 }
2503 break;
2504 case CR_EVALUATE_CONTEXT:
2505 slotid = xhci_get_slot(xhci, &event, &trb);
2506 if (slotid) {
2507 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2508 }
2509 break;
2510 case CR_STOP_ENDPOINT:
2511 slotid = xhci_get_slot(xhci, &event, &trb);
2512 if (slotid) {
2513 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2514 & TRB_CR_EPID_MASK;
2515 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2516 }
2517 break;
2518 case CR_RESET_ENDPOINT:
2519 slotid = xhci_get_slot(xhci, &event, &trb);
2520 if (slotid) {
2521 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2522 & TRB_CR_EPID_MASK;
2523 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2524 }
2525 break;
2526 case CR_SET_TR_DEQUEUE:
2527 slotid = xhci_get_slot(xhci, &event, &trb);
2528 if (slotid) {
2529 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2530 & TRB_CR_EPID_MASK;
2531 unsigned int streamid = (trb.status >> 16) & 0xffff;
2532 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2533 epid, streamid,
2534 trb.parameter);
2535 }
2536 break;
2537 case CR_RESET_DEVICE:
2538 slotid = xhci_get_slot(xhci, &event, &trb);
2539 if (slotid) {
2540 event.ccode = xhci_reset_slot(xhci, slotid);
2541 }
2542 break;
2543 case CR_GET_PORT_BANDWIDTH:
2544 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2545 break;
2546 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2547 xhci_via_challenge(xhci, trb.parameter);
2548 break;
2549 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2550 event.type = 48; /* NEC reply */
2551 event.length = 0x3025;
2552 break;
2553 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2554 {
2555 uint32_t chi = trb.parameter >> 32;
2556 uint32_t clo = trb.parameter;
2557 uint32_t val = xhci_nec_challenge(chi, clo);
2558 event.length = val & 0xFFFF;
2559 event.epid = val >> 16;
2560 slotid = val >> 24;
2561 event.type = 48; /* NEC reply */
2562 }
2563 break;
2564 default:
2565 trace_usb_xhci_unimplemented("command", type);
2566 event.ccode = CC_TRB_ERROR;
2567 break;
2568 }
2569 event.slotid = slotid;
2570 xhci_event(xhci, &event, 0);
2571 }
2572 }
2573
2574 static bool xhci_port_have_device(XHCIPort *port)
2575 {
2576 if (!port->uport->dev || !port->uport->dev->attached) {
2577 return false; /* no device present */
2578 }
2579 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2580 return false; /* speed mismatch */
2581 }
2582 return true;
2583 }
2584
2585 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2586 {
2587 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2588 port->portnr << 24 };
2589
2590 if ((port->portsc & bits) == bits) {
2591 return;
2592 }
2593 trace_usb_xhci_port_notify(port->portnr, bits);
2594 port->portsc |= bits;
2595 if (!xhci_running(port->xhci)) {
2596 return;
2597 }
2598 xhci_event(port->xhci, &ev, 0);
2599 }
2600
2601 static void xhci_port_update(XHCIPort *port, int is_detach)
2602 {
2603 uint32_t pls = PLS_RX_DETECT;
2604
2605 port->portsc = PORTSC_PP;
2606 if (!is_detach && xhci_port_have_device(port)) {
2607 port->portsc |= PORTSC_CCS;
2608 switch (port->uport->dev->speed) {
2609 case USB_SPEED_LOW:
2610 port->portsc |= PORTSC_SPEED_LOW;
2611 pls = PLS_POLLING;
2612 break;
2613 case USB_SPEED_FULL:
2614 port->portsc |= PORTSC_SPEED_FULL;
2615 pls = PLS_POLLING;
2616 break;
2617 case USB_SPEED_HIGH:
2618 port->portsc |= PORTSC_SPEED_HIGH;
2619 pls = PLS_POLLING;
2620 break;
2621 case USB_SPEED_SUPER:
2622 port->portsc |= PORTSC_SPEED_SUPER;
2623 port->portsc |= PORTSC_PED;
2624 pls = PLS_U0;
2625 break;
2626 }
2627 }
2628 set_field(&port->portsc, pls, PORTSC_PLS);
2629 trace_usb_xhci_port_link(port->portnr, pls);
2630 xhci_port_notify(port, PORTSC_CSC);
2631 }
2632
2633 static void xhci_port_reset(XHCIPort *port)
2634 {
2635 trace_usb_xhci_port_reset(port->portnr);
2636
2637 if (!xhci_port_have_device(port)) {
2638 return;
2639 }
2640
2641 usb_device_reset(port->uport->dev);
2642
2643 switch (port->uport->dev->speed) {
2644 case USB_SPEED_LOW:
2645 case USB_SPEED_FULL:
2646 case USB_SPEED_HIGH:
2647 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2648 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2649 port->portsc |= PORTSC_PED;
2650 break;
2651 }
2652
2653 port->portsc &= ~PORTSC_PR;
2654 xhci_port_notify(port, PORTSC_PRC);
2655 }
2656
2657 static void xhci_reset(DeviceState *dev)
2658 {
2659 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
2660 int i;
2661
2662 trace_usb_xhci_reset();
2663 if (!(xhci->usbsts & USBSTS_HCH)) {
2664 fprintf(stderr, "xhci: reset while running!\n");
2665 }
2666
2667 xhci->usbcmd = 0;
2668 xhci->usbsts = USBSTS_HCH;
2669 xhci->dnctrl = 0;
2670 xhci->crcr_low = 0;
2671 xhci->crcr_high = 0;
2672 xhci->dcbaap_low = 0;
2673 xhci->dcbaap_high = 0;
2674 xhci->config = 0;
2675
2676 for (i = 0; i < xhci->numslots; i++) {
2677 xhci_disable_slot(xhci, i+1);
2678 }
2679
2680 for (i = 0; i < xhci->numports; i++) {
2681 xhci_port_update(xhci->ports + i, 0);
2682 }
2683
2684 for (i = 0; i < xhci->numintrs; i++) {
2685 xhci->intr[i].iman = 0;
2686 xhci->intr[i].imod = 0;
2687 xhci->intr[i].erstsz = 0;
2688 xhci->intr[i].erstba_low = 0;
2689 xhci->intr[i].erstba_high = 0;
2690 xhci->intr[i].erdp_low = 0;
2691 xhci->intr[i].erdp_high = 0;
2692 xhci->intr[i].msix_used = 0;
2693
2694 xhci->intr[i].er_ep_idx = 0;
2695 xhci->intr[i].er_pcs = 1;
2696 xhci->intr[i].er_full = 0;
2697 xhci->intr[i].ev_buffer_put = 0;
2698 xhci->intr[i].ev_buffer_get = 0;
2699 }
2700
2701 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
2702 xhci_mfwrap_update(xhci);
2703 }
2704
2705 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2706 {
2707 XHCIState *xhci = ptr;
2708 uint32_t ret;
2709
2710 switch (reg) {
2711 case 0x00: /* HCIVERSION, CAPLENGTH */
2712 ret = 0x01000000 | LEN_CAP;
2713 break;
2714 case 0x04: /* HCSPARAMS 1 */
2715 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2716 | (xhci->numintrs<<8) | xhci->numslots;
2717 break;
2718 case 0x08: /* HCSPARAMS 2 */
2719 ret = 0x0000000f;
2720 break;
2721 case 0x0c: /* HCSPARAMS 3 */
2722 ret = 0x00000000;
2723 break;
2724 case 0x10: /* HCCPARAMS */
2725 if (sizeof(dma_addr_t) == 4) {
2726 ret = 0x00087000;
2727 } else {
2728 ret = 0x00087001;
2729 }
2730 break;
2731 case 0x14: /* DBOFF */
2732 ret = OFF_DOORBELL;
2733 break;
2734 case 0x18: /* RTSOFF */
2735 ret = OFF_RUNTIME;
2736 break;
2737
2738 /* extended capabilities */
2739 case 0x20: /* Supported Protocol:00 */
2740 ret = 0x02000402; /* USB 2.0 */
2741 break;
2742 case 0x24: /* Supported Protocol:04 */
2743 ret = 0x20425355; /* "USB " */
2744 break;
2745 case 0x28: /* Supported Protocol:08 */
2746 ret = 0x00000001 | (xhci->numports_2<<8);
2747 break;
2748 case 0x2c: /* Supported Protocol:0c */
2749 ret = 0x00000000; /* reserved */
2750 break;
2751 case 0x30: /* Supported Protocol:00 */
2752 ret = 0x03000002; /* USB 3.0 */
2753 break;
2754 case 0x34: /* Supported Protocol:04 */
2755 ret = 0x20425355; /* "USB " */
2756 break;
2757 case 0x38: /* Supported Protocol:08 */
2758 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2759 break;
2760 case 0x3c: /* Supported Protocol:0c */
2761 ret = 0x00000000; /* reserved */
2762 break;
2763 default:
2764 trace_usb_xhci_unimplemented("cap read", reg);
2765 ret = 0;
2766 }
2767
2768 trace_usb_xhci_cap_read(reg, ret);
2769 return ret;
2770 }
2771
2772 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2773 {
2774 XHCIPort *port = ptr;
2775 uint32_t ret;
2776
2777 switch (reg) {
2778 case 0x00: /* PORTSC */
2779 ret = port->portsc;
2780 break;
2781 case 0x04: /* PORTPMSC */
2782 case 0x08: /* PORTLI */
2783 ret = 0;
2784 break;
2785 case 0x0c: /* reserved */
2786 default:
2787 trace_usb_xhci_unimplemented("port read", reg);
2788 ret = 0;
2789 }
2790
2791 trace_usb_xhci_port_read(port->portnr, reg, ret);
2792 return ret;
2793 }
2794
2795 static void xhci_port_write(void *ptr, hwaddr reg,
2796 uint64_t val, unsigned size)
2797 {
2798 XHCIPort *port = ptr;
2799 uint32_t portsc, notify;
2800
2801 trace_usb_xhci_port_write(port->portnr, reg, val);
2802
2803 switch (reg) {
2804 case 0x00: /* PORTSC */
2805 /* write-1-to-start bits */
2806 if (val & PORTSC_PR) {
2807 xhci_port_reset(port);
2808 break;
2809 }
2810
2811 portsc = port->portsc;
2812 notify = 0;
2813 /* write-1-to-clear bits*/
2814 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2815 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2816 if (val & PORTSC_LWS) {
2817 /* overwrite PLS only when LWS=1 */
2818 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2819 uint32_t new_pls = get_field(val, PORTSC_PLS);
2820 switch (new_pls) {
2821 case PLS_U0:
2822 if (old_pls != PLS_U0) {
2823 set_field(&portsc, new_pls, PORTSC_PLS);
2824 trace_usb_xhci_port_link(port->portnr, new_pls);
2825 notify = PORTSC_PLC;
2826 }
2827 break;
2828 case PLS_U3:
2829 if (old_pls < PLS_U3) {
2830 set_field(&portsc, new_pls, PORTSC_PLS);
2831 trace_usb_xhci_port_link(port->portnr, new_pls);
2832 }
2833 break;
2834 case PLS_RESUME:
2835 /* windows does this for some reason, don't spam stderr */
2836 break;
2837 default:
2838 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n",
2839 __func__, old_pls, new_pls);
2840 break;
2841 }
2842 }
2843 /* read/write bits */
2844 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2845 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2846 port->portsc = portsc;
2847 if (notify) {
2848 xhci_port_notify(port, notify);
2849 }
2850 break;
2851 case 0x04: /* PORTPMSC */
2852 case 0x08: /* PORTLI */
2853 default:
2854 trace_usb_xhci_unimplemented("port write", reg);
2855 }
2856 }
2857
2858 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2859 {
2860 XHCIState *xhci = ptr;
2861 uint32_t ret;
2862
2863 switch (reg) {
2864 case 0x00: /* USBCMD */
2865 ret = xhci->usbcmd;
2866 break;
2867 case 0x04: /* USBSTS */
2868 ret = xhci->usbsts;
2869 break;
2870 case 0x08: /* PAGESIZE */
2871 ret = 1; /* 4KiB */
2872 break;
2873 case 0x14: /* DNCTRL */
2874 ret = xhci->dnctrl;
2875 break;
2876 case 0x18: /* CRCR low */
2877 ret = xhci->crcr_low & ~0xe;
2878 break;
2879 case 0x1c: /* CRCR high */
2880 ret = xhci->crcr_high;
2881 break;
2882 case 0x30: /* DCBAAP low */
2883 ret = xhci->dcbaap_low;
2884 break;
2885 case 0x34: /* DCBAAP high */
2886 ret = xhci->dcbaap_high;
2887 break;
2888 case 0x38: /* CONFIG */
2889 ret = xhci->config;
2890 break;
2891 default:
2892 trace_usb_xhci_unimplemented("oper read", reg);
2893 ret = 0;
2894 }
2895
2896 trace_usb_xhci_oper_read(reg, ret);
2897 return ret;
2898 }
2899
2900 static void xhci_oper_write(void *ptr, hwaddr reg,
2901 uint64_t val, unsigned size)
2902 {
2903 XHCIState *xhci = ptr;
2904
2905 trace_usb_xhci_oper_write(reg, val);
2906
2907 switch (reg) {
2908 case 0x00: /* USBCMD */
2909 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2910 xhci_run(xhci);
2911 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2912 xhci_stop(xhci);
2913 }
2914 xhci->usbcmd = val & 0xc0f;
2915 xhci_mfwrap_update(xhci);
2916 if (val & USBCMD_HCRST) {
2917 xhci_reset(&xhci->pci_dev.qdev);
2918 }
2919 xhci_intx_update(xhci);
2920 break;
2921
2922 case 0x04: /* USBSTS */
2923 /* these bits are write-1-to-clear */
2924 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2925 xhci_intx_update(xhci);
2926 break;
2927
2928 case 0x14: /* DNCTRL */
2929 xhci->dnctrl = val & 0xffff;
2930 break;
2931 case 0x18: /* CRCR low */
2932 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2933 break;
2934 case 0x1c: /* CRCR high */
2935 xhci->crcr_high = val;
2936 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2937 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2938 xhci->crcr_low &= ~CRCR_CRR;
2939 xhci_event(xhci, &event, 0);
2940 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2941 } else {
2942 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2943 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2944 }
2945 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2946 break;
2947 case 0x30: /* DCBAAP low */
2948 xhci->dcbaap_low = val & 0xffffffc0;
2949 break;
2950 case 0x34: /* DCBAAP high */
2951 xhci->dcbaap_high = val;
2952 break;
2953 case 0x38: /* CONFIG */
2954 xhci->config = val & 0xff;
2955 break;
2956 default:
2957 trace_usb_xhci_unimplemented("oper write", reg);
2958 }
2959 }
2960
2961 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
2962 unsigned size)
2963 {
2964 XHCIState *xhci = ptr;
2965 uint32_t ret = 0;
2966
2967 if (reg < 0x20) {
2968 switch (reg) {
2969 case 0x00: /* MFINDEX */
2970 ret = xhci_mfindex_get(xhci) & 0x3fff;
2971 break;
2972 default:
2973 trace_usb_xhci_unimplemented("runtime read", reg);
2974 break;
2975 }
2976 } else {
2977 int v = (reg - 0x20) / 0x20;
2978 XHCIInterrupter *intr = &xhci->intr[v];
2979 switch (reg & 0x1f) {
2980 case 0x00: /* IMAN */
2981 ret = intr->iman;
2982 break;
2983 case 0x04: /* IMOD */
2984 ret = intr->imod;
2985 break;
2986 case 0x08: /* ERSTSZ */
2987 ret = intr->erstsz;
2988 break;
2989 case 0x10: /* ERSTBA low */
2990 ret = intr->erstba_low;
2991 break;
2992 case 0x14: /* ERSTBA high */
2993 ret = intr->erstba_high;
2994 break;
2995 case 0x18: /* ERDP low */
2996 ret = intr->erdp_low;
2997 break;
2998 case 0x1c: /* ERDP high */
2999 ret = intr->erdp_high;
3000 break;
3001 }
3002 }
3003
3004 trace_usb_xhci_runtime_read(reg, ret);
3005 return ret;
3006 }
3007
3008 static void xhci_runtime_write(void *ptr, hwaddr reg,
3009 uint64_t val, unsigned size)
3010 {
3011 XHCIState *xhci = ptr;
3012 int v = (reg - 0x20) / 0x20;
3013 XHCIInterrupter *intr = &xhci->intr[v];
3014 trace_usb_xhci_runtime_write(reg, val);
3015
3016 if (reg < 0x20) {
3017 trace_usb_xhci_unimplemented("runtime write", reg);
3018 return;
3019 }
3020
3021 switch (reg & 0x1f) {
3022 case 0x00: /* IMAN */
3023 if (val & IMAN_IP) {
3024 intr->iman &= ~IMAN_IP;
3025 }
3026 intr->iman &= ~IMAN_IE;
3027 intr->iman |= val & IMAN_IE;
3028 if (v == 0) {
3029 xhci_intx_update(xhci);
3030 }
3031 xhci_msix_update(xhci, v);
3032 break;
3033 case 0x04: /* IMOD */
3034 intr->imod = val;
3035 break;
3036 case 0x08: /* ERSTSZ */
3037 intr->erstsz = val & 0xffff;
3038 break;
3039 case 0x10: /* ERSTBA low */
3040 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3041 intr->erstba_low = val & 0xffffffc0; */
3042 intr->erstba_low = val & 0xfffffff0;
3043 break;
3044 case 0x14: /* ERSTBA high */
3045 intr->erstba_high = val;
3046 xhci_er_reset(xhci, v);
3047 break;
3048 case 0x18: /* ERDP low */
3049 if (val & ERDP_EHB) {
3050 intr->erdp_low &= ~ERDP_EHB;
3051 }
3052 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3053 break;
3054 case 0x1c: /* ERDP high */
3055 intr->erdp_high = val;
3056 xhci_events_update(xhci, v);
3057 break;
3058 default:
3059 trace_usb_xhci_unimplemented("oper write", reg);
3060 }
3061 }
3062
3063 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3064 unsigned size)
3065 {
3066 /* doorbells always read as 0 */
3067 trace_usb_xhci_doorbell_read(reg, 0);
3068 return 0;
3069 }
3070
3071 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3072 uint64_t val, unsigned size)
3073 {
3074 XHCIState *xhci = ptr;
3075 unsigned int epid, streamid;
3076
3077 trace_usb_xhci_doorbell_write(reg, val);
3078
3079 if (!xhci_running(xhci)) {
3080 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
3081 return;
3082 }
3083
3084 reg >>= 2;
3085
3086 if (reg == 0) {
3087 if (val == 0) {
3088 xhci_process_commands(xhci);
3089 } else {
3090 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n",
3091 (uint32_t)val);
3092 }
3093 } else {
3094 epid = val & 0xff;
3095 streamid = (val >> 16) & 0xffff;
3096 if (reg > xhci->numslots) {
3097 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg);
3098 } else if (epid > 31) {
3099 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n",
3100 (int)reg, (uint32_t)val);
3101 } else {
3102 xhci_kick_ep(xhci, reg, epid, streamid);
3103 }
3104 }
3105 }
3106
3107 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3108 unsigned width)
3109 {
3110 /* nothing */
3111 }
3112
3113 static const MemoryRegionOps xhci_cap_ops = {
3114 .read = xhci_cap_read,
3115 .write = xhci_cap_write,
3116 .valid.min_access_size = 1,
3117 .valid.max_access_size = 4,
3118 .impl.min_access_size = 4,
3119 .impl.max_access_size = 4,
3120 .endianness = DEVICE_LITTLE_ENDIAN,
3121 };
3122
3123 static const MemoryRegionOps xhci_oper_ops = {
3124 .read = xhci_oper_read,
3125 .write = xhci_oper_write,
3126 .valid.min_access_size = 4,
3127 .valid.max_access_size = 4,
3128 .endianness = DEVICE_LITTLE_ENDIAN,
3129 };
3130
3131 static const MemoryRegionOps xhci_port_ops = {
3132 .read = xhci_port_read,
3133 .write = xhci_port_write,
3134 .valid.min_access_size = 4,
3135 .valid.max_access_size = 4,
3136 .endianness = DEVICE_LITTLE_ENDIAN,
3137 };
3138
3139 static const MemoryRegionOps xhci_runtime_ops = {
3140 .read = xhci_runtime_read,
3141 .write = xhci_runtime_write,
3142 .valid.min_access_size = 4,
3143 .valid.max_access_size = 4,
3144 .endianness = DEVICE_LITTLE_ENDIAN,
3145 };
3146
3147 static const MemoryRegionOps xhci_doorbell_ops = {
3148 .read = xhci_doorbell_read,
3149 .write = xhci_doorbell_write,
3150 .valid.min_access_size = 4,
3151 .valid.max_access_size = 4,
3152 .endianness = DEVICE_LITTLE_ENDIAN,
3153 };
3154
3155 static void xhci_attach(USBPort *usbport)
3156 {
3157 XHCIState *xhci = usbport->opaque;
3158 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3159
3160 xhci_port_update(port, 0);
3161 }
3162
3163 static void xhci_detach(USBPort *usbport)
3164 {
3165 XHCIState *xhci = usbport->opaque;
3166 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3167
3168 xhci_detach_slot(xhci, usbport);
3169 xhci_port_update(port, 1);
3170 }
3171
3172 static void xhci_wakeup(USBPort *usbport)
3173 {
3174 XHCIState *xhci = usbport->opaque;
3175 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3176
3177 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3178 return;
3179 }
3180 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3181 xhci_port_notify(port, PORTSC_PLC);
3182 }
3183
3184 static void xhci_complete(USBPort *port, USBPacket *packet)
3185 {
3186 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3187
3188 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3189 xhci_ep_nuke_one_xfer(xfer);
3190 return;
3191 }
3192 xhci_complete_packet(xfer);
3193 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
3194 }
3195
3196 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3197 {
3198 USBBus *bus = usb_bus_from_device(child);
3199 XHCIState *xhci = container_of(bus, XHCIState, bus);
3200
3201 xhci_detach_slot(xhci, uport);
3202 }
3203
3204 static USBPortOps xhci_uport_ops = {
3205 .attach = xhci_attach,
3206 .detach = xhci_detach,
3207 .wakeup = xhci_wakeup,
3208 .complete = xhci_complete,
3209 .child_detach = xhci_child_detach,
3210 };
3211
3212 static int xhci_find_epid(USBEndpoint *ep)
3213 {
3214 if (ep->nr == 0) {
3215 return 1;
3216 }
3217 if (ep->pid == USB_TOKEN_IN) {
3218 return ep->nr * 2 + 1;
3219 } else {
3220 return ep->nr * 2;
3221 }
3222 }
3223
3224 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3225 unsigned int stream)
3226 {
3227 XHCIState *xhci = container_of(bus, XHCIState, bus);
3228 int slotid;
3229
3230 DPRINTF("%s\n", __func__);
3231 slotid = ep->dev->addr;
3232 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3233 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3234 return;
3235 }
3236 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3237 }
3238
3239 static USBBusOps xhci_bus_ops = {
3240 .wakeup_endpoint = xhci_wakeup_endpoint,
3241 };
3242
3243 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
3244 {
3245 XHCIPort *port;
3246 int i, usbports, speedmask;
3247
3248 xhci->usbsts = USBSTS_HCH;
3249
3250 if (xhci->numports_2 > MAXPORTS_2) {
3251 xhci->numports_2 = MAXPORTS_2;
3252 }
3253 if (xhci->numports_3 > MAXPORTS_3) {
3254 xhci->numports_3 = MAXPORTS_3;
3255 }
3256 usbports = MAX(xhci->numports_2, xhci->numports_3);
3257 xhci->numports = xhci->numports_2 + xhci->numports_3;
3258
3259 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
3260
3261 for (i = 0; i < usbports; i++) {
3262 speedmask = 0;
3263 if (i < xhci->numports_2) {
3264 port = &xhci->ports[i];
3265 port->portnr = i + 1;
3266 port->uport = &xhci->uports[i];
3267 port->speedmask =
3268 USB_SPEED_MASK_LOW |
3269 USB_SPEED_MASK_FULL |
3270 USB_SPEED_MASK_HIGH;
3271 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3272 speedmask |= port->speedmask;
3273 }
3274 if (i < xhci->numports_3) {
3275 port = &xhci->ports[i + xhci->numports_2];
3276 port->portnr = i + 1 + xhci->numports_2;
3277 port->uport = &xhci->uports[i];
3278 port->speedmask = USB_SPEED_MASK_SUPER;
3279 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3280 speedmask |= port->speedmask;
3281 }
3282 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3283 &xhci_uport_ops, speedmask);
3284 }
3285 }
3286
3287 static int usb_xhci_initfn(struct PCIDevice *dev)
3288 {
3289 int i, ret;
3290
3291 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
3292
3293 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3294 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3295 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
3296 xhci->pci_dev.config[0x60] = 0x30; /* release number */
3297
3298 usb_xhci_init(xhci, &dev->qdev);
3299
3300 if (xhci->numintrs > MAXINTRS) {
3301 xhci->numintrs = MAXINTRS;
3302 }
3303 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3304 xhci->numintrs++;
3305 }
3306 if (xhci->numintrs < 1) {
3307 xhci->numintrs = 1;
3308 }
3309 if (xhci->numslots > MAXSLOTS) {
3310 xhci->numslots = MAXSLOTS;
3311 }
3312 if (xhci->numslots < 1) {
3313 xhci->numslots = 1;
3314 }
3315
3316 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
3317
3318 xhci->irq = xhci->pci_dev.irq[0];
3319
3320 memory_region_init(&xhci->mem, "xhci", LEN_REGS);
3321 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci,
3322 "capabilities", LEN_CAP);
3323 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci,
3324 "operational", 0x400);
3325 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci,
3326 "runtime", LEN_RUNTIME);
3327 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci,
3328 "doorbell", LEN_DOORBELL);
3329
3330 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3331 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3332 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3333 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3334
3335 for (i = 0; i < xhci->numports; i++) {
3336 XHCIPort *port = &xhci->ports[i];
3337 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3338 port->xhci = xhci;
3339 memory_region_init_io(&port->mem, &xhci_port_ops, port,
3340 port->name, 0x10);
3341 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3342 }
3343
3344 pci_register_bar(&xhci->pci_dev, 0,
3345 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3346 &xhci->mem);
3347
3348 ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0);
3349 assert(ret >= 0);
3350
3351 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
3352 msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false);
3353 }
3354 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
3355 msix_init(&xhci->pci_dev, xhci->numintrs,
3356 &xhci->mem, 0, OFF_MSIX_TABLE,
3357 &xhci->mem, 0, OFF_MSIX_PBA,
3358 0x90);
3359 }
3360
3361 return 0;
3362 }
3363
3364 static const VMStateDescription vmstate_xhci = {
3365 .name = "xhci",
3366 .unmigratable = 1,
3367 };
3368
3369 static Property xhci_properties[] = {
3370 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
3371 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
3372 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3373 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3374 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3375 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3376 DEFINE_PROP_END_OF_LIST(),
3377 };
3378
3379 static void xhci_class_init(ObjectClass *klass, void *data)
3380 {
3381 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3382 DeviceClass *dc = DEVICE_CLASS(klass);
3383
3384 dc->vmsd = &vmstate_xhci;
3385 dc->props = xhci_properties;
3386 dc->reset = xhci_reset;
3387 k->init = usb_xhci_initfn;
3388 k->vendor_id = PCI_VENDOR_ID_NEC;
3389 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3390 k->class_id = PCI_CLASS_SERIAL_USB;
3391 k->revision = 0x03;
3392 k->is_express = 1;
3393 k->no_hotplug = 1;
3394 }
3395
3396 static const TypeInfo xhci_info = {
3397 .name = "nec-usb-xhci",
3398 .parent = TYPE_PCI_DEVICE,
3399 .instance_size = sizeof(XHCIState),
3400 .class_init = xhci_class_init,
3401 };
3402
3403 static void xhci_register_types(void)
3404 {
3405 type_register_static(&xhci_info);
3406 }
3407
3408 type_init(xhci_register_types)
AR7 emulation for QEMU