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tests/boot-serial-test: Add microbit board testcase
[qemu/ar7.git] / memory.c
blob51204aa0794b64b13e796130970b541680922d82
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qom/object.h"
26 #include "trace-root.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/qdev-properties.h"
33 #include "migration/vmstate.h"
34
35 //#define DEBUG_UNASSIGNED
36
37 static unsigned memory_region_transaction_depth;
38 static bool memory_region_update_pending;
39 static bool ioeventfd_update_pending;
40 static bool global_dirty_log = false;
41
42 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
43 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
44
45 static QTAILQ_HEAD(, AddressSpace) address_spaces
46 = QTAILQ_HEAD_INITIALIZER(address_spaces);
47
48 static GHashTable *flat_views;
49
50 typedef struct AddrRange AddrRange;
51
52 /*
53 * Note that signed integers are needed for negative offsetting in aliases
54 * (large MemoryRegion::alias_offset).
55 */
56 struct AddrRange {
57 Int128 start;
58 Int128 size;
59 };
60
61 static AddrRange addrrange_make(Int128 start, Int128 size)
62 {
63 return (AddrRange) { start, size };
64 }
65
66 static bool addrrange_equal(AddrRange r1, AddrRange r2)
67 {
68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
69 }
70
71 static Int128 addrrange_end(AddrRange r)
72 {
73 return int128_add(r.start, r.size);
74 }
75
76 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
77 {
78 int128_addto(&range.start, delta);
79 return range;
80 }
81
82 static bool addrrange_contains(AddrRange range, Int128 addr)
83 {
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86 }
87
88 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89 {
90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
92 }
93
94 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95 {
96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
99 }
100
101 enum ListenerDirection { Forward, Reverse };
102
103 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
128 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
129 do { \
130 MemoryListener *_listener; \
131 struct memory_listeners_as *list = &(_as)->listeners; \
132 \
133 switch (_direction) { \
134 case Forward: \
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
154 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
155 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
160 } while(0)
161
162 struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165 };
166
167 struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
171 EventNotifier *e;
172 };
173
174 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
176 {
177 if (int128_lt(a->addr.start, b->addr.start)) {
178 return true;
179 } else if (int128_gt(a->addr.start, b->addr.start)) {
180 return false;
181 } else if (int128_lt(a->addr.size, b->addr.size)) {
182 return true;
183 } else if (int128_gt(a->addr.size, b->addr.size)) {
184 return false;
185 } else if (a->match_data < b->match_data) {
186 return true;
187 } else if (a->match_data > b->match_data) {
188 return false;
189 } else if (a->match_data) {
190 if (a->data < b->data) {
191 return true;
192 } else if (a->data > b->data) {
193 return false;
194 }
195 }
196 if (a->e < b->e) {
197 return true;
198 } else if (a->e > b->e) {
199 return false;
200 }
201 return false;
202 }
203
204 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
206 {
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209 }
210
211 /* Range of memory in the global map. Addresses are absolute. */
212 struct FlatRange {
213 MemoryRegion *mr;
214 hwaddr offset_in_region;
215 AddrRange addr;
216 uint8_t dirty_log_mask;
217 bool romd_mode;
218 bool readonly;
219 };
220
221 #define FOR_EACH_FLAT_RANGE(var, view) \
222 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
223
224 static inline MemoryRegionSection
225 section_from_flat_range(FlatRange *fr, FlatView *fv)
226 {
227 return (MemoryRegionSection) {
228 .mr = fr->mr,
229 .fv = fv,
230 .offset_within_region = fr->offset_in_region,
231 .size = fr->addr.size,
232 .offset_within_address_space = int128_get64(fr->addr.start),
233 .readonly = fr->readonly,
234 };
235 }
236
237 static bool flatrange_equal(FlatRange *a, FlatRange *b)
238 {
239 return a->mr == b->mr
240 && addrrange_equal(a->addr, b->addr)
241 && a->offset_in_region == b->offset_in_region
242 && a->romd_mode == b->romd_mode
243 && a->readonly == b->readonly;
244 }
245
246 static FlatView *flatview_new(MemoryRegion *mr_root)
247 {
248 FlatView *view;
249
250 view = g_new0(FlatView, 1);
251 view->ref = 1;
252 view->root = mr_root;
253 memory_region_ref(mr_root);
254 trace_flatview_new(view, mr_root);
255
256 return view;
257 }
258
259 /* Insert a range into a given position. Caller is responsible for maintaining
260 * sorting order.
261 */
262 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
263 {
264 if (view->nr == view->nr_allocated) {
265 view->nr_allocated = MAX(2 * view->nr, 10);
266 view->ranges = g_realloc(view->ranges,
267 view->nr_allocated * sizeof(*view->ranges));
268 }
269 memmove(view->ranges + pos + 1, view->ranges + pos,
270 (view->nr - pos) * sizeof(FlatRange));
271 view->ranges[pos] = *range;
272 memory_region_ref(range->mr);
273 ++view->nr;
274 }
275
276 static void flatview_destroy(FlatView *view)
277 {
278 int i;
279
280 trace_flatview_destroy(view, view->root);
281 if (view->dispatch) {
282 address_space_dispatch_free(view->dispatch);
283 }
284 for (i = 0; i < view->nr; i++) {
285 memory_region_unref(view->ranges[i].mr);
286 }
287 g_free(view->ranges);
288 memory_region_unref(view->root);
289 g_free(view);
290 }
291
292 static bool flatview_ref(FlatView *view)
293 {
294 return atomic_fetch_inc_nonzero(&view->ref) > 0;
295 }
296
297 void flatview_unref(FlatView *view)
298 {
299 if (atomic_fetch_dec(&view->ref) == 1) {
300 trace_flatview_destroy_rcu(view, view->root);
301 assert(view->root);
302 call_rcu(view, flatview_destroy, rcu);
303 }
304 }
305
306 static bool can_merge(FlatRange *r1, FlatRange *r2)
307 {
308 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
309 && r1->mr == r2->mr
310 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
311 r1->addr.size),
312 int128_make64(r2->offset_in_region))
313 && r1->dirty_log_mask == r2->dirty_log_mask
314 && r1->romd_mode == r2->romd_mode
315 && r1->readonly == r2->readonly;
316 }
317
318 /* Attempt to simplify a view by merging adjacent ranges */
319 static void flatview_simplify(FlatView *view)
320 {
321 unsigned i, j;
322
323 i = 0;
324 while (i < view->nr) {
325 j = i + 1;
326 while (j < view->nr
327 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
328 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
329 ++j;
330 }
331 ++i;
332 memmove(&view->ranges[i], &view->ranges[j],
333 (view->nr - j) * sizeof(view->ranges[j]));
334 view->nr -= j - i;
335 }
336 }
337
338 static bool memory_region_big_endian(MemoryRegion *mr)
339 {
340 #ifdef TARGET_WORDS_BIGENDIAN
341 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
342 #else
343 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
344 #endif
345 }
346
347 static bool memory_region_wrong_endianness(MemoryRegion *mr)
348 {
349 #ifdef TARGET_WORDS_BIGENDIAN
350 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
351 #else
352 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
353 #endif
354 }
355
356 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
357 {
358 if (memory_region_wrong_endianness(mr)) {
359 switch (size) {
360 case 1:
361 break;
362 case 2:
363 *data = bswap16(*data);
364 break;
365 case 4:
366 *data = bswap32(*data);
367 break;
368 case 8:
369 *data = bswap64(*data);
370 break;
371 default:
372 abort();
373 }
374 }
375 }
376
377 static inline void memory_region_shift_read_access(uint64_t *value,
378 signed shift,
379 uint64_t mask,
380 uint64_t tmp)
381 {
382 if (shift >= 0) {
383 *value |= (tmp & mask) << shift;
384 } else {
385 *value |= (tmp & mask) >> -shift;
386 }
387 }
388
389 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
390 signed shift,
391 uint64_t mask)
392 {
393 uint64_t tmp;
394
395 if (shift >= 0) {
396 tmp = (*value >> shift) & mask;
397 } else {
398 tmp = (*value << -shift) & mask;
399 }
400
401 return tmp;
402 }
403
404 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
405 {
406 MemoryRegion *root;
407 hwaddr abs_addr = offset;
408
409 abs_addr += mr->addr;
410 for (root = mr; root->container; ) {
411 root = root->container;
412 abs_addr += root->addr;
413 }
414
415 return abs_addr;
416 }
417
418 static int get_cpu_index(void)
419 {
420 if (current_cpu) {
421 return current_cpu->cpu_index;
422 }
423 return -1;
424 }
425
426 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
427 hwaddr addr,
428 uint64_t *value,
429 unsigned size,
430 signed shift,
431 uint64_t mask,
432 MemTxAttrs attrs)
433 {
434 uint64_t tmp;
435
436 tmp = mr->ops->read(mr->opaque, addr, size);
437 if (mr->subpage) {
438 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
439 } else if (mr == &io_mem_notdirty) {
440 /* Accesses to code which has previously been translated into a TB show
441 * up in the MMIO path, as accesses to the io_mem_notdirty
442 * MemoryRegion. */
443 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
444 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
445 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
446 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
447 }
448 memory_region_shift_read_access(value, shift, mask, tmp);
449 return MEMTX_OK;
450 }
451
452 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
453 hwaddr addr,
454 uint64_t *value,
455 unsigned size,
456 signed shift,
457 uint64_t mask,
458 MemTxAttrs attrs)
459 {
460 uint64_t tmp = 0;
461 MemTxResult r;
462
463 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
464 if (mr->subpage) {
465 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
466 } else if (mr == &io_mem_notdirty) {
467 /* Accesses to code which has previously been translated into a TB show
468 * up in the MMIO path, as accesses to the io_mem_notdirty
469 * MemoryRegion. */
470 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
471 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
472 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
473 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
474 }
475 memory_region_shift_read_access(value, shift, mask, tmp);
476 return r;
477 }
478
479 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
480 hwaddr addr,
481 uint64_t *value,
482 unsigned size,
483 signed shift,
484 uint64_t mask,
485 MemTxAttrs attrs)
486 {
487 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
488
489 if (mr->subpage) {
490 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
491 } else if (mr == &io_mem_notdirty) {
492 /* Accesses to code which has previously been translated into a TB show
493 * up in the MMIO path, as accesses to the io_mem_notdirty
494 * MemoryRegion. */
495 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
496 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
497 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
498 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
499 }
500 mr->ops->write(mr->opaque, addr, tmp, size);
501 return MEMTX_OK;
502 }
503
504 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
505 hwaddr addr,
506 uint64_t *value,
507 unsigned size,
508 signed shift,
509 uint64_t mask,
510 MemTxAttrs attrs)
511 {
512 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
513
514 if (mr->subpage) {
515 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
516 } else if (mr == &io_mem_notdirty) {
517 /* Accesses to code which has previously been translated into a TB show
518 * up in the MMIO path, as accesses to the io_mem_notdirty
519 * MemoryRegion. */
520 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
521 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
522 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
523 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
524 }
525 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
526 }
527
528 static MemTxResult access_with_adjusted_size(hwaddr addr,
529 uint64_t *value,
530 unsigned size,
531 unsigned access_size_min,
532 unsigned access_size_max,
533 MemTxResult (*access_fn)
534 (MemoryRegion *mr,
535 hwaddr addr,
536 uint64_t *value,
537 unsigned size,
538 signed shift,
539 uint64_t mask,
540 MemTxAttrs attrs),
541 MemoryRegion *mr,
542 MemTxAttrs attrs)
543 {
544 uint64_t access_mask;
545 unsigned access_size;
546 unsigned i;
547 MemTxResult r = MEMTX_OK;
548
549 if (!access_size_min) {
550 access_size_min = 1;
551 }
552 if (!access_size_max) {
553 access_size_max = 4;
554 }
555
556 /* FIXME: support unaligned access? */
557 access_size = MAX(MIN(size, access_size_max), access_size_min);
558 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
559 if (memory_region_big_endian(mr)) {
560 for (i = 0; i < size; i += access_size) {
561 r |= access_fn(mr, addr + i, value, access_size,
562 (size - access_size - i) * 8, access_mask, attrs);
563 }
564 } else {
565 for (i = 0; i < size; i += access_size) {
566 r |= access_fn(mr, addr + i, value, access_size, i * 8,
567 access_mask, attrs);
568 }
569 }
570 return r;
571 }
572
573 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
574 {
575 AddressSpace *as;
576
577 while (mr->container) {
578 mr = mr->container;
579 }
580 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
581 if (mr == as->root) {
582 return as;
583 }
584 }
585 return NULL;
586 }
587
588 /* Render a memory region into the global view. Ranges in @view obscure
589 * ranges in @mr.
590 */
591 static void render_memory_region(FlatView *view,
592 MemoryRegion *mr,
593 Int128 base,
594 AddrRange clip,
595 bool readonly)
596 {
597 MemoryRegion *subregion;
598 unsigned i;
599 hwaddr offset_in_region;
600 Int128 remain;
601 Int128 now;
602 FlatRange fr;
603 AddrRange tmp;
604
605 if (!mr->enabled) {
606 return;
607 }
608
609 int128_addto(&base, int128_make64(mr->addr));
610 readonly |= mr->readonly;
611
612 tmp = addrrange_make(base, mr->size);
613
614 if (!addrrange_intersects(tmp, clip)) {
615 return;
616 }
617
618 clip = addrrange_intersection(tmp, clip);
619
620 if (mr->alias) {
621 int128_subfrom(&base, int128_make64(mr->alias->addr));
622 int128_subfrom(&base, int128_make64(mr->alias_offset));
623 render_memory_region(view, mr->alias, base, clip, readonly);
624 return;
625 }
626
627 /* Render subregions in priority order. */
628 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
629 render_memory_region(view, subregion, base, clip, readonly);
630 }
631
632 if (!mr->terminates) {
633 return;
634 }
635
636 offset_in_region = int128_get64(int128_sub(clip.start, base));
637 base = clip.start;
638 remain = clip.size;
639
640 fr.mr = mr;
641 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
642 fr.romd_mode = mr->romd_mode;
643 fr.readonly = readonly;
644
645 /* Render the region itself into any gaps left by the current view. */
646 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
647 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
648 continue;
649 }
650 if (int128_lt(base, view->ranges[i].addr.start)) {
651 now = int128_min(remain,
652 int128_sub(view->ranges[i].addr.start, base));
653 fr.offset_in_region = offset_in_region;
654 fr.addr = addrrange_make(base, now);
655 flatview_insert(view, i, &fr);
656 ++i;
657 int128_addto(&base, now);
658 offset_in_region += int128_get64(now);
659 int128_subfrom(&remain, now);
660 }
661 now = int128_sub(int128_min(int128_add(base, remain),
662 addrrange_end(view->ranges[i].addr)),
663 base);
664 int128_addto(&base, now);
665 offset_in_region += int128_get64(now);
666 int128_subfrom(&remain, now);
667 }
668 if (int128_nz(remain)) {
669 fr.offset_in_region = offset_in_region;
670 fr.addr = addrrange_make(base, remain);
671 flatview_insert(view, i, &fr);
672 }
673 }
674
675 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
676 {
677 while (mr->enabled) {
678 if (mr->alias) {
679 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
680 /* The alias is included in its entirety. Use it as
681 * the "real" root, so that we can share more FlatViews.
682 */
683 mr = mr->alias;
684 continue;
685 }
686 } else if (!mr->terminates) {
687 unsigned int found = 0;
688 MemoryRegion *child, *next = NULL;
689 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
690 if (child->enabled) {
691 if (++found > 1) {
692 next = NULL;
693 break;
694 }
695 if (!child->addr && int128_ge(mr->size, child->size)) {
696 /* A child is included in its entirety. If it's the only
697 * enabled one, use it in the hope of finding an alias down the
698 * way. This will also let us share FlatViews.
699 */
700 next = child;
701 }
702 }
703 }
704 if (found == 0) {
705 return NULL;
706 }
707 if (next) {
708 mr = next;
709 continue;
710 }
711 }
712
713 return mr;
714 }
715
716 return NULL;
717 }
718
719 /* Render a memory topology into a list of disjoint absolute ranges. */
720 static FlatView *generate_memory_topology(MemoryRegion *mr)
721 {
722 int i;
723 FlatView *view;
724
725 view = flatview_new(mr);
726
727 if (mr) {
728 render_memory_region(view, mr, int128_zero(),
729 addrrange_make(int128_zero(), int128_2_64()), false);
730 }
731 flatview_simplify(view);
732
733 view->dispatch = address_space_dispatch_new(view);
734 for (i = 0; i < view->nr; i++) {
735 MemoryRegionSection mrs =
736 section_from_flat_range(&view->ranges[i], view);
737 flatview_add_to_dispatch(view, &mrs);
738 }
739 address_space_dispatch_compact(view->dispatch);
740 g_hash_table_replace(flat_views, mr, view);
741
742 return view;
743 }
744
745 static void address_space_add_del_ioeventfds(AddressSpace *as,
746 MemoryRegionIoeventfd *fds_new,
747 unsigned fds_new_nb,
748 MemoryRegionIoeventfd *fds_old,
749 unsigned fds_old_nb)
750 {
751 unsigned iold, inew;
752 MemoryRegionIoeventfd *fd;
753 MemoryRegionSection section;
754
755 /* Generate a symmetric difference of the old and new fd sets, adding
756 * and deleting as necessary.
757 */
758
759 iold = inew = 0;
760 while (iold < fds_old_nb || inew < fds_new_nb) {
761 if (iold < fds_old_nb
762 && (inew == fds_new_nb
763 || memory_region_ioeventfd_before(&fds_old[iold],
764 &fds_new[inew]))) {
765 fd = &fds_old[iold];
766 section = (MemoryRegionSection) {
767 .fv = address_space_to_flatview(as),
768 .offset_within_address_space = int128_get64(fd->addr.start),
769 .size = fd->addr.size,
770 };
771 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
772 fd->match_data, fd->data, fd->e);
773 ++iold;
774 } else if (inew < fds_new_nb
775 && (iold == fds_old_nb
776 || memory_region_ioeventfd_before(&fds_new[inew],
777 &fds_old[iold]))) {
778 fd = &fds_new[inew];
779 section = (MemoryRegionSection) {
780 .fv = address_space_to_flatview(as),
781 .offset_within_address_space = int128_get64(fd->addr.start),
782 .size = fd->addr.size,
783 };
784 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
785 fd->match_data, fd->data, fd->e);
786 ++inew;
787 } else {
788 ++iold;
789 ++inew;
790 }
791 }
792 }
793
794 FlatView *address_space_get_flatview(AddressSpace *as)
795 {
796 FlatView *view;
797
798 rcu_read_lock();
799 do {
800 view = address_space_to_flatview(as);
801 /* If somebody has replaced as->current_map concurrently,
802 * flatview_ref returns false.
803 */
804 } while (!flatview_ref(view));
805 rcu_read_unlock();
806 return view;
807 }
808
809 static void address_space_update_ioeventfds(AddressSpace *as)
810 {
811 FlatView *view;
812 FlatRange *fr;
813 unsigned ioeventfd_nb = 0;
814 MemoryRegionIoeventfd *ioeventfds = NULL;
815 AddrRange tmp;
816 unsigned i;
817
818 view = address_space_get_flatview(as);
819 FOR_EACH_FLAT_RANGE(fr, view) {
820 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
821 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
822 int128_sub(fr->addr.start,
823 int128_make64(fr->offset_in_region)));
824 if (addrrange_intersects(fr->addr, tmp)) {
825 ++ioeventfd_nb;
826 ioeventfds = g_realloc(ioeventfds,
827 ioeventfd_nb * sizeof(*ioeventfds));
828 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
829 ioeventfds[ioeventfd_nb-1].addr = tmp;
830 }
831 }
832 }
833
834 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
835 as->ioeventfds, as->ioeventfd_nb);
836
837 g_free(as->ioeventfds);
838 as->ioeventfds = ioeventfds;
839 as->ioeventfd_nb = ioeventfd_nb;
840 flatview_unref(view);
841 }
842
843 static void address_space_update_topology_pass(AddressSpace *as,
844 const FlatView *old_view,
845 const FlatView *new_view,
846 bool adding)
847 {
848 unsigned iold, inew;
849 FlatRange *frold, *frnew;
850
851 /* Generate a symmetric difference of the old and new memory maps.
852 * Kill ranges in the old map, and instantiate ranges in the new map.
853 */
854 iold = inew = 0;
855 while (iold < old_view->nr || inew < new_view->nr) {
856 if (iold < old_view->nr) {
857 frold = &old_view->ranges[iold];
858 } else {
859 frold = NULL;
860 }
861 if (inew < new_view->nr) {
862 frnew = &new_view->ranges[inew];
863 } else {
864 frnew = NULL;
865 }
866
867 if (frold
868 && (!frnew
869 || int128_lt(frold->addr.start, frnew->addr.start)
870 || (int128_eq(frold->addr.start, frnew->addr.start)
871 && !flatrange_equal(frold, frnew)))) {
872 /* In old but not in new, or in both but attributes changed. */
873
874 if (!adding) {
875 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
876 }
877
878 ++iold;
879 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
880 /* In both and unchanged (except logging may have changed) */
881
882 if (adding) {
883 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
884 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
885 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
886 frold->dirty_log_mask,
887 frnew->dirty_log_mask);
888 }
889 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
890 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
891 frold->dirty_log_mask,
892 frnew->dirty_log_mask);
893 }
894 }
895
896 ++iold;
897 ++inew;
898 } else {
899 /* In new */
900
901 if (adding) {
902 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
903 }
904
905 ++inew;
906 }
907 }
908 }
909
910 static void flatviews_init(void)
911 {
912 static FlatView *empty_view;
913
914 if (flat_views) {
915 return;
916 }
917
918 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
919 (GDestroyNotify) flatview_unref);
920 if (!empty_view) {
921 empty_view = generate_memory_topology(NULL);
922 /* We keep it alive forever in the global variable. */
923 flatview_ref(empty_view);
924 } else {
925 g_hash_table_replace(flat_views, NULL, empty_view);
926 flatview_ref(empty_view);
927 }
928 }
929
930 static void flatviews_reset(void)
931 {
932 AddressSpace *as;
933
934 if (flat_views) {
935 g_hash_table_unref(flat_views);
936 flat_views = NULL;
937 }
938 flatviews_init();
939
940 /* Render unique FVs */
941 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
942 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
943
944 if (g_hash_table_lookup(flat_views, physmr)) {
945 continue;
946 }
947
948 generate_memory_topology(physmr);
949 }
950 }
951
952 static void address_space_set_flatview(AddressSpace *as)
953 {
954 FlatView *old_view = address_space_to_flatview(as);
955 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
956 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
957
958 assert(new_view);
959
960 if (old_view == new_view) {
961 return;
962 }
963
964 if (old_view) {
965 flatview_ref(old_view);
966 }
967
968 flatview_ref(new_view);
969
970 if (!QTAILQ_EMPTY(&as->listeners)) {
971 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
972
973 if (!old_view2) {
974 old_view2 = &tmpview;
975 }
976 address_space_update_topology_pass(as, old_view2, new_view, false);
977 address_space_update_topology_pass(as, old_view2, new_view, true);
978 }
979
980 /* Writes are protected by the BQL. */
981 atomic_rcu_set(&as->current_map, new_view);
982 if (old_view) {
983 flatview_unref(old_view);
984 }
985
986 /* Note that all the old MemoryRegions are still alive up to this
987 * point. This relieves most MemoryListeners from the need to
988 * ref/unref the MemoryRegions they get---unless they use them
989 * outside the iothread mutex, in which case precise reference
990 * counting is necessary.
991 */
992 if (old_view) {
993 flatview_unref(old_view);
994 }
995 }
996
997 static void address_space_update_topology(AddressSpace *as)
998 {
999 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1000
1001 flatviews_init();
1002 if (!g_hash_table_lookup(flat_views, physmr)) {
1003 generate_memory_topology(physmr);
1004 }
1005 address_space_set_flatview(as);
1006 }
1007
1008 void memory_region_transaction_begin(void)
1009 {
1010 qemu_flush_coalesced_mmio_buffer();
1011 ++memory_region_transaction_depth;
1012 }
1013
1014 void memory_region_transaction_commit(void)
1015 {
1016 AddressSpace *as;
1017
1018 assert(memory_region_transaction_depth);
1019 assert(qemu_mutex_iothread_locked());
1020
1021 --memory_region_transaction_depth;
1022 if (!memory_region_transaction_depth) {
1023 if (memory_region_update_pending) {
1024 flatviews_reset();
1025
1026 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1027
1028 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1029 address_space_set_flatview(as);
1030 address_space_update_ioeventfds(as);
1031 }
1032 memory_region_update_pending = false;
1033 ioeventfd_update_pending = false;
1034 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1035 } else if (ioeventfd_update_pending) {
1036 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1037 address_space_update_ioeventfds(as);
1038 }
1039 ioeventfd_update_pending = false;
1040 }
1041 }
1042 }
1043
1044 static void memory_region_destructor_none(MemoryRegion *mr)
1045 {
1046 }
1047
1048 static void memory_region_destructor_ram(MemoryRegion *mr)
1049 {
1050 qemu_ram_free(mr->ram_block);
1051 }
1052
1053 static bool memory_region_need_escape(char c)
1054 {
1055 return c == '/' || c == '[' || c == '\\' || c == ']';
1056 }
1057
1058 static char *memory_region_escape_name(const char *name)
1059 {
1060 const char *p;
1061 char *escaped, *q;
1062 uint8_t c;
1063 size_t bytes = 0;
1064
1065 for (p = name; *p; p++) {
1066 bytes += memory_region_need_escape(*p) ? 4 : 1;
1067 }
1068 if (bytes == p - name) {
1069 return g_memdup(name, bytes + 1);
1070 }
1071
1072 escaped = g_malloc(bytes + 1);
1073 for (p = name, q = escaped; *p; p++) {
1074 c = *p;
1075 if (unlikely(memory_region_need_escape(c))) {
1076 *q++ = '\\';
1077 *q++ = 'x';
1078 *q++ = "0123456789abcdef"[c >> 4];
1079 c = "0123456789abcdef"[c & 15];
1080 }
1081 *q++ = c;
1082 }
1083 *q = 0;
1084 return escaped;
1085 }
1086
1087 static void memory_region_do_init(MemoryRegion *mr,
1088 Object *owner,
1089 const char *name,
1090 uint64_t size)
1091 {
1092 mr->size = int128_make64(size);
1093 if (size == UINT64_MAX) {
1094 mr->size = int128_2_64();
1095 }
1096 mr->name = g_strdup(name);
1097 mr->owner = owner;
1098 mr->ram_block = NULL;
1099
1100 if (name) {
1101 char *escaped_name = memory_region_escape_name(name);
1102 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1103
1104 if (!owner) {
1105 owner = container_get(qdev_get_machine(), "/unattached");
1106 }
1107
1108 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1109 object_unref(OBJECT(mr));
1110 g_free(name_array);
1111 g_free(escaped_name);
1112 }
1113 }
1114
1115 void memory_region_init(MemoryRegion *mr,
1116 Object *owner,
1117 const char *name,
1118 uint64_t size)
1119 {
1120 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1121 memory_region_do_init(mr, owner, name, size);
1122 }
1123
1124 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1125 void *opaque, Error **errp)
1126 {
1127 MemoryRegion *mr = MEMORY_REGION(obj);
1128 uint64_t value = mr->addr;
1129
1130 visit_type_uint64(v, name, &value, errp);
1131 }
1132
1133 static void memory_region_get_container(Object *obj, Visitor *v,
1134 const char *name, void *opaque,
1135 Error **errp)
1136 {
1137 MemoryRegion *mr = MEMORY_REGION(obj);
1138 gchar *path = (gchar *)"";
1139
1140 if (mr->container) {
1141 path = object_get_canonical_path(OBJECT(mr->container));
1142 }
1143 visit_type_str(v, name, &path, errp);
1144 if (mr->container) {
1145 g_free(path);
1146 }
1147 }
1148
1149 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1150 const char *part)
1151 {
1152 MemoryRegion *mr = MEMORY_REGION(obj);
1153
1154 return OBJECT(mr->container);
1155 }
1156
1157 static void memory_region_get_priority(Object *obj, Visitor *v,
1158 const char *name, void *opaque,
1159 Error **errp)
1160 {
1161 MemoryRegion *mr = MEMORY_REGION(obj);
1162 int32_t value = mr->priority;
1163
1164 visit_type_int32(v, name, &value, errp);
1165 }
1166
1167 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1168 void *opaque, Error **errp)
1169 {
1170 MemoryRegion *mr = MEMORY_REGION(obj);
1171 uint64_t value = memory_region_size(mr);
1172
1173 visit_type_uint64(v, name, &value, errp);
1174 }
1175
1176 static void memory_region_initfn(Object *obj)
1177 {
1178 MemoryRegion *mr = MEMORY_REGION(obj);
1179 ObjectProperty *op;
1180
1181 mr->ops = &unassigned_mem_ops;
1182 mr->enabled = true;
1183 mr->romd_mode = true;
1184 mr->global_locking = true;
1185 mr->destructor = memory_region_destructor_none;
1186 QTAILQ_INIT(&mr->subregions);
1187 QTAILQ_INIT(&mr->coalesced);
1188
1189 op = object_property_add(OBJECT(mr), "container",
1190 "link<" TYPE_MEMORY_REGION ">",
1191 memory_region_get_container,
1192 NULL, /* memory_region_set_container */
1193 NULL, NULL, &error_abort);
1194 op->resolve = memory_region_resolve_container;
1195
1196 object_property_add(OBJECT(mr), "addr", "uint64",
1197 memory_region_get_addr,
1198 NULL, /* memory_region_set_addr */
1199 NULL, NULL, &error_abort);
1200 object_property_add(OBJECT(mr), "priority", "uint32",
1201 memory_region_get_priority,
1202 NULL, /* memory_region_set_priority */
1203 NULL, NULL, &error_abort);
1204 object_property_add(OBJECT(mr), "size", "uint64",
1205 memory_region_get_size,
1206 NULL, /* memory_region_set_size, */
1207 NULL, NULL, &error_abort);
1208 }
1209
1210 static void iommu_memory_region_initfn(Object *obj)
1211 {
1212 MemoryRegion *mr = MEMORY_REGION(obj);
1213
1214 mr->is_iommu = true;
1215 }
1216
1217 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1218 unsigned size)
1219 {
1220 #ifdef DEBUG_UNASSIGNED
1221 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1222 #endif
1223 if (current_cpu != NULL) {
1224 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1225 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1226 }
1227 return 0;
1228 }
1229
1230 static void unassigned_mem_write(void *opaque, hwaddr addr,
1231 uint64_t val, unsigned size)
1232 {
1233 #ifdef DEBUG_UNASSIGNED
1234 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1235 #endif
1236 if (current_cpu != NULL) {
1237 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1238 }
1239 }
1240
1241 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1242 unsigned size, bool is_write,
1243 MemTxAttrs attrs)
1244 {
1245 return false;
1246 }
1247
1248 const MemoryRegionOps unassigned_mem_ops = {
1249 .valid.accepts = unassigned_mem_accepts,
1250 .endianness = DEVICE_NATIVE_ENDIAN,
1251 };
1252
1253 static uint64_t memory_region_ram_device_read(void *opaque,
1254 hwaddr addr, unsigned size)
1255 {
1256 MemoryRegion *mr = opaque;
1257 uint64_t data = (uint64_t)~0;
1258
1259 switch (size) {
1260 case 1:
1261 data = *(uint8_t *)(mr->ram_block->host + addr);
1262 break;
1263 case 2:
1264 data = *(uint16_t *)(mr->ram_block->host + addr);
1265 break;
1266 case 4:
1267 data = *(uint32_t *)(mr->ram_block->host + addr);
1268 break;
1269 case 8:
1270 data = *(uint64_t *)(mr->ram_block->host + addr);
1271 break;
1272 }
1273
1274 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1275
1276 return data;
1277 }
1278
1279 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1280 uint64_t data, unsigned size)
1281 {
1282 MemoryRegion *mr = opaque;
1283
1284 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1285
1286 switch (size) {
1287 case 1:
1288 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1289 break;
1290 case 2:
1291 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1292 break;
1293 case 4:
1294 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1295 break;
1296 case 8:
1297 *(uint64_t *)(mr->ram_block->host + addr) = data;
1298 break;
1299 }
1300 }
1301
1302 static const MemoryRegionOps ram_device_mem_ops = {
1303 .read = memory_region_ram_device_read,
1304 .write = memory_region_ram_device_write,
1305 .endianness = DEVICE_HOST_ENDIAN,
1306 .valid = {
1307 .min_access_size = 1,
1308 .max_access_size = 8,
1309 .unaligned = true,
1310 },
1311 .impl = {
1312 .min_access_size = 1,
1313 .max_access_size = 8,
1314 .unaligned = true,
1315 },
1316 };
1317
1318 bool memory_region_access_valid(MemoryRegion *mr,
1319 hwaddr addr,
1320 unsigned size,
1321 bool is_write,
1322 MemTxAttrs attrs)
1323 {
1324 int access_size_min, access_size_max;
1325 int access_size, i;
1326
1327 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1328 return false;
1329 }
1330
1331 if (!mr->ops->valid.accepts) {
1332 return true;
1333 }
1334
1335 access_size_min = mr->ops->valid.min_access_size;
1336 if (!mr->ops->valid.min_access_size) {
1337 access_size_min = 1;
1338 }
1339
1340 access_size_max = mr->ops->valid.max_access_size;
1341 if (!mr->ops->valid.max_access_size) {
1342 access_size_max = 4;
1343 }
1344
1345 access_size = MAX(MIN(size, access_size_max), access_size_min);
1346 for (i = 0; i < size; i += access_size) {
1347 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1348 is_write, attrs)) {
1349 return false;
1350 }
1351 }
1352
1353 return true;
1354 }
1355
1356 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1357 hwaddr addr,
1358 uint64_t *pval,
1359 unsigned size,
1360 MemTxAttrs attrs)
1361 {
1362 *pval = 0;
1363
1364 if (mr->ops->read) {
1365 return access_with_adjusted_size(addr, pval, size,
1366 mr->ops->impl.min_access_size,
1367 mr->ops->impl.max_access_size,
1368 memory_region_read_accessor,
1369 mr, attrs);
1370 } else {
1371 return access_with_adjusted_size(addr, pval, size,
1372 mr->ops->impl.min_access_size,
1373 mr->ops->impl.max_access_size,
1374 memory_region_read_with_attrs_accessor,
1375 mr, attrs);
1376 }
1377 }
1378
1379 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1380 hwaddr addr,
1381 uint64_t *pval,
1382 unsigned size,
1383 MemTxAttrs attrs)
1384 {
1385 MemTxResult r;
1386
1387 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1388 *pval = unassigned_mem_read(mr, addr, size);
1389 return MEMTX_DECODE_ERROR;
1390 }
1391
1392 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1393 adjust_endianness(mr, pval, size);
1394 return r;
1395 }
1396
1397 /* Return true if an eventfd was signalled */
1398 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1399 hwaddr addr,
1400 uint64_t data,
1401 unsigned size,
1402 MemTxAttrs attrs)
1403 {
1404 MemoryRegionIoeventfd ioeventfd = {
1405 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1406 .data = data,
1407 };
1408 unsigned i;
1409
1410 for (i = 0; i < mr->ioeventfd_nb; i++) {
1411 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1412 ioeventfd.e = mr->ioeventfds[i].e;
1413
1414 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1415 event_notifier_set(ioeventfd.e);
1416 return true;
1417 }
1418 }
1419
1420 return false;
1421 }
1422
1423 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1424 hwaddr addr,
1425 uint64_t data,
1426 unsigned size,
1427 MemTxAttrs attrs)
1428 {
1429 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1430 unassigned_mem_write(mr, addr, data, size);
1431 return MEMTX_DECODE_ERROR;
1432 }
1433
1434 adjust_endianness(mr, &data, size);
1435
1436 if ((!kvm_eventfds_enabled()) &&
1437 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1438 return MEMTX_OK;
1439 }
1440
1441 if (mr->ops->write) {
1442 return access_with_adjusted_size(addr, &data, size,
1443 mr->ops->impl.min_access_size,
1444 mr->ops->impl.max_access_size,
1445 memory_region_write_accessor, mr,
1446 attrs);
1447 } else {
1448 return
1449 access_with_adjusted_size(addr, &data, size,
1450 mr->ops->impl.min_access_size,
1451 mr->ops->impl.max_access_size,
1452 memory_region_write_with_attrs_accessor,
1453 mr, attrs);
1454 }
1455 }
1456
1457 void memory_region_init_io(MemoryRegion *mr,
1458 Object *owner,
1459 const MemoryRegionOps *ops,
1460 void *opaque,
1461 const char *name,
1462 uint64_t size)
1463 {
1464 memory_region_init(mr, owner, name, size);
1465 mr->ops = ops ? ops : &unassigned_mem_ops;
1466 mr->opaque = opaque;
1467 mr->terminates = true;
1468 }
1469
1470 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1471 Object *owner,
1472 const char *name,
1473 uint64_t size,
1474 Error **errp)
1475 {
1476 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1477 }
1478
1479 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1480 Object *owner,
1481 const char *name,
1482 uint64_t size,
1483 bool share,
1484 Error **errp)
1485 {
1486 Error *err = NULL;
1487 memory_region_init(mr, owner, name, size);
1488 mr->ram = true;
1489 mr->terminates = true;
1490 mr->destructor = memory_region_destructor_ram;
1491 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1492 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1493 if (err) {
1494 mr->size = int128_zero();
1495 object_unparent(OBJECT(mr));
1496 error_propagate(errp, err);
1497 }
1498 }
1499
1500 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1501 Object *owner,
1502 const char *name,
1503 uint64_t size,
1504 uint64_t max_size,
1505 void (*resized)(const char*,
1506 uint64_t length,
1507 void *host),
1508 Error **errp)
1509 {
1510 Error *err = NULL;
1511 memory_region_init(mr, owner, name, size);
1512 mr->ram = true;
1513 mr->terminates = true;
1514 mr->destructor = memory_region_destructor_ram;
1515 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1516 mr, &err);
1517 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1518 if (err) {
1519 mr->size = int128_zero();
1520 object_unparent(OBJECT(mr));
1521 error_propagate(errp, err);
1522 }
1523 }
1524
1525 #ifdef CONFIG_POSIX
1526 void memory_region_init_ram_from_file(MemoryRegion *mr,
1527 struct Object *owner,
1528 const char *name,
1529 uint64_t size,
1530 uint64_t align,
1531 uint32_t ram_flags,
1532 const char *path,
1533 Error **errp)
1534 {
1535 Error *err = NULL;
1536 memory_region_init(mr, owner, name, size);
1537 mr->ram = true;
1538 mr->terminates = true;
1539 mr->destructor = memory_region_destructor_ram;
1540 mr->align = align;
1541 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1542 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1543 if (err) {
1544 mr->size = int128_zero();
1545 object_unparent(OBJECT(mr));
1546 error_propagate(errp, err);
1547 }
1548 }
1549
1550 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1551 struct Object *owner,
1552 const char *name,
1553 uint64_t size,
1554 bool share,
1555 int fd,
1556 Error **errp)
1557 {
1558 Error *err = NULL;
1559 memory_region_init(mr, owner, name, size);
1560 mr->ram = true;
1561 mr->terminates = true;
1562 mr->destructor = memory_region_destructor_ram;
1563 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1564 share ? RAM_SHARED : 0,
1565 fd, &err);
1566 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1567 if (err) {
1568 mr->size = int128_zero();
1569 object_unparent(OBJECT(mr));
1570 error_propagate(errp, err);
1571 }
1572 }
1573 #endif
1574
1575 void memory_region_init_ram_ptr(MemoryRegion *mr,
1576 Object *owner,
1577 const char *name,
1578 uint64_t size,
1579 void *ptr)
1580 {
1581 memory_region_init(mr, owner, name, size);
1582 mr->ram = true;
1583 mr->terminates = true;
1584 mr->destructor = memory_region_destructor_ram;
1585 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1586
1587 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1588 assert(ptr != NULL);
1589 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1590 }
1591
1592 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1593 Object *owner,
1594 const char *name,
1595 uint64_t size,
1596 void *ptr)
1597 {
1598 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1599 mr->ram_device = true;
1600 mr->ops = &ram_device_mem_ops;
1601 mr->opaque = mr;
1602 }
1603
1604 void memory_region_init_alias(MemoryRegion *mr,
1605 Object *owner,
1606 const char *name,
1607 MemoryRegion *orig,
1608 hwaddr offset,
1609 uint64_t size)
1610 {
1611 memory_region_init(mr, owner, name, size);
1612 mr->alias = orig;
1613 mr->alias_offset = offset;
1614 }
1615
1616 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1617 struct Object *owner,
1618 const char *name,
1619 uint64_t size,
1620 Error **errp)
1621 {
1622 Error *err = NULL;
1623 memory_region_init(mr, owner, name, size);
1624 mr->ram = true;
1625 mr->readonly = true;
1626 mr->terminates = true;
1627 mr->destructor = memory_region_destructor_ram;
1628 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1629 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1630 if (err) {
1631 mr->size = int128_zero();
1632 object_unparent(OBJECT(mr));
1633 error_propagate(errp, err);
1634 }
1635 }
1636
1637 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1638 Object *owner,
1639 const MemoryRegionOps *ops,
1640 void *opaque,
1641 const char *name,
1642 uint64_t size,
1643 Error **errp)
1644 {
1645 Error *err = NULL;
1646 assert(ops);
1647 memory_region_init(mr, owner, name, size);
1648 mr->ops = ops;
1649 mr->opaque = opaque;
1650 mr->terminates = true;
1651 mr->rom_device = true;
1652 mr->destructor = memory_region_destructor_ram;
1653 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1654 if (err) {
1655 mr->size = int128_zero();
1656 object_unparent(OBJECT(mr));
1657 error_propagate(errp, err);
1658 }
1659 }
1660
1661 void memory_region_init_iommu(void *_iommu_mr,
1662 size_t instance_size,
1663 const char *mrtypename,
1664 Object *owner,
1665 const char *name,
1666 uint64_t size)
1667 {
1668 struct IOMMUMemoryRegion *iommu_mr;
1669 struct MemoryRegion *mr;
1670
1671 object_initialize(_iommu_mr, instance_size, mrtypename);
1672 mr = MEMORY_REGION(_iommu_mr);
1673 memory_region_do_init(mr, owner, name, size);
1674 iommu_mr = IOMMU_MEMORY_REGION(mr);
1675 mr->terminates = true; /* then re-forwards */
1676 QLIST_INIT(&iommu_mr->iommu_notify);
1677 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1678 }
1679
1680 static void memory_region_finalize(Object *obj)
1681 {
1682 MemoryRegion *mr = MEMORY_REGION(obj);
1683
1684 assert(!mr->container);
1685
1686 /* We know the region is not visible in any address space (it
1687 * does not have a container and cannot be a root either because
1688 * it has no references, so we can blindly clear mr->enabled.
1689 * memory_region_set_enabled instead could trigger a transaction
1690 * and cause an infinite loop.
1691 */
1692 mr->enabled = false;
1693 memory_region_transaction_begin();
1694 while (!QTAILQ_EMPTY(&mr->subregions)) {
1695 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1696 memory_region_del_subregion(mr, subregion);
1697 }
1698 memory_region_transaction_commit();
1699
1700 mr->destructor(mr);
1701 memory_region_clear_coalescing(mr);
1702 g_free((char *)mr->name);
1703 g_free(mr->ioeventfds);
1704 }
1705
1706 Object *memory_region_owner(MemoryRegion *mr)
1707 {
1708 Object *obj = OBJECT(mr);
1709 return obj->parent;
1710 }
1711
1712 void memory_region_ref(MemoryRegion *mr)
1713 {
1714 /* MMIO callbacks most likely will access data that belongs
1715 * to the owner, hence the need to ref/unref the owner whenever
1716 * the memory region is in use.
1717 *
1718 * The memory region is a child of its owner. As long as the
1719 * owner doesn't call unparent itself on the memory region,
1720 * ref-ing the owner will also keep the memory region alive.
1721 * Memory regions without an owner are supposed to never go away;
1722 * we do not ref/unref them because it slows down DMA sensibly.
1723 */
1724 if (mr && mr->owner) {
1725 object_ref(mr->owner);
1726 }
1727 }
1728
1729 void memory_region_unref(MemoryRegion *mr)
1730 {
1731 if (mr && mr->owner) {
1732 object_unref(mr->owner);
1733 }
1734 }
1735
1736 uint64_t memory_region_size(MemoryRegion *mr)
1737 {
1738 if (int128_eq(mr->size, int128_2_64())) {
1739 return UINT64_MAX;
1740 }
1741 return int128_get64(mr->size);
1742 }
1743
1744 const char *memory_region_name(const MemoryRegion *mr)
1745 {
1746 if (!mr->name) {
1747 ((MemoryRegion *)mr)->name =
1748 object_get_canonical_path_component(OBJECT(mr));
1749 }
1750 return mr->name;
1751 }
1752
1753 bool memory_region_is_ram_device(MemoryRegion *mr)
1754 {
1755 return mr->ram_device;
1756 }
1757
1758 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1759 {
1760 uint8_t mask = mr->dirty_log_mask;
1761 if (global_dirty_log && mr->ram_block) {
1762 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1763 }
1764 return mask;
1765 }
1766
1767 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1768 {
1769 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1770 }
1771
1772 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1773 {
1774 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1775 IOMMUNotifier *iommu_notifier;
1776 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1777
1778 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1779 flags |= iommu_notifier->notifier_flags;
1780 }
1781
1782 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1783 imrc->notify_flag_changed(iommu_mr,
1784 iommu_mr->iommu_notify_flags,
1785 flags);
1786 }
1787
1788 iommu_mr->iommu_notify_flags = flags;
1789 }
1790
1791 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1792 IOMMUNotifier *n)
1793 {
1794 IOMMUMemoryRegion *iommu_mr;
1795
1796 if (mr->alias) {
1797 memory_region_register_iommu_notifier(mr->alias, n);
1798 return;
1799 }
1800
1801 /* We need to register for at least one bitfield */
1802 iommu_mr = IOMMU_MEMORY_REGION(mr);
1803 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1804 assert(n->start <= n->end);
1805 assert(n->iommu_idx >= 0 &&
1806 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1807
1808 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1809 memory_region_update_iommu_notify_flags(iommu_mr);
1810 }
1811
1812 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1813 {
1814 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1815
1816 if (imrc->get_min_page_size) {
1817 return imrc->get_min_page_size(iommu_mr);
1818 }
1819 return TARGET_PAGE_SIZE;
1820 }
1821
1822 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1823 {
1824 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1825 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1826 hwaddr addr, granularity;
1827 IOMMUTLBEntry iotlb;
1828
1829 /* If the IOMMU has its own replay callback, override */
1830 if (imrc->replay) {
1831 imrc->replay(iommu_mr, n);
1832 return;
1833 }
1834
1835 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1836
1837 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1838 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1839 if (iotlb.perm != IOMMU_NONE) {
1840 n->notify(n, &iotlb);
1841 }
1842
1843 /* if (2^64 - MR size) < granularity, it's possible to get an
1844 * infinite loop here. This should catch such a wraparound */
1845 if ((addr + granularity) < addr) {
1846 break;
1847 }
1848 }
1849 }
1850
1851 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1852 {
1853 IOMMUNotifier *notifier;
1854
1855 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1856 memory_region_iommu_replay(iommu_mr, notifier);
1857 }
1858 }
1859
1860 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1861 IOMMUNotifier *n)
1862 {
1863 IOMMUMemoryRegion *iommu_mr;
1864
1865 if (mr->alias) {
1866 memory_region_unregister_iommu_notifier(mr->alias, n);
1867 return;
1868 }
1869 QLIST_REMOVE(n, node);
1870 iommu_mr = IOMMU_MEMORY_REGION(mr);
1871 memory_region_update_iommu_notify_flags(iommu_mr);
1872 }
1873
1874 void memory_region_notify_one(IOMMUNotifier *notifier,
1875 IOMMUTLBEntry *entry)
1876 {
1877 IOMMUNotifierFlag request_flags;
1878
1879 /*
1880 * Skip the notification if the notification does not overlap
1881 * with registered range.
1882 */
1883 if (notifier->start > entry->iova + entry->addr_mask ||
1884 notifier->end < entry->iova) {
1885 return;
1886 }
1887
1888 if (entry->perm & IOMMU_RW) {
1889 request_flags = IOMMU_NOTIFIER_MAP;
1890 } else {
1891 request_flags = IOMMU_NOTIFIER_UNMAP;
1892 }
1893
1894 if (notifier->notifier_flags & request_flags) {
1895 notifier->notify(notifier, entry);
1896 }
1897 }
1898
1899 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1900 int iommu_idx,
1901 IOMMUTLBEntry entry)
1902 {
1903 IOMMUNotifier *iommu_notifier;
1904
1905 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1906
1907 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1908 if (iommu_notifier->iommu_idx == iommu_idx) {
1909 memory_region_notify_one(iommu_notifier, &entry);
1910 }
1911 }
1912 }
1913
1914 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1915 enum IOMMUMemoryRegionAttr attr,
1916 void *data)
1917 {
1918 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1919
1920 if (!imrc->get_attr) {
1921 return -EINVAL;
1922 }
1923
1924 return imrc->get_attr(iommu_mr, attr, data);
1925 }
1926
1927 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1928 MemTxAttrs attrs)
1929 {
1930 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1931
1932 if (!imrc->attrs_to_index) {
1933 return 0;
1934 }
1935
1936 return imrc->attrs_to_index(iommu_mr, attrs);
1937 }
1938
1939 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1940 {
1941 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1942
1943 if (!imrc->num_indexes) {
1944 return 1;
1945 }
1946
1947 return imrc->num_indexes(iommu_mr);
1948 }
1949
1950 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1951 {
1952 uint8_t mask = 1 << client;
1953 uint8_t old_logging;
1954
1955 assert(client == DIRTY_MEMORY_VGA);
1956 old_logging = mr->vga_logging_count;
1957 mr->vga_logging_count += log ? 1 : -1;
1958 if (!!old_logging == !!mr->vga_logging_count) {
1959 return;
1960 }
1961
1962 memory_region_transaction_begin();
1963 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
1964 memory_region_update_pending |= mr->enabled;
1965 memory_region_transaction_commit();
1966 }
1967
1968 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1969 hwaddr size, unsigned client)
1970 {
1971 assert(mr->ram_block);
1972 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1973 size, client);
1974 }
1975
1976 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1977 hwaddr size)
1978 {
1979 assert(mr->ram_block);
1980 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1981 size,
1982 memory_region_get_dirty_log_mask(mr));
1983 }
1984
1985 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1986 {
1987 MemoryListener *listener;
1988 AddressSpace *as;
1989 FlatView *view;
1990 FlatRange *fr;
1991
1992 /* If the same address space has multiple log_sync listeners, we
1993 * visit that address space's FlatView multiple times. But because
1994 * log_sync listeners are rare, it's still cheaper than walking each
1995 * address space once.
1996 */
1997 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1998 if (!listener->log_sync) {
1999 continue;
2000 }
2001 as = listener->address_space;
2002 view = address_space_get_flatview(as);
2003 FOR_EACH_FLAT_RANGE(fr, view) {
2004 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2005 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2006 listener->log_sync(listener, &mrs);
2007 }
2008 }
2009 flatview_unref(view);
2010 }
2011 }
2012
2013 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2014 hwaddr addr,
2015 hwaddr size,
2016 unsigned client)
2017 {
2018 assert(mr->ram_block);
2019 memory_region_sync_dirty_bitmap(mr);
2020 return cpu_physical_memory_snapshot_and_clear_dirty(
2021 memory_region_get_ram_addr(mr) + addr, size, client);
2022 }
2023
2024 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2025 hwaddr addr, hwaddr size)
2026 {
2027 assert(mr->ram_block);
2028 return cpu_physical_memory_snapshot_get_dirty(snap,
2029 memory_region_get_ram_addr(mr) + addr, size);
2030 }
2031
2032 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2033 {
2034 if (mr->readonly != readonly) {
2035 memory_region_transaction_begin();
2036 mr->readonly = readonly;
2037 memory_region_update_pending |= mr->enabled;
2038 memory_region_transaction_commit();
2039 }
2040 }
2041
2042 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2043 {
2044 if (mr->romd_mode != romd_mode) {
2045 memory_region_transaction_begin();
2046 mr->romd_mode = romd_mode;
2047 memory_region_update_pending |= mr->enabled;
2048 memory_region_transaction_commit();
2049 }
2050 }
2051
2052 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2053 hwaddr size, unsigned client)
2054 {
2055 assert(mr->ram_block);
2056 cpu_physical_memory_test_and_clear_dirty(
2057 memory_region_get_ram_addr(mr) + addr, size, client);
2058 }
2059
2060 int memory_region_get_fd(MemoryRegion *mr)
2061 {
2062 int fd;
2063
2064 rcu_read_lock();
2065 while (mr->alias) {
2066 mr = mr->alias;
2067 }
2068 fd = mr->ram_block->fd;
2069 rcu_read_unlock();
2070
2071 return fd;
2072 }
2073
2074 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2075 {
2076 void *ptr;
2077 uint64_t offset = 0;
2078
2079 rcu_read_lock();
2080 while (mr->alias) {
2081 offset += mr->alias_offset;
2082 mr = mr->alias;
2083 }
2084 assert(mr->ram_block);
2085 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2086 rcu_read_unlock();
2087
2088 return ptr;
2089 }
2090
2091 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2092 {
2093 RAMBlock *block;
2094
2095 block = qemu_ram_block_from_host(ptr, false, offset);
2096 if (!block) {
2097 return NULL;
2098 }
2099
2100 return block->mr;
2101 }
2102
2103 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2104 {
2105 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2106 }
2107
2108 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2109 {
2110 assert(mr->ram_block);
2111
2112 qemu_ram_resize(mr->ram_block, newsize, errp);
2113 }
2114
2115 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2116 {
2117 FlatView *view;
2118 FlatRange *fr;
2119 CoalescedMemoryRange *cmr;
2120 AddrRange tmp;
2121 MemoryRegionSection section;
2122
2123 view = address_space_get_flatview(as);
2124 FOR_EACH_FLAT_RANGE(fr, view) {
2125 if (fr->mr == mr) {
2126 section = (MemoryRegionSection) {
2127 .fv = view,
2128 .offset_within_address_space = int128_get64(fr->addr.start),
2129 .size = fr->addr.size,
2130 };
2131
2132 MEMORY_LISTENER_CALL(as, coalesced_io_del, Reverse, &section,
2133 int128_get64(fr->addr.start),
2134 int128_get64(fr->addr.size));
2135 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2136 tmp = addrrange_shift(cmr->addr,
2137 int128_sub(fr->addr.start,
2138 int128_make64(fr->offset_in_region)));
2139 if (!addrrange_intersects(tmp, fr->addr)) {
2140 continue;
2141 }
2142 tmp = addrrange_intersection(tmp, fr->addr);
2143 MEMORY_LISTENER_CALL(as, coalesced_io_add, Forward, &section,
2144 int128_get64(tmp.start),
2145 int128_get64(tmp.size));
2146 }
2147 }
2148 }
2149 flatview_unref(view);
2150 }
2151
2152 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2153 {
2154 AddressSpace *as;
2155
2156 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2157 memory_region_update_coalesced_range_as(mr, as);
2158 }
2159 }
2160
2161 void memory_region_set_coalescing(MemoryRegion *mr)
2162 {
2163 memory_region_clear_coalescing(mr);
2164 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2165 }
2166
2167 void memory_region_add_coalescing(MemoryRegion *mr,
2168 hwaddr offset,
2169 uint64_t size)
2170 {
2171 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2172
2173 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2174 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2175 memory_region_update_coalesced_range(mr);
2176 memory_region_set_flush_coalesced(mr);
2177 }
2178
2179 void memory_region_clear_coalescing(MemoryRegion *mr)
2180 {
2181 CoalescedMemoryRange *cmr;
2182 bool updated = false;
2183
2184 qemu_flush_coalesced_mmio_buffer();
2185 mr->flush_coalesced_mmio = false;
2186
2187 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2188 cmr = QTAILQ_FIRST(&mr->coalesced);
2189 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2190 g_free(cmr);
2191 updated = true;
2192 }
2193
2194 if (updated) {
2195 memory_region_update_coalesced_range(mr);
2196 }
2197 }
2198
2199 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2200 {
2201 mr->flush_coalesced_mmio = true;
2202 }
2203
2204 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2205 {
2206 qemu_flush_coalesced_mmio_buffer();
2207 if (QTAILQ_EMPTY(&mr->coalesced)) {
2208 mr->flush_coalesced_mmio = false;
2209 }
2210 }
2211
2212 void memory_region_clear_global_locking(MemoryRegion *mr)
2213 {
2214 mr->global_locking = false;
2215 }
2216
2217 static bool userspace_eventfd_warning;
2218
2219 void memory_region_add_eventfd(MemoryRegion *mr,
2220 hwaddr addr,
2221 unsigned size,
2222 bool match_data,
2223 uint64_t data,
2224 EventNotifier *e)
2225 {
2226 MemoryRegionIoeventfd mrfd = {
2227 .addr.start = int128_make64(addr),
2228 .addr.size = int128_make64(size),
2229 .match_data = match_data,
2230 .data = data,
2231 .e = e,
2232 };
2233 unsigned i;
2234
2235 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2236 userspace_eventfd_warning))) {
2237 userspace_eventfd_warning = true;
2238 error_report("Using eventfd without MMIO binding in KVM. "
2239 "Suboptimal performance expected");
2240 }
2241
2242 if (size) {
2243 adjust_endianness(mr, &mrfd.data, size);
2244 }
2245 memory_region_transaction_begin();
2246 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2247 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2248 break;
2249 }
2250 }
2251 ++mr->ioeventfd_nb;
2252 mr->ioeventfds = g_realloc(mr->ioeventfds,
2253 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2254 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2255 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2256 mr->ioeventfds[i] = mrfd;
2257 ioeventfd_update_pending |= mr->enabled;
2258 memory_region_transaction_commit();
2259 }
2260
2261 void memory_region_del_eventfd(MemoryRegion *mr,
2262 hwaddr addr,
2263 unsigned size,
2264 bool match_data,
2265 uint64_t data,
2266 EventNotifier *e)
2267 {
2268 MemoryRegionIoeventfd mrfd = {
2269 .addr.start = int128_make64(addr),
2270 .addr.size = int128_make64(size),
2271 .match_data = match_data,
2272 .data = data,
2273 .e = e,
2274 };
2275 unsigned i;
2276
2277 if (size) {
2278 adjust_endianness(mr, &mrfd.data, size);
2279 }
2280 memory_region_transaction_begin();
2281 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2282 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2283 break;
2284 }
2285 }
2286 assert(i != mr->ioeventfd_nb);
2287 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2288 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2289 --mr->ioeventfd_nb;
2290 mr->ioeventfds = g_realloc(mr->ioeventfds,
2291 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2292 ioeventfd_update_pending |= mr->enabled;
2293 memory_region_transaction_commit();
2294 }
2295
2296 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2297 {
2298 MemoryRegion *mr = subregion->container;
2299 MemoryRegion *other;
2300
2301 memory_region_transaction_begin();
2302
2303 memory_region_ref(subregion);
2304 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2305 if (subregion->priority >= other->priority) {
2306 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2307 goto done;
2308 }
2309 }
2310 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2311 done:
2312 memory_region_update_pending |= mr->enabled && subregion->enabled;
2313 memory_region_transaction_commit();
2314 }
2315
2316 static void memory_region_add_subregion_common(MemoryRegion *mr,
2317 hwaddr offset,
2318 MemoryRegion *subregion)
2319 {
2320 assert(!subregion->container);
2321 subregion->container = mr;
2322 subregion->addr = offset;
2323 memory_region_update_container_subregions(subregion);
2324 }
2325
2326 void memory_region_add_subregion(MemoryRegion *mr,
2327 hwaddr offset,
2328 MemoryRegion *subregion)
2329 {
2330 subregion->priority = 0;
2331 memory_region_add_subregion_common(mr, offset, subregion);
2332 }
2333
2334 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2335 hwaddr offset,
2336 MemoryRegion *subregion,
2337 int priority)
2338 {
2339 subregion->priority = priority;
2340 memory_region_add_subregion_common(mr, offset, subregion);
2341 }
2342
2343 void memory_region_del_subregion(MemoryRegion *mr,
2344 MemoryRegion *subregion)
2345 {
2346 memory_region_transaction_begin();
2347 assert(subregion->container == mr);
2348 subregion->container = NULL;
2349 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2350 memory_region_unref(subregion);
2351 memory_region_update_pending |= mr->enabled && subregion->enabled;
2352 memory_region_transaction_commit();
2353 }
2354
2355 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2356 {
2357 if (enabled == mr->enabled) {
2358 return;
2359 }
2360 memory_region_transaction_begin();
2361 mr->enabled = enabled;
2362 memory_region_update_pending = true;
2363 memory_region_transaction_commit();
2364 }
2365
2366 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2367 {
2368 Int128 s = int128_make64(size);
2369
2370 if (size == UINT64_MAX) {
2371 s = int128_2_64();
2372 }
2373 if (int128_eq(s, mr->size)) {
2374 return;
2375 }
2376 memory_region_transaction_begin();
2377 mr->size = s;
2378 memory_region_update_pending = true;
2379 memory_region_transaction_commit();
2380 }
2381
2382 static void memory_region_readd_subregion(MemoryRegion *mr)
2383 {
2384 MemoryRegion *container = mr->container;
2385
2386 if (container) {
2387 memory_region_transaction_begin();
2388 memory_region_ref(mr);
2389 memory_region_del_subregion(container, mr);
2390 mr->container = container;
2391 memory_region_update_container_subregions(mr);
2392 memory_region_unref(mr);
2393 memory_region_transaction_commit();
2394 }
2395 }
2396
2397 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2398 {
2399 if (addr != mr->addr) {
2400 mr->addr = addr;
2401 memory_region_readd_subregion(mr);
2402 }
2403 }
2404
2405 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2406 {
2407 assert(mr->alias);
2408
2409 if (offset == mr->alias_offset) {
2410 return;
2411 }
2412
2413 memory_region_transaction_begin();
2414 mr->alias_offset = offset;
2415 memory_region_update_pending |= mr->enabled;
2416 memory_region_transaction_commit();
2417 }
2418
2419 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2420 {
2421 return mr->align;
2422 }
2423
2424 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2425 {
2426 const AddrRange *addr = addr_;
2427 const FlatRange *fr = fr_;
2428
2429 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2430 return -1;
2431 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2432 return 1;
2433 }
2434 return 0;
2435 }
2436
2437 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2438 {
2439 return bsearch(&addr, view->ranges, view->nr,
2440 sizeof(FlatRange), cmp_flatrange_addr);
2441 }
2442
2443 bool memory_region_is_mapped(MemoryRegion *mr)
2444 {
2445 return mr->container ? true : false;
2446 }
2447
2448 /* Same as memory_region_find, but it does not add a reference to the
2449 * returned region. It must be called from an RCU critical section.
2450 */
2451 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2452 hwaddr addr, uint64_t size)
2453 {
2454 MemoryRegionSection ret = { .mr = NULL };
2455 MemoryRegion *root;
2456 AddressSpace *as;
2457 AddrRange range;
2458 FlatView *view;
2459 FlatRange *fr;
2460
2461 addr += mr->addr;
2462 for (root = mr; root->container; ) {
2463 root = root->container;
2464 addr += root->addr;
2465 }
2466
2467 as = memory_region_to_address_space(root);
2468 if (!as) {
2469 return ret;
2470 }
2471 range = addrrange_make(int128_make64(addr), int128_make64(size));
2472
2473 view = address_space_to_flatview(as);
2474 fr = flatview_lookup(view, range);
2475 if (!fr) {
2476 return ret;
2477 }
2478
2479 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2480 --fr;
2481 }
2482
2483 ret.mr = fr->mr;
2484 ret.fv = view;
2485 range = addrrange_intersection(range, fr->addr);
2486 ret.offset_within_region = fr->offset_in_region;
2487 ret.offset_within_region += int128_get64(int128_sub(range.start,
2488 fr->addr.start));
2489 ret.size = range.size;
2490 ret.offset_within_address_space = int128_get64(range.start);
2491 ret.readonly = fr->readonly;
2492 return ret;
2493 }
2494
2495 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2496 hwaddr addr, uint64_t size)
2497 {
2498 MemoryRegionSection ret;
2499 rcu_read_lock();
2500 ret = memory_region_find_rcu(mr, addr, size);
2501 if (ret.mr) {
2502 memory_region_ref(ret.mr);
2503 }
2504 rcu_read_unlock();
2505 return ret;
2506 }
2507
2508 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2509 {
2510 MemoryRegion *mr;
2511
2512 rcu_read_lock();
2513 mr = memory_region_find_rcu(container, addr, 1).mr;
2514 rcu_read_unlock();
2515 return mr && mr != container;
2516 }
2517
2518 void memory_global_dirty_log_sync(void)
2519 {
2520 memory_region_sync_dirty_bitmap(NULL);
2521 }
2522
2523 static VMChangeStateEntry *vmstate_change;
2524
2525 void memory_global_dirty_log_start(void)
2526 {
2527 if (vmstate_change) {
2528 qemu_del_vm_change_state_handler(vmstate_change);
2529 vmstate_change = NULL;
2530 }
2531
2532 global_dirty_log = true;
2533
2534 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2535
2536 /* Refresh DIRTY_LOG_MIGRATION bit. */
2537 memory_region_transaction_begin();
2538 memory_region_update_pending = true;
2539 memory_region_transaction_commit();
2540 }
2541
2542 static void memory_global_dirty_log_do_stop(void)
2543 {
2544 global_dirty_log = false;
2545
2546 /* Refresh DIRTY_LOG_MIGRATION bit. */
2547 memory_region_transaction_begin();
2548 memory_region_update_pending = true;
2549 memory_region_transaction_commit();
2550
2551 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2552 }
2553
2554 static void memory_vm_change_state_handler(void *opaque, int running,
2555 RunState state)
2556 {
2557 if (running) {
2558 memory_global_dirty_log_do_stop();
2559
2560 if (vmstate_change) {
2561 qemu_del_vm_change_state_handler(vmstate_change);
2562 vmstate_change = NULL;
2563 }
2564 }
2565 }
2566
2567 void memory_global_dirty_log_stop(void)
2568 {
2569 if (!runstate_is_running()) {
2570 if (vmstate_change) {
2571 return;
2572 }
2573 vmstate_change = qemu_add_vm_change_state_handler(
2574 memory_vm_change_state_handler, NULL);
2575 return;
2576 }
2577
2578 memory_global_dirty_log_do_stop();
2579 }
2580
2581 static void listener_add_address_space(MemoryListener *listener,
2582 AddressSpace *as)
2583 {
2584 FlatView *view;
2585 FlatRange *fr;
2586
2587 if (listener->begin) {
2588 listener->begin(listener);
2589 }
2590 if (global_dirty_log) {
2591 if (listener->log_global_start) {
2592 listener->log_global_start(listener);
2593 }
2594 }
2595
2596 view = address_space_get_flatview(as);
2597 FOR_EACH_FLAT_RANGE(fr, view) {
2598 MemoryRegionSection section = section_from_flat_range(fr, view);
2599
2600 if (listener->region_add) {
2601 listener->region_add(listener, &section);
2602 }
2603 if (fr->dirty_log_mask && listener->log_start) {
2604 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2605 }
2606 }
2607 if (listener->commit) {
2608 listener->commit(listener);
2609 }
2610 flatview_unref(view);
2611 }
2612
2613 static void listener_del_address_space(MemoryListener *listener,
2614 AddressSpace *as)
2615 {
2616 FlatView *view;
2617 FlatRange *fr;
2618
2619 if (listener->begin) {
2620 listener->begin(listener);
2621 }
2622 view = address_space_get_flatview(as);
2623 FOR_EACH_FLAT_RANGE(fr, view) {
2624 MemoryRegionSection section = section_from_flat_range(fr, view);
2625
2626 if (fr->dirty_log_mask && listener->log_stop) {
2627 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2628 }
2629 if (listener->region_del) {
2630 listener->region_del(listener, &section);
2631 }
2632 }
2633 if (listener->commit) {
2634 listener->commit(listener);
2635 }
2636 flatview_unref(view);
2637 }
2638
2639 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2640 {
2641 MemoryListener *other = NULL;
2642
2643 listener->address_space = as;
2644 if (QTAILQ_EMPTY(&memory_listeners)
2645 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2646 memory_listeners)->priority) {
2647 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2648 } else {
2649 QTAILQ_FOREACH(other, &memory_listeners, link) {
2650 if (listener->priority < other->priority) {
2651 break;
2652 }
2653 }
2654 QTAILQ_INSERT_BEFORE(other, listener, link);
2655 }
2656
2657 if (QTAILQ_EMPTY(&as->listeners)
2658 || listener->priority >= QTAILQ_LAST(&as->listeners,
2659 memory_listeners)->priority) {
2660 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2661 } else {
2662 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2663 if (listener->priority < other->priority) {
2664 break;
2665 }
2666 }
2667 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2668 }
2669
2670 listener_add_address_space(listener, as);
2671 }
2672
2673 void memory_listener_unregister(MemoryListener *listener)
2674 {
2675 if (!listener->address_space) {
2676 return;
2677 }
2678
2679 listener_del_address_space(listener, listener->address_space);
2680 QTAILQ_REMOVE(&memory_listeners, listener, link);
2681 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2682 listener->address_space = NULL;
2683 }
2684
2685 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2686 {
2687 memory_region_ref(root);
2688 as->root = root;
2689 as->current_map = NULL;
2690 as->ioeventfd_nb = 0;
2691 as->ioeventfds = NULL;
2692 QTAILQ_INIT(&as->listeners);
2693 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2694 as->name = g_strdup(name ? name : "anonymous");
2695 address_space_update_topology(as);
2696 address_space_update_ioeventfds(as);
2697 }
2698
2699 static void do_address_space_destroy(AddressSpace *as)
2700 {
2701 assert(QTAILQ_EMPTY(&as->listeners));
2702
2703 flatview_unref(as->current_map);
2704 g_free(as->name);
2705 g_free(as->ioeventfds);
2706 memory_region_unref(as->root);
2707 }
2708
2709 void address_space_destroy(AddressSpace *as)
2710 {
2711 MemoryRegion *root = as->root;
2712
2713 /* Flush out anything from MemoryListeners listening in on this */
2714 memory_region_transaction_begin();
2715 as->root = NULL;
2716 memory_region_transaction_commit();
2717 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2718
2719 /* At this point, as->dispatch and as->current_map are dummy
2720 * entries that the guest should never use. Wait for the old
2721 * values to expire before freeing the data.
2722 */
2723 as->root = root;
2724 call_rcu(as, do_address_space_destroy, rcu);
2725 }
2726
2727 static const char *memory_region_type(MemoryRegion *mr)
2728 {
2729 if (memory_region_is_ram_device(mr)) {
2730 return "ramd";
2731 } else if (memory_region_is_romd(mr)) {
2732 return "romd";
2733 } else if (memory_region_is_rom(mr)) {
2734 return "rom";
2735 } else if (memory_region_is_ram(mr)) {
2736 return "ram";
2737 } else {
2738 return "i/o";
2739 }
2740 }
2741
2742 typedef struct MemoryRegionList MemoryRegionList;
2743
2744 struct MemoryRegionList {
2745 const MemoryRegion *mr;
2746 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2747 };
2748
2749 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2750
2751 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2752 int128_sub((size), int128_one())) : 0)
2753 #define MTREE_INDENT " "
2754
2755 static void mtree_expand_owner(fprintf_function mon_printf, void *f,
2756 const char *label, Object *obj)
2757 {
2758 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2759
2760 mon_printf(f, " %s:{%s", label, dev ? "dev" : "obj");
2761 if (dev && dev->id) {
2762 mon_printf(f, " id=%s", dev->id);
2763 } else {
2764 gchar *canonical_path = object_get_canonical_path(obj);
2765 if (canonical_path) {
2766 mon_printf(f, " path=%s", canonical_path);
2767 g_free(canonical_path);
2768 } else {
2769 mon_printf(f, " type=%s", object_get_typename(obj));
2770 }
2771 }
2772 mon_printf(f, "}");
2773 }
2774
2775 static void mtree_print_mr_owner(fprintf_function mon_printf, void *f,
2776 const MemoryRegion *mr)
2777 {
2778 Object *owner = mr->owner;
2779 Object *parent = memory_region_owner((MemoryRegion *)mr);
2780
2781 if (!owner && !parent) {
2782 mon_printf(f, " orphan");
2783 return;
2784 }
2785 if (owner) {
2786 mtree_expand_owner(mon_printf, f, "owner", owner);
2787 }
2788 if (parent && parent != owner) {
2789 mtree_expand_owner(mon_printf, f, "parent", parent);
2790 }
2791 }
2792
2793 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2794 const MemoryRegion *mr, unsigned int level,
2795 hwaddr base,
2796 MemoryRegionListHead *alias_print_queue,
2797 bool owner)
2798 {
2799 MemoryRegionList *new_ml, *ml, *next_ml;
2800 MemoryRegionListHead submr_print_queue;
2801 const MemoryRegion *submr;
2802 unsigned int i;
2803 hwaddr cur_start, cur_end;
2804
2805 if (!mr) {
2806 return;
2807 }
2808
2809 for (i = 0; i < level; i++) {
2810 mon_printf(f, MTREE_INDENT);
2811 }
2812
2813 cur_start = base + mr->addr;
2814 cur_end = cur_start + MR_SIZE(mr->size);
2815
2816 /*
2817 * Try to detect overflow of memory region. This should never
2818 * happen normally. When it happens, we dump something to warn the
2819 * user who is observing this.
2820 */
2821 if (cur_start < base || cur_end < cur_start) {
2822 mon_printf(f, "[DETECTED OVERFLOW!] ");
2823 }
2824
2825 if (mr->alias) {
2826 MemoryRegionList *ml;
2827 bool found = false;
2828
2829 /* check if the alias is already in the queue */
2830 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2831 if (ml->mr == mr->alias) {
2832 found = true;
2833 }
2834 }
2835
2836 if (!found) {
2837 ml = g_new(MemoryRegionList, 1);
2838 ml->mr = mr->alias;
2839 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2840 }
2841 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2842 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2843 "-" TARGET_FMT_plx "%s",
2844 cur_start, cur_end,
2845 mr->priority,
2846 memory_region_type((MemoryRegion *)mr),
2847 memory_region_name(mr),
2848 memory_region_name(mr->alias),
2849 mr->alias_offset,
2850 mr->alias_offset + MR_SIZE(mr->size),
2851 mr->enabled ? "" : " [disabled]");
2852 if (owner) {
2853 mtree_print_mr_owner(mon_printf, f, mr);
2854 }
2855 } else {
2856 mon_printf(f,
2857 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s",
2858 cur_start, cur_end,
2859 mr->priority,
2860 memory_region_type((MemoryRegion *)mr),
2861 memory_region_name(mr),
2862 mr->enabled ? "" : " [disabled]");
2863 if (owner) {
2864 mtree_print_mr_owner(mon_printf, f, mr);
2865 }
2866 }
2867 mon_printf(f, "\n");
2868
2869 QTAILQ_INIT(&submr_print_queue);
2870
2871 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2872 new_ml = g_new(MemoryRegionList, 1);
2873 new_ml->mr = submr;
2874 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2875 if (new_ml->mr->addr < ml->mr->addr ||
2876 (new_ml->mr->addr == ml->mr->addr &&
2877 new_ml->mr->priority > ml->mr->priority)) {
2878 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2879 new_ml = NULL;
2880 break;
2881 }
2882 }
2883 if (new_ml) {
2884 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2885 }
2886 }
2887
2888 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2889 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2890 alias_print_queue, owner);
2891 }
2892
2893 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2894 g_free(ml);
2895 }
2896 }
2897
2898 struct FlatViewInfo {
2899 fprintf_function mon_printf;
2900 void *f;
2901 int counter;
2902 bool dispatch_tree;
2903 bool owner;
2904 };
2905
2906 static void mtree_print_flatview(gpointer key, gpointer value,
2907 gpointer user_data)
2908 {
2909 FlatView *view = key;
2910 GArray *fv_address_spaces = value;
2911 struct FlatViewInfo *fvi = user_data;
2912 fprintf_function p = fvi->mon_printf;
2913 void *f = fvi->f;
2914 FlatRange *range = &view->ranges[0];
2915 MemoryRegion *mr;
2916 int n = view->nr;
2917 int i;
2918 AddressSpace *as;
2919
2920 p(f, "FlatView #%d\n", fvi->counter);
2921 ++fvi->counter;
2922
2923 for (i = 0; i < fv_address_spaces->len; ++i) {
2924 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2925 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2926 if (as->root->alias) {
2927 p(f, ", alias %s", memory_region_name(as->root->alias));
2928 }
2929 p(f, "\n");
2930 }
2931
2932 p(f, " Root memory region: %s\n",
2933 view->root ? memory_region_name(view->root) : "(none)");
2934
2935 if (n <= 0) {
2936 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2937 return;
2938 }
2939
2940 while (n--) {
2941 mr = range->mr;
2942 if (range->offset_in_region) {
2943 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2944 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx,
2945 int128_get64(range->addr.start),
2946 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2947 mr->priority,
2948 range->readonly ? "rom" : memory_region_type(mr),
2949 memory_region_name(mr),
2950 range->offset_in_region);
2951 } else {
2952 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2953 TARGET_FMT_plx " (prio %d, %s): %s",
2954 int128_get64(range->addr.start),
2955 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2956 mr->priority,
2957 range->readonly ? "rom" : memory_region_type(mr),
2958 memory_region_name(mr));
2959 }
2960 if (fvi->owner) {
2961 mtree_print_mr_owner(p, f, mr);
2962 }
2963 p(f, "\n");
2964 range++;
2965 }
2966
2967 #if !defined(CONFIG_USER_ONLY)
2968 if (fvi->dispatch_tree && view->root) {
2969 mtree_print_dispatch(p, f, view->dispatch, view->root);
2970 }
2971 #endif
2972
2973 p(f, "\n");
2974 }
2975
2976 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
2977 gpointer user_data)
2978 {
2979 FlatView *view = key;
2980 GArray *fv_address_spaces = value;
2981
2982 g_array_unref(fv_address_spaces);
2983 flatview_unref(view);
2984
2985 return true;
2986 }
2987
2988 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
2989 bool dispatch_tree, bool owner)
2990 {
2991 MemoryRegionListHead ml_head;
2992 MemoryRegionList *ml, *ml2;
2993 AddressSpace *as;
2994
2995 if (flatview) {
2996 FlatView *view;
2997 struct FlatViewInfo fvi = {
2998 .mon_printf = mon_printf,
2999 .f = f,
3000 .counter = 0,
3001 .dispatch_tree = dispatch_tree,
3002 .owner = owner,
3003 };
3004 GArray *fv_address_spaces;
3005 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3006
3007 /* Gather all FVs in one table */
3008 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3009 view = address_space_get_flatview(as);
3010
3011 fv_address_spaces = g_hash_table_lookup(views, view);
3012 if (!fv_address_spaces) {
3013 fv_address_spaces = g_array_new(false, false, sizeof(as));
3014 g_hash_table_insert(views, view, fv_address_spaces);
3015 }
3016
3017 g_array_append_val(fv_address_spaces, as);
3018 }
3019
3020 /* Print */
3021 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3022
3023 /* Free */
3024 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3025 g_hash_table_unref(views);
3026
3027 return;
3028 }
3029
3030 QTAILQ_INIT(&ml_head);
3031
3032 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3033 mon_printf(f, "address-space: %s\n", as->name);
3034 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head, owner);
3035 mon_printf(f, "\n");
3036 }
3037
3038 /* print aliased regions */
3039 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3040 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3041 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head, owner);
3042 mon_printf(f, "\n");
3043 }
3044
3045 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3046 g_free(ml);
3047 }
3048 }
3049
3050 void memory_region_init_ram(MemoryRegion *mr,
3051 struct Object *owner,
3052 const char *name,
3053 uint64_t size,
3054 Error **errp)
3055 {
3056 DeviceState *owner_dev;
3057 Error *err = NULL;
3058
3059 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3060 if (err) {
3061 error_propagate(errp, err);
3062 return;
3063 }
3064 /* This will assert if owner is neither NULL nor a DeviceState.
3065 * We only want the owner here for the purposes of defining a
3066 * unique name for migration. TODO: Ideally we should implement
3067 * a naming scheme for Objects which are not DeviceStates, in
3068 * which case we can relax this restriction.
3069 */
3070 owner_dev = DEVICE(owner);
3071 vmstate_register_ram(mr, owner_dev);
3072 }
3073
3074 void memory_region_init_rom(MemoryRegion *mr,
3075 struct Object *owner,
3076 const char *name,
3077 uint64_t size,
3078 Error **errp)
3079 {
3080 DeviceState *owner_dev;
3081 Error *err = NULL;
3082
3083 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3084 if (err) {
3085 error_propagate(errp, err);
3086 return;
3087 }
3088 /* This will assert if owner is neither NULL nor a DeviceState.
3089 * We only want the owner here for the purposes of defining a
3090 * unique name for migration. TODO: Ideally we should implement
3091 * a naming scheme for Objects which are not DeviceStates, in
3092 * which case we can relax this restriction.
3093 */
3094 owner_dev = DEVICE(owner);
3095 vmstate_register_ram(mr, owner_dev);
3096 }
3097
3098 void memory_region_init_rom_device(MemoryRegion *mr,
3099 struct Object *owner,
3100 const MemoryRegionOps *ops,
3101 void *opaque,
3102 const char *name,
3103 uint64_t size,
3104 Error **errp)
3105 {
3106 DeviceState *owner_dev;
3107 Error *err = NULL;
3108
3109 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3110 name, size, &err);
3111 if (err) {
3112 error_propagate(errp, err);
3113 return;
3114 }
3115 /* This will assert if owner is neither NULL nor a DeviceState.
3116 * We only want the owner here for the purposes of defining a
3117 * unique name for migration. TODO: Ideally we should implement
3118 * a naming scheme for Objects which are not DeviceStates, in
3119 * which case we can relax this restriction.
3120 */
3121 owner_dev = DEVICE(owner);
3122 vmstate_register_ram(mr, owner_dev);
3123 }
3124
3125 static const TypeInfo memory_region_info = {
3126 .parent = TYPE_OBJECT,
3127 .name = TYPE_MEMORY_REGION,
3128 .instance_size = sizeof(MemoryRegion),
3129 .instance_init = memory_region_initfn,
3130 .instance_finalize = memory_region_finalize,
3131 };
3132
3133 static const TypeInfo iommu_memory_region_info = {
3134 .parent = TYPE_MEMORY_REGION,
3135 .name = TYPE_IOMMU_MEMORY_REGION,
3136 .class_size = sizeof(IOMMUMemoryRegionClass),
3137 .instance_size = sizeof(IOMMUMemoryRegion),
3138 .instance_init = iommu_memory_region_initfn,
3139 .abstract = true,
3140 };
3141
3142 static void memory_register_types(void)
3143 {
3144 type_register_static(&memory_region_info);
3145 type_register_static(&iommu_memory_region_info);
3146 }
3147
3148 type_init(memory_register_types)
AR7 emulation for QEMU